diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
index cb60b74884f4f480984fcbd7e617ff210149f83a..9b7ac16c162ae9800f67ce7d745287ff3580d3ce 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
@@ -28,11 +28,20 @@
-- > run 1 us.
--
-- Or try some MM:
+-- > as 12
-- > run -a (or run 100 us)
-- On command line do:
-- > python $UPE_GEAR/peripherals/util_system_info.py --gn 0 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/pi_diag_block_gen_reg.py --gn 0 -s ETH_0 --reg gapsize=199999000
--
-
+-- To run BG eth_tester in simuation do:
+-- > run -a (or run 1 ms)
+-- > tc_unb2_test_eth_sim_start.sh
+-- > tc_unb2_test_eth_sim_stop.sh
+-- or use python script:
+-- . use -n 10000 packets/s to have 1 packet per BG sync interval of 100 us in sim
+-- > tc_unb2_test_eth.py --gn2 0 --stream 0 -n 10000 --dest loopback --range 1000,1001,1 --interval 100 --scheme tx --sim
+-- stop simulation.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
@@ -57,6 +66,8 @@ BEGIN
eth_clk(0) <= NOT eth_clk(0) AFTER 8 ns;
eth_clk(1) <= NOT eth_clk(1) AFTER 8 ns;
+ pps <= NOT pps AFTER 80 ns;
+
eth_sgin <= eth_sgout; -- loopback eth0 and eth1
u_unb2c_test_1GbE_I : ENTITY work.unb2c_test_1GbE_I
@@ -76,7 +87,6 @@ BEGIN
ID => "00000000",
TESTIO => OPEN,
-
-- 1GbE Control Interface
ETH_CLK => eth_clk,
ETH_SGIN => eth_sgin,
diff --git a/boards/uniboard2c/images/images.txt b/boards/uniboard2c/images/images.txt
index 1579a7bf7813e28d9bcc368c70632d79378ab7c3..16dc63fc0add4cd765cd374723431c784149d45a 100644
--- a/boards/uniboard2c/images/images.txt
+++ b/boards/uniboard2c/images/images.txt
@@ -1,3 +1,21 @@
Image name | Date | Author | Usage
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
unb2c_test_heater-r6825a1822 | 2021-12-10 | R vd Walle | See, $UPE_GEAR/peripherals/util_heater.py.
+
+unb2c_test_1GbE_I-r7dbc0316d.tar.gz | 2021-12-10 | E. Kooistra | See, $UPE_GEAR/peripherals/tc_unb2_test_eth.py
+
+
+
+
+
+
+
+
+
+
+Example:
+
+# Create tar.gz file:
+> tar -cvzf unb2c_test_1GbE_I-r7dbc0316d.tar.gz unb2c_test_1GbE_I.rbf unb2c_test_1GbE_I.sof
+# Extract tar.gz file:
+> tar -xvzf unb2c_test_1GbE_I-r7dbc0316d.tar.gz
diff --git a/boards/uniboard2c/images/unb2c_test_1GbE_I-r7dbc0316d.tar.gz b/boards/uniboard2c/images/unb2c_test_1GbE_I-r7dbc0316d.tar.gz
new file mode 100644
index 0000000000000000000000000000000000000000..5cb7cc715f4b04c9ca2b3698f7515cfdec8181f5
Binary files /dev/null and b/boards/uniboard2c/images/unb2c_test_1GbE_I-r7dbc0316d.tar.gz differ
diff --git a/doc/erko_howto_tools.txt b/doc/erko_howto_tools.txt
index eee61c714df8ba91089b8ed81f6c3b59454a6401..089aedec26d78b9b7f26b00fd8b46baedd3fc57e 100755
--- a/doc/erko_howto_tools.txt
+++ b/doc/erko_howto_tools.txt
@@ -1,4 +1,5 @@
* RadioHDL with GIT (LOFAR2.0)
+* Flash and reboot unb2
* RadioHDL with SVN (APERTIF/ARTS)
* RadioHDL issues
* ARGS
@@ -164,6 +165,32 @@ run_rbf unb2b lofar2_unb2b_sdp_station_full_wg
> quartus_config unb2b; run_qsys_pro unb2b lofar2_unb2b_sdp_station_full_wg; gen_rom_mmap.py --avalon -d lofar2_unb2b_sdp_station -r lofar2_unb2b_sdp_station_full_wg; run_reg unb2b lofar2_unb2b_sdp_station_full_wg; run_qcomp unb2b lofar2_unb2b_sdp_station_full_wg --clk=CLK; run_rbf unb2b lofar2_unb2b_sdp_station_full_wg
+
+*******************************************************************************
+* Flash and reboot unb2
+*******************************************************************************
+# Copy rbf image to machine
+scp build/unb2c/quartus/unb2c_test_1GbE_I/unb2c_test_1GbE_I.rbf kooistra@dop421:/home/kooistra/git/upe_gear
+
+# Flash and reboot with UPE_GEAR
+util_epcs.py --unb2 0 --pn2 0:3 -v 5 -n 9 # load factory image from flash
+util_epcs.py --unb2 0 --pn2 0:3 -v 5 -n 4 -s unb2c_test_1GbE_I.rbf # write rbf into flash
+util_epcs.py --unb2 0 --pn2 0:3 -v 5 -n 7 -s unb2c_test_1GbE_I.rbf # write rbf into flash and verify
+util_epcs.py --unb2 0 --pn2 0:3 -v 5 -n 8 # load user image from flash
+util_system_info.py --unb2 0 --pn2 0:3 -v 3 -n 2
+
+# Flash and reboot with SDPTR
+cd ../sdptr/
+. ./init_sdptr.sh
+sdp_rw.py --host 10.99.0.250 -r firmware_version
+sdp_firmware.py --host 10.99.0.250 -n 0:3 --reboot --image FACT
+sdp_rw.py --host 10.99.0.250 -r firmware_version
+sdp_firmware.py --host 10.99.0.250 -n 0:3 --write --image USER --file ../upe_gear/unb2c_test_1GbE_I.rbf
+sdp_rw.py --host 10.99.0.250 -r firmware_version
+sdp_firmware.py --host 10.99.0.250 -n 0:3 --reboot --image USER
+sdp_rw.py --host 10.99.0.250 -r firmware_version
+
+
*******************************************************************************
* RadioHDL with SVN
*******************************************************************************
@@ -1189,4 +1216,4 @@ Alt-F7 to move window on screen
> Via dop421 upe_gear:
. ./init_upe.sh
mkdir reginfo
- util_unb2.py --unb2 0 --pn2 0:3 --seq REGMAPt
+ util_unb2.py --unb2 0 --pn2 0:3 --seq REGMAP
diff --git a/libraries/base/diag/src/vhdl/diag_block_gen.vhd b/libraries/base/diag/src/vhdl/diag_block_gen.vhd
index 7e48ee30e5199d813937d0747c05a394401df2b9..79f568ad307299388350f71e6f94e17311868b24 100644
--- a/libraries/base/diag/src/vhdl/diag_block_gen.vhd
+++ b/libraries/base/diag/src/vhdl/diag_block_gen.vhd
@@ -36,6 +36,14 @@
--
-- The samples_per_packet >= 2, because the in the p_comb state machine the
-- eop cannot occur at the sop.
+-- The blocks_per_sync >= 1, so it is possible to have one block per sync
+-- interval.
+-- The gapsize >= 0, so it is possible to have blocks directly after
+-- eachother without emoty cylces.
+--
+-- The BG sync interval takes blocks_per_sync * (samples_per_packet +
+-- gapsize) clock cylces. However in case of back pressure from out_siso
+-- the BG sync interval become longer, due to clock cycles with valid = '0'.
--
-- The MM reading starts at mem_low_adrs when the BG is first enabled. If
-- the mem_high_adrs-mem_low_adrs+1 < samples_per_packet then the reading
@@ -107,7 +115,7 @@ architecture rtl of diag_block_gen is
sop : std_logic;
eop : std_logic;
rd_ena : std_logic;
- samples_cnt : natural range 0 to 2**c_diag_bg_samples_per_packet_w-1;
+ samples_cnt : natural range 0 to 2**c_diag_bg_gapsize_w-1;
blocks_cnt : natural range 0 to 2**c_diag_bg_blocks_per_sync_w-1;
bsn_cnt : std_logic_vector(c_diag_bg_bsn_init_w-1 downto 0); -- = c_dp_stream_bsn_w
mem_cnt : natural range 0 to 2**g_buf_addr_w-1;
@@ -146,14 +154,16 @@ begin
v.rd_ena := '0';
-- Control block generator enable
- if ctrl.enable='0' then
- v.blk_en := '0'; -- disable immediately
- elsif ctrl.enable_sync='0' then
- v.blk_en := '1'; -- enable immediately or keep enabled
- elsif en_sync='1' then
- v.blk_en := '1'; -- enable at input sync pulse or keep enabled
+ if ctrl.enable_sync='0' then
+ -- apply ctrl.enable immediately
+ v.blk_en := ctrl.enable;
+ else
+ -- keep blk_en and apply ctrl.enable (on or off) at input sync pulse
+ if en_sync='1' then
+ v.blk_en := ctrl.enable;
+ end if;
end if;
-
+
-- The pulse sync is high at the sop of the first block, the block sync is high during the entire block until the eop
if r.eop='1' then
v.blk_sync := '0';
@@ -286,7 +296,7 @@ begin
out_sosi_i.re <= RESIZE_DP_DSP_DATA(buf_rddat(g_buf_dat_w/2-1 downto 0)); -- treat as signed
out_sosi_i.im <= RESIZE_DP_DSP_DATA(buf_rddat(g_buf_dat_w-1 downto g_buf_dat_w/2)); -- treat as signed
out_sosi_i.data <= RESIZE_DP_DATA( buf_rddat(g_buf_dat_w-1 downto 0)); -- treat as unsigned
-
+
out_sosi <= out_sosi_i;
buf_addr <= TO_UVEC(r.mem_cnt, g_buf_addr_w);
buf_rden <= r.rd_ena;
diff --git a/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd b/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd
index 198c4fcddcd4c9da8f485fa79dff385c3ed17998..a1237047023fc7ea3d9b3a452ad99c006ce7d072 100644
--- a/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd
@@ -39,7 +39,7 @@ entity diag_block_gen_reg is
dp_clk : in std_logic;
mm_mosi : in t_mem_mosi; -- Memory Mapped Slave in mm_clk domain
mm_miso : out t_mem_miso := c_mem_miso_rst;
- bg_ctrl : out t_diag_block_gen := g_diag_block_gen_rst
+ bg_ctrl : out t_diag_block_gen := g_diag_block_gen_rst
);
end diag_block_gen_reg;
@@ -111,7 +111,7 @@ begin
when 6 =>
mm_miso.rddata(31 downto 0) <= mm_bg_ctrl.bsn_init(31 downto 0);
when 7 =>
- mm_miso.rddata(31 downto 0) <= mm_bg_ctrl.bsn_init(63 downto 32);
+ mm_miso.rddata(31 downto 0) <= mm_bg_ctrl.bsn_init(63 downto 32);
when others => null; -- not used MM addresses
end case;
end if;
diff --git a/libraries/base/diag/src/vhdl/diag_pkg.vhd b/libraries/base/diag/src/vhdl/diag_pkg.vhd
index 8e3c0eb5e50914ed7a5090ba1d3c5c19fd2dc169..9758197ca6366db3ed31ad3c2b7a709034378934 100644
--- a/libraries/base/diag/src/vhdl/diag_pkg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_pkg.vhd
@@ -106,10 +106,12 @@ PACKAGE diag_pkg IS
CONSTANT c_diag_bg_reg_adr_w : NATURAL := ceil_log2(c_diag_bg_reg_nof_dat);
CONSTANT c_diag_bg_reg_adr_span : NATURAL := 2**c_diag_bg_reg_adr_w;
+ -- Use c_diag_bg_gapsize_w = 31 to fit gapsize in 31 bit NATURAL. At 200 MHz
+ -- clock this allows a gap of 2**31 / 200e6 = 10.7 s
CONSTANT c_diag_bg_mode_w : NATURAL := 8;
CONSTANT c_diag_bg_samples_per_packet_w : NATURAL := 24;
CONSTANT c_diag_bg_blocks_per_sync_w : NATURAL := 24;
- CONSTANT c_diag_bg_gapsize_w : NATURAL := 24;
+ CONSTANT c_diag_bg_gapsize_w : NATURAL := 31;
CONSTANT c_diag_bg_mem_adrs_w : NATURAL := 24;
CONSTANT c_diag_bg_mem_low_adrs_w : NATURAL := c_diag_bg_mem_adrs_w;
CONSTANT c_diag_bg_mem_high_adrs_w : NATURAL := c_diag_bg_mem_adrs_w;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd b/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
index 93839197c820227c38c773b7a93429bef4e087a6..043664ee67e24d2b62a71a019da4f6caecb0032b 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
@@ -174,7 +174,7 @@ ARCHITECTURE rtl OF mms_diag_block_gen IS
SIGNAL ram_bg_data_mosi_arr : t_mem_mosi_arr(g_nof_streams -1 DOWNTO 0);
SIGNAL ram_bg_data_miso_arr : t_mem_miso_arr(g_nof_streams -1 DOWNTO 0);
SIGNAL bg_ctrl : t_diag_block_gen;
-
+
SIGNAL mux_ctrl : NATURAL RANGE 0 TO c_mux_nof_input-1;
SIGNAL mux_snk_out_2arr_2 : t_dp_siso_2arr_2(g_nof_streams-1 DOWNTO 0); -- [g_nof_streams-1:0][c_mux_nof_input-1:0] = [1:0]
SIGNAL mux_snk_in_2arr_2 : t_dp_sosi_2arr_2(g_nof_streams-1 DOWNTO 0); -- [g_nof_streams-1:0][c_mux_nof_input-1:0] = [1:0]
@@ -216,7 +216,7 @@ BEGIN
dp_clk => dp_clk,
mm_mosi => reg_bg_ctrl_mosi,
mm_miso => reg_bg_ctrl_miso,
- bg_ctrl => bg_ctrl
+ bg_ctrl => bg_ctrl
);
-- Combine the internal array of mm interfaces for the bg_data to one array that is connected to the port of the MM bus
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
index c54f89ca2b88ddfb950a84562bf02a26d84009a3..a6ca9a81d00d3153b472c8e995de1ef2f14f86b2 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
@@ -45,6 +45,9 @@ ENTITY tb_diag_block_gen IS
-- general
g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
-- specific
+ g_nof_samples_per_packet : NATURAL := 2; -- >= 2
+ g_nof_blocks_per_sync : NATURAL := 10; -- >= 1
+ g_gapsize : NATURAL := 32; -- >= 0
g_buf_adr_w : NATURAL := 7; -- Waveform buffer address width (requires corresponding c_buf_file)
g_buf_dat_w : NATURAL := 32; -- Waveform buffer stored data width (requires corresponding c_buf_file)
g_try_phasor : BOOLEAN := FALSE -- use TRUE to see BG phasor in wave window with out_sosi.re/im in radix
@@ -92,17 +95,15 @@ ARCHITECTURE tb OF tb_diag_block_gen IS
-- Default BG control
CONSTANT c_bg_ctrl : t_diag_block_gen := ( '0',
'0',
- TO_UVEC(96, c_diag_bg_samples_per_packet_w),
- TO_UVEC(10, c_diag_bg_blocks_per_sync_w),
- TO_UVEC(32, c_diag_bg_gapsize_w),
+ TO_UVEC(g_nof_samples_per_packet, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(g_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC(g_gapsize, c_diag_bg_gapsize_w),
TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
TO_UVEC(95, c_diag_bg_mem_high_adrs_w),
TO_UVEC(42, c_diag_bg_bsn_init_w));
CONSTANT c_bg_period : NATURAL := TO_UINT(c_bg_ctrl.samples_per_packet) + TO_UINT(c_bg_ctrl.gapsize);
-- Some alternative BG control settings
- CONSTANT c_more_samples_per_packet : NATURAL := c_buf.nof_dat;
- CONSTANT c_less_samples_per_packet : NATURAL := 5;
CONSTANT c_alternative_mem_low_adrs : NATURAL := 1;
CONSTANT c_alternative_mem_high_adrs : NATURAL := 64;
CONSTANT c_alternative_data_gap : NATURAL := 1+c_alternative_mem_low_adrs;
@@ -111,7 +112,7 @@ ARCHITECTURE tb OF tb_diag_block_gen IS
CONSTANT c_bg_ctrl2 : t_diag_block_gen := ( '0',
'0',
TO_UVEC(17, c_diag_bg_samples_per_packet_w),
- TO_UVEC(10, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC(g_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
TO_UVEC( 0, c_diag_bg_gapsize_w),
TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
TO_UVEC(16, c_diag_bg_mem_high_adrs_w),
@@ -142,7 +143,7 @@ ARCHITECTURE tb OF tb_diag_block_gen IS
SIGNAL out_siso : t_dp_siso;
SIGNAL out_sosi : t_dp_sosi;
SIGNAL prev_out_sosi : t_dp_sosi;
- SIGNAL hold_sop : STD_LOGIC;
+ SIGNAL hold_sop : STD_LOGIC := '0';
SIGNAL last_size : NATURAL;
SIGNAL exp_size : NATURAL;
SIGNAL cnt_size : NATURAL;
diff --git a/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd
index bd97553f1659f99827d32e1c5b9e4b719a19a335..99d6ec387a17fb3964bf9ef1835b52445c855ae7 100644
--- a/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd
@@ -45,12 +45,17 @@ BEGIN
-- -- general
-- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
-- -- specific
+ -- g_nof_samples_per_packet : NATURAL := 96;
+ -- g_nof_blocks_per_sync : NATURAL := 10;
+ -- g_gapsize : NATURAL := 32; -- >= 0
-- g_buf_adr_w : NATURAL := 7; -- Waveform buffer address width (requires corresponding c_buf_file)
-- g_buf_dat_w : NATURAL := 32 -- Waveform buffer stored data width (requires corresponding c_buf_file)
-- g_try_phasor : BOOLEAN := FALSE -- use TRUE to see BG phasor in wave window with out_sosi.re/im in radix
-- decimal and analogue format, no self test
- u_bg : ENTITY work.tb_diag_block_gen GENERIC MAP (e_active, 7, 32, FALSE);
- u_bg_ready : ENTITY work.tb_diag_block_gen GENERIC MAP (e_random, 7, 32, FALSE);
-
+ u_bg : ENTITY work.tb_diag_block_gen GENERIC MAP (e_active, 96, 10, 32, 7, 32, FALSE);
+ u_bg_ready : ENTITY work.tb_diag_block_gen GENERIC MAP (e_random, 96, 10, 32, 7, 32, FALSE);
+ u_bg_minimal_gap_0 : ENTITY work.tb_diag_block_gen GENERIC MAP (e_active, 2, 1, 0, 7, 32, FALSE);
+ u_bg_minimal_gap_1 : ENTITY work.tb_diag_block_gen GENERIC MAP (e_active, 2, 1, 1, 7, 32, FALSE);
+
END tb;
diff --git a/libraries/base/dp/dp.peripheral.yaml b/libraries/base/dp/dp.peripheral.yaml
index 23ed67a9ea89b4d4af72a7c355e6e2ecb07e24b6..fe9527c02280374ecc1c3604f7e2355c3520e8e1 100644
--- a/libraries/base/dp/dp.peripheral.yaml
+++ b/libraries/base/dp/dp.peripheral.yaml
@@ -451,18 +451,22 @@ peripherals:
# MM port for dp_strobe_total_count.vhd
- mm_port_name: REG_DP_STROBE_TOTAL_COUNT
mm_port_type: REG
- mm_port_span: ceil_pow2(g_nof_counts_max*2 + 1) * MM_BUS_SIZE # = 32 * MM_BUS_SIZE
+ mm_port_span: ceil_pow2(g_nof_counts_max*2 + 2) * MM_BUS_SIZE # = 32 * MM_BUS_SIZE
mm_port_description: ""
fields:
- - field_name: counts
- field_description: "Total number of strobes counters."
+ field_description: "Total number of strobes counters, updated at internal sync."
number_of_fields: g_nof_counts
address_offset: 0
user_width: 64
radix: uint64
access_mode: RO
- - field_name: clear
- field_description: "Read or write this register to clear all counters."
+ field_description: "Read or write this register to clear all counts."
+ address_offset: (g_nof_counts_max*2 + 0) * MM_BUS_SIZE # 30 * MM_BUS_SIZE
+ access_mode: RW
+ - - field_name: flush
+ field_description: "Flush current strobe counter values into the counts."
address_offset: (g_nof_counts_max*2 + 1) * MM_BUS_SIZE # 31 * MM_BUS_SIZE
access_mode: RW
diff --git a/libraries/base/dp/src/vhdl/dp_components_pkg.vhd b/libraries/base/dp/src/vhdl/dp_components_pkg.vhd
index 994b5988181f6921038a36ca7ca57313c2ff9716..308d866dfcd8196c1874da22e3c3db0c1445f871 100644
--- a/libraries/base/dp/src/vhdl/dp_components_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_components_pkg.vhd
@@ -36,11 +36,12 @@ PACKAGE dp_components_pkg IS
CONSTANT c_dp_bsn_monitor_v2_reg_adr_w : NATURAL := ceil_log2(7); -- = 3
CONSTANT c_dp_bsn_monitor_v2_reg_adr_span : NATURAL := 2**c_dp_bsn_monitor_v2_reg_adr_w; -- = 8
- CONSTANT c_dp_strobe_total_count_reg_nof_words : NATURAL := 15*2 + 1; -- = 31
+ CONSTANT c_dp_strobe_total_count_reg_nof_words : NATURAL := 15*2 + 2; -- = 32
CONSTANT c_dp_strobe_total_count_reg_adr_w : NATURAL := ceil_log2(c_dp_strobe_total_count_reg_nof_words); -- = 5
CONSTANT c_dp_strobe_total_count_reg_adr_span : NATURAL := 2**c_dp_strobe_total_count_reg_adr_w; -- = 32
CONSTANT c_dp_strobe_total_count_reg_nof_counts_max : NATURAL := 2**c_dp_strobe_total_count_reg_adr_w / 2 - 1; -- = 15
CONSTANT c_dp_strobe_total_count_reg_clear_adr : NATURAL := c_dp_strobe_total_count_reg_nof_counts_max*2; -- after counters in REGMAP
+ CONSTANT c_dp_strobe_total_count_reg_flush_adr : NATURAL := c_dp_strobe_total_count_reg_nof_counts_max*2 + 1;
END dp_components_pkg;
diff --git a/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd b/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
index 5f05e64a48373ba8ad06ca1a1573faf837685ca5..2332d5953b824f0b7d0653621a336a661ce3dc0e 100644
--- a/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
+++ b/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
@@ -26,8 +26,8 @@
-- * g_nof_counts >= 1, maximum c_nof_counts_max = 15
-- There are g_nof_counts in parallel, one clear that clears them all
-- . count any strobe like e.g. sync, sop, valid, error flag, ...
--- . MM read or write of clear registers clears all counter immediately,
--- the clear data value is dont care.
+-- . MM write of clear registers clears all counter immediately, the
+-- clear data value is dont care.
-- . the count clips at 2**g_count_w-1 in case of overflow when g_clip =
-- TRUE, else it wraps and continues from 0.
-- * g_count_w <= 64
@@ -61,13 +61,18 @@
-- (c_nof_counts_max-1)*2 [31..0] RO count[c_nof_counts_max-1] 0x0
-- (c_nof_counts_max-1)*2 + 1 [63.32]
-- c_nof_counts_max*2 [31..0] RW clear 0x0
--- c_nof_counts_max*2 + 1 [31..0] RO rsvd 0x0
+-- c_nof_counts_max*2 + 1 [31..0] RW flush 0x0
-- ===========================================================================
--
-- Remark:
-- * This dp_strobe_total_count could have been a common_strobe_total_count
-- component, because it does not use sosi/siso signals. However it is fine
-- to keep it in dp_lib, to avoid extra work of moving and renaming.
+-- * Use clear to clear the total counters
+-- * The MM counter values are held at sync. Use flush to force the current
+-- last counter values into the MM counter values. This is useful if the
+-- ref_sync stopped already.
+
LIBRARY IEEE, common_lib;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
@@ -102,6 +107,7 @@ ARCHITECTURE rtl OF dp_strobe_total_count IS
-- Fixed by REGMAP
CONSTANT c_nof_counts_max : NATURAL := c_dp_strobe_total_count_reg_nof_counts_max;
CONSTANT c_clear_adr : NATURAL := c_dp_strobe_total_count_reg_clear_adr;
+ CONSTANT c_flush_adr : NATURAL := c_dp_strobe_total_count_reg_flush_adr;
-- Define the size of the MM slave register
CONSTANT c_mm_reg : t_c_mem := (latency => 1,
@@ -118,7 +124,9 @@ ARCHITECTURE rtl OF dp_strobe_total_count IS
SIGNAL in_strobe_reg_arr : STD_LOGIC_VECTOR(g_nof_counts-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL in_strobe_reg2_arr : STD_LOGIC_VECTOR(g_nof_counts-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL rd_reg : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL mm_cnt_clr : STD_LOGIC;
+ SIGNAL mm_cnt_clear : STD_LOGIC;
+ SIGNAL mm_cnt_flush : STD_LOGIC;
+ SIGNAL cnt_flush : STD_LOGIC;
SIGNAL cnt_clr : STD_LOGIC;
SIGNAL cnt_en : STD_LOGIC := '0';
SIGNAL cnt_en_arr : STD_LOGIC_VECTOR(g_nof_counts-1 DOWNTO 0);
@@ -130,17 +138,29 @@ BEGIN
ASSERT g_nof_counts <= c_nof_counts_max REPORT "Too many counters to fit REGMAP." SEVERITY FAILURE;
ASSERT g_count_w <= g_mm_w*2 REPORT "Too wide counter to fit REGMAP." SEVERITY FAILURE;
- mm_cnt_clr <= (reg_mosi.rd OR reg_mosi.wr) WHEN TO_UINT(reg_mosi.address(c_mm_reg.adr_w-1 DOWNTO 0)) = c_clear_adr ELSE '0' ;
+ -- Only clear on MM write, to allow MM read of all register fields without clear
+ mm_cnt_clear <= reg_mosi.wr WHEN TO_UINT(reg_mosi.address(c_mm_reg.adr_w-1 DOWNTO 0)) = c_clear_adr ELSE '0';
+ mm_cnt_flush <= reg_mosi.wr WHEN TO_UINT(reg_mosi.address(c_mm_reg.adr_w-1 DOWNTO 0)) = c_flush_adr ELSE '0';
- u_common_spulse : ENTITY common_lib.common_spulse
- PORT MAP (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => mm_cnt_clr,
- out_rst => dp_rst,
- out_clk => dp_clk,
- out_pulse => cnt_clr
- );
+ u_common_spulse_clear : ENTITY common_lib.common_spulse
+ PORT MAP (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => mm_cnt_clear,
+ out_rst => dp_rst,
+ out_clk => dp_clk,
+ out_pulse => cnt_clr
+ );
+
+ u_common_spulse_flush : ENTITY common_lib.common_spulse
+ PORT MAP (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => mm_cnt_flush,
+ out_rst => dp_rst,
+ out_clk => dp_clk,
+ out_pulse => cnt_flush
+ );
-- Register inputs to ease timing closure
-- . register ref_sync to ease timing closure for ref_sync fanout
@@ -173,7 +193,7 @@ BEGIN
-- strobe counters
gen_counters : FOR I IN 0 TO g_nof_counts-1 GENERATE
- cnt_en_arr(I) <= cnt_en AND in_strobe_reg_arr(I);
+ cnt_en_arr(I) <= cnt_en AND in_strobe_reg2_arr(I);
u_counter : ENTITY common_lib.common_counter
GENERIC MAP (
@@ -191,13 +211,14 @@ BEGIN
END GENERATE;
-- Hold counter values at ref_sync_reg2 to have stable values for MM read
- -- for comparision between nodes
+ -- for comparision between nodes. Use mm_cnt_flush/cnt_flush to support
+ -- observing the current counter values via MM.
p_hold_counters : PROCESS(dp_clk)
BEGIN
IF rising_edge(dp_clk) THEN
IF cnt_clr = '1' THEN
hold_cnt_arr <= (OTHERS=>(OTHERS=>'0'));
- ELSIF ref_sync_reg2 = '1' THEN
+ ELSIF ref_sync_reg2 = '1' OR cnt_flush = '1' THEN
hold_cnt_arr <= cnt_arr;
END IF;
END IF;
diff --git a/libraries/io/eth/src/vhdl/eth.vhd b/libraries/io/eth/src/vhdl/eth.vhd
index 04dcd650ac50b462b64b433c7cf78dc61c5e1b5b..f9b99edced2f6b88d05512c2919209a838ac241d 100644
--- a/libraries/io/eth/src/vhdl/eth.vhd
+++ b/libraries/io/eth/src/vhdl/eth.vhd
@@ -365,7 +365,7 @@ BEGIN
u_frm_discard : ENTITY work.eth_frm_discard
GENERIC MAP (
g_support_dhcp => TRUE,
- g_support_udp_onload => FALSE
+ g_support_udp_onload => TRUE
)
PORT MAP (
-- Clocks and reset
diff --git a/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd b/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd
index defeba8d5c5541a777b972d1a5e296eccf172b61..4d66ad7c5abc15947f4b81c82be18d0141cb4e7f 100644
--- a/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd
+++ b/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd
@@ -107,8 +107,10 @@ PACKAGE eth_tester_pkg is
CONSTANT c_eth_tester_ip_src_addr_31_16 : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"0A63";
CONSTANT c_eth_tester_udp_src_port_15_8 : STD_LOGIC_VECTOR( 7 DOWNTO 0) := x"E0";
- -- Default eth_tester Rx UDP port for single stream via 1GbE-II
- CONSTANT c_eth_tester_eth1g_II_rx_udp_port : STD_LOGIC_VECTOR(15 DOWNTO 0) := TO_UVEC(6001, 16); -- 0x1771 = 6001
+ -- Default eth_tester UDP port for first stream via 1GbE.
+ -- Do not use UDP port 0x1388 = 5000 for eth_tester, because port 5000 is
+ -- used for M&C via 1GbE-I.
+ CONSTANT c_eth_tester_udp_port : STD_LOGIC_VECTOR(15 DOWNTO 0) := TO_UVEC(6001, 16); -- 0x1771 = 6001
TYPE t_eth_tester_app_header IS RECORD
dp_length : STD_LOGIC_VECTOR(15 DOWNTO 0);
diff --git a/libraries/io/eth/src/vhdl/eth_tester_tx.vhd b/libraries/io/eth/src/vhdl/eth_tester_tx.vhd
index 0ee2539d169bee295d7e9053d505170e88493e00..a110e63720b8dd841afff9b5af9d8c3fbd52d844 100644
--- a/libraries/io/eth/src/vhdl/eth_tester_tx.vhd
+++ b/libraries/io/eth/src/vhdl/eth_tester_tx.vhd
@@ -353,7 +353,7 @@ BEGIN
in_sosi_arr(0) => tx_fifo_sosi
);
- in_strobe_arr(0) <= tx_fifo_sosi.sop; -- count total nof Tx packets
+ in_strobe_arr(0) <= tx_fifo_sosi.sop WHEN rising_edge(st_clk); -- count total nof Tx packets
u_dp_strobe_total_count : ENTITY dp_lib.dp_strobe_total_count
GENERIC MAP (
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd b/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
index 8cd8710c7db6fc600784ddd6839be0b851ba9223..09ac6c31595ac980950cb9a8aee193ebb3ddf28f 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
@@ -60,7 +60,7 @@ ENTITY tb_eth_tester IS
g_nof_sync : NATURAL := 2; -- number of BG sync intervals to set c_run_time
g_nof_streams : NATURAL := 1; -- <= c_eth_nof_udp_ports = 4 when g_loopback_tx_rx = 1
g_loopback_eth : BOOLEAN := TRUE; -- FALSE = sosi loopback, TRUE = eth loopback (using sim_tse or tech_tse)
- g_eth_sim_level : NATURAL := 0; -- when g_loopback_eth = TRUE, then 0 = use tech_tse IP; 1 = use fast sim_tse model
+ g_eth_sim_level : NATURAL := 1; -- when g_loopback_eth = TRUE, then 0 = use tech_tse IP; 1 = use fast sim_tse model
g_corrupted_en : BOOLEAN := FALSE; -- when TRUE cause a corrupted Rx packet, when tech_tse is used
-- t_diag_block_gen_integer =
@@ -158,7 +158,7 @@ ARCHITECTURE tb OF tb_eth_tester IS
SIGNAL eth_rxp : STD_LOGIC;
SIGNAL eth_corrupt : STD_LOGIC := '0';
- -- Use same bg_ctrl for all streams, this provides sufficient test coverage
+ -- Use same bg_ctrl for all others streams, this provides sufficient test coverage
SIGNAL bg_ctrl_arr : t_diag_block_gen_integer_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL tx_fifo_rd_emp_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
@@ -392,8 +392,8 @@ BEGIN
print_str(c_tb_str &
"Rx total counts monitor(" & NATURAL'IMAGE(I) & ") :" &
" nof_packet = " & NATURAL'IMAGE(rx_total_count_nof_packet_arr(I)) &
- ", nof_valid = " & NATURAL'IMAGE(rx_total_count_nof_valid_arr(I)) &
- ", nof_corrupted = " & NATURAL'IMAGE(rx_total_count_nof_corrupted_arr(I)));
+ ", nof_valid = " & NATURAL'IMAGE(rx_total_count_nof_valid_arr(I)) &
+ ", nof_corrupted = " & NATURAL'IMAGE(rx_total_count_nof_corrupted_arr(I)));
-- Verify, only log when wrong
IF g_corrupted_en = FALSE THEN
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd b/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd
index 93ca1f7791404443c6bcde867d3aada200646a1c..e202e3b19bd3993624b81e21f7b14c63f83eb43c 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd
@@ -37,7 +37,7 @@ PACKAGE tb_eth_tester_pkg is
CONSTANT c_eth_tester_eth_dst_mac : STD_LOGIC_VECTOR(47 DOWNTO 0) := x"001B217176B9"; -- 001B217176B9 = DOP36-enp2s0
CONSTANT c_eth_tester_ip_dst_addr : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"0A6300FE"; -- 0A6300FE = '10.99.0.254' = DOP36-enp2s0
- CONSTANT c_eth_tester_udp_dst_port : STD_LOGIC_VECTOR(15 DOWNTO 0) := c_eth_tester_eth1g_II_rx_udp_port;
+ CONSTANT c_eth_tester_udp_dst_port : STD_LOGIC_VECTOR(15 DOWNTO 0) := c_eth_tester_udp_port;
-- Ethernet packet length in octets inclduing eth header and CRC
FUNCTION func_eth_tester_eth_packet_length(block_len : NATURAL) RETURN NATURAL;
diff --git a/libraries/unb_osy/unbos_eth.h b/libraries/unb_osy/unbos_eth.h
index 1a16a87f039dfd870d39070b00c804fe7785d5d7..b799911db5926ef3038ea5f9b84fc63d538493a7 100644
--- a/libraries/unb_osy/unbos_eth.h
+++ b/libraries/unb_osy/unbos_eth.h
@@ -34,7 +34,7 @@
// Start address of the rx and tx frame in the frame buffer
#define ETH_RX_RAM_BASE 0
#define ETH_TX_RAM_BASE (AVS_ETH_0_MMS_RAM_SPAN/2)
-#define ETH_FRAME_LENGTH 1518
+#define ETH_FRAME_LENGTH 9018
#define UNB_ETH_SRC_MAC_BASE ((TUInt32)0x00228608)
#define UNB_ETH_SRC_MAC_BASE_HI ((UNB_ETH_SRC_MAC_BASE >> 16) & 0xFFFF)
#define UNB_ETH_SRC_MAC_BASE_LO ( UNB_ETH_SRC_MAC_BASE & 0xFFFF)