diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb_ddr3_transpose_pins_constraints.tcl b/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb_ddr3_transpose_pins_constraints.tcl
index b9ce36731371a4359b96be5be5c6c57ce58cdf5d..5d3473fc4bc6246cfcd3e7111ae1799513f2cbc8 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb_ddr3_transpose_pins_constraints.tcl
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb_ddr3_transpose_pins_constraints.tcl
@@ -1,517 +1,517 @@
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].ba[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].ba[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].ba[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].ba[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].ba[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].ba[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].cs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].cs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].cs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].cs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].we_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].we_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].ras_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].ras_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].cas_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].cas_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].cke[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].cke[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].cke[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].cke[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].odt[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].odt[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].odt[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].odt[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD 1.5V -to MB_I_OU[0].reset_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].reset_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_OU[0].dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_OU[0].dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_OU[0].dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_OU[0].dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_OU[0].dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_OU[0].dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_OU[0].dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_OU[0].dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU[0].ck[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU[0].ck[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU[0].ck[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU[0].ck[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU[0].ck_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU[0].ck_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU[0].ck_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU[0].ck_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[1]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[2]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[3]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[5]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[6]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|ureset|phy_reset_mem_stable_n" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|ureset|phy_reset_n" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|s0|sequencer_rw_mgr_inst|rw_mgr_inst|rw_mgr_core_inst|rw_soft_reset_n" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[4]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[4]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[5]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[5]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[6]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[6]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[7]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[7]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[0]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[1]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[2]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[3]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[4]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[5]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[6]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[7]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name PLL_ENFORCE_USER_PHASE_SHIFT ON -to "u_ddr3_T|u_ddr3|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|pll1" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU.ck[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU.ck[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU.ck[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU.ck[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU.ck_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU.ck_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU.ck_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU.ck_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.ba[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.ba[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.ba[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.ba[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.ba[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.ba[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.cs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.cs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.cs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.cs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.we_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.we_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.ras_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.ras_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.cas_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.cas_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.cke[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.cke[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.cke[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.cke[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.odt[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.odt[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.odt[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.odt[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD 1.5V -to MB_I_OU.reset_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.reset_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[1]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[2]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[3]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[5]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[6]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|ureset|phy_reset_mem_stable_n" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|ureset|phy_reset_n" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|s0|sequencer_rw_mgr_inst|rw_mgr_inst|rw_mgr_core_inst|rw_soft_reset_n" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[4]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[4]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[5]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[5]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[6]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[6]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[7]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[7]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[0]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[1]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[2]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[3]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[4]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[5]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[6]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[7]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name PLL_ENFORCE_USER_PHASE_SHIFT ON -to "u_ddr3_T|u_ddr3|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|pll1" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
 set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
 set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
 set_global_assignment -name UNIPHY_TEMP_VER_CODE 1207645311
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
index ec8ca4f279b12d954ba43504b31315ca6d7314e3..b97cefdfa2c21c93503fe8f53b9388d6919bf828 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
@@ -20,7 +20,7 @@
 --
 -------------------------------------------------------------------------------
 
-LIBRARY IEEE, common_lib, unb1_board_lib, eth_lib, diag_lib, dp_lib, ddr3_lib;
+LIBRARY IEEE, common_lib, unb1_board_lib, eth_lib, diag_lib, dp_lib, ddr3_lib, tech_ddr_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
@@ -29,6 +29,7 @@ USE unb1_board_lib.unb1_board_pkg.ALL;
 USE eth_lib.eth_pkg.ALL;
 USE diag_lib.diag_pkg.ALL; 
 USE dp_lib.dp_stream_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
 USE ddr3_lib.ddr3_pkg.ALL; 
 
 ENTITY unb1_ddr3_transpose IS
@@ -67,9 +68,9 @@ ENTITY unb1_ddr3_transpose IS
     ETH_SGOUT    : OUT   STD_LOGIC;
     
     -- SO-DIMM Memory Bank I
-    MB_I_IN       : IN    t_ddr3_phy_in_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0) := (OTHERS=>c_ddr3_phy_in_rst);
-    MB_I_IO       : INOUT t_ddr3_phy_io_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0);
-    MB_I_OU       : OUT   t_ddr3_phy_ou_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0)
+    MB_I_IN       : IN    t_tech_ddr3_phy_in := c_tech_ddr3_phy_in_x;
+    MB_I_IO       : INOUT t_tech_ddr3_phy_io;
+    MB_I_OU       : OUT   t_tech_ddr3_phy_ou
   );
 END unb1_ddr3_transpose;
 
@@ -492,9 +493,9 @@ BEGIN
     ser_term_ctrl_in      => OPEN,
     par_term_ctrl_in      => OPEN,
                           
-    phy_in                => MB_I_in(0),
-    phy_io                => MB_I_io(0),     
-    phy_ou                => MB_I_ou(0)
+    phy_in                => MB_I_in,
+    phy_io                => MB_I_io,     
+    phy_ou                => MB_I_ou
   );
 
   ----------------------------------------------------------------------------
diff --git a/libraries/io/ddr3/hdllib.cfg b/libraries/io/ddr3/hdllib.cfg
index 7b03308e7c25972e832f742daca115efd22de1b1..85f135f0f9399e8d6a89b734c05ca11857699564 100644
--- a/libraries/io/ddr3/hdllib.cfg
+++ b/libraries/io/ddr3/hdllib.cfg
@@ -21,8 +21,8 @@ synth_files =
     src/vhdl/ddr3.vhd
     src/vhdl/ddr3_transpose.vhd
     src/vhdl/mms_ddr3.vhd
-    $UNB/Firmware/modules/ddr3/src/vhdl/mms_ddr3_capture.vhd
-    $UNB/Firmware/modules/ddr3/src/vhdl/seq_ddr3.vhd
+    src/vhdl/mms_ddr3_capture.vhd
+    src/vhdl/seq_ddr3.vhd
 
 test_bench_files = 
     tb/vhdl/tb_ddr3.vhd
diff --git a/libraries/io/ddr3/src/vhdl/ddr3.vhd b/libraries/io/ddr3/src/vhdl/ddr3.vhd
index b11c2b3d181bab89438e6a14491bab387c3bfb10..7485a037c978ee492fdb78a871ebd50836c5ef33 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3.vhd
@@ -24,11 +24,13 @@
 LIBRARY ip_stratixiv_ddr3_uphy_4g_800_master_lib;
 LIBRARY ip_stratixiv_ddr3_uphy_4g_800_slave_lib;
 
-LIBRARY IEEE, common_lib, dp_lib, tech_ddr_lib;
+LIBRARY IEEE, common_lib, technology_lib, dp_lib, tech_ddr_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL; 
 USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 USE tech_ddr_lib.tech_ddr_pkg.ALL;
 USE work.ddr3_pkg.ALL;
@@ -112,14 +114,15 @@ ARCHITECTURE str OF ddr3 IS
   CONSTANT c_wr_fifo_depth  : NATURAL := g_wr_fifo_depth * (c_ddr3_ctlr_data_w/g_wr_data_w); -- Multiply fifo depth by the fifo's rd/wr width ratio to get write side depth
                             
   CONSTANT c_latency        : NATURAL := 1;
+
+  CONSTANT c_ctlr_address_w : NATURAL := func_tech_ddr_ctlr_address_w(c_tech_ddr3_4g_800m_master);
+  CONSTANT c_ctlr_data_w    : NATURAL := func_tech_ddr_ctlr_data_w(c_tech_ddr3_4g_800m_master);
                             
   SIGNAL ctlr_burst         : STD_LOGIC; 
   SIGNAL ctlr_burst_size    : STD_LOGIC_VECTOR(c_ddr3_ctlr_maxburstsize_w-1 DOWNTO 0);
-  SIGNAL ctlr_address       : STD_LOGIC_VECTOR(ceil_log2(g_ddr.cs_w-1) + g_ddr.ba_w + g_ddr.a_w + g_ddr.a_col_w - c_ddr3_ctlr_rsl_w-1 DOWNTO 0); -- ceil_log2(..-1) because the chip select lines are converted to a logical address
   SIGNAL ctlr_rd_req        : STD_LOGIC;
   SIGNAL ctlr_wr_req        : STD_LOGIC;
                             
-  SIGNAL ctlr_rst_n         : STD_LOGIC;
   SIGNAL ctlr_gen_rst_n     : STD_LOGIC;
                             
   SIGNAL i_ctlr_gen_clk     : STD_LOGIC;
@@ -148,14 +151,17 @@ ARCHITECTURE str OF ddr3 IS
   
   CONSTANT c_mem_reg_io_ddr : t_c_mem := (c_mem_reg_rd_latency, 1 , 32 , 1, 'X');
   SIGNAL mm_reg_io_ddr      : STD_LOGIC_VECTOR(31 DOWNTO 0);                     
+
+  SIGNAL term_ctrl_out      : t_tech_ddr3_phy_terminationcontrol;
+  SIGNAL term_ctrl_in       : t_tech_ddr3_phy_terminationcontrol;
+
+  SIGNAL ctlr_tech_mosi     : t_mem_ctlr_mosi;
+  SIGNAL ctlr_tech_miso     : t_mem_ctlr_miso;
   
 BEGIN 
 
   dvr_done <= i_dvr_done;
 
-  ctlr_rst_n      <= NOT(ctlr_rst);  
-  i_ctlr_gen_rst  <= NOT(ctlr_gen_rst_n);
-
   ctlr_gen_clk    <= i_ctlr_gen_clk;
   ctlr_gen_rst    <= i_ctlr_gen_rst;
   ctlr_gen_clk_2x <= i_ctlr_gen_clk_2x;   
@@ -318,120 +324,64 @@ BEGIN
 
   mm_reg_io_ddr <= RESIZE_UVEC(local_cal_fail & local_cal_success & i_ctlr_gen_rst & flush_ena & i_ctlr_rdy & i_ctlr_init_done, 32);   
 
-  ctlr_address <= dvr_cur_addr.chip & dvr_cur_addr.bank & dvr_cur_addr.row(g_ddr.a_w-1 DOWNTO 0) & dvr_cur_addr.column(g_ddr.a_col_w -1 DOWNTO c_ddr3_ctlr_rsl_w);
-
-  gen_ip_stratixiv_ddr3_uphy_4g_800_master : IF g_mts = 800 AND g_phy = 1 GENERATE
-    u_ip_stratixiv_ddr3_uphy_4g_800_master : ip_stratixiv_ddr3_uphy_4g_800_master
-	   PORT MAP (
-	  	pll_ref_clk                => ctlr_ref_clk,                         
-	  	global_reset_n             => ctlr_rst_n,                           
-	  	soft_reset_n               => '1',                                  
-	  	afi_clk                    => i_ctlr_gen_clk,                       
-	  	afi_half_clk               => OPEN,                                 
-	  	afi_reset_n                => ctlr_gen_rst_n,                       
-	  	mem_a                      => phy_ou.a(g_ddr.a_w-1 DOWNTO 0),       
-	  	mem_ba                     => phy_ou.ba(g_ddr.ba_w-1 DOWNTO 0),     
-	  	mem_ck                     => phy_ou.ck(g_ddr.clk_w-1 DOWNTO 0),   
-	  	mem_ck_n                   => phy_ou.ck_n(g_ddr.clk_w-1 DOWNTO 0), 
-	  	mem_cke                    => phy_ou.cke(g_ddr.clk_w-1 DOWNTO 0),   
-	  	mem_cs_n                   => phy_ou.cs_n(g_ddr.cs_w-1 DOWNTO 0),   
-	  	mem_dm                     => phy_ou.dm(g_ddr.dm_w-1 DOWNTO 0),     
-	  	mem_ras_n                  => phy_ou.ras_n,                         
-	  	mem_cas_n                  => phy_ou.cas_n,                         
-	  	mem_we_n                   => phy_ou.we_n,                          
-	  	mem_reset_n                => phy_ou.reset_n,                       
-	  	mem_dq                     => phy_io.dq(g_ddr.dq_w-1 DOWNTO 0),     
-	  	mem_dqs                    => phy_io.dqs(g_ddr.dqs_w-1 DOWNTO 0),   
-	  	mem_dqs_n                  => phy_io.dqs_n(g_ddr.dqs_w-1 DOWNTO 0), 
-	  	mem_odt                    => phy_ou.odt(g_ddr.cs_w-1 DOWNTO 0),    
-	  	avl_ready                  => i_ctlr_rdy,                           
-	  	avl_burstbegin             => ctlr_burst,                           
-	  	avl_addr                   => ctlr_address,                         
-	  	avl_rdata_valid            => ctlr_rd_sosi.valid,                   
-	  	avl_rdata                  => ctlr_rd_sosi.data(c_ddr3_ctlr_data_w-1 DOWNTO 0),                    
-	  	avl_wdata                  => ctlr_wr_sosi.data(c_ddr3_ctlr_data_w-1 DOWNTO 0),                    
-	  	avl_be                     => (OTHERS => '1'),                      
-	  	avl_read_req               => ctlr_rd_req,                          
-	  	avl_write_req              => ctlr_wr_req,                          
-	  	avl_size                   => ctlr_burst_size,          
-	  	local_init_done            => i_ctlr_init_done,                     
-	  	local_cal_success          => local_cal_success,
-	  	local_cal_fail             => local_cal_fail,                                 
-	  	oct_rdn                    => phy_in.oct_rdn,                       
-	  	oct_rup                    => phy_in.oct_rup,                       
-  		seriesterminationcontrol   => ser_term_ctrl_out,                                 
-	  	parallelterminationcontrol => par_term_ctrl_out,                                 
-	  	pll_mem_clk                => i_ctlr_gen_clk_2x,
-      pll_write_clk              => OPEN,
-      pll_write_clk_pre_phy_clk  => OPEN,
-      pll_addr_cmd_clk           => OPEN,
-      pll_locked                 => OPEN,
-      pll_avl_clk                => OPEN,
-      pll_config_clk             => OPEN,
-      dll_delayctrl              => OPEN
-	  );    
-  END GENERATE;  
-
-  gen_ip_stratixiv_ddr3_uphy_4g_800_slave : IF g_mts = 800 AND g_phy = 2 GENERATE
-    u_ip_stratixiv_ddr3_uphy_4g_800_slave : ip_stratixiv_ddr3_uphy_4g_800_slave
-	   PORT MAP (
-	  	pll_ref_clk                => ctlr_ref_clk,                         
-	  	global_reset_n             => ctlr_rst_n,                           
-	  	soft_reset_n               => '1',                                  
-	  	afi_clk                    => i_ctlr_gen_clk,                       
-	  	afi_half_clk               => OPEN,                                 
-	  	afi_reset_n                => ctlr_gen_rst_n,                       
-	  	mem_a                      => phy_ou.a(g_ddr.a_w-1 DOWNTO 0),       
-	  	mem_ba                     => phy_ou.ba(g_ddr.ba_w-1 DOWNTO 0),     
-	  	mem_ck                     => phy_ou.ck(g_ddr.clk_w-1 DOWNTO 0),   
-	  	mem_ck_n                   => phy_ou.ck_n(g_ddr.clk_w-1 DOWNTO 0), 
-	  	mem_cke                    => phy_ou.cke(g_ddr.clk_w-1 DOWNTO 0),   
-	  	mem_cs_n                   => phy_ou.cs_n(g_ddr.cs_w-1 DOWNTO 0),   
-	  	mem_dm                     => phy_ou.dm(g_ddr.dm_w-1 DOWNTO 0),     
-	  	mem_ras_n                  => phy_ou.ras_n,                         
-	  	mem_cas_n                  => phy_ou.cas_n,                         
-	  	mem_we_n                   => phy_ou.we_n,                          
-	  	mem_reset_n                => phy_ou.reset_n,                       
-	  	mem_dq                     => phy_io.dq(g_ddr.dq_w-1 DOWNTO 0),     
-	  	mem_dqs                    => phy_io.dqs(g_ddr.dqs_w-1 DOWNTO 0),   
-	  	mem_dqs_n                  => phy_io.dqs_n(g_ddr.dqs_w-1 DOWNTO 0), 
-	  	mem_odt                    => phy_ou.odt(g_ddr.cs_w-1 DOWNTO 0),    
-	  	avl_ready                  => i_ctlr_rdy,                           
-	  	avl_burstbegin             => ctlr_burst,                           
-	  	avl_addr                   => ctlr_address,                         
-	  	avl_rdata_valid            => ctlr_rd_sosi.valid,                   
-	  	avl_rdata                  => ctlr_rd_sosi.data(c_ddr3_ctlr_data_w-1 DOWNTO 0),                    
-	  	avl_wdata                  => ctlr_wr_sosi.data(c_ddr3_ctlr_data_w-1 DOWNTO 0),              
-	  	avl_be                     => (OTHERS => '1'),                      
-	  	avl_read_req               => ctlr_rd_req,                          
-	  	avl_write_req              => ctlr_wr_req,                          
-	  	avl_size                   => ctlr_burst_size,          
-	  	local_init_done            => i_ctlr_init_done,                     
-	  	local_cal_success          => OPEN,                                 
-	  	local_cal_fail             => OPEN,                                 
-  		seriesterminationcontrol   => ser_term_ctrl_in,                                 
-	  	parallelterminationcontrol => par_term_ctrl_in,                                 
-	  	pll_mem_clk                => i_ctlr_gen_clk_2x,
-      pll_write_clk              => OPEN,
-      pll_write_clk_pre_phy_clk  => OPEN,
-      pll_addr_cmd_clk           => OPEN,
-      pll_locked                 => OPEN,
-      pll_avl_clk                => OPEN,
-      pll_config_clk             => OPEN,
-      dll_delayctrl              => OPEN
-	  );    
-  END GENERATE;  
-
-  u_async_ctlr_gen_rst_2x: ENTITY common_lib.common_async
-  GENERIC MAP(
-    g_rst_level => '0'
+
+
+
+
+
+  ser_term_ctrl_out <= term_ctrl_out.seriesterminationcontrol;
+  par_term_ctrl_out <= term_ctrl_out.parallelterminationcontrol;
+  term_ctrl_in.seriesterminationcontrol   <= ser_term_ctrl_in;
+  term_ctrl_in.parallelterminationcontrol <= par_term_ctrl_in;
+
+
+
+  ctlr_tech_mosi.burstbegin <= ctlr_burst;
+  ctlr_tech_mosi.address    <= RESIZE_UVEC(dvr_cur_addr.chip & dvr_cur_addr.bank & dvr_cur_addr.row(g_ddr.a_w-1 DOWNTO 0) & dvr_cur_addr.column(g_ddr.a_col_w -1 DOWNTO c_ddr3_ctlr_rsl_w),32);
+  ctlr_tech_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0) <= ctlr_wr_sosi.data(c_ctlr_data_w-1 DOWNTO 0);
+  ctlr_tech_mosi.rd         <= ctlr_rd_req;
+  ctlr_tech_mosi.wr         <= ctlr_wr_req;
+  ctlr_tech_mosi.burstsize  <= RESIZE_UVEC(ctlr_burst_size,32);
+
+  i_ctlr_rdy                                  <= ctlr_tech_miso.waitrequest_n;
+  ctlr_rd_sosi.valid                          <= ctlr_tech_miso.rdval;
+  ctlr_rd_sosi.data(c_ctlr_data_w-1 DOWNTO 0) <= ctlr_tech_miso.rddata(c_ctlr_data_w-1 DOWNTO 0);
+  i_ctlr_init_done                            <= ctlr_tech_miso.done;
+  local_cal_success                           <= ctlr_tech_miso.cal_ok;
+  local_cal_fail                              <= ctlr_tech_miso.cal_fail;
+
+
+
+
+
+
+  u_tech_ddr : ENTITY tech_ddr_lib.tech_ddr
+  GENERIC MAP (
+    g_technology    => c_tech_stratixiv,
+    g_tech_ddr      => c_tech_ddr3_4g_800m_master
   )
-  PORT MAP(
-    rst  => ctlr_rst,
-    clk  => i_ctlr_gen_clk_2x,
-    din  => i_ctlr_gen_rst,
-    dout => ctlr_gen_rst_2x
-  );
-              
+  PORT MAP (
+    -- PLL reference clock
+    ref_clk         => ctlr_ref_clk,
+    ref_rst         => ctlr_rst,
+
+    -- Controller user interface
+    ctlr_gen_clk    => i_ctlr_gen_clk,
+    ctlr_gen_rst    => i_ctlr_gen_rst,
+    ctlr_gen_clk_2x => i_ctlr_gen_clk_2x,
+    ctlr_gen_rst_2x => ctlr_gen_rst_2x,
+
+    ctlr_mosi       => ctlr_tech_mosi,
+    ctlr_miso       => ctlr_tech_miso,
+
+    term_ctrl_out   => term_ctrl_out,
+    term_ctrl_in    => term_ctrl_in,
+
+    -- DDR3 PHY interface
+    phy3_in         => phy_in,
+    phy3_io         => phy_io,
+    phy3_ou         => phy_ou
+  );  
+
 END str;
 
diff --git a/libraries/io/ddr3/src/vhdl/mms_ddr3_capture.vhd b/libraries/io/ddr3/src/vhdl/mms_ddr3_capture.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..112832162213e67619b4e8583105591fc5c9ab53
--- /dev/null
+++ b/libraries/io/ddr3/src/vhdl/mms_ddr3_capture.vhd
@@ -0,0 +1,168 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib, tech_ddr_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+USE work.ddr3_pkg.ALL;
+
+ENTITY mms_ddr3_capture IS
+  GENERIC (
+    g_sim                     : BOOLEAN := FALSE; 
+    g_ddr                     : t_c_ddr3_phy := c_ddr3_phy_4g;
+    g_mts                     : NATURAL := 800;
+    g_wr_data_w               : NATURAL := c_ddr3_ctlr_data_w; 
+    g_wr_use_ctrl             : BOOLEAN := FALSE;
+    g_wr_fifo_depth           : NATURAL := 128;
+    g_rd_fifo_depth           : NATURAL := 256;  
+    g_rd_data_w               : NATURAL := c_ddr3_ctlr_data_w;  
+    g_flush_wr_fifo           : BOOLEAN := FALSE;  
+    g_flush_sop               : BOOLEAN := FALSE;  
+    g_flush_sop_channel       : BOOLEAN := FALSE;  
+    g_flush_sop_start_channel : NATURAL := 0; 
+    g_flush_nof_channels      : NATURAL := 0;
+    g_use_bsn_scheduler       : BOOLEAN := FALSE
+  );
+  PORT (
+    mm_rst          : IN    STD_LOGIC;
+    mm_clk          : IN    STD_LOGIC;
+
+    ctlr_ref_clk    : IN    STD_LOGIC;
+    ctlr_rst        : IN    STD_LOGIC; -- asynchronous reset input to controller
+
+    ctlr_gen_clk    : OUT   STD_LOGIC; -- Controller generated clock
+    ctlr_gen_rst    : OUT   STD_LOGIC;    
+
+    wr_clk          : IN    STD_LOGIC;
+    wr_rst          : IN    STD_LOGIC;
+
+    wr_sosi         : IN    t_dp_sosi;
+    wr_siso         : OUT   t_dp_siso;
+    
+    flush_ena       : IN    STD_LOGIC := '0';
+ 
+    -- MM registers
+    ddr3_mosi       : IN    t_mem_mosi := c_mem_mosi_rst;
+    ddr3_miso       : OUT   t_mem_miso;
+  
+    dpmm_ctrl_mosi  : IN    t_mem_mosi := c_mem_mosi_rst;
+    dpmm_ctrl_miso  : OUT   t_mem_miso := c_mem_miso_rst;
+
+    dpmm_data_mosi  : IN    t_mem_mosi := c_mem_mosi_rst;
+    dpmm_data_miso  : OUT   t_mem_miso := c_mem_miso_rst;
+    
+    -- SO-DIMM Memory Bank
+    ddr3_in         : IN    t_tech_ddr3_phy_in;
+    ddr3_io         : INOUT t_tech_ddr3_phy_io;
+    ddr3_ou         : OUT   t_tech_ddr3_phy_ou
+  );
+END mms_ddr3_capture;
+
+
+ARCHITECTURE str OF mms_ddr3_capture IS
+ 
+  SIGNAL rd_sosi    : t_dp_sosi;
+  SIGNAL rd_siso    : t_dp_siso;
+  
+  SIGNAL rd_clk     : STD_LOGIC;
+  SIGNAL rd_rst     : STD_LOGIC;
+
+  SIGNAL rd_fifo_usedw : STD_LOGIC_VECTOR(ceil_log2(g_rd_fifo_depth * (c_ddr3_ctlr_data_w/g_rd_data_w) )-1 DOWNTO 0);
+
+BEGIN
+
+  u_mms_ddr3: ENTITY work.mms_ddr3
+  GENERIC MAP(
+    g_sim                      => g_sim,
+    g_ddr                      => g_ddr,
+    g_mts                      => g_mts,
+    g_wr_data_w                => g_wr_data_w,
+    g_wr_use_ctrl              => g_wr_use_ctrl,      
+    g_wr_fifo_depth            => g_wr_fifo_depth,
+    g_rd_fifo_depth            => g_rd_fifo_depth,     
+    g_rd_data_w                => c_word_w, 
+    g_flush_wr_fifo            => g_flush_wr_fifo,
+    g_flush_sop                => g_flush_sop,
+    g_flush_sop_channel        => g_flush_sop_channel,
+    g_flush_sop_start_channel  => g_flush_sop_start_channel,
+    g_flush_nof_channels       => g_flush_nof_channels
+  )                          
+  PORT MAP (        
+    mm_rst             => mm_rst, 
+    mm_clk             => mm_clk,
+            
+    ctlr_ref_clk       => ctlr_ref_clk,
+    ctlr_rst           => ctlr_rst,
+
+    ctlr_gen_clk       => ctlr_gen_clk,
+    ctlr_gen_rst       => ctlr_gen_rst,      
+
+    wr_clk             => wr_clk,
+    wr_rst             => wr_rst,
+
+    wr_sosi            => wr_sosi, 
+    wr_siso            => wr_siso,
+    
+    flush_ena          => flush_ena,
+  
+    rd_sosi            => rd_sosi,
+    rd_siso            => rd_siso,
+
+    rd_clk             => mm_clk,
+    rd_rst             => mm_rst,
+
+    rd_fifo_usedw      => rd_fifo_usedw, -- relative to FIFO wr side
+
+    ctrl_mosi          => ddr3_mosi,
+    ctrl_miso          => ddr3_miso,
+
+    ddr3_in            => ddr3_in,
+    ddr3_io            => ddr3_io,     
+    ddr3_ou            => ddr3_ou
+  );
+
+  u_mms_dp_fifo_to_mm: ENTITY dp_lib.mms_dp_fifo_to_mm
+  GENERIC MAP(
+    g_rd_fifo_depth => g_rd_fifo_depth * (c_ddr3_ctlr_data_w/g_rd_data_w)
+  )                          
+  PORT MAP (        
+    mm_rst             => mm_rst, 
+    mm_clk             => mm_clk,        
+ 
+    rd_sosi            => rd_sosi,
+    rd_siso            => rd_siso,
+
+    ctrl_mosi          => dpmm_ctrl_mosi,
+    ctrl_miso          => dpmm_ctrl_miso,
+
+    data_mosi          => dpmm_data_mosi,
+    data_miso          => dpmm_data_miso,
+
+    rd_usedw           => rd_fifo_usedw
+
+  );
+
+
+END str;
+
diff --git a/libraries/io/ddr3/src/vhdl/seq_ddr3.vhd b/libraries/io/ddr3/src/vhdl/seq_ddr3.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2a1685b9dda69154ce353e0119e261ab6e420679
--- /dev/null
+++ b/libraries/io/ddr3/src/vhdl/seq_ddr3.vhd
@@ -0,0 +1,189 @@
+
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib, tech_ddr_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+USE work.ddr3_pkg.ALL;
+
+ENTITY seq_ddr3 IS
+  GENERIC (
+    g_ddr      : t_c_ddr3_phy := c_ddr3_phy_4g;    
+    g_phy      : NATURAL      := 1; 
+    g_mts      : NATURAL      := 800;
+    g_data_w   : NATURAL      := c_ddr3_ctlr_data_w; 
+    g_ddr3_seq : t_ddr3_seq   := c_ddr3_seq
+  );
+  PORT (
+    ctlr_ref_clk      : IN    STD_LOGIC;
+    ctlr_rst          : IN    STD_LOGIC; -- asynchronous reset input to controller
+                      
+    ctlr_gen_clk      : OUT   STD_LOGIC; -- Controller generated clock
+    ctlr_gen_rst      : OUT   STD_LOGIC;    
+                      
+    wr_clk            : IN    STD_LOGIC;
+    wr_rst            : IN    STD_LOGIC;
+                      
+    wr_sosi           : IN    t_dp_sosi;
+    wr_siso           : OUT   t_dp_siso;  
+    
+    flush_ena         : IN    STD_LOGIC;
+                      
+    rd_sosi           : OUT   t_dp_sosi;
+    rd_siso           : IN    t_dp_siso;
+                      
+    rd_clk            : IN    STD_LOGIC;
+    rd_rst            : IN    STD_LOGIC;
+                      
+    rd_data_mosi      : IN    t_mem_mosi := c_mem_mosi_rst;
+    rd_data_miso      : OUT   t_mem_miso := c_mem_miso_rst;   
+    
+    ser_term_ctrl_out : OUT   STD_LOGIC_VECTOR(13 DOWNTO 0);
+    par_term_ctrl_out : OUT   STD_LOGIC_VECTOR(13 DOWNTO 0);
+                      
+    ser_term_ctrl_in  : IN    STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
+    par_term_ctrl_in  : IN    STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
+
+    -- SO-DIMM Memory Bank
+    ddr3_in          : IN    t_tech_ddr3_phy_in;
+    ddr3_io          : INOUT t_tech_ddr3_phy_io;
+    ddr3_ou          : OUT   t_tech_ddr3_phy_ou
+  );
+END seq_ddr3;
+
+
+ARCHITECTURE str OF seq_ddr3 IS
+  
+  CONSTANT c_min_fifo_size    : POSITIVE := 256;
+  CONSTANT c_blocksize        : POSITIVE := g_ddr3_seq.wr_nof_chunks * g_ddr3_seq.wr_chunksize;  
+  CONSTANT c_wr_fifo_depth    : NATURAL  := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size);--c_blocksize * 2;
+  CONSTANT c_rd_fifo_depth    : NATURAL  := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size);--c_blocksize * 2;
+                              
+  SIGNAL i_ctlr_gen_rst       : STD_LOGIC;
+  SIGNAL i_ctlr_gen_clk       : STD_LOGIC;
+  
+  -- ctrl & status DDR3 driver
+  SIGNAL dvr_start_addr       : t_ddr3_addr;
+  SIGNAL dvr_end_addr         : t_ddr3_addr; 
+                              
+  SIGNAL dvr_en               : STD_LOGIC;
+  SIGNAL dvr_wr_not_rd        : STD_LOGIC;
+  SIGNAL dvr_done             : STD_LOGIC;        
+
+  -- DDR3 controller status
+  SIGNAL ctlr_init_done       : STD_LOGIC;    
+  SIGNAL ctlr_rdy             : STD_LOGIC; 
+  SIGNAL init_done_data_start : STD_LOGIC;  
+  
+BEGIN
+
+  ctlr_gen_clk    <= i_ctlr_gen_clk;
+  ctlr_gen_rst    <= i_ctlr_gen_rst;
+
+  u_ddr3: ENTITY work.ddr3
+  GENERIC MAP(
+    g_ddr                     => g_ddr, 
+    g_phy                     => g_phy,
+    g_mts                     => g_mts,
+    g_wr_data_w               => g_data_w,
+    g_wr_use_ctrl             => TRUE,
+    g_wr_fifo_depth           => c_wr_fifo_depth,
+    g_rd_fifo_depth           => c_rd_fifo_depth,
+    g_rd_data_w               => g_data_w,
+    g_flush_wr_fifo           => TRUE,
+    g_flush_sop               => TRUE,
+    g_flush_sop_sync          => TRUE,
+    g_flush_sop_channel       => FALSE,
+    g_flush_sop_start_channel => 0,    
+    g_flush_nof_channels      => 0     
+  )                          
+  PORT MAP (                      
+    ctlr_ref_clk       => ctlr_ref_clk,
+    ctlr_rst           => ctlr_rst,
+
+    phy_in             => ddr3_in,
+    phy_io             => ddr3_io,    
+    phy_ou             => ddr3_ou,  
+
+    ctlr_gen_clk       => i_ctlr_gen_clk,
+    ctlr_gen_rst       => i_ctlr_gen_rst,      
+
+    ctlr_init_done     => ctlr_init_done,
+
+    ctlr_rdy           => ctlr_rdy,
+    dvr_start_addr     => dvr_start_addr,
+    dvr_end_addr       => dvr_end_addr,
+
+    dvr_done           => dvr_done,
+    dvr_wr_not_rd      => dvr_wr_not_rd,
+    dvr_en             => dvr_en,
+    
+    wr_clk             => wr_clk,
+    wr_rst             => wr_rst,
+
+    wr_sosi            => wr_sosi, 
+    wr_siso            => wr_siso,
+    
+    flush_ena          => flush_ena,
+  
+    rd_sosi            => rd_sosi,
+    rd_siso            => rd_siso,
+
+    rd_clk             => rd_clk,
+    rd_rst             => rd_rst,    
+
+    ser_term_ctrl_out  => ser_term_ctrl_out,
+    par_term_ctrl_out  => par_term_ctrl_out,
+
+    ser_term_ctrl_in   => ser_term_ctrl_in, 
+    par_term_ctrl_in   => par_term_ctrl_in, 
+
+    rd_fifo_usedw      => OPEN
+  );
+  
+  init_done_data_start <= ctlr_init_done AND wr_sosi.sync; 
+
+  u_ddr3_sequencer: ENTITY work.ddr3_seq
+  GENERIC MAP(
+    g_ddr      => g_ddr, 
+    g_ddr3_seq => g_ddr3_seq
+  )                      
+  PORT MAP (       
+    dp_rst     => wr_rst,
+    dp_clk     => wr_clk,
+    
+    en_evt     => dvr_en, 
+    wr_not_rd  => dvr_wr_not_rd,
+
+    start_addr => dvr_start_addr,
+    end_addr   => dvr_end_addr,
+
+    done       => dvr_done,
+    init_done  => init_done_data_start,
+    ctlr_rdy   => ctlr_rdy
+  );
+    
+END str;
+