diff --git a/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..bf5fcd921ed889ca348433387b814f265bb68786
--- /dev/null
+++ b/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
@@ -0,0 +1,311 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose:
+-- Provide input ready control and use output ready control to the FIFO.
+-- Pass sop and eop along with the data through the FIFO if g_use_ctrl=TRUE.
+-- Default the RL=1, use g_fifo_rl=0 for a the show ahead FIFO.
+-- Description:
+-- Provide the sink ready for FIFO write control and use source ready for
+-- FIFO read access. The sink ready output is derived from FIFO almost full.
+-- Data without framing can use g_use_ctrl=FALSE to avoid implementing two
+-- data bits for sop and eop in the FIFO word width. Idem for g_use_sync,
+-- g_use_empty, g_use_channel, g_use_error and g_use_aux.
+-- Remark:
+-- . The bsn, empty, channel and error fields are valid at the sop and or eop.
+-- Therefore alternatively these fields can be passed on through a separate
+-- FIFO, with only one entry per frame, to save FIFO memory in case
+-- concatenating them makes the FIFO word width larger than a standard
+-- memory data word width.
+-- . The FIFO makes that the src_in.ready and snk_out.ready are not
+-- combinatorially connected, so this can ease the timing closure for the
+-- ready signal.
+-- . It is assumed all inputs are synchronous (identical control signals).
+-- If the inputs are asynchronous, better use multiple instances of
+-- dp_fifo_core.
+-- . It is possible to use additonal signals to the fifo using in_aux/out_aux.
+
+LIBRARY IEEE, common_lib, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+ENTITY dp_fifo_core_arr IS
+ GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
+ g_nof_streams : NATURAL := 1;
+ g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_use_dual_clock : BOOLEAN := FALSE;
+ g_use_lut_sc : BOOLEAN := FALSE; -- when TRUE then force using LUTs instead of block RAM for single clock FIFO (bot available for dual clock FIFO)
+ g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_data_signed : BOOLEAN := FALSE; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
+ g_bsn_w : NATURAL := 1;
+ g_empty_w : NATURAL := 1;
+ g_channel_w : NATURAL := 1;
+ g_error_w : NATURAL := 1;
+ g_aux_w : NATURAL := 1;
+ g_use_bsn : BOOLEAN := FALSE;
+ g_use_empty : BOOLEAN := FALSE;
+ g_use_channel : BOOLEAN := FALSE;
+ g_use_error : BOOLEAN := FALSE;
+ g_use_sync : BOOLEAN := FALSE;
+ g_use_aux : BOOLEAN := FALSE; -- extra signal in_aux/out_aux
+ g_use_ctrl : BOOLEAN := TRUE; -- sop & eop
+ g_use_complex : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_fifo_size : NATURAL := 512; -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full
+ g_fifo_rl : NATURAL := 1
+ );
+ PORT (
+ wr_rst : IN STD_LOGIC;
+ wr_clk : IN STD_LOGIC;
+ rd_rst : IN STD_LOGIC;
+ rd_clk : IN STD_LOGIC;
+ -- Monitor FIFO filling
+ wr_ful : OUT STD_LOGIC; -- corresponds to the carry bit of wr_usedw when FIFO is full
+ wr_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_fifo_size)-1 DOWNTO 0);
+ rd_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_fifo_size)-1 DOWNTO 0);
+ rd_emp : OUT STD_LOGIC;
+ -- ST sink
+ snk_out_arr : OUT t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+ snk_in_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ in_aux : IN STD_LOGIC_VECTOR(g_aux_w-1 DOWNTO 0) := (OTHERS => '0');
+ -- ST source
+ src_in_arr : IN t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+ src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ out_aux : OUT STD_LOGIC_VECTOR(g_aux_w-1 DOWNTO 0)
+ );
+END dp_fifo_core_arr;
+
+
+ARCHITECTURE str OF dp_fifo_core_arr IS
+
+ CONSTANT c_use_data : BOOLEAN := TRUE;
+ CONSTANT c_total_data_w : NATURAL := g_nof_streams * g_data_w;
+ CONSTANT c_ctrl_w : NATURAL := 2; -- sop and eop
+
+ CONSTANT c_complex_w : NATURAL := smallest(c_dp_stream_dsp_data_w, g_data_w/2); -- needed to cope with g_data_w > 2*c_dp_stream_dsp_data_w
+
+ CONSTANT c_fifo_almost_full : NATURAL := g_fifo_size-g_fifo_af_margin; -- FIFO almost full level for snk_out.ready
+ CONSTANT c_fifo_dat_w : NATURAL := func_slv_concat_w(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux,
+ c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w); -- concat via FIFO
+
+ SIGNAL nxt_snk_out : t_dp_siso := c_dp_siso_rst;
+
+ SIGNAL arst : STD_LOGIC;
+
+ TYPE t_wr_data_complex_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(2*c_complex_w-1 DOWNTO 0);
+ TYPE t_rd_data_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
+
+ SIGNAL wr_data_complex_arr : t_wr_data_complex_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL wr_data : STD_LOGIC_VECTOR(c_total_data_w-1 DOWNTO 0);
+ SIGNAL rd_data : STD_LOGIC_VECTOR(c_total_data_w-1 DOWNTO 0);
+ SIGNAL rd_data_arr : t_rd_data_arr(g_nof_streams-1 DOWNTO 0);
+
+ SIGNAL fifo_wr_dat : STD_LOGIC_VECTOR(c_fifo_dat_w-1 DOWNTO 0);
+ SIGNAL fifo_wr_req : STD_LOGIC;
+ SIGNAL fifo_wr_ful : STD_LOGIC;
+ SIGNAL fifo_wr_usedw : STD_LOGIC_VECTOR(wr_usedw'RANGE);
+
+ SIGNAL fifo_rd_dat : STD_LOGIC_VECTOR(c_fifo_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL fifo_rd_val : STD_LOGIC;
+ SIGNAL fifo_rd_req : STD_LOGIC;
+ SIGNAL fifo_rd_emp : STD_LOGIC;
+ SIGNAL fifo_rd_usedw : STD_LOGIC_VECTOR(rd_usedw'RANGE);
+
+ SIGNAL wr_sync : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL rd_sync : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL wr_ctrl : STD_LOGIC_VECTOR(1 DOWNTO 0);
+ SIGNAL rd_ctrl : STD_LOGIC_VECTOR(1 DOWNTO 0);
+ SIGNAL wr_aux : STD_LOGIC_VECTOR(g_aux_w-1 DOWNTO 0);
+
+ SIGNAL rd_siso_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL rd_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); -- initialize default values for unused sosi fields
+
+ SIGNAL in_aux_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL out_aux_sosi : t_dp_sosi := c_dp_sosi_rst;
+
+BEGIN
+
+ -- Output monitor FIFO filling
+ wr_ful <= fifo_wr_ful;
+ wr_usedw <= fifo_wr_usedw;
+ rd_usedw <= fifo_rd_usedw;
+ rd_emp <= fifo_rd_emp;
+
+ p_wr_clk: PROCESS(wr_clk, wr_rst)
+ BEGIN
+ IF wr_rst='1' THEN
+ snk_out_arr <= (OTHERS => c_dp_siso_rst);
+ ELSIF rising_edge(wr_clk) THEN
+ FOR I IN 0 TO g_nof_streams-1 LOOP
+ snk_out_arr(I) <= nxt_snk_out;
+ END LOOP;
+ END IF;
+ END PROCESS;
+
+ wr_sync(0) <= snk_in_arr(0).sync;
+ wr_ctrl <= snk_in_arr(0).sop & snk_in_arr(0).eop;
+ wr_aux <= in_aux;
+
+ -- Assign the snk_in_arr data field or concatenated complex fields to the FIFO wr_data depending on g_use_complex
+ gen_streams : FOR I IN 0 TO g_nof_streams-1 GENERATE
+ wr_data_complex_arr(I) <= snk_in_arr(I).im(c_complex_w-1 DOWNTO 0) & snk_in_arr(I).re(c_complex_w-1 DOWNTO 0);
+ wr_data((I+1) * g_data_w -1 DOWNTO I * g_data_w) <= snk_in_arr(I).data(g_data_w-1 DOWNTO 0) WHEN g_use_complex = FALSE ELSE RESIZE_UVEC(wr_data_complex_arr(I), g_data_w);
+ END GENERATE;
+ -- fifo wr wires
+ fifo_wr_req <= snk_in_arr(0).valid;
+ fifo_wr_dat <= func_slv_concat(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux,
+ wr_data,
+ snk_in_arr(0).bsn( g_bsn_w-1 DOWNTO 0),
+ snk_in_arr(0).empty( g_empty_w-1 DOWNTO 0),
+ snk_in_arr(0).channel(g_channel_w-1 DOWNTO 0),
+ snk_in_arr(0).err( g_error_w-1 DOWNTO 0),
+ wr_sync,
+ wr_ctrl,
+ wr_aux);
+
+ -- pass on frame level flow control
+ nxt_snk_out.xon <= src_in_arr(0).xon;
+
+ -- up stream use fifo almost full to control snk_out.ready
+ nxt_snk_out.ready <= '1' WHEN UNSIGNED(fifo_wr_usedw)<c_fifo_almost_full ELSE '0';
+
+ gen_common_fifo_sc : IF g_use_dual_clock=FALSE GENERATE
+ u_common_fifo_sc : ENTITY common_lib.common_fifo_sc
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_note_is_ful => g_note_is_ful,
+ g_use_lut => g_use_lut_sc,
+ g_dat_w => c_fifo_dat_w,
+ g_nof_words => g_fifo_size
+ )
+ PORT MAP (
+ rst => rd_rst,
+ clk => rd_clk,
+ wr_dat => fifo_wr_dat,
+ wr_req => fifo_wr_req,
+ wr_ful => fifo_wr_ful,
+ rd_dat => fifo_rd_dat,
+ rd_req => fifo_rd_req,
+ rd_emp => fifo_rd_emp,
+ rd_val => fifo_rd_val,
+ usedw => fifo_rd_usedw
+ );
+
+ fifo_wr_usedw <= fifo_rd_usedw;
+ END GENERATE;
+
+ gen_common_fifo_dc : IF g_use_dual_clock=TRUE GENERATE
+ u_common_fifo_dc : ENTITY common_lib.common_fifo_dc
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_dat_w => c_fifo_dat_w,
+ g_nof_words => g_fifo_size
+ )
+ PORT MAP (
+ rst => arst,
+ wr_clk => wr_clk,
+ wr_dat => fifo_wr_dat,
+ wr_req => fifo_wr_req,
+ wr_ful => fifo_wr_ful,
+ wrusedw => fifo_wr_usedw,
+ rd_clk => rd_clk,
+ rd_dat => fifo_rd_dat,
+ rd_req => fifo_rd_req,
+ rd_emp => fifo_rd_emp,
+ rdusedw => fifo_rd_usedw,
+ rd_val => fifo_rd_val
+ );
+
+ arst <= wr_rst OR rd_rst;
+ END GENERATE;
+
+ -- Extract the data from the wide FIFO output SLV. rd_data will be assigned to rd_sosi.data or rd_sosi.im & rd_sosi.re depending on g_use_complex.
+ rd_data <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux,
+ c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w,
+ fifo_rd_dat, 0);
+
+ -- fifo rd wires
+ -- SISO
+ fifo_rd_req <= rd_siso_arr(0).ready;
+ rd_sync <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 5);
+ rd_ctrl <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 6);
+
+ -- AUX
+ in_aux_sosi.data <= RESIZE_DP_DATA(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 7));
+ in_aux_sosi.valid <= fifo_rd_val;
+ out_aux <= out_aux_sosi.data(g_aux_w-1 DOWNTO 0);
+
+ -- SOSI
+ gen_rd_streams : FOR I IN 0 TO g_nof_streams-1 GENERATE
+ rd_data_arr(I) <= rd_data( (I+1) * g_data_w -1 DOWNTO I * g_data_w);
+ rd_sosi_arr(I).data <= RESIZE_DP_SDATA(rd_data_arr(I)) WHEN g_data_signed=TRUE ELSE RESIZE_DP_DATA(rd_data_arr(I));
+ rd_sosi_arr(I).re <= RESIZE_DP_DSP_DATA(rd_data_arr(I)( c_complex_w-1 DOWNTO 0));
+ rd_sosi_arr(I).im <= RESIZE_DP_DSP_DATA(rd_data_arr(I)(2*c_complex_w-1 DOWNTO c_complex_w));
+ rd_sosi_arr(I).bsn <= RESIZE_DP_BSN(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 1));
+ rd_sosi_arr(I).empty <= RESIZE_DP_EMPTY(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 2));
+ rd_sosi_arr(I).channel <= RESIZE_DP_CHANNEL(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 3));
+ rd_sosi_arr(I).err <= RESIZE_DP_ERROR(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 4));
+ rd_sosi_arr(I).sync <= fifo_rd_val AND rd_sync(0);
+ rd_sosi_arr(I).valid <= fifo_rd_val;
+ rd_sosi_arr(I).sop <= fifo_rd_val AND rd_ctrl(1);
+ rd_sosi_arr(I).eop <= fifo_rd_val AND rd_ctrl(0);
+
+ u_ready_latency : ENTITY work.dp_latency_adapter
+ GENERIC MAP (
+ g_in_latency => 1,
+ g_out_latency => g_fifo_rl
+ )
+ PORT MAP (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- ST sink
+ snk_out => rd_siso_arr(I),
+ snk_in => rd_sosi_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
+ );
+ END GENERATE;
+
+ -- Using extra dp_latency_adapter for aux signal
+ u_ready_latency_aux : ENTITY work.dp_latency_adapter
+ GENERIC MAP (
+ g_in_latency => 1,
+ g_out_latency => g_fifo_rl
+ )
+ PORT MAP (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- ST sink
+ snk_in => in_aux_sosi,
+ -- ST source
+ src_in => src_in_arr(0),
+ src_out => out_aux_sosi
+ );
+
+
+END str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e788c2b57913f8cef7638e3288e83aa7ef55da3c
--- /dev/null
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
@@ -0,0 +1,124 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: DP FIFO array for dual clock (= dc) domain wr and rd.
+-- Description: See dp_fifo_core_arr.vhd.
+
+LIBRARY IEEE,common_lib, technology_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+ENTITY dp_fifo_dc_arr IS
+ GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
+ g_nof_streams : NATURAL := 1;
+ g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_bsn_w : NATURAL := 1;
+ g_empty_w : NATURAL := 1;
+ g_channel_w : NATURAL := 1;
+ g_error_w : NATURAL := 1;
+ g_aux_w : NATURAL := 1;
+ g_use_bsn : BOOLEAN := FALSE;
+ g_use_empty : BOOLEAN := FALSE;
+ g_use_channel : BOOLEAN := FALSE;
+ g_use_error : BOOLEAN := FALSE;
+ g_use_sync : BOOLEAN := FALSE;
+ g_use_aux : BOOLEAN := FALSE;
+ g_use_ctrl : BOOLEAN := TRUE; -- sop & eop
+ g_use_complex : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_fifo_size : NATURAL := 512; -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full
+ g_fifo_rl : NATURAL := 1
+ );
+ PORT (
+ wr_rst : IN STD_LOGIC;
+ wr_clk : IN STD_LOGIC;
+ rd_rst : IN STD_LOGIC;
+ rd_clk : IN STD_LOGIC;
+ -- Monitor FIFO filling
+ wr_ful : OUT STD_LOGIC;
+ wr_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_fifo_size)-1 DOWNTO 0);
+ rd_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_fifo_size)-1 DOWNTO 0);
+ rd_emp : OUT STD_LOGIC;
+ -- ST sink
+ snk_out_arr : OUT t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+ snk_in_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ in_aux : IN STD_LOGIC_VECTOR(g_aux_w-1 DOWNTO 0);
+ -- ST source
+ src_in_arr : IN t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ out_aux : OUT STD_LOGIC_VECTOR(g_aux_w-1 DOWNTO 0)
+ );
+END dp_fifo_dc_arr;
+
+
+ARCHITECTURE str OF dp_fifo_dc_arr IS
+BEGIN
+
+ u_dp_fifo_core_arr : ENTITY work.dp_fifo_core_arr
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_use_dual_clock => TRUE,
+ g_data_w => g_data_w,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_aux_w => g_aux_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_aux => g_use_aux,
+ g_use_ctrl => g_use_ctrl,
+ g_use_complex => g_use_complex,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_rl => g_fifo_rl
+ )
+ PORT MAP (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => wr_usedw,
+ rd_usedw => rd_usedw,
+ rd_emp => rd_emp,
+ -- ST sink
+ snk_out_arr => snk_out_arr,
+ snk_in_arr => snk_in_arr,
+ in_aux => in_aux,
+ -- ST source
+ src_in_arr => src_in_arr,
+ src_out_arr => src_out_arr,
+ out_aux => out_aux
+ );
+
+END str;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..514ebe5def34235e3eab48d0502a83b7c860190d
--- /dev/null
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
@@ -0,0 +1,251 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Test dp_fifo_dc_arr.
+-- Description:
+-- Verifies output data and ctrl signals of DUT. This is configurable using generics.
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+USE work.tb_dp_pkg.ALL;
+
+ENTITY tb_dp_fifo_dc_arr IS
+ GENERIC (
+ -- Try FIFO settings
+ g_dut_nof_streams : NATURAL := 3;
+ g_dut_wr_clk_freq : POSITIVE := 2; -- normalized write clock frequency
+ g_dut_rd_clk_freq : POSITIVE := 3; -- normalized read clock frequency
+ g_dut_use_bsn : BOOLEAN := TRUE;
+ g_dut_use_empty : BOOLEAN := TRUE;
+ g_dut_use_channel : BOOLEAN := TRUE;
+ g_dut_use_sync : BOOLEAN := TRUE;
+ g_dut_use_ctrl : BOOLEAN := TRUE;
+ g_dut_use_aux : BOOLEAN := TRUE;
+ g_dut_out_latency : NATURAL := 1 -- selectable for dp_fifo_dc_arr: default 1 or 0 for look ahead FIFO
+ );
+END tb_dp_fifo_dc_arr;
+
+
+ARCHITECTURE tb OF tb_dp_fifo_dc_arr IS
+
+ -- See tb_dp_pkg.vhd for explanation and run time, increase the run time by g_dut_rd_clk_freq/g_dut_wr_clk_freq if g_dut_rd_clk_freq>g_dut_wr_clk_freq
+
+ -- DUT
+ CONSTANT c_dut_fifo_size : NATURAL := 64;
+ CONSTANT c_dut_in_latency : NATURAL := 1; -- fixed for dp_fifo_dc_arr
+
+ -- Stimuli
+ CONSTANT c_tx_latency : NATURAL := c_dut_in_latency; -- TX ready latency of TB
+ CONSTANT c_tx_void : NATURAL := sel_a_b(c_tx_latency, 1, 0); -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ CONSTANT c_tx_offset_sop : NATURAL := 3;
+ CONSTANT c_tx_period_sop : NATURAL := 7; -- sop in data valid cycle 3, 10, 17, ...
+ CONSTANT c_tx_offset_eop : NATURAL := 5; -- eop in data valid cycle 5, 12, 19, ...
+ CONSTANT c_tx_period_eop : NATURAL := c_tx_period_sop;
+ CONSTANT c_tx_offset_sync : NATURAL := 3; -- sync in data valid cycle 3, 20, 37, ...
+ CONSTANT c_tx_period_sync : NATURAL := 17;
+ CONSTANT c_rx_latency : NATURAL := g_dut_out_latency; -- RX ready latency from DUT
+ CONSTANT c_verify_en_wait : NATURAL := 20; -- wait some cycles before asserting verify enable
+
+ CONSTANT c_bsn_offset : NATURAL := 1;
+ CONSTANT c_empty_offset : NATURAL := 2;
+ CONSTANT c_channel_offset : NATURAL := 3;
+
+ CONSTANT c_random_w : NATURAL := 19;
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL wr_clk : STD_LOGIC := '0';
+ SIGNAL rd_clk : STD_LOGIC := '0';
+ SIGNAL rst : STD_LOGIC;
+ SIGNAL sync : STD_LOGIC;
+ SIGNAL lfsr1 : STD_LOGIC_VECTOR(c_random_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL lfsr2 : STD_LOGIC_VECTOR(c_random_w DOWNTO 0) := (OTHERS=>'0');
+
+ SIGNAL cnt_dat : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0);
+ SIGNAL cnt_val : STD_LOGIC;
+ SIGNAL cnt_en : STD_LOGIC;
+
+ SIGNAL tx_data : t_dp_data_arr(0 TO c_tx_latency + c_tx_void) := (OTHERS=>(OTHERS=>'0'));
+ SIGNAL tx_val : STD_LOGIC_VECTOR(0 TO c_tx_latency + c_tx_void) := (OTHERS=>'0');
+
+ SIGNAL in_ready : STD_LOGIC;
+ SIGNAL in_data : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL in_bsn : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL in_empty : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL in_channel : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL in_sync : STD_LOGIC;
+ SIGNAL in_val : STD_LOGIC;
+ SIGNAL in_sop : STD_LOGIC;
+ SIGNAL in_eop : STD_LOGIC;
+ SIGNAL in_aux : STD_LOGIC;
+
+ SIGNAL in_siso_arr : t_dp_siso_arr(g_dut_nof_streams-1 DOWNTO 0);
+ SIGNAL in_sosi_arr : t_dp_sosi_arr(g_dut_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL out_siso_arr : t_dp_siso_arr(g_dut_nof_streams-1 DOWNTO 0);
+ SIGNAL out_sosi_arr : t_dp_sosi_arr(g_dut_nof_streams-1 DOWNTO 0);
+
+ SIGNAL out_ready : STD_LOGIC;
+ SIGNAL prev_out_ready : STD_LOGIC_VECTOR(0 TO c_rx_latency);
+ SIGNAL out_data : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0);
+ SIGNAL out_bsn : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL out_empty : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL out_channel : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL out_sync : STD_LOGIC;
+ SIGNAL out_val : STD_LOGIC;
+ SIGNAL out_sop : STD_LOGIC;
+ SIGNAL out_eop : STD_LOGIC;
+ SIGNAL out_aux : STD_LOGIC;
+ SIGNAL prev_out_data : STD_LOGIC_VECTOR(out_data'RANGE);
+
+ SIGNAL state : t_dp_state_enum;
+
+ SIGNAL verify_en : STD_LOGIC;
+ SIGNAL verify_done : STD_LOGIC;
+
+ SIGNAL exp_data : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := TO_UVEC(19000/g_dut_wr_clk_freq, c_dp_data_w);
+
+ SIGNAL usedw : STD_LOGIC_VECTOR(ceil_log2(c_dut_fifo_size)-1 DOWNTO 0);
+
+BEGIN
+
+ wr_clk <= NOT wr_clk OR tb_end AFTER g_dut_rd_clk_freq*clk_period/2;
+ rd_clk <= NOT rd_clk OR tb_end AFTER g_dut_wr_clk_freq*clk_period/2;
+ rst <= '1', '0' AFTER clk_period*7;
+
+ -- Sync interval
+ proc_dp_sync_interval(wr_clk, sync);
+
+ -- Input data
+ cnt_val <= in_ready AND cnt_en;
+
+ proc_dp_cnt_dat(rst, wr_clk, cnt_val, cnt_dat);
+ proc_dp_tx_data(c_tx_latency, rst, wr_clk, cnt_val, cnt_dat, tx_data, tx_val, in_data, in_val);
+ proc_dp_tx_ctrl(c_tx_offset_sync, c_tx_period_sync, in_data, in_val, in_sync);
+ proc_dp_tx_ctrl(c_tx_offset_sop, c_tx_period_sop, in_data, in_val, in_sop);
+ proc_dp_tx_ctrl(c_tx_offset_eop, c_tx_period_eop, in_data, in_val, in_eop);
+
+ in_bsn <= INCR_UVEC(in_data, c_bsn_offset);
+ in_empty <= INCR_UVEC(in_data, c_empty_offset);
+ in_channel <= INCR_UVEC(in_data, c_channel_offset);
+
+ -- Stimuli control
+ proc_dp_count_en(rst, wr_clk, sync, lfsr1, state, verify_done, tb_end, cnt_en);
+ proc_dp_out_ready(rst, wr_clk, sync, lfsr2, out_ready);
+
+ -- Output verify
+ proc_dp_verify_en(c_verify_en_wait, rst, rd_clk, sync, verify_en);
+ proc_dp_verify_data("out_sosi.data", c_rx_latency, rd_clk, verify_en, out_ready, out_val, out_data, prev_out_data);
+ proc_dp_verify_valid(c_rx_latency, rd_clk, verify_en, out_ready, prev_out_ready, out_val);
+
+ gen_verify_sync : IF g_dut_use_sync=TRUE GENERATE
+ proc_dp_verify_ctrl(c_tx_offset_sync, c_tx_period_sync, "sync", rd_clk, verify_en, out_data, out_val, out_sync);
+ END GENERATE;
+
+ gen_verify_aux : IF g_dut_use_aux=TRUE GENERATE
+ proc_dp_verify_ctrl(c_tx_offset_sync, c_tx_period_sync, "aux", rd_clk, verify_en, out_data, out_val, out_aux);
+ END GENERATE;
+
+ gen_verify_ctrl : IF g_dut_use_ctrl=TRUE GENERATE
+ proc_dp_verify_ctrl(c_tx_offset_sop, c_tx_period_sop, "sop", rd_clk, verify_en, out_data, out_val, out_sop);
+ proc_dp_verify_ctrl(c_tx_offset_eop, c_tx_period_eop, "eop", rd_clk, verify_en, out_data, out_val, out_eop);
+ END GENERATE;
+
+ gen_verify_bsn : IF g_dut_use_bsn=TRUE GENERATE
+ proc_dp_verify_other_sosi("bsn", INCR_UVEC(out_data, c_bsn_offset), rd_clk, verify_en, out_bsn);
+ END GENERATE;
+
+ gen_verify_empty : IF g_dut_use_empty=TRUE GENERATE
+ proc_dp_verify_other_sosi("empty", INCR_UVEC(out_data, c_empty_offset), rd_clk, verify_en, out_empty);
+ END GENERATE;
+
+ gen_verify_channel : IF g_dut_use_channel=TRUE GENERATE
+ proc_dp_verify_other_sosi("channel", INCR_UVEC(out_data, c_channel_offset), rd_clk, verify_en, out_channel);
+ END GENERATE;
+
+ -- Check that the test has ran at all
+ proc_dp_verify_value(e_at_least, rd_clk, verify_done, exp_data, out_data);
+
+ ------------------------------------------------------------------------------
+ -- DUT dp_fifo_dc_arr
+ ------------------------------------------------------------------------------
+
+ -- map sl, slv to record
+ in_ready <= in_siso_arr(0).ready; -- SISO
+ in_aux <= in_sync; -- use sync to test aux data
+ gen_streams : FOR I IN 0 TO g_dut_nof_streams -1 GENERATE
+ in_sosi_arr(I).data(c_dp_data_w-1 DOWNTO 0) <= in_data; -- SOSI
+ in_sosi_arr(I).bsn(c_dp_bsn_w-1 DOWNTO 0) <= in_bsn(c_dp_bsn_w-1 DOWNTO 0);
+ in_sosi_arr(I).empty <= in_empty(c_dp_empty_w-1 DOWNTO 0);
+ in_sosi_arr(I).channel <= in_channel(c_dp_channel_w-1 DOWNTO 0);
+ in_sosi_arr(I).sync <= in_sync;
+ in_sosi_arr(I).valid <= in_val;
+ in_sosi_arr(I).sop <= in_sop;
+ in_sosi_arr(I).eop <= in_eop;
+ out_siso_arr(I).ready <= out_ready; -- SISO
+ END GENERATE;
+ out_data <= out_sosi_arr(0).data(c_dp_data_w-1 DOWNTO 0); -- SOSI
+ out_bsn(c_dp_bsn_w-1 DOWNTO 0) <= out_sosi_arr(0).bsn(c_dp_bsn_w-1 DOWNTO 0);
+ out_empty(c_dp_empty_w-1 DOWNTO 0) <= out_sosi_arr(0).empty;
+ out_channel(c_dp_channel_w-1 DOWNTO 0) <= out_sosi_arr(0).channel;
+ out_sync <= out_sosi_arr(0).sync;
+ out_val <= out_sosi_arr(0).valid;
+ out_sop <= out_sosi_arr(0).sop;
+ out_eop <= out_sosi_arr(0).eop;
+
+ dut : ENTITY work.dp_fifo_dc_arr
+ GENERIC MAP (
+ g_nof_streams => g_dut_nof_streams,
+ g_data_w => c_dp_data_w,
+ g_bsn_w => c_dp_bsn_w,
+ g_empty_w => c_dp_empty_w,
+ g_channel_w => c_dp_channel_w,
+ g_error_w => 1,
+ g_aux_w => 1,
+ g_use_bsn => g_dut_use_bsn,
+ g_use_empty => g_dut_use_empty,
+ g_use_channel => g_dut_use_channel,
+ g_use_error => FALSE,
+ g_use_sync => g_dut_use_sync,
+ g_use_aux => g_dut_use_aux,
+ g_use_ctrl => g_dut_use_ctrl,
+ g_fifo_size => c_dut_fifo_size,
+ g_fifo_rl => g_dut_out_latency
+ )
+ PORT MAP (
+ wr_rst => rst,
+ wr_clk => wr_clk,
+ rd_rst => rst,
+ rd_clk => rd_clk,
+ snk_out_arr => in_siso_arr, -- OUT = request to upstream ST source
+ snk_in_arr => in_sosi_arr,
+ in_aux(0) => in_aux,
+ wr_usedw => usedw,
+ rd_usedw => OPEN,
+ src_in_arr => out_siso_arr, -- IN = request from downstream ST sink
+ src_out_arr => out_sosi_arr,
+ out_aux(0) => out_aux
+ );
+
+END tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a5a8429a8e0cefa5eae73755b8df3b083df2b55b
--- /dev/null
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd
@@ -0,0 +1,67 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Test multiple instances of tb_dp_fifo_dc_arr.
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+
+ENTITY tb_tb_dp_fifo_dc_arr IS
+END tb_tb_dp_fifo_dc_arr;
+
+
+ARCHITECTURE tb OF tb_tb_dp_fifo_dc_arr IS
+ SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+BEGIN
+
+ -- > as 10
+ -- > run g_dut_rd_clk_freq * 330 us --> OK
+
+ -- Try FIFO settings : GENERIC MAP (g_dut_wr_clk_freq, g_dut_rd_clk_freq, g_dut_use_bsn, g_dut_use_empty, g_dut_use_channel, g_dut_use_sync, g_dut_use_ctrl, g_dut_out_latency)
+
+ u_use_all_rl_0 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 0);
+ u_use_all_rl_0_clk_2_1 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 2, 1, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 0);
+ u_use_all_rl_0_clk_1_2 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 2, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 0);
+ u_use_all_rl_0_clk_3_2 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 3, 2, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 0);
+ u_use_all_rl_0_clk_2_3 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 2, 3, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 0);
+
+ u_use_all : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (1, 1, 1, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 1);
+ u_use_all_clk_3_1 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 3, 1, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 1);
+ u_use_all_clk_1_3 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 3, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 1);
+
+ u_use_ctrl_rl_0 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (1, 1, 1, FALSE, FALSE, FALSE, FALSE, TRUE, TRUE, 0);
+ u_use_ctrl_rl_0_clk_1_3 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 3, FALSE, FALSE, FALSE, FALSE, TRUE, TRUE, 0);
+ u_use_ctrl_rl_0_clk_3_1 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 3, 1, FALSE, FALSE, FALSE, FALSE, TRUE, TRUE, 0);
+ u_use_ctrl : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, FALSE, FALSE, FALSE, FALSE, TRUE, TRUE, 1);
+ u_use_ctrl_clk_1_2 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 2, FALSE, FALSE, FALSE, FALSE, TRUE, TRUE, 1);
+ u_use_ctrl_clk_2_1 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 2, 1, FALSE, FALSE, FALSE, FALSE, TRUE, TRUE, 1);
+
+ u_no_bsn : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, FALSE, TRUE, TRUE, TRUE, TRUE, TRUE, 1);
+ u_no_empty : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, TRUE, FALSE, TRUE, TRUE, TRUE, TRUE, 1);
+ u_no_channel : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, TRUE, TRUE, FALSE, TRUE, TRUE, TRUE, 1);
+ u_no_sync : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, TRUE, TRUE, TRUE, FALSE, TRUE, TRUE, 1);
+ u_no_ctrl : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, TRUE, TRUE, TRUE, TRUE, FALSE, TRUE, 1);
+ u_no_aux : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, 1);
+
+END tb;