From 314010b7d6fec304d4a67e3ab11bc4f8ce9bdfd9 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Tue, 31 May 2022 08:40:13 +0200
Subject: [PATCH] Verify jesd204b_rddata.
---
.../technology/jesd204b/tb_tech_jesd204b.vhd | 37 ++++++++++++++++---
1 file changed, 31 insertions(+), 6 deletions(-)
diff --git a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
index 8653d132d7..2b39695384 100644
--- a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
+++ b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
@@ -39,15 +39,18 @@ USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE work.tech_jesd204b_component_pkg.ALL;
+USE work.tech_jesd204b_pkg.ALL;
ENTITY tb_tech_jesd204b IS
END tb_tech_jesd204b;
ARCHITECTURE tb OF tb_tech_jesd204b IS
- CONSTANT c_sim : BOOLEAN := TRUE;
+ -- FALSE is use mm_clk in JESD IP, TRUE is use rxlink_clk as mm_clk in JESD IP
+ CONSTANT c_sim : BOOLEAN := FALSE; -- use FALSE as on HW, to verify jesd204b_rddata
CONSTANT c_jesd204b_sampclk_period : TIME := 5 ns;
CONSTANT c_bondingclk_period : TIME := 10 ns;
@@ -108,7 +111,7 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
SIGNAL bonding_clock_5 : STD_LOGIC := '0';
SIGNAL pll_locked : STD_LOGIC_VECTOR(0 downto 0);
- CONSTANT c_mm_clk_period : TIME := 20 ns;
+ CONSTANT c_mm_clk_period : TIME := 20 ns;
SIGNAL mm_clk : STD_LOGIC := '0';
-- Tb
@@ -120,7 +123,8 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
-- JESD
SIGNAL jesd204b_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL jesd204b_miso : t_mem_miso := c_mem_miso_rst;
-
+ SIGNAL jesd204b_rddata : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
-- serial transceivers
SIGNAL serial_tx : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
SIGNAL bck_rx : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 downto 0) := (others => '0');
@@ -168,7 +172,6 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
BEGIN
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -178,7 +181,6 @@ BEGIN
jesd204b_disable_arr <= (OTHERS => '0');
-
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
@@ -193,7 +195,6 @@ BEGIN
jesd204b_sysref => jesd204b_sysref_fpga,
jesd204b_sync_n_arr => jesd204b_sync_n_fpga,
-
jesd204b_disable_arr => jesd204b_disable_arr,
rx_sosi_arr => rx_sosi_arr,
@@ -213,7 +214,31 @@ BEGIN
serial_rx_arr => bck_rx(c_nof_streams_jesd204b-1 downto 0)
);
+ p_monitor_jesd204b : PROCESS
+ BEGIN
+ WAIT UNTIL sim_done = '1';
+ proc_common_wait_some_cycles(mm_clk, 1); -- align with mm_clk domain
+
+ proc_mem_mm_bus_rd(tech_jesd204b_field_rx_err_enable_adr, mm_clk, jesd204b_miso, jesd204b_mosi);
+ proc_common_wait_some_cycles(mm_clk, 1);
+ ASSERT UNSIGNED(jesd204b_rddata) = tech_jesd204b_field_rx_err_enable_reset
+ REPORT "Wrong rx_err_enable_reset: " & INTEGER'IMAGE(TO_SINT(jesd204b_rddata)) & " /= " & INTEGER'IMAGE(tech_jesd204b_field_rx_err_enable_reset) SEVERITY ERROR;
+
+ proc_mem_mm_bus_rd(tech_jesd204b_field_rx_err_link_reinit_adr, mm_clk, jesd204b_miso, jesd204b_mosi);
+ proc_common_wait_some_cycles(mm_clk, 1);
+ ASSERT UNSIGNED(jesd204b_rddata) = tech_jesd204b_field_rx_err_link_reinit_reset
+ REPORT "Wrong rx_err_link_reinit_reset: " & INTEGER'IMAGE(TO_SINT(jesd204b_rddata)) & " /= " & INTEGER'IMAGE(tech_jesd204b_field_rx_err_link_reinit_reset) SEVERITY ERROR;
+
+ proc_mem_mm_bus_rd(tech_jesd204b_field_rx_syncn_sysref_ctrl_adr, mm_clk, jesd204b_miso, jesd204b_mosi);
+
+ proc_mem_mm_bus_rd(tech_jesd204b_field_rx_err0_adr, mm_clk, jesd204b_miso, jesd204b_mosi);
+ proc_mem_mm_bus_rd(tech_jesd204b_field_rx_err1_adr, mm_clk, jesd204b_miso, jesd204b_mosi);
+ proc_mem_mm_bus_rd(tech_jesd204b_field_csr_rbd_count_adr, mm_clk, jesd204b_miso, jesd204b_mosi);
+ proc_mem_mm_bus_rd(tech_jesd204b_field_csr_dev_syncn_adr, mm_clk, jesd204b_miso, jesd204b_mosi);
+ WAIT;
+ END PROCESS;
+ jesd204b_rddata <= jesd204b_miso.rddata(c_word_w-1 DOWNTO 0);
-----------------------------------------------------------------------------
-- Transport
--
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