diff --git a/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd
index 6642ee4df41cdbdb0bbb7cd4456700fb1f0e4e61..f022f32169652eeecb5661f949fc8de2286cc7be 100644
--- a/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd
@@ -28,7 +28,7 @@
 --   > load simulation configuration: tb_unb_ddr3
 --   > run -all 
 
-LIBRARY IEEE, common_lib, dp_lib, unb_common_lib, diag_lib, aduh_lib, ddr3_lib;
+LIBRARY IEEE, common_lib, dp_lib, unb1_board_lib, diag_lib, tech_ddr_lib, technology_lib;
 USE IEEE.std_logic_1164.ALL;
 USE IEEE.numeric_std.ALL;
 USE IEEE.MATH_REAL.ALL;
@@ -36,31 +36,36 @@ USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE common_lib.tb_common_pkg.ALL;
 USE common_lib.tb_common_mem_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_mem_model_component_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 USE diag_lib.diag_pkg.ALL;
-USE aduh_lib.aduh_dd_pkg.ALL;
-USE unb_common_lib.unb_common_pkg.ALL;
-USE ddr3_lib.ddr3_pkg.ALL;
 
-ENTITY tb_unb_ddr3 IS
-END tb_unb_ddr3;
 
-ARCHITECTURE tb OF tb_unb_ddr3 IS
+ENTITY tb_unb1_ddr3 IS
+  GENERIC (
+    g_design_name : STRING  := "unb1_reorder";
+    g_sim_unb_nr  : NATURAL := 0; -- UniBoard 0
+    g_sim_node_nr : NATURAL := 7  -- Back node 3
+  );
+END tb_unb1_ddr3;
+
+ARCHITECTURE tb OF tb_unb1_ddr3 IS
 
   -- UniBoard
   CONSTANT c_sim             : BOOLEAN := TRUE;
   CONSTANT c_unb_nr          : NATURAL := 0; -- UniBoard 0
   CONSTANT c_node_nr         : NATURAL := 3; -- Front node 3
+  CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(g_sim_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(g_sim_node_nr, c_unb1_board_nof_chip_w);
 
   CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
-  CONSTANT c_fw_version      : t_unb_fw_version := (1, 0);   
-
-  CONSTANT c_ddr             : t_c_ddr3_phy := c_ddr3_phy_4g;
-  CONSTANT c_mts             : NATURAL := 800;
+  CONSTANT c_fw_version      : t_unb1_board_fw_version := (1, 0);
   
-  CONSTANT c_nof_MB          : NATURAL := 2;
-  CONSTANT c_use_MB_I        : NATURAL := 1;
-  CONSTANT c_use_MB_II       : NATURAL := 1;
+  CONSTANT c_ddr             : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
+
   CONSTANT c_st_dat_w        : NATURAL := 64; -- Any power of two 8..256
   
   CONSTANT c_cable_delay     : TIME := 12 ns;
@@ -69,15 +74,10 @@ ARCHITECTURE tb OF tb_unb_ddr3 IS
   CONSTANT c_pps_period      : NATURAL := 1000; 
   
    -- SO-DIMM Memory Bank I = ddr3_I
-  SIGNAL MB_I_in             : t_ddr3_phy_in_arr(sel_a_b(c_sim, 1, c_use_MB_I) -1 DOWNTO 0);
-  SIGNAL MB_I_io             : t_ddr3_phy_io_arr(sel_a_b(c_sim, 1, c_use_MB_I) -1 DOWNTO 0);
-  SIGNAL MB_I_ou             : t_ddr3_phy_ou_arr(sel_a_b(c_sim, 1, c_use_MB_I) -1 DOWNTO 0);
+  SIGNAL MB_I_in             : t_tech_ddr3_phy_in;
+  SIGNAL MB_I_io             : t_tech_ddr3_phy_io;
+  SIGNAL MB_I_ou             : t_tech_ddr3_phy_ou;
 
-    -- SO-DIMM Memory Bank II = ddr3_II
-  SIGNAL MB_II_in            : t_ddr3_phy_in_arr(sel_a_b(c_sim, 1, c_use_MB_II) -1 DOWNTO 0);
-  SIGNAL MB_II_io            : t_ddr3_phy_io_arr(sel_a_b(c_sim, 1, c_use_MB_II) -1 DOWNTO 0);
-  SIGNAL MB_II_ou            : t_ddr3_phy_ou_arr(sel_a_b(c_sim, 1, c_use_MB_II) -1 DOWNTO 0);
-    
   -- DUT  
   SIGNAL clk                 : STD_LOGIC := '0';
   SIGNAL pps                 : STD_LOGIC := '0';
@@ -91,9 +91,9 @@ ARCHITECTURE tb OF tb_unb_ddr3 IS
   SIGNAL eth_txp             : STD_LOGIC;
   SIGNAL eth_rxp             : STD_LOGIC;
 
-  SIGNAL VERSION             : STD_LOGIC_VECTOR(c_unb_aux.version_w-1 DOWNTO 0);
-  SIGNAL ID                  : STD_LOGIC_VECTOR(c_unb_aux.id_w-1 DOWNTO 0); 
-  SIGNAL TESTIO              : STD_LOGIC_VECTOR(c_unb_aux.testio_w-1 DOWNTO 0);
+  SIGNAL VERSION             : STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0) := c_version; 
+  SIGNAL ID                  : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0)      := c_id;
+  SIGNAL TESTIO              : STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
   
   SIGNAL sens_scl            : STD_LOGIC;
   SIGNAL sens_sda            : STD_LOGIC;     
@@ -135,17 +135,12 @@ BEGIN
   -- DUT
   ------------------------------------------------------------------------------
   
-  dut : ENTITY work.unb_ddr3
+  dut : ENTITY work.unb1_ddr3
   GENERIC MAP (
     g_sim           => c_sim,     
     g_sim_unb_nr    => c_unb_nr, 
     g_sim_node_nr   => c_node_nr,
     -- Stamps are passed via QIP at compile start if $UNB_COMPILE_STAMPS is set
-    g_nof_MB        => c_nof_MB,   
-    g_use_MB_I      => c_use_MB_I, 
-    g_use_MB_II     => c_use_MB_II,
-    g_ddr           => c_ddr,
-    g_mts           => c_mts,
     g_st_dat_w      => c_st_dat_w
 
   )
@@ -173,135 +168,28 @@ BEGIN
     -- SO-DIMM Memory Bank I = ddr3_I
     MB_I_IN     => MB_I_in,
     MB_I_IO     => MB_I_io,
-    MB_I_OU     => MB_I_ou,
-
-    -- SO-DIMM Memory Bank II = ddr3_II
-    MB_II_IN    => MB_II_in,
-    MB_II_IO    => MB_II_io,
-    MB_II_OU    => MB_II_ou    
+    MB_I_OU     => MB_I_ou
    );
-    
-  gen_MB_I : IF c_use_MB_I = 1 GENERATE
 
-    MB_I_io(0).scl <= 'H';
-    MB_I_io(0).sda <= 'H';
-    
-    MB_I_in(0).evt <= '0';
-    MB_I_in(0).oct_rup <= 'X';
-    MB_I_in(0).oct_rdn <= 'X';
-    
-    u_4gb_800_ddr3_model : COMPONENT alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
-		GENERIC MAP (
-			MEM_IF_ADDR_WIDTH            => 15,
-			MEM_IF_ROW_ADDR_WIDTH        => 15,
-			MEM_IF_COL_ADDR_WIDTH        => 10,
-			MEM_IF_CS_PER_RANK           => 1,
-			MEM_IF_CONTROL_WIDTH         => 1,
-			MEM_IF_DQS_WIDTH             => 8,
-			MEM_IF_CS_WIDTH              => 2,
-			MEM_IF_BANKADDR_WIDTH        => 3,
-			MEM_IF_DQ_WIDTH              => 64,
-			MEM_IF_CK_WIDTH              => 2,
-			MEM_IF_CLK_EN_WIDTH          => 2,
-			DEVICE_WIDTH                 => 1,
-			MEM_TRCD                     => 6,
-			MEM_TRTP                     => 3,
-			MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
-			MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
-			MEM_IF_ODT_WIDTH             => 2,
-			MEM_MIRROR_ADDRESSING_DEC    => 0,
-			MEM_REGDIMM_ENABLED          => false,
-			DEVICE_DEPTH                 => 1,
-			MEM_GUARANTEED_WRITE_INIT    => false,
-			MEM_VERBOSE                  => true,
-			MEM_INIT_EN                  => false,
-			MEM_INIT_FILE                => "",
-			DAT_DATA_WIDTH               => 32
-		)
-		PORT MAP (
-			mem_a       => MB_I_OU(0).a(c_ddr.a_w-1 DOWNTO 0),      
-			mem_ba      => MB_I_OU(0).ba,       
-			mem_ck      => MB_I_IO(0).clk,      
-			mem_ck_n    => MB_I_IO(0).clk_n,    
-			mem_cke     => MB_I_OU(0).cke(c_ddr.cs_w-1 DOWNTO 0),   
-			mem_cs_n    => MB_I_OU(0).cs_n(c_ddr.cs_w-1 DOWNTO 0),  
-			mem_dm      => MB_I_OU(0).dm,       
-			mem_ras_n   => ras_I_n,           
-			mem_cas_n   => cas_I_n,           
-			mem_we_n    => we_I_n,            
-			mem_reset_n => MB_I_OU(0).reset_n, 
-			mem_dq      => MB_I_IO(0).dq,       
-			mem_dqs     => MB_I_IO(0).dqs,      
-			mem_dqs_n   => MB_I_IO(0).dqs_n,    
-			mem_odt     => MB_I_OU(0).odt       
-		);               
-		
-		ras_I_n(0) <= MB_I_OU(0).ras_n;
-		cas_I_n(0) <= MB_I_OU(0).cas_n;
-		we_I_n(0)  <= MB_I_OU(0).we_n;
+  MB_I_io.scl <= 'H';
+  MB_I_io.sda <= 'H';
+  
+  MB_I_in.evt <= '0';
+  MB_I_in.oct_rup <= 'X';
+  MB_I_in.oct_rdn <= 'X';
 
-  END GENERATE;
+  ------------------------------------------------------------------------------
+  -- DDR3 memory model
+  ------------------------------------------------------------------------------
+  u_tech_ddr_memory_model : ENTITY tech_ddr_lib.tech_ddr_memory_model
+  GENERIC MAP (
+    g_tech_ddr => c_ddr
+  )
+  PORT MAP (
+    mem3_in => MB_I_ou,
+    mem3_io => MB_I_io,
+    mem3_ou => MB_I_in
+  );
  
-  gen_MB_II : IF c_use_MB_II = 1 GENERATE
-
-    MB_II_io(0).scl <= 'H';
-    MB_II_io(0).sda <= 'H';
-    
-    MB_II_in(0).evt <= '0';
-    MB_II_in(0).oct_rup <= 'X';
-    MB_II_in(0).oct_rdn <= 'X';
-    
-    u_4gb_800_ddr3_model : COMPONENT alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
-		GENERIC MAP (
-			MEM_IF_ADDR_WIDTH            => 15,
-			MEM_IF_ROW_ADDR_WIDTH        => 15,
-			MEM_IF_COL_ADDR_WIDTH        => 10,
-			MEM_IF_CS_PER_RANK           => 1,
-			MEM_IF_CONTROL_WIDTH         => 1,
-			MEM_IF_DQS_WIDTH             => 8,
-			MEM_IF_CS_WIDTH              => 2,
-			MEM_IF_BANKADDR_WIDTH        => 3,
-			MEM_IF_DQ_WIDTH              => 64,
-			MEM_IF_CK_WIDTH              => 2,
-			MEM_IF_CLK_EN_WIDTH          => 2,
-			DEVICE_WIDTH                 => 1,
-			MEM_TRCD                     => 6,
-			MEM_TRTP                     => 3,
-			MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
-			MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
-			MEM_IF_ODT_WIDTH             => 2,
-			MEM_MIRROR_ADDRESSING_DEC    => 0,
-			MEM_REGDIMM_ENABLED          => false,
-			DEVICE_DEPTH                 => 1,
-			MEM_GUARANTEED_WRITE_INIT    => false,
-			MEM_VERBOSE                  => true,
-			MEM_INIT_EN                  => false,
-			MEM_INIT_FILE                => "",
-			DAT_DATA_WIDTH               => 32
-		)
-		PORT MAP (
-			mem_a       => MB_II_OU(0).a(c_ddr.a_w-1 DOWNTO 0),      
-			mem_ba      => MB_II_OU(0).ba,       
-			mem_ck      => MB_II_IO(0).clk,      
-			mem_ck_n    => MB_II_IO(0).clk_n,    
-			mem_cke     => MB_II_OU(0).cke(c_ddr.cs_w-1 DOWNTO 0),   
-			mem_cs_n    => MB_II_OU(0).cs_n(c_ddr.cs_w-1 DOWNTO 0),  
-			mem_dm      => MB_II_OU(0).dm,       
-			mem_ras_n   => ras_II_n,           
-			mem_cas_n   => cas_II_n,           
-			mem_we_n    => we_II_n,            
-			mem_reset_n => MB_II_OU(0).reset_n, 
-			mem_dq      => MB_II_IO(0).dq,       
-			mem_dqs     => MB_II_IO(0).dqs,      
-			mem_dqs_n   => MB_II_IO(0).dqs_n,    
-			mem_odt     => MB_II_OU(0).odt       
-		);               
-		
-		ras_II_n(0) <= MB_II_OU(0).ras_n;
-		cas_II_n(0) <= MB_II_OU(0).cas_n;
-		we_II_n(0)  <= MB_II_OU(0).we_n;
-
-  END GENERATE;
-
 END tb;