diff --git a/libraries/technology/ddr/tech_ddr_mem_model.vhd b/libraries/technology/ddr/tech_ddr_mem_model.vhd
index 546849e8a81045ec8f1235595a7b555804a886e9..aad4c64ca3db3c5ae139f66f2d915f7691f9fe4d 100644
--- a/libraries/technology/ddr/tech_ddr_mem_model.vhd
+++ b/libraries/technology/ddr/tech_ddr_mem_model.vhd
@@ -27,6 +27,7 @@
-- Declare IP libraries to ensure default binding in simulation.
LIBRARY ip_stratixiv_ddr3_mem_model_lib;
+LIBRARY ed_sim_altera_emif_mem_model_core_ddr4_141;
LIBRARY IEEE, common_lib;
@@ -42,14 +43,19 @@ ENTITY tech_ddr_memory_model IS
PORT (
-- PHY interface
mem_in : IN t_tech_ddr_phy_ou;
- mem_io : INOUT t_tech_ddr_phy_io
+ mem_io : INOUT t_tech_ddr_phy_io;
+ mem_ou : OUT t_tech_ddr_phy_in
);
END tech_ddr_memory_model;
ARCHITECTURE str OF tech_ddr_memory_model IS
+ CONSTANT c_gigabytes : NATURAL := func_tech_ddr_module_size(g_tech_ddr);
+ SIGNAL dbg_g_tech_ddr : t_c_tech_ddr := g_tech_ddr;
+ SIGNAL dbg_c_gigabytes : NATURAL := c_gigabytes;
+
BEGIN
gen_ip_stratixiv_ddr_memory_model : IF g_tech_ddr.name="DDR3" GENERATE
@@ -100,5 +106,27 @@ BEGIN
);
END GENERATE;
+ gen_ip_arria10_ddr_memory_model : IF g_tech_ddr.name="DDR4" AND c_gigabytes=4 GENERATE
+ u_ip_arria10_ddr_memory_model : ed_sim_altera_emif_mem_model_141_z3tvrmq
+ PORT MAP (
+ mem_ck => mem_in.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- mem_conduit_end.mem_ck
+ mem_ck_n => mem_in.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck_n
+ mem_a => mem_in.a(g_tech_ddr.a_w-1 DOWNTO 0), -- .mem_a
+ mem_act_n => slv(mem_in.act_n), -- .mem_act_n
+ mem_ba => mem_in.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba
+ mem_bg => mem_in.bg(g_tech_ddr.bg_w-1 DOWNTO 0), -- .mem_bg
+ mem_cke => mem_in.cke(g_tech_ddr.cke_w-1 DOWNTO 0), -- .mem_cke
+ mem_cs_n => mem_in.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
+ mem_odt => mem_in.odt(g_tech_ddr.odt_w-1 DOWNTO 0), -- .mem_odt
+ mem_reset_n => slv(mem_in.reset_n), -- .mem_reset_n
+ mem_par => slv(mem_in.par), -- .mem_par
+ sl(mem_alert_n) => mem_ou.alert_n, -- .mem_alert_n
+ mem_dqs => mem_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs
+ mem_dqs_n => mem_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
+ mem_dq => mem_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq
+ mem_dbi_n => mem_io.dbi_n(g_tech_ddr.dbi_w-1 DOWNTO 0) -- .mem_dbi_n
+ );
+ END GENERATE;
+
END str;
diff --git a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
index e61e0e142e7098bcc99e482e6b11bfc60252fe95..a715eed9a500e4b774924d50ca00325ad21a30a9 100644
--- a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
@@ -81,6 +81,34 @@ PACKAGE tech_ddr_mem_model_component_pkg IS
);
END COMPONENT alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en;
+ ------------------------------------------------------------------------------
+ -- ip_arria10
+ ------------------------------------------------------------------------------
+
+ -- Manually derived VHDL entity from ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd in:
+ -- $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_141/sim
+ COMPONENT ed_sim_altera_emif_mem_model_141_z3tvrmq IS
+ PORT (
+ mem_ck : in std_logic_vector(0 downto 0) := (others => '0'); -- mem_conduit_end.mem_ck
+ mem_ck_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_ck_n
+ mem_a : in std_logic_vector(16 downto 0) := (others => '0'); -- .mem_a
+ mem_act_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_act_n
+ mem_ba : in std_logic_vector(1 downto 0) := (others => '0'); -- .mem_ba
+ mem_bg : in std_logic_vector(1 downto 0) := (others => '0'); -- .mem_bg
+ mem_cke : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_cke
+ mem_cs_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_cs_n
+ mem_odt : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_odt
+ mem_reset_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_reset_n
+ mem_par : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_par
+ mem_alert_n : out std_logic_vector(0 downto 0); -- .mem_alert_n
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0') -- .mem_dbi_n
+ );
+ END COMPONENT ed_sim_altera_emif_mem_model_141_z3tvrmq;
+
+
END tech_ddr_mem_model_component_pkg;
PACKAGE BODY tech_ddr_mem_model_component_pkg IS