From 30acb0e2ef141abc64a853da2a111c91906b8563 Mon Sep 17 00:00:00 2001
From: donker <donker@astron.nl>
Date: Wed, 7 Aug 2019 09:28:18 +0200
Subject: [PATCH] change environ variable name
---
.../unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd | 2 +-
.../src/vhdl/mmm_unb1_ddr3_reorder.vhd | 2 +-
.../src/vhdl/mmm_unb1_ddr3_transpose.vhd | 2 +-
.../tb/python/unb_ddr3_transpose.py | 6 +++---
.../src/vhdl/mmm_unb1_fn_terminal_db.vhd | 2 +-
.../tb/vhdl/tb_unb1_fn_terminal_db.vhd | 2 +-
.../unb1_heater/src/vhdl/mmm_unb1_heater.vhd | 2 +-
.../unb1_heater/tb/vhdl/tb_unb1_heater.vhd | 6 +++---
.../mmm_unb1_minimal_qsys_wo_pll.vhd | 2 +-
.../tb_unb1_minimal_qsys_wo_pll.vhd | 6 +++---
.../unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd | 2 +-
.../unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd | 6 +++---
.../src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd | 2 +-
.../src/python/gen_hex_file_dp_ram_from_mm.py | 2 +-
.../unb1_test/src/vhdl/mmm_unb1_test.vhd | 2 +-
.../designs/unb1_test/tb/vhdl/tb_unb1_test.vhd | 6 +++---
.../unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd | 2 +-
.../unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd | 6 +++---
.../unb2_test/src/vhdl/mmm_unb2_test.vhd | 2 +-
.../designs/unb2_test/tb/vhdl/tb_unb2_test.vhd | 6 +++---
.../unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd | 2 +-
.../unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd | 6 +++---
.../designs/unb2a_minimal/doc/README.txt | 4 ++--
.../src/vhdl/mmm_unb2a_minimal.vhd | 2 +-
.../unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd | 6 +++---
.../unb2a_test/src/vhdl/mmm_unb2a_test.vhd | 2 +-
.../unb2a_test/tb/vhdl/tb_unb2a_test.vhd | 6 +++---
.../unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd | 2 +-
.../unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd | 6 +++---
.../src/vhdl/mmm_unb2b_minimal.vhd | 2 +-
.../unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd | 6 +++---
.../unb2b_test/src/vhdl/mmm_unb2b_test.vhd | 2 +-
.../unb2b_test/tb/vhdl/tb_unb2b_test.vhd | 6 +++---
init_hdl.sh | 9 ++++++---
.../dp/designs/unb1_dp_offload/doc/readme.txt | 14 +++++++-------
.../src/vhdl/mmm_unb1_dp_offload.vhd | 2 +-
.../unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd | 2 +-
.../src/vhdl/mmm_unb1_correlator.vhd | 2 +-
.../dsp/filter/src/python/diff_lofar_coefs | 2 +-
.../tb/vhdl/tb_mmf_fringe_stop_unit.vhd | 18 +++++++++---------
.../unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd | 2 +-
.../tb/python/unb1_eth_10g_keep_alive.py | 4 ++--
42 files changed, 89 insertions(+), 86 deletions(-)
diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
index 580cbfe024..7a27dbfa21 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
@@ -160,7 +160,7 @@ BEGIN
cal_clk <= i_cal_clk;
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
index bc69bb0c49..b22bc96ef6 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
@@ -167,7 +167,7 @@ BEGIN
cal_clk <= i_cal_clk;
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
index b7a80e485d..1bbf679a9b 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
@@ -133,7 +133,7 @@ BEGIN
mm_clk <= i_mm_clk;
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/tb/python/unb_ddr3_transpose.py b/boards/uniboard1/designs/unb1_ddr3_transpose/tb/python/unb_ddr3_transpose.py
index 45dfba60ef..e99a7c3afe 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/tb/python/unb_ddr3_transpose.py
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/tb/python/unb_ddr3_transpose.py
@@ -31,9 +31,9 @@ from auto_sim import *
LIBRARY_NAME = 'unb_ddr3_transpose'
TB_NAME = 'tb_unb_ddr3_transpose'
TARGET_NODES = ' --unb 0 --bn 3 '
-COMMANDS = ['$UPE/peripherals/util_system_info.py' +TARGET_NODES+ '-n 2',
- '$UPE/peripherals/util_system_info.py' +TARGET_NODES+ '-n 4',
- '$UPE/peripherals/util_unb_sens.py' +TARGET_NODES+ '-n 0'
+COMMANDS = ['$UPE_GEAR/peripherals/util_system_info.py' +TARGET_NODES+ '-n 2',
+ '$UPE_GEAR/peripherals/util_system_info.py' +TARGET_NODES+ '-n 4',
+ '$UPE_GEAR/peripherals/util_unb_sens.py' +TARGET_NODES+ '-n 0'
]
# Give sim some time until the sensors have been read
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
index 8d90ce298d..48b37524cc 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
@@ -146,7 +146,7 @@ BEGIN
eth1g_tse_clk <= i_tse_clk;
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
index d9185ca3e9..ecd34649ec 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
@@ -60,7 +60,7 @@
-- . Try again (edit the do file to affect lane 0 on back or mesh)
--
-- Shell:
--- > cd $UPE
+-- > cd $UPE_GEAR
--
-- . For example do with g_unb_sys = (1, 1, 1):
-- > python apps/bn_bg_terminal_fn_db/tc_bn_bg_terminal_fn_db.py --unb 0 --bn 0 --fn 0 --sim
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
index d770b309cb..bb47b661ed 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
@@ -122,7 +122,7 @@ BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd
index afabf87f52..d2818f3661 100644
--- a/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd
@@ -37,9 +37,9 @@
-- > run 100 us (or run -all)
--
-- On command line do:
--- > python $UPE/peripherals/util_system_info.py --unb 0 --bn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_unb_sens.py --unb 0 --bn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_ppsh.py --unb 0 --bn 3 -n 1 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_system_info.py --unb 0 --bn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_unb_sens.py --unb 0 --bn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_ppsh.py --unb 0 --bn 3 -n 1 -v 5 --sim
--
LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
index d983de6e64..96883ccde9 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
@@ -122,7 +122,7 @@ ARCHITECTURE str OF mmm_unb1_minimal_qsys_wo_pll IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd
index 8826854cb6..40b4c341ba 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd
@@ -37,9 +37,9 @@
-- > run 100 us (or run -all)
--
-- On command line do:
--- > python $UPE/peripherals/util_system_info.py --unb 0 --bn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_unb_sens.py --unb 0 --bn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_ppsh.py --unb 0 --bn 3 -n 1 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_system_info.py --unb 0 --bn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_unb_sens.py --unb 0 --bn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_ppsh.py --unb 0 --bn 3 -n 1 -v 5 --sim
--
LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib;
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
index 36ec44d522..2c0fee9797 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
@@ -151,7 +151,7 @@ BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd
index eadda88bc7..b9a19b5356 100644
--- a/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd
@@ -37,9 +37,9 @@
-- > run 100 us (or run -all)
--
-- On command line do:
--- > python $UPE/peripherals/util_system_info.py --unb 0 --bn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_unb_sens.py --unb 0 --bn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_ppsh.py --unb 0 --bn 3 -n 1 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_system_info.py --unb 0 --bn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_unb_sens.py --unb 0 --bn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_ppsh.py --unb 0 --bn 3 -n 1 -v 5 --sim
--
LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib;
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
index 60ac564fd3..bd3dee21cc 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
@@ -268,7 +268,7 @@ ARCHITECTURE str OF mmm_unb1_terminal_bg_mesh_db IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
diff --git a/boards/uniboard1/designs/unb1_test/src/python/gen_hex_file_dp_ram_from_mm.py b/boards/uniboard1/designs/unb1_test/src/python/gen_hex_file_dp_ram_from_mm.py
index 02ccd9781e..f765881945 100644
--- a/boards/uniboard1/designs/unb1_test/src/python/gen_hex_file_dp_ram_from_mm.py
+++ b/boards/uniboard1/designs/unb1_test/src/python/gen_hex_file_dp_ram_from_mm.py
@@ -30,7 +30,7 @@ from mem_init_file import list_to_hex
# header in the RAM.
# . The HEX file generated here makes up the initial RAM contents.
# . The RAM contents can be changed during run-time using
-# $UPE/peripherals/pi_dp_ram_from_mm.py.
+# $UPE_GEAR/peripherals/pi_dp_ram_from_mm.py.
###############################################################################
# Constants
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
index adc210b9f6..7fd9b5198b 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
@@ -257,7 +257,7 @@ ARCHITECTURE str OF mmm_unb1_test IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
index 66d7c98fe4..df788a872f 100644
--- a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
@@ -37,9 +37,9 @@
-- > run 100 us (or run -all)
--
-- On command line do:
--- > python $UPE/peripherals/util_system_info.py --unb 0 --bn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_unb_sens.py --unb 0 --bn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_ppsh.py --unb 0 --bn 3 -n 1 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_system_info.py --unb 0 --bn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_unb_sens.py --unb 0 --bn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_ppsh.py --unb 0 --bn 3 -n 1 -v 5 --sim
--
LIBRARY ip_stratixiv_ddr3_mem_model_lib;
diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
index 7b9a29911f..db4628496d 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
@@ -111,7 +111,7 @@ ARCHITECTURE str OF mmm_unb2_minimal IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd
index 8bc8b42190..934e79fbf3 100644
--- a/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd
@@ -37,9 +37,9 @@
-- > run 100 us (or run -all)
--
-- On command line do:
--- > python $UPE/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
--
LIBRARY IEEE, common_lib, unb2_board_lib, i2c_lib;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
index 25d0302493..a9226f63e6 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
@@ -284,7 +284,7 @@ ARCHITECTURE str OF mmm_unb2_test IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
index cf4c5decef..8ee6475ea4 100644
--- a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
@@ -37,9 +37,9 @@
-- > run 100 us (or run -all)
--
-- On command line do:
--- > python $UPE/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
--
LIBRARY IEEE, common_lib, unb2_board_lib, i2c_lib, technology_lib, tech_pll_lib, tech_ddr_lib;
diff --git a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
index ccd5f167bb..7d97a93016 100644
--- a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
@@ -115,7 +115,7 @@ ARCHITECTURE str OF mmm_unb2a_heater IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd
index cebcb02006..15a188fc0d 100644
--- a/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd
@@ -37,9 +37,9 @@
-- > run 100 us (or run -all)
--
-- On command line do:
--- > python $UPE/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
--
LIBRARY IEEE, common_lib, unb2a_board_lib, i2c_lib;
diff --git a/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt b/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
index 30b3db4521..76b19ccab7 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
+++ b/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
@@ -39,7 +39,7 @@ Modelsim instructions:
run 500us
# while the simulation runs... in another bash session do:
- cd $UPE/peripherals
+ cd $UPE_GEAR/peripherals
python util_unb2.py --sim --unb 0 --fn 3 --seq INFO,SENSORS
# (sensor results only show up after 1000us of simulation runtime)
@@ -80,7 +80,7 @@ LCU computer.
# To read out the design_name and sensors; do:
-cd $UPE/peripherals
+cd $UPE_GEAR/peripherals
python util_unb2.py --unb 1 --fn 0:3 --seq REGMAP,INFO,SENSORS
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
index f2e4fd38dd..3388784703 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
@@ -111,7 +111,7 @@ ARCHITECTURE str OF mmm_unb2a_minimal IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
index 75cada4a39..3fbfc42a40 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
@@ -37,9 +37,9 @@
-- > run 100 us (or run -all)
--
-- On command line do:
--- > python $UPE/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
--
LIBRARY IEEE, common_lib, unb2a_board_lib, i2c_lib;
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
index 102462244b..7f07f1f7f3 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
@@ -287,7 +287,7 @@ ARCHITECTURE str OF mmm_unb2a_test IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd
index 63114610eb..03af55401b 100644
--- a/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd
@@ -37,9 +37,9 @@
-- > run 100 us (or run -all)
--
-- On command line do:
--- > python $UPE/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
--
LIBRARY IEEE, common_lib, unb2a_board_lib, i2c_lib, technology_lib, tech_pll_lib, tech_ddr_lib;
diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
index f401444b33..cdc4c14fd9 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
@@ -115,7 +115,7 @@ ARCHITECTURE str OF mmm_unb2b_heater IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
index 022ea137fa..73ece6e76e 100644
--- a/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
@@ -37,9 +37,9 @@
-- > run 100 us (or run -all)
--
-- On command line do:
--- > python $UPE/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
--
LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib;
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
index 315fbdfe35..a0c4d79f3b 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
@@ -111,7 +111,7 @@ ARCHITECTURE str OF mmm_unb2b_minimal IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
index 859aeba6a5..0f76fc12f3 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
@@ -37,9 +37,9 @@
-- > run 100 us (or run -all)
--
-- On command line do:
--- > python $UPE/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
--
LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
index f7163ec98b..2a6b14500f 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
@@ -287,7 +287,7 @@ ARCHITECTURE str OF mmm_unb2b_test IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
index 23c9b84139..5ffbd258ad 100644
--- a/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
@@ -37,9 +37,9 @@
-- > run 100 us (or run -all)
--
-- On command line do:
--- > python $UPE/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
--- > python $UPE/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
+-- > python $UPE_GEAR/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
--
LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, technology_lib, tech_pll_lib, tech_ddr_lib;
diff --git a/init_hdl.sh b/init_hdl.sh
index b57e5f36d9..caf40204b4 100644
--- a/init_hdl.sh
+++ b/init_hdl.sh
@@ -28,8 +28,9 @@
#
# Make sure it is sourced and no one accidentally gave the script execution rights and just executes it.
-if [ "${0}" != "bash" ]; then
+if [[ "$_" == "${0}" ]]; then
echo "ERROR: Use this command with '. ' or 'source '"
+ sleep 1
exit
fi
@@ -37,6 +38,8 @@ fi
export RADIOHDL_WORK="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
# setup paths to build and config dir if not already defined by the user.
export HDL_BUILD_DIR=${HDL_BUILD_DIR:-${RADIOHDL_WORK}/build}
-echo "RadioHDL environment will be setup for" $RADIOHDL_WORK
+echo "HDL environment will be setup for" $RADIOHDL_WORK
-. ../radiohdl/init_radiohdl.sh
+if [ -z "${RADIOHDL_GEAR}" ]; then
+ . ../radiohdl/init_radiohdl.sh
+fi
diff --git a/libraries/base/dp/designs/unb1_dp_offload/doc/readme.txt b/libraries/base/dp/designs/unb1_dp_offload/doc/readme.txt
index 1a86e0e3b3..e3bb2d780d 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/doc/readme.txt
+++ b/libraries/base/dp/designs/unb1_dp_offload/doc/readme.txt
@@ -5,13 +5,13 @@ Hardware:
$ run_rbf unb1 unb1_dp_offload
Copy the resulting unb1_dp_offload.rbf from the build directory to your UniBoard LCU (e.g. home dir).
. On the UniBoard LCU:
- $ python $UPE/peripherals/util_system_info.py --unb 0 --fn 0:3 --bn 0:3 -n 2 # show all designs running on board
- $ python $UPE/peripherals/util_system_info.py --unb 0 --fn 0:3 --bn 0:3 -n 4 # Get memory maps of all designs
- $ python $UPE/peripherals/util_wdi.py --unb 0 --fn 0:3 --bn 0:3 -n 0 # Revert all FPGAs to unb_factory
- $ python $UPE/peripherals/util_system_info.py --unb 0 --fn 0:3 --bn 0:3 -n 4 # Get memory maps of all designs
- $ python $UPE/peripherals/util_epcs.py --unb 0 --fn 0:1 -n 4 -s ~/unb1_dp_offload.rbf # Program RBF to flash user section of 2 FPGAs
- $ python $UPE/peripherals/util_epcs.py --unb 0 --fn 0:1 -n 8 # Load the user image on the 2 FPGAs
- $ python $UPE/peripherals/util_system_info.py --unb 0 --fn 0:3 --bn 0:3 -n 4 # Get memory maps of all FPGAs
+ $ python $UPE_GEAR/peripherals/util_system_info.py --unb 0 --fn 0:3 --bn 0:3 -n 2 # show all designs running on board
+ $ python $UPE_GEAR/peripherals/util_system_info.py --unb 0 --fn 0:3 --bn 0:3 -n 4 # Get memory maps of all designs
+ $ python $UPE_GEAR/peripherals/util_wdi.py --unb 0 --fn 0:3 --bn 0:3 -n 0 # Revert all FPGAs to unb_factory
+ $ python $UPE_GEAR/peripherals/util_system_info.py --unb 0 --fn 0:3 --bn 0:3 -n 4 # Get memory maps of all designs
+ $ python $UPE_GEAR/peripherals/util_epcs.py --unb 0 --fn 0:1 -n 4 -s ~/unb1_dp_offload.rbf # Program RBF to flash user section of 2 FPGAs
+ $ python $UPE_GEAR/peripherals/util_epcs.py --unb 0 --fn 0:1 -n 8 # Load the user image on the 2 FPGAs
+ $ python $UPE_GEAR/peripherals/util_system_info.py --unb 0 --fn 0:3 --bn 0:3 -n 4 # Get memory maps of all FPGAs
Finally, run the test case:
diff --git a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
index 30678e5889..f5dd5eccc8 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
@@ -176,7 +176,7 @@ BEGIN
dp_clk <= i_dp_clk;
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
index 08eb301e38..aeff190347 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
@@ -169,7 +169,7 @@ BEGIN
eth1g_tse_clk <= i_tse_clk;
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
index b07b899a85..c43cbeca4f 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
+++ b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
@@ -198,7 +198,7 @@ BEGIN
mm_clk <= i_mm_clk;
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/libraries/dsp/filter/src/python/diff_lofar_coefs b/libraries/dsp/filter/src/python/diff_lofar_coefs
index 4f5f0be0d5..1a0a6070fe 100755
--- a/libraries/dsp/filter/src/python/diff_lofar_coefs
+++ b/libraries/dsp/filter/src/python/diff_lofar_coefs
@@ -31,7 +31,7 @@
# the subband statistics will not peak low to 0 dB.
echo "1) Check that copies of LOFAR FIR coefficient reference files are equal"
-diff $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $UPE/apps/commissioning_apertif_beamformer/coeffs16384Kaiser-quant.dat
+diff $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $UPE_GEAR/apps/commissioning_apertif_beamformer/coeffs16384Kaiser-quant.dat
diff $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $UNB/Firmware/modules/Lofar/pfs/src/data/Coeffs16384Kaiser-quant.dat
diff $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-withdc.dat
diff --git a/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd
index 6310a436bd..d94c1b82d5 100644
--- a/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd
+++ b/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd
@@ -46,15 +46,15 @@
-- > as 5
-- > run 1000 us
-- On command line:
--- > python $UPE/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 99
--- > python $UPE/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 2 -r 4 write 4 in entire offset RAM
--- > python $UPE/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 3 -r 5 write 5 in entire step RAM
--- > python $UPE/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 0 read entire offset RAM
--- > python $UPE/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 1 read entire step RAM
--- > python $UPE/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 4 -r 6,0,1 write 6 in instance 0 at address 1 in offset RAM
--- > python $UPE/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 5 -r 7,0,2 write 7 in instance 0 at address 2 in offset RAM
--- > python $UPE/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 0 read entire offset RAM
--- > python $UPE/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 1 read entire step RAM
+-- > python $UPE_GEAR/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 99
+-- > python $UPE_GEAR/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 2 -r 4 write 4 in entire offset RAM
+-- > python $UPE_GEAR/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 3 -r 5 write 5 in entire step RAM
+-- > python $UPE_GEAR/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 0 read entire offset RAM
+-- > python $UPE_GEAR/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 1 read entire step RAM
+-- > python $UPE_GEAR/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 4 -r 6,0,1 write 6 in instance 0 at address 1 in offset RAM
+-- > python $UPE_GEAR/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 5 -r 7,0,2 write 7 in instance 0 at address 2 in offset RAM
+-- > python $UPE_GEAR/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 0 read entire offset RAM
+-- > python $UPE_GEAR/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 1 read entire step RAM
LIBRARY IEEE, common_lib, technology_lib, mm_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
diff --git a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
index 0acdd308d3..d48b4e138b 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
+++ b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
@@ -419,7 +419,7 @@ ARCHITECTURE str OF mmm_unb1_eth_10g IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
diff --git a/libraries/io/eth/designs/unb1_eth_10g/tb/python/unb1_eth_10g_keep_alive.py b/libraries/io/eth/designs/unb1_eth_10g/tb/python/unb1_eth_10g_keep_alive.py
index a166aa3462..aedd65b042 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/tb/python/unb1_eth_10g_keep_alive.py
+++ b/libraries/io/eth/designs/unb1_eth_10g/tb/python/unb1_eth_10g_keep_alive.py
@@ -10,7 +10,7 @@ from shell import ssh_cmd_bkgnd
from commands import *
lcu = "dop36"
-script_name = "util_dp_xonoff.py" #should be located in $UPE/peripherals
+script_name = "util_dp_xonoff.py" #should be located in $UPE_GEAR/peripherals
sleep_time = 5
# Create a test case object
@@ -58,7 +58,7 @@ def run_command(cmd, lcu_name = 'local', back = False):
def set_lcupath(lcu_name):
- cmd = "ssh " + lcu_name + " 'printf $UPE'"
+ cmd = "ssh " + lcu_name + " 'printf $UPE_GEAR'"
output = run_command(cmd)[0] + "/peripherals/"
return output
--
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