diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
index 580cbfe0248120c71dfb70b60eb91ebb6bf7a325..7a27dbfa212ce9fc6f38a7f1463d59354c6b4862 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
@@ -160,7 +160,7 @@ BEGIN
   cal_clk       <= i_cal_clk;
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
index bc69bb0c4972a5b6679cabe570d6b68acbdddb5d..b22bc96ef6876c494d0f5959118f569732f3daaf 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
@@ -167,7 +167,7 @@ BEGIN
   cal_clk       <= i_cal_clk;
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
index b7a80e485d4124e2b7daaf952a1b60bf2d724260..1bbf679a9b2be2030f0f4d4d3f20ccfb801d3259 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
@@ -133,7 +133,7 @@ BEGIN
   mm_clk <= i_mm_clk;
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/tb/python/unb_ddr3_transpose.py b/boards/uniboard1/designs/unb1_ddr3_transpose/tb/python/unb_ddr3_transpose.py
index 45dfba60ef8cd0679ec0047566453fffe0b4d9fb..e99a7c3afeafebcc353e1c1652f456a509f9cdcf 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/tb/python/unb_ddr3_transpose.py
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/tb/python/unb_ddr3_transpose.py
@@ -31,9 +31,9 @@ from auto_sim import *
 LIBRARY_NAME = 'unb_ddr3_transpose'
 TB_NAME      = 'tb_unb_ddr3_transpose'   
 TARGET_NODES = ' --unb 0 --bn 3 '
-COMMANDS     = ['$UPE/peripherals/util_system_info.py' +TARGET_NODES+ '-n 2',
-                '$UPE/peripherals/util_system_info.py' +TARGET_NODES+ '-n 4',
-                '$UPE/peripherals/util_unb_sens.py'    +TARGET_NODES+ '-n 0'
+COMMANDS     = ['$UPE_GEAR/peripherals/util_system_info.py' +TARGET_NODES+ '-n 2',
+                '$UPE_GEAR/peripherals/util_system_info.py' +TARGET_NODES+ '-n 4',
+                '$UPE_GEAR/peripherals/util_unb_sens.py'    +TARGET_NODES+ '-n 0'
                ]
 
 # Give sim some time until the sensors have been read
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
index 8d90ce298d29d74d33fece71f9bee40216093704..48b37524cc93f255f3a4479aba797b50df15aabc 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
@@ -146,7 +146,7 @@ BEGIN
   eth1g_tse_clk <= i_tse_clk;
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
index d9185ca3e9f7b9cb98090dfddb7b44ab7fc5925a..ecd34649ecd4c7a1abc06a0ba70f3172dfaef0af 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
@@ -60,7 +60,7 @@
 --     . Try again (edit the do file to affect lane 0 on back or mesh)
 --
 --   Shell:
---   > cd $UPE
+--   > cd $UPE_GEAR
 --
 --   . For example do with g_unb_sys = (1, 1, 1):
 --   > python apps/bn_bg_terminal_fn_db/tc_bn_bg_terminal_fn_db.py --unb 0 --bn 0 --fn 0 --sim
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
index d770b309cb47bfa8167a5d214353bcd4347f299f..bb47b661ed4d6abbaa0974821036d3669adc6479 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
@@ -122,7 +122,7 @@ BEGIN
 
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd
index afabf87f5295ffc5d1813fc1ed3886b3ea83975a..d2818f36610baf6e1333eed4f78b95cbf343e6b5 100644
--- a/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd
@@ -37,9 +37,9 @@
 --     > run 100 us (or run -all)
 --
 --   On command line do:
---     > python $UPE/peripherals/util_system_info.py --unb 0 --bn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_unb_sens.py --unb 0 --bn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_ppsh.py --unb 0 --bn 3 -n 1 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_system_info.py --unb 0 --bn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_unb_sens.py --unb 0 --bn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_ppsh.py --unb 0 --bn 3 -n 1 -v 5 --sim
 --
 
 LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
index d983de6e64d20c38c75cd801e22ec6d6b1ea5a34..96883ccde9b40f852b8bd541ccd5948b839cc74c 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
@@ -122,7 +122,7 @@ ARCHITECTURE str OF mmm_unb1_minimal_qsys_wo_pll IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd
index 8826854cb647f53d7b829376360f3bc0267ec381..40b4c341ba34f870d5db73ba21fa9fda94694eb4 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd
@@ -37,9 +37,9 @@
 --     > run 100 us (or run -all)
 --
 --   On command line do:
---     > python $UPE/peripherals/util_system_info.py --unb 0 --bn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_unb_sens.py --unb 0 --bn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_ppsh.py --unb 0 --bn 3 -n 1 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_system_info.py --unb 0 --bn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_unb_sens.py --unb 0 --bn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_ppsh.py --unb 0 --bn 3 -n 1 -v 5 --sim
 --
 
 LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib;
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
index 36ec44d5226f9b612d377644cf349224feb6cd14..2c0fee9797b0edc7eb88bc91077cced153f16be9 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
@@ -151,7 +151,7 @@ BEGIN
 
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd
index eadda88bc727e46cd15162ce6c89e55ad72b368d..b9a19b53566a2ce51275ed019dea5322ffa2cd58 100644
--- a/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd
@@ -37,9 +37,9 @@
 --     > run 100 us (or run -all)
 --
 --   On command line do:
---     > python $UPE/peripherals/util_system_info.py --unb 0 --bn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_unb_sens.py --unb 0 --bn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_ppsh.py --unb 0 --bn 3 -n 1 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_system_info.py --unb 0 --bn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_unb_sens.py --unb 0 --bn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_ppsh.py --unb 0 --bn 3 -n 1 -v 5 --sim
 --
 
 LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib;
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
index 60ac564fd37bc6811e8ac60a9c3beab10f2bbc56..bd3dee21cce9a4163932f7d00ec78c4ab3d1cadd 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
@@ -268,7 +268,7 @@ ARCHITECTURE str OF mmm_unb1_terminal_bg_mesh_db IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
     u_mm_file_reg_wdi  :  mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
diff --git a/boards/uniboard1/designs/unb1_test/src/python/gen_hex_file_dp_ram_from_mm.py b/boards/uniboard1/designs/unb1_test/src/python/gen_hex_file_dp_ram_from_mm.py
index 02ccd9781ee56e5af4a82fb915c7d156d3358085..f76588194581a17e0bfc0a8faf4dd82a5b5da75d 100644
--- a/boards/uniboard1/designs/unb1_test/src/python/gen_hex_file_dp_ram_from_mm.py
+++ b/boards/uniboard1/designs/unb1_test/src/python/gen_hex_file_dp_ram_from_mm.py
@@ -30,7 +30,7 @@ from mem_init_file import list_to_hex
 #   header in the RAM.
 # . The HEX file generated here makes up the initial RAM contents.
 # . The RAM contents can be changed during run-time using 
-#   $UPE/peripherals/pi_dp_ram_from_mm.py.
+#   $UPE_GEAR/peripherals/pi_dp_ram_from_mm.py.
 
 ###############################################################################
 # Constants
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
index adc210b9f66a6aa8c4ddbdb05edbf54d2575f209..7fd9b5198b0b5bae433650aa53e8b847c17365a8 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
@@ -257,7 +257,7 @@ ARCHITECTURE str OF mmm_unb1_test IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
index 66d7c98fe430ca916b4c3b96cdedcab233e86fbe..df788a872f5bfbaecaa002957b96994aa4c7c936 100644
--- a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
@@ -37,9 +37,9 @@
 --     > run 100 us (or run -all)
 --
 --   On command line do:
---     > python $UPE/peripherals/util_system_info.py --unb 0 --bn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_unb_sens.py --unb 0 --bn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_ppsh.py --unb 0 --bn 3 -n 1 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_system_info.py --unb 0 --bn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_unb_sens.py --unb 0 --bn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_ppsh.py --unb 0 --bn 3 -n 1 -v 5 --sim
 --
 
 LIBRARY ip_stratixiv_ddr3_mem_model_lib;
diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
index 7b9a29911f1fc08864a1095acbc323391d5c5e17..db4628496d5407dcebe64cc739e0371b8220c88e 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
@@ -111,7 +111,7 @@ ARCHITECTURE str OF mmm_unb2_minimal IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd
index 8bc8b42190fa6b3653504a57ec4533f1df9ea37a..934e79fbf31595c7531040435bc29b345ef6e3f9 100644
--- a/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd
@@ -37,9 +37,9 @@
 --     > run 100 us (or run -all)
 --
 --   On command line do:
---     > python $UPE/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
 --
 
 LIBRARY IEEE, common_lib, unb2_board_lib, i2c_lib;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
index 25d03024937032ab5033005e7102dfe52ca4a474..a9226f63e6109e91ed3663c7f3b489139345f023 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
@@ -284,7 +284,7 @@ ARCHITECTURE str OF mmm_unb2_test IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
index cf4c5decef1f79342a05275dd2fe701f0167c70d..8ee6475ea449b79e4413f0baacb14548ec42bb61 100644
--- a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
@@ -37,9 +37,9 @@
 --     > run 100 us (or run -all)
 --
 --   On command line do:
---     > python $UPE/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
 --
 
 LIBRARY IEEE, common_lib, unb2_board_lib, i2c_lib, technology_lib, tech_pll_lib, tech_ddr_lib;
diff --git a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
index ccd5f167bb3fae1d1a0222002b4ea0994203d2c3..7d97a930169989f621da500a586be25d11782034 100644
--- a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
@@ -115,7 +115,7 @@ ARCHITECTURE str OF mmm_unb2a_heater IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd
index cebcb0200629b00bd3b7a386e47b1805a8efc5e8..15a188fc0d6aebf246654631ce1a2a55c5520bb9 100644
--- a/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd
@@ -37,9 +37,9 @@
 --     > run 100 us (or run -all)
 --
 --   On command line do:
---     > python $UPE/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
 --
 
 LIBRARY IEEE, common_lib, unb2a_board_lib, i2c_lib;
diff --git a/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt b/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
index 30b3db452169ee49c1360164d925d5d1a91baa12..76b19ccab70672452c443ede6553c37aa43fa764 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
+++ b/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
@@ -39,7 +39,7 @@ Modelsim instructions:
     run 500us
 
     # while the simulation runs... in another bash session do:
-    cd $UPE/peripherals
+    cd $UPE_GEAR/peripherals
     python util_unb2.py --sim --unb 0 --fn 3 --seq INFO,SENSORS
 
     # (sensor results only show up after 1000us of simulation runtime)
@@ -80,7 +80,7 @@ LCU computer.
 
 # To read out the design_name and sensors; do:
 
-cd $UPE/peripherals
+cd $UPE_GEAR/peripherals
 python util_unb2.py --unb 1 --fn 0:3 --seq REGMAP,INFO,SENSORS
 
 
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
index f2e4fd38dda6cd79a13fb69f740dec777202403e..338878470393169081645cc7eb20659a0bc95803 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
@@ -111,7 +111,7 @@ ARCHITECTURE str OF mmm_unb2a_minimal IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
index 75cada4a39447a8248f53c0902bc6432ab2e7089..3fbfc42a40edabe23090e869ff329f70992425c2 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
@@ -37,9 +37,9 @@
 --     > run 100 us (or run -all)
 --
 --   On command line do:
---     > python $UPE/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
 --
 
 LIBRARY IEEE, common_lib, unb2a_board_lib, i2c_lib;
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
index 102462244b26910e31245e6aea83d0ad733ef2fe..7f07f1f7f3ed4e55110b774aa62bbd87d13794b1 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
@@ -287,7 +287,7 @@ ARCHITECTURE str OF mmm_unb2a_test IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd
index 63114610eb8330f727fb3fb7f001b0ded181632a..03af55401bc73d4b251464ae1a9e5c235c48e517 100644
--- a/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd
@@ -37,9 +37,9 @@
 --     > run 100 us (or run -all)
 --
 --   On command line do:
---     > python $UPE/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
 --
 
 LIBRARY IEEE, common_lib, unb2a_board_lib, i2c_lib, technology_lib, tech_pll_lib, tech_ddr_lib;
diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
index f401444b33ad8c7adb696d3271f735dd80bfa337..cdc4c14fd96e98b0b24e48ec89114455cfcb4528 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
@@ -115,7 +115,7 @@ ARCHITECTURE str OF mmm_unb2b_heater IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
index 022ea137fa9178d6bd2ff8cb3813eff43f40cfde..73ece6e76e2bc8e9ccf906b9ec0e46f0b5e7e8bd 100644
--- a/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
@@ -37,9 +37,9 @@
 --     > run 100 us (or run -all)
 --
 --   On command line do:
---     > python $UPE/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
 --
 
 LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib;
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
index 315fbdfe35f47511380b1b31eb25d79a2c15e318..a0c4d79f3bc65bf86d7ff064947d7632db6f0286 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
@@ -111,7 +111,7 @@ ARCHITECTURE str OF mmm_unb2b_minimal IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
index 859aeba6a5062d1066f108f62c6a67388d5b3d8f..0f76fc12f302e61638eae4c468454d82bcaaaed0 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
@@ -37,9 +37,9 @@
 --     > run 100 us (or run -all)
 --
 --   On command line do:
---     > python $UPE/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
 --
 
 LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
index f7163ec98b4ea9096bb5ea9b3497466ccf5f793d..2a6b14500f9321740e6c11975b7e0eb25e7026a9 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
@@ -287,7 +287,7 @@ ARCHITECTURE str OF mmm_unb2b_test IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
index 23c9b84139f9bd5a0b40c1e412a2a9274260e3d6..5ffbd258ad789af8a841120c718f94e7ead46d22 100644
--- a/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
@@ -37,9 +37,9 @@
 --     > run 100 us (or run -all)
 --
 --   On command line do:
---     > python $UPE/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
+--     > python $UPE_GEAR/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
 --
 
 LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, technology_lib, tech_pll_lib, tech_ddr_lib;
diff --git a/init_hdl.sh b/init_hdl.sh
index b57e5f36d91a1b2b2fe02b6b9e8350a78d7f01c1..caf40204b464f47119f3fe643915c3af823e9033 100644
--- a/init_hdl.sh
+++ b/init_hdl.sh
@@ -28,8 +28,9 @@
 
 # 
 # Make sure it is sourced and no one accidentally gave the script execution rights and just executes it.
-if [ "${0}" != "bash" ]; then
+if [[ "$_" == "${0}" ]]; then
     echo "ERROR: Use this command with '. ' or 'source '"
+    sleep 1
     exit
 fi
 
@@ -37,6 +38,8 @@ fi
 export RADIOHDL_WORK="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
 # setup paths to build and config dir if not already defined by the user.
 export HDL_BUILD_DIR=${HDL_BUILD_DIR:-${RADIOHDL_WORK}/build}
-echo "RadioHDL environment will be setup for" $RADIOHDL_WORK
+echo "HDL environment will be setup for" $RADIOHDL_WORK
 
-. ../radiohdl/init_radiohdl.sh
+if [ -z "${RADIOHDL_GEAR}" ]; then
+    . ../radiohdl/init_radiohdl.sh
+fi
diff --git a/libraries/base/dp/designs/unb1_dp_offload/doc/readme.txt b/libraries/base/dp/designs/unb1_dp_offload/doc/readme.txt
index 1a86e0e3b307e2dd265436899ebf8b0b2a8bef3a..e3bb2d780d9da20cdfcc261b1401a798e27ff8b6 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/doc/readme.txt
+++ b/libraries/base/dp/designs/unb1_dp_offload/doc/readme.txt
@@ -5,13 +5,13 @@ Hardware:
   $ run_rbf unb1 unb1_dp_offload
   Copy the resulting unb1_dp_offload.rbf from the build directory to your UniBoard LCU (e.g. home dir).
 . On the UniBoard LCU:
-  $ python $UPE/peripherals/util_system_info.py --unb 0 --fn 0:3 --bn 0:3 -n 2                 # show all designs running on board
-  $ python $UPE/peripherals/util_system_info.py --unb 0 --fn 0:3 --bn 0:3 -n 4                 # Get memory maps of all designs
-  $ python $UPE/peripherals/util_wdi.py         --unb 0 --fn 0:3 --bn 0:3 -n 0                 # Revert all FPGAs to unb_factory
-  $ python $UPE/peripherals/util_system_info.py --unb 0 --fn 0:3 --bn 0:3 -n 4                 # Get memory maps of all designs
-  $ python $UPE/peripherals/util_epcs.py        --unb 0 --fn 0:1 -n 4 -s ~/unb1_dp_offload.rbf # Program RBF to flash user section of 2 FPGAs
-  $ python $UPE/peripherals/util_epcs.py        --unb 0 --fn 0:1 -n 8                          # Load the user image on the 2 FPGAs
-  $ python $UPE/peripherals/util_system_info.py --unb 0 --fn 0:3 --bn 0:3 -n 4                 # Get memory maps of all FPGAs
+  $ python $UPE_GEAR/peripherals/util_system_info.py --unb 0 --fn 0:3 --bn 0:3 -n 2                 # show all designs running on board
+  $ python $UPE_GEAR/peripherals/util_system_info.py --unb 0 --fn 0:3 --bn 0:3 -n 4                 # Get memory maps of all designs
+  $ python $UPE_GEAR/peripherals/util_wdi.py         --unb 0 --fn 0:3 --bn 0:3 -n 0                 # Revert all FPGAs to unb_factory
+  $ python $UPE_GEAR/peripherals/util_system_info.py --unb 0 --fn 0:3 --bn 0:3 -n 4                 # Get memory maps of all designs
+  $ python $UPE_GEAR/peripherals/util_epcs.py        --unb 0 --fn 0:1 -n 4 -s ~/unb1_dp_offload.rbf # Program RBF to flash user section of 2 FPGAs
+  $ python $UPE_GEAR/peripherals/util_epcs.py        --unb 0 --fn 0:1 -n 8                          # Load the user image on the 2 FPGAs
+  $ python $UPE_GEAR/peripherals/util_system_info.py --unb 0 --fn 0:3 --bn 0:3 -n 4                 # Get memory maps of all FPGAs
   
   Finally, run the test case:
 
diff --git a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
index 30678e5889fbe77e870ab30c8eecfb5d5cdd9771..f5dd5eccc8c00cccbdc16cbffe8c61f4adace468 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
@@ -176,7 +176,7 @@ BEGIN
   dp_clk        <= i_dp_clk;
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
index 08eb301e385902195d57ccde8f6adc5f610f13a1..aeff190347ba10b63d455fdba7fd03f3f7089899 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
@@ -169,7 +169,7 @@ BEGIN
   eth1g_tse_clk <= i_tse_clk;
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
index b07b899a85087a4ccdbd70b46d281bb442c6db3e..c43cbeca4faa08defe29a5f662848ba3475f00ee 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
+++ b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
@@ -198,7 +198,7 @@ BEGIN
   mm_clk   <= i_mm_clk;
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/libraries/dsp/filter/src/python/diff_lofar_coefs b/libraries/dsp/filter/src/python/diff_lofar_coefs
index 4f5f0be0d5046ec7bbbe6dd4d6b9a83f66cde383..1a0a6070fed5a01d523c208c9a848ca929b14d3c 100755
--- a/libraries/dsp/filter/src/python/diff_lofar_coefs
+++ b/libraries/dsp/filter/src/python/diff_lofar_coefs
@@ -31,7 +31,7 @@
 #   the subband statistics will not peak low to 0 dB.
 
 echo "1) Check that copies of LOFAR FIR coefficient reference files are equal"
-diff $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $UPE/apps/commissioning_apertif_beamformer/coeffs16384Kaiser-quant.dat
+diff $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $UPE_GEAR/apps/commissioning_apertif_beamformer/coeffs16384Kaiser-quant.dat
 diff $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $UNB/Firmware/modules/Lofar/pfs/src/data/Coeffs16384Kaiser-quant.dat
 diff $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $RADIOHDL/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-withdc.dat
 
diff --git a/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd
index 6310a436bd5d673395acfcaae826f9abfc103fbc..d94c1b82d58dd249fe96033df448e6ac02b85b3b 100644
--- a/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd
+++ b/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd
@@ -46,15 +46,15 @@
 --     > as 5
 --     > run 1000 us
 --   On command line:
---     > python $UPE/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 99
---     > python $UPE/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 2 -r 4   write 4 in entire offset RAM
---     > python $UPE/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 3 -r 5   write 5 in entire step RAM
---     > python $UPE/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 0        read entire offset RAM
---     > python $UPE/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 1        read entire step RAM
---     > python $UPE/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 4 -r 6,0,1   write 6 in instance 0 at address 1 in offset RAM
---     > python $UPE/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 5 -r 7,0,2   write 7 in instance 0 at address 2 in offset RAM
---     > python $UPE/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 0        read entire offset RAM
---     > python $UPE/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 1        read entire step RAM
+--     > python $UPE_GEAR/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 99
+--     > python $UPE_GEAR/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 2 -r 4   write 4 in entire offset RAM
+--     > python $UPE_GEAR/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 3 -r 5   write 5 in entire step RAM
+--     > python $UPE_GEAR/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 0        read entire offset RAM
+--     > python $UPE_GEAR/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 1        read entire step RAM
+--     > python $UPE_GEAR/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 4 -r 6,0,1   write 6 in instance 0 at address 1 in offset RAM
+--     > python $UPE_GEAR/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 5 -r 7,0,2   write 7 in instance 0 at address 2 in offset RAM
+--     > python $UPE_GEAR/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 0        read entire offset RAM
+--     > python $UPE_GEAR/peripherals/util_fringe_stop.py --sim --unb 0 --fn 0 -n 1        read entire step RAM
 
 LIBRARY IEEE, common_lib, technology_lib, mm_lib, dp_lib;
 USE IEEE.std_logic_1164.ALL;
diff --git a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
index 0acdd308d3e0534504a3a90db52f45e42b72922d..d48b4e138bc67ad1cf28af1fc924b441e98c0526 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
+++ b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
@@ -419,7 +419,7 @@ ARCHITECTURE str OF mmm_unb1_eth_10g IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
     u_mm_file_reg_wdi  :  mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
diff --git a/libraries/io/eth/designs/unb1_eth_10g/tb/python/unb1_eth_10g_keep_alive.py b/libraries/io/eth/designs/unb1_eth_10g/tb/python/unb1_eth_10g_keep_alive.py
index a166aa346255ab9d5d0b9e98ada73a500d81c980..aedd65b042782220528c0bd74ea2fd1619f54e7e 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/tb/python/unb1_eth_10g_keep_alive.py
+++ b/libraries/io/eth/designs/unb1_eth_10g/tb/python/unb1_eth_10g_keep_alive.py
@@ -10,7 +10,7 @@ from shell import ssh_cmd_bkgnd
 from commands import *
 
 lcu = "dop36"
-script_name = "util_dp_xonoff.py" #should be located in $UPE/peripherals
+script_name = "util_dp_xonoff.py" #should be located in $UPE_GEAR/peripherals
 sleep_time = 5
 
 # Create a test case object
@@ -58,7 +58,7 @@ def run_command(cmd, lcu_name = 'local', back = False):
 
         
 def set_lcupath(lcu_name):
-    cmd = "ssh " + lcu_name + " 'printf $UPE'"
+    cmd = "ssh " + lcu_name + " 'printf $UPE_GEAR'"
     output = run_command(cmd)[0] + "/peripherals/"
     return output