diff --git a/libraries/base/reorder/tb/python/tc_reorder_transpose.py b/libraries/base/reorder/tb/python/tc_reorder_transpose.py
index 22d405788d6998f74c4d72353e356eaec26dcc07..5e79af77095902d1176ca9722af08a64a96014a1 100644
--- a/libraries/base/reorder/tb/python/tc_reorder_transpose.py
+++ b/libraries/base/reorder/tb/python/tc_reorder_transpose.py
@@ -39,6 +39,7 @@ import unb_apertif as apr
import pi_diag_block_gen
import pi_diag_data_buffer
import pi_ss_ss_wide
+import pi_io_ddr
import dsp_test
import sys, os
@@ -60,12 +61,14 @@ tc = test_case.Testcase('TB - ', '')
# Constants/Generics that are shared between VHDL and Python
# Name Value Default Description
# START_VHDL_GENERICS
-g_wr_chunksize = 256
+g_wr_chunksize = 240
g_rd_chunksize = 16
-g_rd_nof_chunks = 16
+g_rd_nof_chunks = 15
g_rd_interval = 16
g_gapsize = 0
g_nof_blocks = 32
+g_frame_size_in = 256
+g_frame_sie_out = 128
# END_VHDL_GENERICS
# Overwrite generics with argumented generics from autoscript or command line.
@@ -76,16 +79,18 @@ if tc.generics != None:
g_rd_interval = tc.generics['g_rd_interval']
g_gapsize = tc.generics['g_gapsize']
g_nof_blocks = tc.generics['g_nof_blocks']
+ g_frame_size_in = tc.generics['g_frame_size_in']
+ g_frame_size_out = tc.generics['g_frame_size_out']
c_blocksize = (g_wr_chunksize + g_gapsize)
c_pagesize = c_blocksize * g_nof_blocks
+c_ss_pagesize = g_frame_size_in * g_rd_chunksize
c_rd_increment = g_rd_interval * c_blocksize
c_bg_nof_streams = 4
-c_bg_ram_size = g_wr_chunksize * g_nof_blocks
+c_bg_ram_size = g_frame_size_in * g_nof_blocks
c_in_dat_w = 8
c_db_nof_streams = c_bg_nof_streams
c_db_ram_size = c_bg_ram_size
-c_frame_size = g_wr_chunksize
c_nof_int_streams = 1
c_ena_pre_transpose = True
c_gap_size = 0 #g_rd_chunksize
@@ -110,7 +115,10 @@ db_re = pi_diag_data_buffer.PiDiagDataBuffer(tc, io, instanceName = 'REAL', nofS
db_im = pi_diag_data_buffer.PiDiagDataBuffer(tc, io, instanceName = 'IMAG', nofStreams=c_db_nof_streams, ramSizePerStream=c_db_ram_size)
# Create subandselect instance for pre-transpose.
-ss = pi_ss_ss_wide.PiSsSsWide (tc, io, c_frame_size*g_rd_chunksize, c_nof_int_streams)
+ss = pi_ss_ss_wide.PiSsSsWide (tc, io, g_wr_chunksize*g_rd_chunksize, c_nof_int_streams)
+
+# Create object for DDR register map
+ddr = pi_io_ddr.PiIoDdr(tc, io, nof_inst = 1)
# Create dsp_test instance for helpful methods
dsp_test_bg = dsp_test.DspTest(inDatW=c_in_dat_w)
@@ -138,9 +146,9 @@ if __name__ == "__main__":
#
###############################################################################
ss_list = []
- for i in range(c_frame_size):
+ for i in range(g_wr_chunksize):
for j in range(g_rd_chunksize):
- ss_list.append(i + j*c_frame_size)
+ ss_list.append(i + j*g_frame_size_in)
if c_ena_pre_transpose:
ss.write_selects(ss_list)
@@ -151,7 +159,7 @@ if __name__ == "__main__":
#
###############################################################################
# Prepare x stimuli for block generator
- bg_data = gen_bg_hex_files(c_frame_size, g_nof_blocks, c_bg_nof_streams)
+ bg_data = gen_bg_hex_files(g_frame_size_in, g_nof_blocks, c_bg_nof_streams)
################################################################################
##
@@ -159,7 +167,7 @@ if __name__ == "__main__":
##
################################################################################
# Write setting for the block generator:
- bg.write_block_gen_settings(samplesPerPacket=c_frame_size, blocksPerSync=g_nof_blocks, gapSize=c_gap_size, memLowAddr=0, memHighAddr=c_bg_ram_size-1, BSNInit=10)
+ bg.write_block_gen_settings(samplesPerPacket=g_frame_size_in, blocksPerSync=g_nof_blocks, gapSize=c_gap_size, memLowAddr=0, memHighAddr=c_bg_ram_size-1, BSNInit=10)
# Write the stimuli to the block generator and enable the block generator
for i in range(c_bg_nof_streams):
@@ -177,17 +185,18 @@ if __name__ == "__main__":
bg_data = flatten(bg_data)
# Wait until the DDR3 model is initialized.
- do_until_gt(io.simIO.getSimTime, ms_retry=1000, val=110000, s_timeout=13600) # 110000
+ if tc.sim == True:
+ do_until_eq(ddr.read_init_done, ms_retry=1000, val=1, s_timeout=13600) # 110000
# Enable the blockgenerator
bg.write_enable()
if(c_force_late_sync == 1):
do_until_gt(io.simIO.getSimTime, ms_retry=1000, val=180000, s_timeout=13600) # 110000
- bg.write_block_gen_settings(samplesPerPacket=c_frame_size, blocksPerSync=g_nof_blocks+1, gapSize=c_gap_size, memLowAddr=0, memHighAddr=c_bg_ram_size-1, BSNInit=10)
+ bg.write_block_gen_settings(samplesPerPacket=g_frame_size_in, blocksPerSync=g_nof_blocks+1, gapSize=c_gap_size, memLowAddr=0, memHighAddr=c_bg_ram_size-1, BSNInit=10)
elif(c_force_early_sync == 1):
do_until_gt(io.simIO.getSimTime, ms_retry=1000, val=180000, s_timeout=13600) # 110000
- bg.write_block_gen_settings(samplesPerPacket=c_frame_size, blocksPerSync=g_nof_blocks-1, gapSize=c_gap_size, memLowAddr=0, memHighAddr=c_bg_ram_size-1, BSNInit=10)
+ bg.write_block_gen_settings(samplesPerPacket=g_frame_size_in, blocksPerSync=g_nof_blocks-1, gapSize=c_gap_size, memLowAddr=0, memHighAddr=c_bg_ram_size-1, BSNInit=10)
###############################################################################
#
@@ -197,8 +206,8 @@ if __name__ == "__main__":
# Subband Select pre-transpose
if c_ena_pre_transpose:
bg_data_ss =[]
- for i in range(len(bg_data)/len(ss_list)):
- bg_data_ss.append(ss.subband_select(bg_data[i*len(ss_list):(i+1)*len(ss_list)], ss_list))
+ for i in range(len(bg_data)/c_ss_pagesize): # len(ss_list)):
+ bg_data_ss.append(ss.subband_select(bg_data[i*c_ss_pagesize:(i+1)*c_ss_pagesize], ss_list))
bg_data = bg_data_ss
bg_data = flatten(bg_data)
@@ -270,7 +279,7 @@ if __name__ == "__main__":
#
###############################################################################
for i in range(c_bg_nof_streams):
- for j in range(c_db_ram_size):
+ for j in range(len(ref_data_re[0])):
if db_out_re[i][j] != ref_data_re[i][j]:
tc.append_log(2, 'Error in real output data. Expected data: %d Data read: %d Iteration nr: %d %d' % (ref_data_re[i][j], db_out_re[i][j], i, j))
tc.set_result('FAILED')
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd
index ed14cf176ce6a18fc54b276d3e8a6e3eafb31726..5185114734d42b6beac277f42f44c576bdbc5960 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd
@@ -50,15 +50,17 @@ USE work.reorder_pkg.ALL;
ENTITY tb_reorder_transpose IS
GENERIC (
- g_wr_chunksize : POSITIVE := 256;
+ g_wr_chunksize : POSITIVE := 240; --256;
g_rd_chunksize : POSITIVE := 16;
- g_rd_nof_chunks : POSITIVE := 16;
- g_rd_interval : POSITIVE := 16; -- When pre-transpose is used equal to g_rd_chunksize.
+ g_rd_nof_chunks : POSITIVE := 15; --16;
+ g_rd_interval : POSITIVE := 16; -- When pre-transpose is used equal to g_rd_chunksize.
g_gapsize : NATURAL := 0;
g_nof_blocks : POSITIVE := 32;
g_nof_streams : POSITIVE := 4;
g_in_dat_w : POSITIVE := 8;
g_mem_dat_w : NATURAL := 256; -- The data width to the attached memory.
+ g_frame_size_in : NATURAL := 256;
+ g_frame_size_out : NATURAL := 128;
g_ena_pre_transp : BOOLEAN := TRUE
);
END tb_reorder_transpose;
@@ -106,8 +108,11 @@ ARCHITECTURE tb OF tb_reorder_transpose IS
-- DUT
SIGNAL ram_ss_ss_transp_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_ss_ss_transp_miso : t_mem_miso := c_mem_miso_rst;
-
+ SIGNAL ram_ss_ss_transp_miso : t_mem_miso := c_mem_miso_rst;
+
+ SIGNAL reg_io_ddr_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_io_ddr_miso : t_mem_miso := c_mem_miso_rst;
+
----------------------------------------------------------------------------
-- Component declaration of mm_file
----------------------------------------------------------------------------
@@ -153,8 +158,8 @@ ARCHITECTURE tb OF tb_reorder_transpose IS
CONSTANT c_ctrl_ref_clk_period : TIME := 5000 ps;
-- Custom definitions of constants
- CONSTANT c_bg_block_len : NATURAL := c_blocksize * g_nof_blocks;
- CONSTANT c_db_block_len : NATURAL := c_blocksize * g_nof_blocks;
+ CONSTANT c_bg_block_len : NATURAL := g_frame_size_in * g_nof_blocks;
+ CONSTANT c_db_block_len : NATURAL := g_frame_size_in * g_nof_blocks;
-- Configuration of the block generator:
CONSTANT c_bg_nof_output_streams : POSITIVE := g_nof_streams;
@@ -238,6 +243,10 @@ BEGIN
u_mm_file_ram_ss_ss_transp : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "RAM_SS_SS_WIDE")
PORT MAP(mm_rst, mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
+ u_mm_file_reg_io_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "REG_IO_DDR")
+ PORT MAP(mm_rst, mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
+
+
----------------------------------------------------------------------------
-- Source: block generator
----------------------------------------------------------------------------
@@ -273,8 +282,8 @@ BEGIN
GENERIC MAP(
g_nof_streams => c_bg_nof_output_streams,
g_in_dat_w => c_bg_buf_dat_w/c_nof_complex,
- g_frame_size_in => g_wr_chunksize,
- g_frame_size_out => g_wr_chunksize,
+ g_frame_size_in => g_frame_size_in,
+ g_frame_size_out => g_frame_size_out,
g_use_complex => c_use_complex,
g_mem_dat_w => g_mem_dat_w,
g_ena_pre_transp => g_ena_pre_transp,
@@ -337,6 +346,14 @@ BEGIN
ctlr_clk_in => dp_clk,
ctlr_rst_in => dp_rst,
+ -- MM clock + reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
-- Driver clock domain
dvr_clk => dp_clk,
dvr_rst => dp_rst,
@@ -430,3 +447,4 @@ BEGIN
);
END tb;
+