diff --git a/libraries/base/sens/hdllib.cfg b/libraries/base/sens/hdllib.cfg index fabc9009b10925c5c411ed7abc08bf2b14e6638a..928d2960b87c2aedd557c63d399445895cbbc4bd 100644 --- a/libraries/base/sens/hdllib.cfg +++ b/libraries/base/sens/hdllib.cfg @@ -11,6 +11,9 @@ synth_files = test_bench_files = tb/vhdl/tb_sens.vhd +regression_test_vhdl = + tb/vhdl/tb_sens.vhd + [modelsim_project_file] diff --git a/libraries/base/sens/tb/vhdl/tb_sens.vhd b/libraries/base/sens/tb/vhdl/tb_sens.vhd index 03f128e1dc8bae5509a59ce93f9cb48be230565a..a28f29d91195ed1d191d843fb5689da96005bb38 100644 --- a/libraries/base/sens/tb/vhdl/tb_sens.vhd +++ b/libraries/base/sens/tb/vhdl/tb_sens.vhd @@ -22,9 +22,11 @@ ENTITY tb_sens IS END tb_sens; -LIBRARY IEEE, i2c_lib; +LIBRARY IEEE, common_lib, i2c_lib; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; +USE common_lib.common_pkg.ALL; +USE common_lib.tb_common_pkg.ALL; ARCHITECTURE tb OF tb_sens IS @@ -55,6 +57,7 @@ ARCHITECTURE tb OF tb_sens IS TYPE t_sens_data_arr IS ARRAY (0 TO c_sens_temp_volt_sz-1) OF STD_LOGIC_VECTOR(c_bus_dat_w-1 DOWNTO 0); + SIGNAL tb_end : STD_LOGIC := '0'; SIGNAL clk : STD_LOGIC := '0'; SIGNAL rst : STD_LOGIC := '1'; @@ -66,14 +69,14 @@ ARCHITECTURE tb OF tb_sens IS SIGNAL sens_data : STD_LOGIC_VECTOR(c_sens_temp_volt_sz*c_bus_dat_w-1 DOWNTO 0); SIGNAL sens_data_bytes : t_sens_data_arr; + SIGNAL exp_data_bytes : t_nat_natural_arr(0 TO c_sens_temp_volt_sz-1) := (92, 147, 127, 40, 60, 70, 71, 72, 73); -- expected 9 bytes as read by SEQUENCE in sens_ctrl BEGIN - -- Run 50 us - -- Expected sens_data_bytes : 92, 147, 127, 40, 60, 70, 71, 72, 73 -- 9 bytes as read by SEQUENCE in sens_ctrl + -- run -all rst <= '0' AFTER 4*c_clk_period; - clk <= NOT clk AFTER c_clk_period/2; + clk <= NOT clk or tb_end AFTER c_clk_period/2; p_debug : PROCESS (sens_data) BEGIN @@ -81,6 +84,22 @@ BEGIN sens_data_bytes(c_sens_temp_volt_sz-1-i) <= sens_data((i+1)*c_bus_dat_w-1 DOWNTO i*c_bus_dat_w); END LOOP; END PROCESS; + + p_verify : PROCESS + BEGIN + proc_common_wait_until_high(clk, sens_evt); + proc_common_wait_until_low(clk, sens_evt); + proc_common_wait_some_cycles(clk, 10); + FOR I IN sens_data_bytes'RANGE LOOP + IF TO_UINT(sens_data_bytes(I))/=exp_data_bytes(I) THEN + REPORT "Unexpected I2C read sensors result." SEVERITY ERROR; + EXIT; + END IF; + END LOOP; + proc_common_wait_some_cycles(clk, 100); + tb_end <= '1'; + WAIT; + END PROCESS; -- I2C bus scl <= 'H'; -- model I2C pull up