From 301b584d39d2cef4cd9c8ad1f0a7cf00598c9dee Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 12 Feb 2015 09:54:36 +0000
Subject: [PATCH] Use proc from tb_diag_pkg. Added verify g_mm_broadcast_tx.
---
.../base/diag/tb/vhdl/tb_mms_diag_seq.vhd | 320 +++++-------------
1 file changed, 92 insertions(+), 228 deletions(-)
diff --git a/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd b/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
index 51388d04a3..b996da705d 100644
--- a/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
@@ -29,7 +29,6 @@
LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_lfsr_sequences_pkg.ALL;
@@ -38,183 +37,30 @@ USE common_lib.tb_common_mem_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE dp_lib.tb_dp_pkg.ALL;
+USE work.tb_diag_pkg.ALL;
ENTITY tb_mms_diag_seq IS
GENERIC (
-- general
- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
+ g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active or random flow control
-- specific
- g_data_w : NATURAL := 40; -- >= g_seq_dat_w
- g_seq_dat_w : NATURAL := 32
+ g_nof_streams : NATURAL := 2;
+ g_mm_broadcast_tx : BOOLEAN := TRUE;
+ g_data_w : NATURAL := 40; -- >= g_seq_dat_w
+ g_seq_dat_w : NATURAL := 32
);
END ENTITY tb_mms_diag_seq;
ARCHITECTURE str of tb_mms_diag_seq IS
- CONSTANT c_nof_streams : NATURAL := 1;
-
CONSTANT mm_clk_period : TIME := 8 ns; -- 125 MHz
CONSTANT dp_clk_period : TIME := 5 ns; -- 200 MHz
-
- PROCEDURE proc_readback(SIGNAL clk : IN STD_LOGIC;
- SIGNAL tx_miso : IN t_mem_miso;
- SIGNAL tx_mosi : OUT t_mem_mosi;
- SIGNAL rx_miso : IN t_mem_miso;
- SIGNAL rx_mosi : OUT t_mem_mosi;
- SIGNAL tx_init : OUT STD_LOGIC_VECTOR;
- SIGNAL tx_ctrl : OUT STD_LOGIC_VECTOR;
- SIGNAL rx_ctrl : OUT STD_LOGIC_VECTOR) IS
- BEGIN
- -- read back Tx data init
- proc_mem_mm_bus_rd(1, clk, tx_miso, tx_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- tx_init <= tx_miso.rddata(c_word_w-1 DOWNTO 0);
- -- read back Tx control
- proc_mem_mm_bus_rd(0, clk, tx_miso, tx_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- tx_ctrl <= tx_miso.rddata(c_word_w-1 DOWNTO 0);
- -- read back Rx control
- proc_mem_mm_bus_rd(0, clk, rx_miso, rx_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- rx_ctrl <= rx_miso.rddata(c_word_w-1 DOWNTO 0);
- END proc_readback;
-
- PROCEDURE proc_enable_tx(CONSTANT c_pattern : IN STRING; -- "PSRG", "CNTR"
- CONSTANT c_tx_init : IN NATURAL;
- SIGNAL mm_clk : IN STD_LOGIC;
- SIGNAL dp_clk : IN STD_LOGIC;
- SIGNAL tx_miso : IN t_mem_miso; -- tx ctrl
- SIGNAL tx_mosi : OUT t_mem_mosi;
- SIGNAL rx_miso : IN t_mem_miso; -- rx ctrl
- SIGNAL rx_mosi : OUT t_mem_mosi;
- SIGNAL tx_init : OUT STD_LOGIC_VECTOR; -- readback
- SIGNAL tx_ctrl : OUT STD_LOGIC_VECTOR;
- SIGNAL rx_ctrl : OUT STD_LOGIC_VECTOR) IS
- CONSTANT c_en : NATURAL := 1;
- VARIABLE v_sel : NATURAL;
- VARIABLE v_ctlr : NATURAL;
- BEGIN
- IF c_pattern="PSRG" THEN
- v_sel := 0; -- pseudo random data
- ELSE
- v_sel := 1; -- counter data
- END IF;
- v_ctlr := v_sel * 2 + c_en; -- bits [1:0]
- -- Enable Tx
- proc_mem_mm_bus_wr(0, v_ctlr, mm_clk, tx_miso, tx_mosi);
- proc_mem_mm_bus_wr(1, c_tx_init, mm_clk, tx_miso, tx_mosi);
- proc_common_wait_some_cycles(mm_clk, dp_clk, 10); -- wait for clock domain crossing
- proc_readback(mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, tx_init, tx_ctrl, rx_ctrl);
- END proc_enable_tx;
-
- PROCEDURE proc_enable_rx(CONSTANT c_pattern : IN STRING; -- "PSRG", "CNTR"
- SIGNAL mm_clk : IN STD_LOGIC;
- SIGNAL dp_clk : IN STD_LOGIC;
- SIGNAL tx_miso : IN t_mem_miso; -- tx ctrl
- SIGNAL tx_mosi : OUT t_mem_mosi;
- SIGNAL rx_miso : IN t_mem_miso; -- rx ctrl
- SIGNAL rx_mosi : OUT t_mem_mosi;
- SIGNAL tx_init : OUT STD_LOGIC_VECTOR; -- readback
- SIGNAL tx_ctrl : OUT STD_LOGIC_VECTOR;
- SIGNAL rx_ctrl : OUT STD_LOGIC_VECTOR) IS
- CONSTANT c_en : NATURAL := 1;
- VARIABLE v_sel : NATURAL;
- VARIABLE v_ctlr : NATURAL;
- BEGIN
- IF c_pattern="PSRG" THEN
- v_sel := 0; -- pseudo random data
- ELSE
- v_sel := 1; -- counter data
- END IF;
- v_ctlr := v_sel * 2 + c_en; -- bits [1:0]
- proc_mem_mm_bus_wr(0, v_ctlr, mm_clk, rx_miso, rx_mosi);
- proc_common_wait_some_cycles(mm_clk, dp_clk, 10); -- wait for clock domain crossing
- proc_readback(mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, tx_init, tx_ctrl, rx_ctrl);
- END proc_enable_rx;
-
- PROCEDURE proc_disable_tx(SIGNAL mm_clk : IN STD_LOGIC;
- SIGNAL dp_clk : IN STD_LOGIC;
- SIGNAL tx_miso : IN t_mem_miso; -- tx ctrl
- SIGNAL tx_mosi : OUT t_mem_mosi;
- SIGNAL rx_miso : IN t_mem_miso; -- rx ctrl
- SIGNAL rx_mosi : OUT t_mem_mosi;
- SIGNAL tx_init : OUT STD_LOGIC_VECTOR; -- readback
- SIGNAL tx_ctrl : OUT STD_LOGIC_VECTOR;
- SIGNAL rx_ctrl : OUT STD_LOGIC_VECTOR) IS
- BEGIN
- proc_mem_mm_bus_wr(0, 0, mm_clk, tx_miso, tx_mosi);
- proc_common_wait_some_cycles(mm_clk, dp_clk, 10); -- wait for clock domain crossing
- proc_readback(mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, tx_init, tx_ctrl, rx_ctrl);
- END proc_disable_tx;
-
- PROCEDURE proc_disable_rx(SIGNAL mm_clk : IN STD_LOGIC;
- SIGNAL dp_clk : IN STD_LOGIC;
- SIGNAL tx_miso : IN t_mem_miso; -- tx ctrl
- SIGNAL tx_mosi : OUT t_mem_mosi;
- SIGNAL rx_miso : IN t_mem_miso; -- rx ctrl
- SIGNAL rx_mosi : OUT t_mem_mosi;
- SIGNAL tx_init : OUT STD_LOGIC_VECTOR; -- readback
- SIGNAL tx_ctrl : OUT STD_LOGIC_VECTOR;
- SIGNAL rx_ctrl : OUT STD_LOGIC_VECTOR) IS
- BEGIN
- proc_mem_mm_bus_wr(0, 0, mm_clk, rx_miso, rx_mosi);
- proc_common_wait_some_cycles(mm_clk, dp_clk, 10); -- wait for clock domain crossing
- proc_readback(mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, tx_init, tx_ctrl, rx_ctrl);
- END proc_disable_rx;
-
- TYPE t_tb_mode_enum IS (
- s_off,
- s_expect_ok,
- s_expect_error,
- s_expect_no_result
- );
-
- PROCEDURE proc_read_and_verify_rx_stat(SIGNAL clk : IN STD_LOGIC;
- SIGNAL mm_miso : IN t_mem_miso;
- SIGNAL mm_mosi : OUT t_mem_mosi;
- SIGNAL tb_mode : INOUT t_tb_mode_enum;
- SIGNAL tb_verify : OUT STD_LOGIC;
- SIGNAL rx_stat : INOUT STD_LOGIC_VECTOR) IS
- BEGIN
- -- Read
- proc_mem_mm_bus_rd(1, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- rx_stat <= mm_miso.rddata(c_word_w-1 DOWNTO 0);
- proc_common_wait_some_cycles(clk, 1);
-
- -- Issue tb_verify pulse eg. to easy recognition in Wave window
- tb_verify <= '1';
- proc_common_wait_some_cycles(clk, 1);
- tb_verify <= '0';
-
- -- Verify
- IF tb_mode=s_expect_ok THEN
- IF rx_stat(1)/='0' THEN
- REPORT "Wrong diag result: no valid result." SEVERITY ERROR;
- ELSIF rx_stat(0)/='0' THEN
- REPORT "Wrong diag result: one or more data errors." SEVERITY ERROR;
- END IF;
- ELSIF tb_mode=s_expect_error THEN
- IF rx_stat(1)/='0' THEN
- REPORT "Wrong diag result: no valid result." SEVERITY ERROR;
- ELSIF rx_stat(0)/='1' THEN
- REPORT "Wrong diag result: must detect data errors." SEVERITY ERROR;
- END IF;
- ELSIF tb_mode=s_expect_no_result THEN
- IF rx_stat(1)/='1' THEN
- REPORT "Wrong diag result: must indicate no valid result." SEVERITY ERROR;
- END IF;
- ELSE
- REPORT "Unknown verify mode" SEVERITY FAILURE;
- END IF;
- END proc_read_and_verify_rx_stat;
SIGNAL random : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS=>'0'); -- use different lengths to have different random sequences
- SIGNAL pulse : STD_LOGIC;
SIGNAL ready : STD_LOGIC;
SIGNAL tb_end : STD_LOGIC := '0';
- SIGNAL tb_mode : t_tb_mode_enum := s_off;
+ SIGNAL tb_mode : t_tb_diag_seq_mode_enum := s_off;
SIGNAL tb_verify : STD_LOGIC := '0';
SIGNAL mm_rst : STD_LOGIC;
SIGNAL mm_clk : STD_LOGIC := '0';
@@ -227,18 +73,15 @@ ARCHITECTURE str of tb_mms_diag_seq IS
SIGNAL reg_rx_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_rx_miso : t_mem_miso;
- SIGNAL tx_ctrl : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- SIGNAL tx_init : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- SIGNAL rx_ctrl : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- SIGNAL rx_stat : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
-
- SIGNAL tx_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
- SIGNAL tx_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL rd_reg : t_diag_seq_mm_reg;
+
+ SIGNAL tx_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL tx_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL force_low_error : STD_LOGIC;
SIGNAL force_replicate_error : STD_LOGIC;
- SIGNAL rx_snk_in_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL rx_snk_in_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
BEGIN
@@ -256,7 +99,7 @@ BEGIN
ready <= '1' WHEN g_flow_control_verify=e_active ELSE
random(random'HIGH) WHEN g_flow_control_verify=e_random ELSE
- pulse WHEN g_flow_control_verify=e_pulse;
+ '1';
tx_src_in_arr <= func_dp_stream_arr_set(tx_src_in_arr, ready, "READY");
@@ -264,103 +107,124 @@ BEGIN
-- Stimuli
------------------------------------------------------------------------------
- p_stimuli : PROCESS
+ p_stimuli_and_verify : PROCESS
BEGIN
force_low_error <= '0';
force_replicate_error <= '0';
tb_mode <= s_off;
proc_common_wait_until_low(mm_clk, mm_rst);
proc_common_wait_some_cycles(mm_clk, 10);
+ proc_diag_seq_verify(mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg);
-------------------------------------------------------------------------
-- Verify Tx and Rx on and both with the same pattern
-------------------------------------------------------------------------
tb_mode <= s_expect_ok;
- proc_disable_tx(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tx_init, tx_ctrl, rx_ctrl);
- proc_disable_rx(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tx_init, tx_ctrl, rx_ctrl);
- proc_enable_tx("CNTR", 17, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tx_init, tx_ctrl, rx_ctrl);
- proc_enable_rx("CNTR", mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tx_init, tx_ctrl, rx_ctrl);
+ proc_diag_seq_tx_disable(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
+ proc_diag_seq_rx_disable(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
+ proc_diag_seq_tx_enable("CNTR", 17, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
+ proc_diag_seq_rx_enable("CNTR", mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
-- Run test and read and verify Rx status
- proc_common_wait_some_cycles(mm_clk, 100);
- proc_read_and_verify_rx_stat(mm_clk, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rx_stat);
+ proc_common_wait_some_cycles(mm_clk, 200);
+ proc_diag_seq_verify(mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg);
-------------------------------------------------------------------------
-- Verify Tx and Rx on but with different pattern
-------------------------------------------------------------------------
tb_mode <= s_expect_error;
- proc_enable_tx("PSRG", 17, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tx_init, tx_ctrl, rx_ctrl);
+ proc_diag_seq_tx_enable("PSRG", 17, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
-- Run test and read and verify Rx status
- proc_common_wait_some_cycles(mm_clk, 100);
- proc_read_and_verify_rx_stat(mm_clk, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rx_stat);
+ proc_common_wait_some_cycles(mm_clk, 200);
+ proc_diag_seq_verify(mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg);
-------------------------------------------------------------------------
-- Verify Rx off
-------------------------------------------------------------------------
tb_mode <= s_expect_no_result;
- proc_disable_rx(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tx_init, tx_ctrl, rx_ctrl);
+ proc_diag_seq_rx_disable(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
-- Run test and read and verify Rx status
- proc_common_wait_some_cycles(mm_clk, 100);
- proc_read_and_verify_rx_stat(mm_clk, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rx_stat);
+ proc_common_wait_some_cycles(mm_clk, 200);
+ proc_diag_seq_verify(mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg);
- -------------------------------------------------------------------------
- -- Verify Tx and Rx on with error in sequence low part
- -------------------------------------------------------------------------
- tb_mode <= s_expect_ok;
- proc_disable_tx(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tx_init, tx_ctrl, rx_ctrl);
- proc_disable_rx(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tx_init, tx_ctrl, rx_ctrl);
- proc_enable_tx("CNTR", 17, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tx_init, tx_ctrl, rx_ctrl);
- proc_enable_rx("CNTR", mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tx_init, tx_ctrl, rx_ctrl);
-
- -- Run test and read and verify Rx status
- proc_common_wait_some_cycles(mm_clk, 100);
- proc_read_and_verify_rx_stat(mm_clk, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rx_stat);
-
- tb_mode <= s_expect_error;
- proc_common_wait_some_cycles(dp_clk, 1);
- force_low_error <= '1';
- proc_common_wait_some_cycles(dp_clk, 1);
- force_low_error <= '0';
- proc_common_wait_some_cycles(mm_clk, 100);
- proc_read_and_verify_rx_stat(mm_clk, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rx_stat);
-
- -------------------------------------------------------------------------
- -- Verify Tx and Rx on with error in sequence replicate part
- -------------------------------------------------------------------------
- tb_mode <= s_expect_ok;
- proc_disable_tx(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tx_init, tx_ctrl, rx_ctrl);
- proc_disable_rx(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tx_init, tx_ctrl, rx_ctrl);
- proc_enable_tx("CNTR", 17, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tx_init, tx_ctrl, rx_ctrl);
- proc_enable_rx("CNTR", mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tx_init, tx_ctrl, rx_ctrl);
-
- -- Run test and read and verify Rx status
- proc_common_wait_some_cycles(mm_clk, 100);
- proc_read_and_verify_rx_stat(mm_clk, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rx_stat);
-
- tb_mode <= s_expect_error;
- proc_common_wait_some_cycles(dp_clk, 1);
- force_replicate_error <= '1';
- proc_common_wait_some_cycles(dp_clk, 1);
- force_replicate_error <= '0';
- proc_common_wait_some_cycles(mm_clk, 100);
- proc_read_and_verify_rx_stat(mm_clk, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rx_stat);
+ IF g_mm_broadcast_tx=FALSE THEN
+ -------------------------------------------------------------------------
+ -- Verify Tx and Rx on with error in sequence low part
+ -------------------------------------------------------------------------
+ tb_mode <= s_expect_ok;
+ proc_diag_seq_tx_disable(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
+ proc_diag_seq_rx_disable(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
+ proc_diag_seq_tx_enable("CNTR", 17, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
+ proc_diag_seq_rx_enable("CNTR", mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
+
+ -- Run test and read and verify Rx status
+ proc_common_wait_some_cycles(mm_clk, 200);
+ proc_diag_seq_verify(mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg);
+
+ tb_mode <= s_expect_error;
+ proc_common_wait_some_cycles(dp_clk, 1);
+ force_low_error <= '1';
+ proc_common_wait_some_cycles(dp_clk, 1);
+ force_low_error <= '0';
+ proc_common_wait_some_cycles(mm_clk, 200);
+ proc_diag_seq_verify(mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg);
+
+ -------------------------------------------------------------------------
+ -- Verify Tx and Rx on with error in sequence replicate part
+ -------------------------------------------------------------------------
+ tb_mode <= s_expect_ok;
+ proc_diag_seq_tx_disable(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
+ proc_diag_seq_rx_disable(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
+ proc_diag_seq_tx_enable("CNTR", 17, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
+ proc_diag_seq_rx_enable("CNTR", mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
+
+ -- Run test and read and verify Rx status
+ proc_common_wait_some_cycles(mm_clk, 200);
+ proc_diag_seq_verify(mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg);
+
+ tb_mode <= s_expect_error;
+ proc_common_wait_some_cycles(dp_clk, 1);
+ force_replicate_error <= '1';
+ proc_common_wait_some_cycles(dp_clk, 1);
+ force_replicate_error <= '0';
+ proc_common_wait_some_cycles(mm_clk, 200);
+ proc_diag_seq_verify(mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg);
+ END IF;
-------------------------------------------------------------------------
-- Both off
-------------------------------------------------------------------------
tb_mode <= s_off;
- proc_disable_tx(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tx_init, tx_ctrl, rx_ctrl);
+ proc_diag_seq_tx_disable(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
+ proc_common_wait_some_cycles(mm_clk, 100);
+ proc_diag_seq_verify(mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg);
proc_common_wait_some_cycles(mm_clk, 10);
tb_end <= '1';
WAIT;
END PROCESS;
+ p_verify_mm_broadcast : PROCESS(rx_snk_in_arr)
+ VARIABLE v_snk_in : t_dp_sosi;
+ BEGIN
+ IF g_mm_broadcast_tx=TRUE AND g_nof_streams>1 THEN
+ v_snk_in := rx_snk_in_arr(0);
+ FOR I IN 1 TO g_nof_streams-1 LOOP
+ IF v_snk_in/=rx_snk_in_arr(I) THEN
+ REPORT "Wrong diag result: for g_mm_broadcast_tx=TRUE all streams should carry the same data." SEVERITY ERROR;
+ EXIT;
+ END IF;
+ END LOOP;
+ END IF;
+ END PROCESS;
+
+
u_mms_diag_tx_seq: ENTITY WORK.mms_diag_tx_seq
GENERIC MAP(
- g_nof_streams => c_nof_streams,
- g_seq_dat_w => g_seq_dat_w
+ g_mm_broadcast => g_mm_broadcast_tx,
+ g_nof_streams => g_nof_streams,
+ g_seq_dat_w => g_seq_dat_w
)
PORT MAP(
-- Clocks and reset
@@ -380,7 +244,7 @@ BEGIN
u_mms_diag_rx_seq: ENTITY WORK.mms_diag_rx_seq
GENERIC MAP(
- g_nof_streams => c_nof_streams,
+ g_nof_streams => g_nof_streams,
g_seq_dat_w => g_seq_dat_w,
g_data_w => g_data_w
)
--
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