diff --git a/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3.vhd b/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3.vhd
index b9cf00ec52a8ad37832223625b012cf49a107604..6b5c996bdac5c12415a499d1a04cbbfc8304f0e5 100644
--- a/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3.vhd
+++ b/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3.vhd
@@ -32,10 +32,18 @@
-- . [ 8 CB sets * 3 10G ] * [ packed data ]
-- (<--- 24 streams --->) * (<-- 9 Gbps -->)
-- (<--- 24 streams * 9 Gbps = 216 Gbps -->)
--- Output:
--- . TODO
+-- Output: QSFP_0_TX, QSFP_1_TX
+-- . [ 8 CB sets * 10G ] * [ packed data ]
+-- . (<--- 8 streams --->) * (<-- 1.6875 Gbps -->)
+-- (<--- 8 streams * 1.6875 Gbps = 13.5 Gbps -->)
-- Details:
--- . TODO
+-- . Even though the output is only 13.5Gbps, it needs to be carried on 8
+-- separate optical fibers such that each fiber carries its own CB set.
+-- Each of the 8 fibers (CB sets) connects to its own switch 0..7,
+-- implementing a physical transpose:
+-- . CB set 0 (CB 0...5) -> switch 0 -> GPU nodes 0...5
+-- . ..
+-- . CB set 7 (CB 30..39) -> switch 7 -> GPU nodes 30..39
-- FIXME I've put the data dimension on the very right of the serial dimensions,
-- and the time interval behind an '@' on the right, too. Looking at
@@ -109,17 +117,17 @@ ENTITY arts_unb2b_sc3 IS
PMBUS_ALERT : IN STD_LOGIC := '0';
-- front transceivers
- QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- Input
QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
@@ -133,148 +141,6 @@ END arts_unb2b_sc3;
ARCHITECTURE str OF arts_unb2b_sc3 IS
-
- -- Firmware version x.y
- CONSTANT c_fw_version : t_unb2_board_fw_version := (1, 1);
- CONSTANT c_mm_clk_freq : NATURAL := c_unb2_board_mm_clk_freq_125M;
-
- -- 1GbE
- CONSTANT c_use_1GbE : BOOLEAN := FALSE;
- CONSTANT c_nof_streams_1GbE : NATURAL := sel_a_b(c_use_1GbE,1,0); --sel_a_b(c_use_1GbE,c_unb2_board_nof_eth,0);
-
- -- 10GbE
- CONSTANT c_nof_streams_qsfp : NATURAL := 24;
- CONSTANT c_nof_qsfp_bus : NATURAL := 6;
- CONSTANT c_def_10GbE_block_size : NATURAL := 700; -- (700/1000) * 200MHz * 64b = 8.96Gbps user rate (excl. header overhead (16 words/packet) )
-
- -- System
- SIGNAL cs_sim : STD_LOGIC;
-
- SIGNAL ext_clk200 : STD_LOGIC;
- SIGNAL ext_rst200 : STD_LOGIC;
-
- SIGNAL xo_ethclk : STD_LOGIC;
- SIGNAL xo_rst : STD_LOGIC;
- SIGNAL xo_rst_n : STD_LOGIC;
-
- SIGNAL mm_clk : STD_LOGIC;
- SIGNAL mm_rst : STD_LOGIC;
-
- SIGNAL dp_clk : STD_LOGIC;
- SIGNAL dp_rst : STD_LOGIC;
-
- SIGNAL mb_I_ref_rst : STD_LOGIC;
- SIGNAL mb_II_ref_rst : STD_LOGIC;
-
- -- PIOs
- SIGNAL pout_wdi : STD_LOGIC;
-
- -- WDI override
- SIGNAL reg_wdi_mosi : t_mem_mosi;
- SIGNAL reg_wdi_miso : t_mem_miso;
-
- -- PPSH
- SIGNAL reg_ppsh_mosi : t_mem_mosi;
- SIGNAL reg_ppsh_miso : t_mem_miso;
-
- -- UniBoard system info
- SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
- SIGNAL reg_unb_system_info_miso : t_mem_miso;
- SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
- SIGNAL rom_unb_system_info_miso : t_mem_miso;
-
- -- UniBoard I2C sens
- SIGNAL reg_unb_sens_mosi : t_mem_mosi;
- SIGNAL reg_unb_sens_miso : t_mem_miso;
-
- -- pm bus
- SIGNAL reg_unb_pmbus_mosi : t_mem_mosi;
- SIGNAL reg_unb_pmbus_miso : t_mem_miso;
-
- -- FPGA sensors
- SIGNAL reg_fpga_temp_sens_mosi : t_mem_mosi;
- SIGNAL reg_fpga_temp_sens_miso : t_mem_miso;
- SIGNAL reg_fpga_voltage_sens_mosi : t_mem_mosi;
- SIGNAL reg_fpga_voltage_sens_miso : t_mem_miso;
-
- -- eth1g ch0
- SIGNAL eth1g_eth0_mm_rst : STD_LOGIC;
- SIGNAL eth1g_eth0_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
- SIGNAL eth1g_eth0_tse_miso : t_mem_miso;
- SIGNAL eth1g_eth0_reg_mosi : t_mem_mosi; -- ETH control and status registers
- SIGNAL eth1g_eth0_reg_miso : t_mem_miso;
- SIGNAL eth1g_eth0_reg_interrupt : STD_LOGIC; -- Interrupt
- SIGNAL eth1g_eth0_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
- SIGNAL eth1g_eth0_ram_miso : t_mem_miso;
-
- -- eth1g ch1
- SIGNAL eth1g_eth1_mm_rst : STD_LOGIC;
- SIGNAL eth1g_eth1_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
- SIGNAL eth1g_eth1_tse_miso : t_mem_miso;
- SIGNAL eth1g_eth1_reg_mosi : t_mem_mosi; -- ETH control and status registers
- SIGNAL eth1g_eth1_reg_miso : t_mem_miso;
- SIGNAL eth1g_eth1_reg_interrupt : STD_LOGIC; -- Interrupt
- SIGNAL eth1g_eth1_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
- SIGNAL eth1g_eth1_ram_miso : t_mem_miso;
-
- -- EPCS read
- SIGNAL reg_dpmm_data_mosi : t_mem_mosi;
- SIGNAL reg_dpmm_data_miso : t_mem_miso;
- SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi;
- SIGNAL reg_dpmm_ctrl_miso : t_mem_miso;
-
- -- EPCS write
- SIGNAL reg_mmdp_data_mosi : t_mem_mosi;
- SIGNAL reg_mmdp_data_miso : t_mem_miso;
- SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi;
- SIGNAL reg_mmdp_ctrl_miso : t_mem_miso;
-
- -- EPCS status/control
- SIGNAL reg_epcs_mosi : t_mem_mosi;
- SIGNAL reg_epcs_miso : t_mem_miso;
-
- -- Remote Update
- SIGNAL reg_remu_mosi : t_mem_mosi;
- SIGNAL reg_remu_miso : t_mem_miso;
-
- -- 10GbE
- SIGNAL i_QSFP_TX : t_unb2_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0);
- SIGNAL i_QSFP_RX : t_unb2_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0);
-
- SIGNAL unb2_board_10gbe_serial_tx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0);
- SIGNAL unb2_board_10gbe_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0);
-
- SIGNAL unb2_board_front_io_serial_tx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL unb2_board_front_io_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0);
-
- SIGNAL unb2_board_10gbe_snk_in_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL unb2_board_10gbe_snk_out_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
- SIGNAL unb2_board_10gbe_src_out_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL unb2_board_10gbe_src_in_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
-
- SIGNAL reg_tr_10GbE_qsfp_ring_mosi : t_mem_mosi;
- SIGNAL reg_tr_10GbE_qsfp_ring_miso : t_mem_miso;
-
- SIGNAL reg_eth10g_qsfp_ring_mosi : t_mem_mosi;
- SIGNAL reg_eth10g_qsfp_ring_miso : t_mem_miso;
-
- SIGNAL reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi : t_mem_mosi;
- SIGNAL reg_ip_arria10_e1sg_phy_10gbase_r_24_miso : t_mem_miso;
-
- -- Interface: 1GbE UDP streaming ports
- SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
- SIGNAL eth1g_udp_tx_siso_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
- SIGNAL eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
- SIGNAL eth1g_udp_rx_siso_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
-
- -- QSFP leds
- SIGNAL unb2_board_qsfp_leds_tx_snk_in_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL unb2_board_qsfp_leds_tx_src_in_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
- SIGNAL unb2_board_qsfp_leds_rx_snk_in_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
-
- SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0);
- SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0);
-
-------------------------------------------------------------------------------
-- ARTS SC3 constants
@@ -296,6 +162,81 @@ ARCHITECTURE str OF arts_unb2b_sc3 IS
-------------------------------------------------------------------------------
SIGNAL arts_unb2b_sc3_input_src_out_2arr : t_dp_sosi_2arr_8(c_nof_cbsets-1 DOWNTO 0); -- 8 CB sets * 8 dishes
+ -------------------------------------------------------------------------------
+ -- ctrl_unb2_board
+ -------------------------------------------------------------------------------
+ CONSTANT c_fw_version : t_unb2_board_fw_version := (1, 1);
+ CONSTANT c_mm_clk_freq : NATURAL := c_unb2_board_mm_clk_freq_125M;
+ CONSTANT c_use_1GbE : BOOLEAN := FALSE;
+ CONSTANT c_nof_streams_1GbE : NATURAL := sel_a_b(c_use_1GbE,1,0); --sel_a_b(c_use_1GbE,c_unb2_board_nof_eth,0);
+ CONSTANT c_nof_streams_qsfp : NATURAL := 24;
+ CONSTANT c_nof_qsfp_bus : NATURAL := 6;
+ CONSTANT c_def_10GbE_block_size : NATURAL := 700; -- (700/1000) * 200MHz * 64b = 8.96Gbps user rate (excl. header overhead (16 words/packet) )
+
+ SIGNAL ext_clk200 : STD_LOGIC;
+ SIGNAL ext_rst200 : STD_LOGIC;
+ SIGNAL xo_ethclk : STD_LOGIC;
+ SIGNAL xo_rst : STD_LOGIC;
+ SIGNAL xo_rst_n : STD_LOGIC;
+ SIGNAL mm_clk : STD_LOGIC;
+ SIGNAL mm_rst : STD_LOGIC;
+ SIGNAL dp_clk : STD_LOGIC;
+ SIGNAL dp_rst : STD_LOGIC;
+ SIGNAL mb_I_ref_rst : STD_LOGIC;
+ SIGNAL mb_II_ref_rst : STD_LOGIC;
+ SIGNAL pout_wdi : STD_LOGIC;
+
+ SIGNAL reg_wdi_mosi : t_mem_mosi;
+ SIGNAL reg_wdi_miso : t_mem_miso;
+ SIGNAL reg_ppsh_mosi : t_mem_mosi;
+ SIGNAL reg_ppsh_miso : t_mem_miso;
+ SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL reg_unb_system_info_miso : t_mem_miso;
+ SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL rom_unb_system_info_miso : t_mem_miso;
+ SIGNAL reg_unb_sens_mosi : t_mem_mosi;
+ SIGNAL reg_unb_sens_miso : t_mem_miso;
+ SIGNAL reg_unb_pmbus_mosi : t_mem_mosi;
+ SIGNAL reg_unb_pmbus_miso : t_mem_miso;
+ SIGNAL reg_fpga_temp_sens_mosi : t_mem_mosi;
+ SIGNAL reg_fpga_temp_sens_miso : t_mem_miso;
+ SIGNAL reg_fpga_voltage_sens_mosi : t_mem_mosi;
+ SIGNAL reg_fpga_voltage_sens_miso : t_mem_miso;
+ SIGNAL eth1g_eth0_mm_rst : STD_LOGIC;
+ SIGNAL eth1g_eth0_tse_mosi : t_mem_mosi;
+ SIGNAL eth1g_eth0_tse_miso : t_mem_miso;
+ SIGNAL eth1g_eth0_reg_mosi : t_mem_mosi;
+ SIGNAL eth1g_eth0_reg_miso : t_mem_miso;
+ SIGNAL eth1g_eth0_reg_interrupt : STD_LOGIC;
+ SIGNAL eth1g_eth0_ram_mosi : t_mem_mosi;
+ SIGNAL eth1g_eth0_ram_miso : t_mem_miso;
+ SIGNAL eth1g_eth1_mm_rst : STD_LOGIC;
+ SIGNAL eth1g_eth1_tse_mosi : t_mem_mosi;
+ SIGNAL eth1g_eth1_tse_miso : t_mem_miso;
+ SIGNAL eth1g_eth1_reg_mosi : t_mem_mosi;
+ SIGNAL eth1g_eth1_reg_miso : t_mem_miso;
+ SIGNAL eth1g_eth1_reg_interrupt : STD_LOGIC;
+ SIGNAL eth1g_eth1_ram_mosi : t_mem_mosi;
+ SIGNAL eth1g_eth1_ram_miso : t_mem_miso;
+ SIGNAL reg_dpmm_data_mosi : t_mem_mosi;
+ SIGNAL reg_dpmm_data_miso : t_mem_miso;
+ SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi;
+ SIGNAL reg_dpmm_ctrl_miso : t_mem_miso;
+ SIGNAL reg_mmdp_data_mosi : t_mem_mosi;
+ SIGNAL reg_mmdp_data_miso : t_mem_miso;
+ SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi;
+ SIGNAL reg_mmdp_ctrl_miso : t_mem_miso;
+ SIGNAL reg_epcs_mosi : t_mem_mosi;
+ SIGNAL reg_epcs_miso : t_mem_miso;
+ SIGNAL reg_remu_mosi : t_mem_mosi;
+ SIGNAL reg_remu_miso : t_mem_miso;
+ SIGNAL reg_tr_10GbE_qsfp_ring_mosi : t_mem_mosi;
+ SIGNAL reg_tr_10GbE_qsfp_ring_miso : t_mem_miso;
+ SIGNAL reg_eth10g_qsfp_ring_mosi : t_mem_mosi;
+ SIGNAL reg_eth10g_qsfp_ring_miso : t_mem_miso;
+ SIGNAL reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi : t_mem_mosi;
+ SIGNAL reg_ip_arria10_e1sg_phy_10gbase_r_24_miso : t_mem_miso;
+
BEGIN
-------------------------------------------------------------------------------
@@ -507,10 +448,7 @@ BEGIN
g_dp_clk_use_pll => TRUE,
g_factory_image => g_factory_image
)
- PORT MAP (
- -- Clock an reset signals
- cs_sim => cs_sim,
-
+ PORT MAP (
ext_clk200 => ext_clk200,
ext_rst200 => ext_rst200,
@@ -590,12 +528,6 @@ BEGIN
eth1g_ram_mosi => eth1g_eth0_ram_mosi,
eth1g_ram_miso => eth1g_eth0_ram_miso,
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
- udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
- udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
-
-- FPGA pins
-- . General
CLK => CLK,