From 2f89ae19092fc38e24cbe1e1ffc561b5400cb743 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Fri, 28 Jan 2022 14:17:47 +0100
Subject: [PATCH] Pass on g_data_signed, to support preserving sign extension
at FIFO output.
---
.../libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd | 1 +
libraries/base/dp/src/vhdl/dp_fifo_dc.vhd | 2 ++
libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd | 2 ++
libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd | 5 ++++-
libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd | 4 +++-
libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd | 4 +++-
libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd | 4 +++-
libraries/base/dp/src/vhdl/dp_fifo_sc.vhd | 2 ++
8 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index 7be0497290..54d4befcf2 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -482,6 +482,7 @@ BEGIN
GENERIC MAP (
g_nof_streams => c_sdp_S_pn,
g_data_w => c_sdp_W_adc,
+ g_data_signed => TRUE,
g_bsn_w => c_bs_bsn_w,
g_use_empty => FALSE,
g_use_ctrl => TRUE,
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
index d36166ae61..f5638052d7 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
@@ -33,6 +33,7 @@ ENTITY dp_fifo_dc IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_data_signed : BOOLEAN := FALSE; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
g_bsn_w : NATURAL := 1;
g_empty_w : NATURAL := 1;
g_channel_w : NATURAL := 1;
@@ -76,6 +77,7 @@ BEGIN
g_technology => g_technology,
g_use_dual_clock => TRUE,
g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
g_bsn_w => g_bsn_w,
g_empty_w => g_empty_w,
g_channel_w => g_channel_w,
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
index e788c2b579..45d65e14cd 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
@@ -36,6 +36,7 @@ ENTITY dp_fifo_dc_arr IS
g_technology : NATURAL := c_tech_select_default;
g_nof_streams : NATURAL := 1;
g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_data_signed : BOOLEAN := FALSE; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
g_bsn_w : NATURAL := 1;
g_empty_w : NATURAL := 1;
g_channel_w : NATURAL := 1;
@@ -84,6 +85,7 @@ BEGIN
g_nof_streams => g_nof_streams,
g_use_dual_clock => TRUE,
g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
g_bsn_w => g_bsn_w,
g_empty_w => g_empty_w,
g_channel_w => g_channel_w,
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
index 655faa6c83..ef89bbe422 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
@@ -67,7 +67,8 @@ ENTITY dp_fifo_fill_core IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_use_dual_clock : BOOLEAN := FALSE;
- g_data_w : NATURAL := 16;
+ g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_data_signed : BOOLEAN := FALSE; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
g_bsn_w : NATURAL := 1;
g_empty_w : NATURAL := 1;
g_channel_w : NATURAL := 1;
@@ -161,6 +162,7 @@ BEGIN
GENERIC MAP (
g_technology => g_technology,
g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
g_bsn_w => g_bsn_w,
g_empty_w => g_empty_w,
g_channel_w => g_channel_w,
@@ -199,6 +201,7 @@ BEGIN
GENERIC MAP (
g_technology => g_technology,
g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
g_bsn_w => g_bsn_w,
g_empty_w => g_empty_w,
g_channel_w => g_channel_w,
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd
index 4939abf2ce..53f57dc77f 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd
@@ -33,7 +33,8 @@ USE technology_lib.technology_select_pkg.ALL;
ENTITY dp_fifo_fill_dc IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
- g_data_w : NATURAL := 16;
+ g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_data_signed : BOOLEAN := FALSE; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
g_bsn_w : NATURAL := 1;
g_empty_w : NATURAL := 1;
g_channel_w : NATURAL := 1;
@@ -81,6 +82,7 @@ BEGIN
g_technology => g_technology,
g_use_dual_clock => TRUE,
g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
g_bsn_w => g_bsn_w,
g_empty_w => g_empty_w,
g_channel_w => g_channel_w,
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
index cd8c20ec66..b38116a290 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
@@ -46,7 +46,8 @@ ENTITY dp_fifo_fill_eop IS
g_technology : NATURAL := c_tech_select_default;
g_note_is_ful : BOOLEAN := TRUE;
g_use_dual_clock : BOOLEAN := FALSE;
- g_data_w : NATURAL := 16;
+ g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_data_signed : BOOLEAN := FALSE; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
g_bsn_w : NATURAL := 1;
g_empty_w : NATURAL := 1;
g_channel_w : NATURAL := 1;
@@ -151,6 +152,7 @@ BEGIN
g_note_is_ful => g_note_is_ful,
g_use_dual_clock => g_use_dual_clock,
g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
g_bsn_w => g_bsn_w,
g_empty_w => g_empty_w,
g_channel_w => g_channel_w,
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
index 86d1151bd3..6c677dc7e3 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
@@ -33,7 +33,8 @@ USE technology_lib.technology_select_pkg.ALL;
ENTITY dp_fifo_fill_sc IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
- g_data_w : NATURAL := 16;
+ g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_data_signed : BOOLEAN := FALSE; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
g_bsn_w : NATURAL := 1;
g_empty_w : NATURAL := 1;
g_channel_w : NATURAL := 1;
@@ -81,6 +82,7 @@ BEGIN
g_technology => g_technology,
g_use_dual_clock => FALSE,
g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
g_bsn_w => g_bsn_w,
g_empty_w => g_empty_w,
g_channel_w => g_channel_w,
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
index a504b5ba0a..6421ae0d6a 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
@@ -35,6 +35,7 @@ ENTITY dp_fifo_sc IS
g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
g_use_lut : BOOLEAN := FALSE; -- when TRUE then force using LUTs instead of block RAM
g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_data_signed : BOOLEAN := FALSE; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
g_bsn_w : NATURAL := 1;
g_empty_w : NATURAL := 1;
g_channel_w : NATURAL := 1;
@@ -77,6 +78,7 @@ BEGIN
g_use_dual_clock => FALSE,
g_use_lut_sc => g_use_lut,
g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
g_bsn_w => g_bsn_w,
g_empty_w => g_empty_w,
g_channel_w => g_channel_w,
--
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