diff --git a/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys b/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
index 0776996779c75dcf4e92d1fc534c60fae1018ec7..a664ad91c196138ad086c25c8629125b80ec493b 100644
--- a/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
+++ b/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
@@ -29,7 +29,7 @@
{
datum baseAddress
{
- value = "303104";
+ value = "24576";
type = "String";
}
}
@@ -178,7 +178,7 @@
{
datum _sortIndex
{
- value = "29";
+ value = "28";
type = "int";
}
}
@@ -194,7 +194,7 @@
{
datum _sortIndex
{
- value = "27";
+ value = "26";
type = "int";
}
}
@@ -218,7 +218,7 @@
{
datum baseAddress
{
- value = "294912";
+ value = "16384";
type = "String";
}
}
@@ -226,7 +226,7 @@
{
datum _sortIndex
{
- value = "28";
+ value = "27";
type = "int";
}
}
@@ -242,7 +242,7 @@
{
datum _sortIndex
{
- value = "26";
+ value = "25";
type = "int";
}
}
@@ -302,22 +302,6 @@
type = "String";
}
}
- element reg_dp_offload_tx_hdr_ovr
- {
- datum _sortIndex
- {
- value = "25";
- type = "int";
- }
- }
- element reg_dp_offload_tx_hdr_ovr.mem
- {
- datum baseAddress
- {
- value = "16384";
- type = "String";
- }
- }
element reg_dpmm_ctrl
{
datum _sortIndex
@@ -974,41 +958,6 @@
internal="reg_dp_offload_tx_hdr_dat.writedata"
type="conduit"
dir="end" />
- <interface
- name="reg_dp_offload_tx_hdr_ovr_address"
- internal="reg_dp_offload_tx_hdr_ovr.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_hdr_ovr_clk"
- internal="reg_dp_offload_tx_hdr_ovr.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_hdr_ovr_read"
- internal="reg_dp_offload_tx_hdr_ovr.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_hdr_ovr_readdata"
- internal="reg_dp_offload_tx_hdr_ovr.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_hdr_ovr_reset"
- internal="reg_dp_offload_tx_hdr_ovr.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_hdr_ovr_write"
- internal="reg_dp_offload_tx_hdr_ovr.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_offload_tx_hdr_ovr_writedata"
- internal="reg_dp_offload_tx_hdr_ovr.writedata"
- type="conduit"
- dir="end" />
<interface
name="reg_dp_offload_tx_read"
internal="reg_dp_offload_tx.read"
@@ -1481,7 +1430,7 @@
<parameter name="dataAddrWidth" value="23" />
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="dataMasterHighPerformanceMapParam" value="" />
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer.mem' start='0x80' end='0x100' /><slave name='avs_eth_0.mms_reg' start='0x100' end='0x140' /><slave name='timer_0.s1' start='0x140' end='0x160' /><slave name='reg_diag_bg.mem' start='0x160' end='0x180' /><slave name='reg_epcs.mem' start='0x180' end='0x1A0' /><slave name='reg_remu.mem' start='0x1A0' end='0x1C0' /><slave name='reg_unb_sens.mem' start='0x1C0' end='0x1E0' /><slave name='pio_wdi.s1' start='0x1E0' end='0x1F0' /><slave name='reg_mmdp_data.mem' start='0x1F0' end='0x1F8' /><slave name='reg_mmdp_ctrl.mem' start='0x1F8' end='0x200' /><slave name='reg_dpmm_data.mem' start='0x200' end='0x208' /><slave name='reg_dpmm_ctrl.mem' start='0x208' end='0x210' /><slave name='pio_pps.mem' start='0x210' end='0x218' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x218' end='0x220' /><slave name='reg_dp_offload_tx.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='reg_dp_offload_tx_hdr_ovr.mem' start='0x4000' end='0x8000' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x8000' end='0x10000' /><slave name='ram_diag_data_buffer.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x40000' end='0x48000' /><slave name='reg_bsn_monitor.mem' start='0x48000' end='0x4A000' /><slave name='avs_eth_0.mms_ram' start='0x4A000' end='0x4B000' /><slave name='ram_diag_bg.mem' start='0x80000' end='0x100000' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer.mem' start='0x80' end='0x100' /><slave name='avs_eth_0.mms_reg' start='0x100' end='0x140' /><slave name='timer_0.s1' start='0x140' end='0x160' /><slave name='reg_diag_bg.mem' start='0x160' end='0x180' /><slave name='reg_epcs.mem' start='0x180' end='0x1A0' /><slave name='reg_remu.mem' start='0x1A0' end='0x1C0' /><slave name='reg_unb_sens.mem' start='0x1C0' end='0x1E0' /><slave name='pio_wdi.s1' start='0x1E0' end='0x1F0' /><slave name='reg_mmdp_data.mem' start='0x1F0' end='0x1F8' /><slave name='reg_mmdp_ctrl.mem' start='0x1F8' end='0x200' /><slave name='reg_dpmm_data.mem' start='0x200' end='0x208' /><slave name='reg_dpmm_ctrl.mem' start='0x208' end='0x210' /><slave name='pio_pps.mem' start='0x210' end='0x218' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x218' end='0x220' /><slave name='reg_dp_offload_tx.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='reg_bsn_monitor.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x8000' end='0x10000' /><slave name='ram_diag_data_buffer.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x40000' end='0x48000' /><slave name='ram_diag_bg.mem' start='0x80000' end='0x100000' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' /></address-map>]]></parameter>
<parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="data_master_paddr_base" value="0" />
@@ -1769,15 +1718,6 @@
<parameter name="g_adr_w" value="13" />
<parameter name="g_dat_w" value="32" />
</module>
- <module
- name="reg_dp_offload_tx_hdr_ovr"
- kind="avs_common_mm"
- version="1.0"
- enabled="1">
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
- <parameter name="g_adr_w" value="12" />
- <parameter name="g_dat_w" value="32" />
- </module>
<module name="reg_dpmm_ctrl" kind="avs_common_mm" version="1.0" enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
<parameter name="g_adr_w" value="1" />
@@ -1993,7 +1933,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00048000" />
+ <parameter name="baseAddress" value="0x4000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -2023,15 +1963,6 @@
<parameter name="baseAddress" value="0x8000" />
<parameter name="defaultConnection" value="false" />
</connection>
- <connection
- kind="avalon"
- version="14.1"
- start="cpu_0.data_master"
- end="reg_dp_offload_tx_hdr_ovr.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x4000" />
- <parameter name="defaultConnection" value="false" />
- </connection>
<connection
kind="avalon"
version="14.1"
@@ -2092,7 +2023,7 @@
start="cpu_0.data_master"
end="avs_eth_0.mms_ram">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0004a000" />
+ <parameter name="baseAddress" value="0x6000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@@ -2232,11 +2163,6 @@
version="14.1"
start="clk_0.clk"
end="reg_dp_offload_rx_hdr_dat.system" />
- <connection
- kind="clock"
- version="14.1"
- start="clk_0.clk"
- end="reg_dp_offload_tx_hdr_ovr.system" />
<connection
kind="clock"
version="14.1"
@@ -2390,11 +2316,6 @@
version="14.1"
start="clk_0.clk_reset"
end="reg_dp_offload_rx_hdr_dat.system_reset" />
- <connection
- kind="reset"
- version="14.1"
- start="clk_0.clk_reset"
- end="reg_dp_offload_tx_hdr_ovr.system_reset" />
<connection
kind="reset"
version="14.1"
@@ -2535,11 +2456,6 @@
version="14.1"
start="cpu_0.debug_reset_request"
end="reg_dp_offload_rx_hdr_dat.system_reset" />
- <connection
- kind="reset"
- version="14.1"
- start="cpu_0.debug_reset_request"
- end="reg_dp_offload_tx_hdr_ovr.system_reset" />
<connection
kind="reset"
version="14.1"
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
index fc08b69e9fc5395b2a23462d18a68074165a43a7..bd6f13a9d1f870a1e24e9d98588d37d7c4bab4b2 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
@@ -120,9 +120,6 @@ ENTITY mmm_unb2_test IS
reg_dp_offload_tx_hdr_dat_mosi : OUT t_mem_mosi;
reg_dp_offload_tx_hdr_dat_miso : IN t_mem_miso;
- reg_dp_offload_tx_hdr_ovr_mosi : OUT t_mem_mosi;
- reg_dp_offload_tx_hdr_ovr_miso : IN t_mem_miso;
-
reg_dp_offload_rx_hdr_dat_mosi : OUT t_mem_mosi;
reg_dp_offload_rx_hdr_dat_miso : IN t_mem_miso;
@@ -163,10 +160,6 @@ ARCHITECTURE str OF mmm_unb2_test IS
CONSTANT c_reg_dp_offload_tx_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_dat_nof_words);
CONSTANT c_reg_dp_offload_tx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_dp_offload_tx_hdr_dat_adr_w));
- CONSTANT c_reg_dp_offload_tx_hdr_ovr_nof_words : NATURAL := g_hdr_field_arr'LENGTH;
- CONSTANT c_reg_dp_offload_tx_hdr_ovr_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_ovr_nof_words);
- CONSTANT c_reg_dp_offload_tx_hdr_ovr_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_dp_offload_tx_hdr_ovr_adr_w));
-
CONSTANT c_reg_dp_offload_rx_hdr_dat_nof_words : NATURAL := field_nof_words(g_hdr_field_arr, c_word_w);
CONSTANT c_reg_dp_offload_rx_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_hdr_dat_nof_words);
CONSTANT c_reg_dp_offload_rx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams* pow2(c_reg_dp_offload_rx_hdr_dat_adr_w));
@@ -244,9 +237,6 @@ BEGIN
u_mm_file_reg_dp_offload_tx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT")
PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_dat_mosi, reg_dp_offload_tx_hdr_dat_miso );
- u_mm_file_reg_dp_offload_tx_hdr_ovr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_OVR")
- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_ovr_mosi, reg_dp_offload_tx_hdr_ovr_miso );
-
u_mm_file_reg_dp_offload_rx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_HDR_DAT")
PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_hdr_dat_mosi, reg_dp_offload_rx_hdr_dat_miso );
@@ -490,14 +480,6 @@ BEGIN
reg_dp_offload_rx_hdr_dat_read_export => reg_dp_offload_rx_hdr_dat_mosi.rd,
reg_dp_offload_rx_hdr_dat_readdata_export => reg_dp_offload_rx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_dp_offload_tx_hdr_ovr_reset_export => OPEN,
- reg_dp_offload_tx_hdr_ovr_clk_export => OPEN,
- reg_dp_offload_tx_hdr_ovr_address_export => reg_dp_offload_tx_hdr_ovr_mosi.address(c_reg_dp_offload_tx_hdr_ovr_multi_adr_w-1 DOWNTO 0),
- reg_dp_offload_tx_hdr_ovr_write_export => reg_dp_offload_tx_hdr_ovr_mosi.wr,
- reg_dp_offload_tx_hdr_ovr_writedata_export => reg_dp_offload_tx_hdr_ovr_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_dp_offload_tx_hdr_ovr_read_export => reg_dp_offload_tx_hdr_ovr_mosi.rd,
- reg_dp_offload_tx_hdr_ovr_readdata_export => reg_dp_offload_tx_hdr_ovr_miso.rddata(c_word_w-1 DOWNTO 0),
-
reg_diag_data_buffer_reset_export => OPEN,
reg_diag_data_buffer_clk_export => OPEN,
reg_diag_data_buffer_address_export => reg_diag_data_buf_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
index b09f62aff26781e9cc0bf5b046286626a8eb7fcd..2e5da620a8b0c0af0fb5ebeb46b7210a672f39a4 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
@@ -189,14 +189,6 @@ PACKAGE qsys_unb2_test_pkg IS
reg_dp_offload_rx_hdr_dat_read_export : out std_logic; -- export
reg_dp_offload_rx_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_tx_hdr_ovr_reset_export : out std_logic; -- export
- reg_dp_offload_tx_hdr_ovr_clk_export : out std_logic; -- export
- reg_dp_offload_tx_hdr_ovr_address_export : out std_logic_vector(12-1 downto 0); -- export
- reg_dp_offload_tx_hdr_ovr_write_export : out std_logic; -- export
- reg_dp_offload_tx_hdr_ovr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_hdr_ovr_read_export : out std_logic; -- export
- reg_dp_offload_tx_hdr_ovr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
-
reg_diag_data_buffer_reset_export : out std_logic; -- export
reg_diag_data_buffer_clk_export : out std_logic; -- export
reg_diag_data_buffer_address_export : out std_logic_vector(4 downto 0); -- export
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index e7dde03675a2c9f29533f20b7157c909c7ccbdaa..72f970100c9817e4b62249f01d82714b2c731a3f 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -47,6 +47,7 @@ ENTITY unb2_test IS
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
g_factory_image : BOOLEAN := FALSE;
+ g_nof_streams_1GbE : NATURAL := 0;
g_nof_streams_qsfp : NATURAL := c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w;
g_nof_streams_ring : NATURAL := c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w;
g_nof_streams_back0: NATURAL := c_unb2_board_tr_back.bus_w;
@@ -121,20 +122,17 @@ END unb2_test;
ARCHITECTURE str OF unb2_test IS
-- Firmware version x.y
- CONSTANT c_fw_version : t_unb2_board_fw_version := (1, 1);
-
- CONSTANT c_lpbk_data_w : NATURAL := 32; -- 128 c_eth_data_w, c_xgmii_data_w
+ CONSTANT c_fw_version : t_unb2_board_fw_version := (1, 1);
-- Revision controlled constants
CONSTANT c_use_1GbE : BOOLEAN := FALSE; --g_design_name = "unb2_test_1GbE";
CONSTANT c_use_10GbE : BOOLEAN := TRUE; --g_design_name = "unb2_test_10GbE";
- CONSTANT g_nof_streams : NATURAL := g_nof_streams_qsfp + g_nof_streams_ring + g_nof_streams_back0 + g_nof_streams_back1;
+ CONSTANT g_nof_streams : NATURAL := g_nof_streams_qsfp + g_nof_streams_ring + g_nof_streams_back0 + g_nof_streams_back1 + g_nof_streams_1GbE;
CONSTANT g_nof_qsfp_bus : NATURAL := ceil_div(g_nof_streams_qsfp,c_unb2_board_tr_qsfp.bus_w);
CONSTANT g_nof_ring_bus : NATURAL := ceil_div(g_nof_streams_ring,c_unb2_board_tr_ring.bus_w);
CONSTANT g_nof_back_bus : NATURAL := ceil_div(g_nof_streams_back0,c_unb2_board_tr_back.bus_w) + ceil_div(g_nof_streams_back1,c_unb2_board_tr_back.bus_w);
- CONSTANT c_data_w : NATURAL := sel_a_b(FALSE, c_lpbk_data_w, -- Select correct c_data_w when one interface is used
- sel_a_b(c_use_1GbE, c_eth_data_w,
- sel_a_b(c_use_10GbE, c_xgmii_data_w, 0)));
+ CONSTANT c_data_w : NATURAL := sel_a_b(c_use_1GbE, c_eth_data_w,
+ sel_a_b(c_use_10GbE, c_xgmii_data_w, 0));
-- Block generator
@@ -298,14 +296,14 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL reg_tr_10GbE_back1_mosi : t_mem_mosi;
SIGNAL reg_tr_10GbE_back1_miso : t_mem_miso;
- SIGNAL reg_dp_ram_from_mm_mosi : t_mem_mosi;
- SIGNAL reg_dp_ram_from_mm_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_dp_ram_from_mm_mosi : t_mem_mosi;
+ SIGNAL reg_dp_ram_from_mm_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL ram_dp_ram_from_mm_mosi : t_mem_mosi;
- SIGNAL ram_dp_ram_from_mm_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_dp_ram_from_mm_mosi : t_mem_mosi;
+ SIGNAL ram_dp_ram_from_mm_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL ram_dp_ram_to_mm_mosi : t_mem_mosi;
- SIGNAL ram_dp_ram_to_mm_miso : t_mem_miso;
+ SIGNAL ram_dp_ram_to_mm_mosi : t_mem_mosi;
+ SIGNAL ram_dp_ram_to_mm_miso : t_mem_miso;
SIGNAL reg_diag_bg_mosi : t_mem_mosi;
@@ -317,8 +315,6 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL reg_dp_offload_tx_miso : t_mem_miso;
SIGNAL reg_dp_offload_tx_hdr_dat_mosi : t_mem_mosi;
SIGNAL reg_dp_offload_tx_hdr_dat_miso : t_mem_miso;
- SIGNAL reg_dp_offload_tx_hdr_ovr_mosi : t_mem_mosi;
- SIGNAL reg_dp_offload_tx_hdr_ovr_miso : t_mem_miso;
SIGNAL reg_dp_offload_rx_hdr_dat_mosi : t_mem_mosi;
SIGNAL reg_dp_offload_rx_hdr_dat_miso : t_mem_miso;
@@ -332,6 +328,9 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL block_gen_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL block_gen_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
+ SIGNAL fifo_block_gen_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL fifo_block_gen_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
+
SIGNAL dp_offload_tx_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL dp_offload_tx_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
@@ -348,10 +347,10 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL user_red_led_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0);
-- Interface: 1GbE UDP streaming ports
- SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL eth1g_udp_tx_siso_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL eth1g_udp_rx_siso_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(g_nof_streams_1GbE-1 DOWNTO 0);
+ SIGNAL eth1g_udp_tx_siso_arr : t_dp_siso_arr(g_nof_streams_1GbE-1 DOWNTO 0);
+ SIGNAL eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(g_nof_streams_1GbE-1 DOWNTO 0);
+ SIGNAL eth1g_udp_rx_siso_arr : t_dp_siso_arr(g_nof_streams_1GbE-1 DOWNTO 0);
BEGIN
@@ -371,7 +370,7 @@ BEGIN
g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
g_aux => c_unb2_board_aux,
g_udp_offload => c_use_1GbE,
- g_udp_offload_nof_streams => g_nof_streams,
+ g_udp_offload_nof_streams => g_nof_streams_1GbE,
g_dp_clk_use_pll => TRUE,
g_factory_image => g_factory_image
)
@@ -551,9 +550,6 @@ BEGIN
reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
- reg_dp_offload_tx_hdr_ovr_mosi => reg_dp_offload_tx_hdr_ovr_mosi,
- reg_dp_offload_tx_hdr_ovr_miso => reg_dp_offload_tx_hdr_ovr_miso,
-
reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
@@ -610,6 +606,24 @@ BEGIN
ram_bg_data_miso => ram_diag_bg_miso
);
+ gen_dp_fifo_sc : FOR i IN 0 TO g_nof_streams-1 GENERATE
+ u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
+ GENERIC MAP (
+ g_data_w => c_data_w,
+ g_fifo_size => 50
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink (BG)
+ snk_out => block_gen_src_in_arr(i),
+ snk_in => block_gen_src_out_arr(i),
+ -- ST source (tx_offload)
+ src_in => fifo_block_gen_src_in_arr(i),
+ src_out => fifo_block_gen_src_out_arr(i)
+ );
+ END GENERATE;
+
-----------------------------------------------------------------------------
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
@@ -622,9 +636,9 @@ BEGIN
g_def_nof_words_per_block => c_def_nof_words_per_block,
g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet,
g_def_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
- g_output_fifo_depth => c_max_frame_nof_words,
+ --g_output_fifo_depth => c_max_frame_nof_words,
g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_ovr_init => c_hdr_field_ovr_init
+ g_hdr_field_sel => c_hdr_field_ovr_init
)
PORT MAP (
mm_rst => mm_rst,
@@ -639,11 +653,8 @@ BEGIN
reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
- reg_hdr_ovr_mosi => reg_dp_offload_tx_hdr_ovr_mosi,
- reg_hdr_ovr_miso => reg_dp_offload_tx_hdr_ovr_miso,
-
- snk_in_arr => block_gen_src_out_arr,
- snk_out_arr => block_gen_src_in_arr,
+ snk_in_arr => fifo_block_gen_src_out_arr,
+ snk_out_arr => fifo_block_gen_src_in_arr,
src_out_arr => dp_offload_tx_src_out_arr,
src_in_arr => dp_offload_tx_src_in_arr,