From 2e3aab01a4c166fdddda07757f55c8abb8f9342a Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Mon, 9 Mar 2020 16:50:18 +0100
Subject: [PATCH] Renamed g_pipeline_miso_rd into g_pipeline_miso_rdval.
---
.../base/mm/tb/vhdl/tb_mm_master_mux.vhd | 42 +++++++++----------
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd b/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd
index ae7150e154..5902094761 100644
--- a/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd
@@ -52,13 +52,13 @@ USE common_lib.tb_common_mem_pkg.ALL;
ENTITY tb_mm_master_mux IS
GENERIC (
- g_nof_masters : POSITIVE := 2; -- Number of master memory interfaces on the MM bus array.
- g_base_arr : t_nat_natural_arr := (0, 256); -- Address base per slave port of mm_bus
- g_width_arr : t_nat_natural_arr := (4, 8); -- Address width per slave port of mm_bus
- g_waitrequest : BOOLEAN := TRUE; -- When TRUE model waitrequest by the MM RAM slave, else fixed '0'
- g_pipeline_bus_mosi : BOOLEAN := FALSE;
- g_pipeline_bus_miso_rd : BOOLEAN := FALSE;
- g_pipeline_bus_miso_wait : BOOLEAN := FALSE
+ g_nof_masters : POSITIVE := 2; -- Number of master memory interfaces on the MM bus array.
+ g_base_arr : t_nat_natural_arr := (0, 256); -- Address base per slave port of mm_bus
+ g_width_arr : t_nat_natural_arr := (4, 8); -- Address width per slave port of mm_bus
+ g_waitrequest : BOOLEAN := TRUE; -- When TRUE model waitrequest by the MM RAM slave, else fixed '0'
+ g_pipeline_bus_mosi : BOOLEAN := FALSE;
+ g_pipeline_bus_miso_rdval : BOOLEAN := FALSE;
+ g_pipeline_bus_miso_wait : BOOLEAN := FALSE
);
END tb_mm_master_mux;
@@ -71,14 +71,14 @@ ARCHITECTURE tb OF tb_mm_master_mux IS
CONSTANT mm_clk_period : TIME := 10 ns;
- CONSTANT c_repeat : NATURAL := sel_a_b(g_waitrequest, 10, 2); -- repeat 2 for deterministic, more often for random
- CONSTANT c_bus_pipeline_mosi : NATURAL := sel_a_b(g_pipeline_bus_mosi, 1, 0);
- CONSTANT c_bus_pipeline_miso_rd : NATURAL := sel_a_b(g_pipeline_bus_miso_rd, 1, 0);
- CONSTANT c_bus_pipeline_miso_wait : NATURAL := sel_a_b(g_pipeline_bus_miso_wait, 1, 0);
- CONSTANT c_ram_rd_latency : NATURAL := 1;
- CONSTANT c_ram_rd_latency_arr : t_nat_natural_arr := array_init(c_ram_rd_latency, g_nof_masters);
+ CONSTANT c_repeat : NATURAL := sel_a_b(g_waitrequest, 10, 2); -- repeat 2 for deterministic, more often for random
+ CONSTANT c_bus_pipeline_mosi : NATURAL := sel_a_b(g_pipeline_bus_mosi, 1, 0);
+ CONSTANT c_bus_pipeline_miso_rdval : NATURAL := sel_a_b(g_pipeline_bus_miso_rdval, 1, 0);
+ CONSTANT c_bus_pipeline_miso_wait : NATURAL := sel_a_b(g_pipeline_bus_miso_wait, 1, 0);
+ CONSTANT c_ram_rd_latency : NATURAL := 1;
+ CONSTANT c_ram_rd_latency_arr : t_nat_natural_arr := array_init(c_ram_rd_latency, g_nof_masters);
- CONSTANT c_read_latency : NATURAL := c_bus_pipeline_mosi + c_ram_rd_latency + c_bus_pipeline_miso_rd;
+ CONSTANT c_read_latency : NATURAL := c_bus_pipeline_mosi + c_ram_rd_latency + c_bus_pipeline_miso_rdval;
CONSTANT c_addr_w : NATURAL := largest(ceil_log2(largest(g_base_arr)), largest(g_width_arr)) + 1;
CONSTANT c_data_w : NATURAL := 32;
@@ -157,13 +157,13 @@ BEGIN
-- Model multiple masters using stimuli from a single master
u_masters : ENTITY work.mm_bus
GENERIC MAP (
- g_nof_slaves => g_nof_masters,
- g_base_arr => g_base_arr,
- g_width_arr => g_width_arr,
- g_rd_latency_arr => c_ram_rd_latency_arr,
- g_pipeline_mosi => g_pipeline_bus_mosi,
- g_pipeline_miso_rd => g_pipeline_bus_miso_rd,
- g_pipeline_miso_wait => g_pipeline_bus_miso_wait
+ g_nof_slaves => g_nof_masters,
+ g_base_arr => g_base_arr,
+ g_width_arr => g_width_arr,
+ g_rd_latency_arr => c_ram_rd_latency_arr,
+ g_pipeline_mosi => g_pipeline_bus_mosi,
+ g_pipeline_miso_rdval => g_pipeline_bus_miso_rdval,
+ g_pipeline_miso_wait => g_pipeline_bus_miso_wait
)
PORT MAP (
mm_clk => mm_clk,
--
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