diff --git a/applications/apertif/designs/apertif_unb1_cor_mesh_ref/quartus/.qsys_edit/filters.xml b/applications/apertif/designs/apertif_unb1_cor_mesh_ref/quartus/.qsys_edit/filters.xml
deleted file mode 100644
index 09c596d8647cbe4d867ca31f0f9bea2b07d3b390..0000000000000000000000000000000000000000
--- a/applications/apertif/designs/apertif_unb1_cor_mesh_ref/quartus/.qsys_edit/filters.xml
+++ /dev/null
@@ -1,2 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<filters version="11.1sp2" />
diff --git a/applications/apertif/designs/apertif_unb1_cor_mesh_ref/quartus/.qsys_edit/preferences.xml b/applications/apertif/designs/apertif_unb1_cor_mesh_ref/quartus/.qsys_edit/preferences.xml
deleted file mode 100644
index dbb0727dc5c541e7f282ce990b9d65468546aa48..0000000000000000000000000000000000000000
--- a/applications/apertif/designs/apertif_unb1_cor_mesh_ref/quartus/.qsys_edit/preferences.xml
+++ /dev/null
@@ -1,21 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<preferences>
- <debug showDebugMenu="0" />
- <systemtable filter="Default">
-  <columns>
-   <connections preferredWidth="63" />
-   <irq preferredWidth="34" />
-  </columns>
- </systemtable>
- <clocktable>
-  <columns>
-   <clockname preferredWidth="324" />
-   <clocksource preferredWidth="323" />
-   <frequency preferredWidth="304" />
-  </columns>
- </clocktable>
- <library expandedCategories="Library,Project,Library/Uniboard" />
- <window width="1262" height="1079" x="0" y="0" />
- <hdlexample language="VHDL" />
- <generation simulation="VHDL" testbench_system="NONE" />
-</preferences>