From 2ddf082451bcb9be82d7c91c0e80b3bf009287b4 Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Thu, 18 Mar 2021 00:20:09 +0100
Subject: [PATCH] unb2c_test more revisions
---
.../designs/unb2c_minimal/doc/README | 135 ----------------
.../designs/unb2c_minimal/doc/README.flash | 56 +++++++
.../designs/unb2c_minimal/doc/README.txt | 64 ++++++++
.../unb2c_minimal/src/vhdl/unb2c_minimal.vhd | 8 +-
.../designs/unb2c_test/doc/README.txt | 67 ++++----
.../uniboard2c/designs/unb2c_test/hdllib.cfg | 2 +-
.../unb2c_test_10GbE/unb2c_test_10GbE.vhd | 40 ++---
.../revisions/unb2c_test_ddr/hdllib.cfg | 115 ++++++++++++++
.../unb2c_test_ddr/quartus/unb2c_test_ddr.sdc | 1 +
.../quartus/unb2c_test_ddr_pins.tcl | 23 +++
.../unb2c_test_ddr/tb_unb2c_test_ddr.vhd | 38 +++++
.../unb2c_test_ddr/unb2c_test_ddr.vhd | 146 ++++++++++++++++++
.../revisions/unb2c_test_heater/hdllib.cfg | 112 ++++++++++++++
.../quartus/unb2c_test_heater.sdc | 1 +
.../quartus/unb2c_test_heater_pins.tcl | 22 +++
.../tb_unb2c_test_heater.vhd | 38 +++++
.../unb2c_test_heater/unb2c_test_heater.vhd | 117 ++++++++++++++
.../revisions/unb2c_test_jesd204b/hdllib.cfg | 112 ++++++++++++++
.../quartus/unb2c_test_jesd204b.sdc | 1 +
.../quartus/unb2c_test_jesd204b_pins.tcl | 23 +++
.../tb_unb2c_test_jesd204b.vhd | 38 +++++
.../unb2c_test_jesd204b.vhd | 117 ++++++++++++++
.../unb2c_test_minimal/unb2c_test_minimal.vhd | 2 +-
.../unb2c_test/src/vhdl/mmm_unb2c_test.vhd | 19 ++-
.../unb2c_test/src/vhdl/unb2c_test.vhd | 66 +++++---
.../unb2c_test/src/vhdl/unb2c_test_pkg.vhd | 21 +--
.../quartus/pinning/unb2c_10GbE_pins.tcl | 31 ----
.../quartus/pinning/unb2c_minimal_pins.tcl | 17 --
.../src/vhdl/unb2c_board_back_io.vhd | 6 +-
.../src/vhdl/unb2c_board_front_io.vhd | 2 -
.../ip_arria10_e2sg_ddr4_8g_1600.ip | 59 +------
31 files changed, 1153 insertions(+), 346 deletions(-)
delete mode 100644 boards/uniboard2c/designs/unb2c_minimal/doc/README
create mode 100644 boards/uniboard2c/designs/unb2c_minimal/doc/README.flash
create mode 100644 boards/uniboard2c/designs/unb2c_minimal/doc/README.txt
create mode 100644 boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/hdllib.cfg
create mode 100644 boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/quartus/unb2c_test_ddr.sdc
create mode 100644 boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/quartus/unb2c_test_ddr_pins.tcl
create mode 100644 boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd
create mode 100644 boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd
create mode 100644 boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/hdllib.cfg
create mode 100644 boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/quartus/unb2c_test_heater.sdc
create mode 100644 boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/quartus/unb2c_test_heater_pins.tcl
create mode 100644 boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd
create mode 100644 boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd
create mode 100644 boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/hdllib.cfg
create mode 100644 boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/quartus/unb2c_test_jesd204b.sdc
create mode 100644 boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/quartus/unb2c_test_jesd204b_pins.tcl
create mode 100644 boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd
create mode 100644 boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd
diff --git a/boards/uniboard2c/designs/unb2c_minimal/doc/README b/boards/uniboard2c/designs/unb2c_minimal/doc/README
deleted file mode 100644
index d371fc8f5d..0000000000
--- a/boards/uniboard2c/designs/unb2c_minimal/doc/README
+++ /dev/null
@@ -1,135 +0,0 @@
-Quick steps to compile and use design [unb2c_minimal] in RadionHDL
-------------------------------------------------------------------
-
-
-
--> In case of a new installation, the IP's have to be generated for Arria10.
- :~/git$ ./radiohdl/core/generate_ip_libs unb2c
-
-
--> For compilation it might be necessary to check the .vhd file:
- $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
-
--> Make sure you have set up the RadioHDL/trunk/tools/quartus/set_quartus script correctly to use quartus 17 for unb2c.
-
--> Make sure you use the modified avs2_eth_coe_hw.tcl (see attachment of this e-mail), this file is placed in RadioHDL/trunk/libraries/io/eth/src/vhdl.
-
-1. Start with the Oneclick Commands:
- python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2c
- python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2c
-
-# 2. Generate MMM for QSYS:
-# run_qsys unb2c unb2c_minimal
-
-3. -> From here either continue to Modelsim (simulation) or Quartus (synthesis)
-
-Simulation
-----------
-Modelsim instructions:
- # in bash do:
- rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
- run_modelsim unb2c
-
- # in Modelsim do:
- lp unb2c_minimal
- mk all
- # now double click on testbench file
- as 10
- run 500us
-
- # while the simulation runs... in another bash session do:
- cd unb2c_minimal/tb/python
- python tc_unb2c_minimal.py --sim --unb 0 --fn 3 --seq INFO,PPSH,SENSORS
-
- # (sensor results only show up after 1000us of simulation runtime)
-
- # to end simulation in Modelsim do:
- quit -sim
-
-
-Synthesis
----------
-# Quartus instructions:
-# run_qcomp unb2 unb2c_minimal
-
-
-# scripts are not yet working for quartus 17.0.2, this is the workaround.
-- "run_quartus unb2c &"
-- Open the unb2c_minumal quartus project from the build directory.
-- Open the qsys_unb2c_minimal.qsys file from the build directory.
-- Generate the HDL files for the qsys using the GUI.
-- "cd $RADIOHDL_WORK/build/unb2c/quartus/unb2c_minimal"
-- "cp qsys_unb2c_minimal/qsys_unb2c_minimal* ."
-- "run_app unb2c unb2c_minimal use=gen2"
-- In Quartus, click the play button to compile the design.
-
-if project ip's are missing problably /home/[user name]/.altera.quartus/ip/17.0.2/ is missing.
- (just make a copy of the previous one and rename it)
-
-
-4. Load firmware
-----------------
-Using JTAG: Start the Quartus GUI and open: tools->programmer.
- Then click auto-detect;
- Use 'change file' to select the correct .sof file for each FPGA
- Select the FPGA(s) which has to be programmed
- Click 'start'
-Using EPCS: See step 6 below.
-
-
-
-
-5. Testing on hardware
-----------------------
-Assuming the firmware is loaded and running already in the FPGA, the firmware can be tested from the connected
-LCU computer.
-
-# (assume that the Uniboard is --unb 1)
-
-# To read out the design_name, ppsh and sensors; do:
-
-python tc_unb2_minimal.py --unb 1 --fn 0:3 --seq REGMAP,INFO,PPSH,SENSORS -v5
-
-
-
-6. Programming the EPCS flash.
-------------------------------
-On an empty new board the factory image must be loaded using the programmer and a yic file.
-
-when the EPCS module works (factory image is loaded in flash) an RBF file can be generated to program the flash,
-then the .sof file file can be converted to .rbf with the 'run_rbf' script.
-
-But for now the only way to program the EPCS flash is via JTAG.
-Firstly a JIC file has to be generated from the SOF file.
-In Quartus GUI; open current project; File -> Convert Programming Files.
-Then setup:
-- Output programming file: JIC
-- Configuration device: EPCQ-L1024
-- Mode: Active Serial x4
-- Flash Loader: Add/Select Device Arria10 / 10AX115U2
-- SOF Data: add file (the generated .sof file)
- - click the .sof file; Set property 'Compression' to ON
-- Press 'Generate'
-- Press "Done"
-
-In Quartus GUI:
-Setup Device (if needed):
-- click in menu: 'Assignments' -> 'Device'
-- Name: 10AX115U2F45E1SG
-- click 'Device and Pin Options' button.
-- Configuration scheme: Active Serial x4
-- check Use Configuration device: EPCQL1024.
-- Configuration device I/O voltage: 1.8V
-- check Generate compressed bitstreams.
-- Active clock source: 12.5 MHz Internal Oscillator.
-
-Then program the .JIC file (output_file.jic) to EPCS flash:
-- Make sure that the JTAG (on server connected to board) runs at 16MHz:
- /home/software/software/Altera/17.0/quartus/bin/jtagconfig USB-BlasterII JtagClock 16M
-- open tools->programmer
-- make sure the 4 fpga icons have the device 10AX115U2F45
-- right-click each fpga icon and attach flash device EPCQ-L1024
-- right-click each EPCQ-L1024 and change file from <none> to output_file.jic
-- check each Program/Configure radiobutton for the EPCQ-L1024, the right 'sfl' file is auto selected and checked.
-- click start and wait for 'Successful'
-- restart the board by toggling the button on the front (only needed the first time)
diff --git a/boards/uniboard2c/designs/unb2c_minimal/doc/README.flash b/boards/uniboard2c/designs/unb2c_minimal/doc/README.flash
new file mode 100644
index 0000000000..6c1d39a207
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_minimal/doc/README.flash
@@ -0,0 +1,56 @@
+
+ Load firmware
+----------------
+Using JTAG: Start the Quartus GUI and open: tools->programmer.
+ Then click auto-detect;
+ Use 'change file' to select the correct .sof file for each FPGA
+ Select the FPGA(s) which has to be programmed
+ Click 'start'
+Using EPCS: See step 6 below.
+
+
+
+
+
+
+ Programming the EPCS flash.
+------------------------------
+On an empty new board the factory image must be loaded using the programmer and a yic file.
+
+when the EPCS module works (factory image is loaded in flash) an RBF file can be generated to program the flash,
+then the .sof file file can be converted to .rbf with the 'run_rbf' script.
+
+But for now the only way to program the EPCS flash is via JTAG.
+Firstly a JIC file has to be generated from the SOF file.
+In Quartus GUI; open current project; File -> Convert Programming Files.
+Then setup:
+- Output programming file: JIC
+- Configuration device: EPCQ-L1024
+- Mode: Active Serial x4
+- Flash Loader: Add/Select Device Arria10 / 10AX115U2
+- SOF Data: add file (the generated .sof file)
+ - click the .sof file; Set property 'Compression' to ON
+- Press 'Generate'
+- Press "Done"
+
+In Quartus GUI:
+Setup Device (if needed):
+- click in menu: 'Assignments' -> 'Device'
+- Name: 10AX115U2F45E1SG
+- click 'Device and Pin Options' button.
+- Configuration scheme: Active Serial x4
+- check Use Configuration device: EPCQL1024.
+- Configuration device I/O voltage: 1.8V
+- check Generate compressed bitstreams.
+- Active clock source: 12.5 MHz Internal Oscillator.
+
+Then program the .JIC file (output_file.jic) to EPCS flash:
+- Make sure that the JTAG (on server connected to board) runs at 16MHz:
+ /home/software/software/Altera/17.0/quartus/bin/jtagconfig USB-BlasterII JtagClock 16M
+- open tools->programmer
+- make sure the 4 fpga icons have the device 10AX115U2F45
+- right-click each fpga icon and attach flash device EPCQ-L1024
+- right-click each EPCQ-L1024 and change file from <none> to output_file.jic
+- check each Program/Configure radiobutton for the EPCQ-L1024, the right 'sfl' file is auto selected and checked.
+- click start and wait for 'Successful'
+- restart the board by toggling the button on the front (only needed the first time)
diff --git a/boards/uniboard2c/designs/unb2c_minimal/doc/README.txt b/boards/uniboard2c/designs/unb2c_minimal/doc/README.txt
new file mode 100644
index 0000000000..33bcfbb2be
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_minimal/doc/README.txt
@@ -0,0 +1,64 @@
+This is the minimal design for Uniboard2c.
+
+Here are quick steps to compile and use designs in RadionHDL.
+-------------------------------------------------------------
+
+
+Steps to go:
+------------
+
+-> At all times run:
+
+ cd ${GIT}/hdl
+ . init_hdl.sh
+
+-> In case of a new installation, the IP's have to be generated for Arria10.
+
+ echo $RADIOHDL_BUILD_DIR # should be something like /home/user/git/hdl/build
+ rm -r $RADIOHDL_BUILD_DIR/unb2c # optional
+ compile_altera_simlibs unb2c
+ generate_ip_libs unb2c
+
+
+1. Start with the Oneclick Commands:
+ modelsim_config unb2c
+ quartus_config unb2c
+
+
+2. Generate MMM for QSYS (select one of these revisions):
+ run_qsys_pro unb2c unb2c_minimal
+
+
+
+3. -> From here either continue to Modelsim (simulation) or Quartus (synthesis)
+
+Simulation
+----------
+ run_modelsim unb2c
+
+
+
+
+Synthesis
+---------
+Quartus instructions: (select one of these revisions):
+ run_qcomp unb2c unb2c_minimal
+
+
+Or compile using the Quartus GUI:
+ run_quartus unb2c
+load the project now from the build directory.
+
+
+
+
+4. Load firmware
+----------------
+Using JTAG: Start the Quartus GUI and open: tools->programmer.
+ Then click auto-detect; (click 4x ok)
+ Use 'change file' to select the correct .sof file (in $RADIOHDL_WORK/build/unb2c/quartus/unb2c_test_...) for each FPGA
+ Select the FPGA(s) which has to be programmed
+ Click 'start'
+Using EPCS: See step 6 below.
+
+
diff --git a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
index 5aef81ed37..6aa79630d1 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
@@ -64,7 +64,7 @@ ENTITY unb2c_minimal IS
PMBUS_ALERT : IN STD_LOGIC := '0';
-- 1GbE Control Interface
- ETH_CLK : IN STD_LOGIC;
+ ETH_CLK : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
@@ -282,9 +282,9 @@ BEGIN
PMBUS_ALERT => PMBUS_ALERT,
-- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
+ ETH_clk => ETH_CLK(0),
+ ETH_SGIN => ETH_SGIN(0),
+ ETH_SGOUT => ETH_SGOUT(0)
);
-----------------------------------------------------------------------------
diff --git a/boards/uniboard2c/designs/unb2c_test/doc/README.txt b/boards/uniboard2c/designs/unb2c_test/doc/README.txt
index bf6717f045..dc0de17d70 100644
--- a/boards/uniboard2c/designs/unb2c_test/doc/README.txt
+++ b/boards/uniboard2c/designs/unb2c_test/doc/README.txt
@@ -1,50 +1,39 @@
-Quick steps to compile and use design [unb2c_test] in RadionHDL
----------------------------------------------------------------
+This is the testsuite for Uniboard2c.
+Here are quick steps to compile and use test designs in RadionHDL.
+------------------------------------------------------------------
-The following revisions are available for unb2c_test (see the directories in ../revisions/):
+Ideally the test design "unb2c_test" would contain all test suites in one but that does
+not fit in the device. Therefore revisions are prepared.
- unb2c_test_1GbE : same as unb2c_minimal design but with extra 1GbE offload
- STATUS: copied from unb2_test but not tested yet
+The available revisions for unb2c_test are in the directory: ../revisions/
+The specifications and features of each revision is listed in the VHDL file:
+../src/vhdl/unb2c_test_pkg.vhd , below the comment "Revision Control".
- unb2c_test_10GbE : same as unb2c_test_1GbE but with 10GbE offload channels (24 QSFP channels)
- STATUS: copied from unb2_test but not tested yet
- unb2c_test_ddr_MB_I : same as unb2c_test_1GbE but with 1 DDR4 module (I)
- STATUS: tested OK
-
- unb2c_test_ddr_MB_II : same as unb2c_test_1GbE but with 1 DDR4 module (II)
- STATUS: tested OK
-
- unb2c_test_ddr_MB_I_II : same as unb2c_test_1GbE but with 2 DDR4 modules (I,II)
- STATUS: tested OK
-
- unb2c_test_all : unb2c_test_1GbE + unb2c_test_10GbE + unb2c_test_ddr_MB_I_II
- STATUS: copied from unb2_test but not tested yet
+Steps to go:
+------------
+-> At all times run:
+ cd ${GIT}/hdl
+ . init_hdl.sh
-> In case of a new installation, the IP's have to be generated for Arria10.
- In the: $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg
- directory; run the bash script: ./generate-all-ip.sh
- -> The TSE IP gives a lot of critical warnings. To fix them, run this patch:
- cd $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds
- ./run_patch.sh
+ echo $RADIOHDL_BUILD_DIR # should be something like /home/user/git/hdl/build
+ rm -r $RADIOHDL_BUILD_DIR/unb2c # optional
+ compile_altera_simlibs unb2c
+ generate_ip_libs unb2c
1. Start with the Oneclick Commands:
- python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2c
- python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2c
+ modelsim_config unb2c
+ quartus_config unb2c
2. Generate MMM for QSYS (select one of these revisions):
- run_qsys unb2c unb2c_test_1GbE
- run_qsys unb2c unb2c_test_10GbE
- run_qsys unb2c unb2c_test_ddr_MB_I
- run_qsys unb2c unb2c_test_ddr_MB_II
- run_qsys unb2c unb2c_test_ddr_MB_I_II
- run_qsys unb2c unb2c_test_all
+ run_qsys_pro unb2c revision # where 'revision' is 1 design out of ../revisions/
@@ -52,8 +41,6 @@ The following revisions are available for unb2c_test (see the directories in ../
Simulation
----------
- # in bash do:
- rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
run_modelsim unb2c
Further Modelsim instructions: see the README file in the ../revisions/* directories
@@ -63,19 +50,19 @@ Further Modelsim instructions: see the README file in the ../revisions/* directo
Synthesis
---------
Quartus instructions: (select one of these revisions):
- run_qcomp unb2c unb2c_test_1GbE
- run_qcomp unb2c unb2c_test_10GbE
- run_qcomp unb2c unb2c_test_ddr_MB_I
- run_qcomp unb2c unb2c_test_ddr_MB_II
- run_qcomp unb2c unb2c_test_ddr_MB_I_II
- run_qcomp unb2c unb2c_test_all
+ run_qcomp unb2c revision # where 'revision' is 1 design out of ../revisions/
-In case of needing the Quartus GUI for inspection (this starts the Quartus 15.1 GUI):
+Or compile using the Quartus GUI:
run_quartus unb2c
load the project now from the build directory.
+
+
+
+
+
4. Load firmware
----------------
Using JTAG: Start the Quartus GUI and open: tools->programmer.
diff --git a/boards/uniboard2c/designs/unb2c_test/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/hdllib.cfg
index 7adbf2e952..108fda6f6f 100644
--- a/boards/uniboard2c/designs/unb2c_test/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = unb2c_test
hdl_library_clause_name = unb2c_test_lib
-hdl_lib_uses_synth = common technology mm unb2c_board unb2c_board_10gbe dp eth tech_tse diagnostics diag tech_mac_10g io_ddr tech_ddr tech_jesd204b
+hdl_lib_uses_synth = common technology mm unb2c_board unb2c_board_10gbe dp eth tech_tse diagnostics diag tech_mac_10g io_ddr tech_ddr tech_jesd204b util
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e2sg
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
index d8505d23aa..73337f8198 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
@@ -37,7 +37,7 @@ ENTITY unb2c_test_10GbE IS
g_sim_node_nr : NATURAL := 0;
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : STRING := 0 -- revision ID -- set by QSF
+ g_revision_id : STRING := "" -- revision ID -- set by QSF
);
PORT (
-- GENERAL
@@ -57,7 +57,7 @@ ENTITY unb2c_test_10GbE IS
SENS_SD : INOUT STD_LOGIC;
-- 1GbE Control Interface
- ETH_CLK : IN STD_LOGIC;
+ ETH_CLK : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
@@ -67,20 +67,15 @@ ENTITY unb2c_test_10GbE IS
BCK_REF_CLK : IN STD_LOGIC; -- Clock 10GbE back lower 24 lines
-- back transceivers
--- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2c_board_tr_back.bus_w * c_unb2c_board_tr_back.nof_bus)-1 downto 0);
--- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2c_board_tr_back.bus_w * c_unb2c_board_tr_back.nof_bus)-1 downto 0);
--- BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
--- BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
-
- BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2c_board_tr_back.i2c_w-1 downto 0);
- BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2c_board_tr_back.i2c_w-1 downto 0);
- BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2c_board_tr_back.i2c_w-1 downto 0);
+ BCK_RX : IN STD_LOGIC_VECTOR((c_unb2c_board_tr_back.bus_w * c_unb2c_board_tr_back.nof_bus)-1 downto 0);
+ BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2c_board_tr_back.bus_w * c_unb2c_board_tr_back.nof_bus)-1 downto 0);
-- ring transceivers
- -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_ring.bus_w-1 downto 0);
- -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_ring.bus_w-1 downto 0);
- -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_ring.bus_w-1 downto 0);
- -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_ring.bus_w-1 downto 0);
+ RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_ring.bus_w-1 downto 0);
+ RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_ring.bus_w-1 downto 0);
+ RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_ring.bus_w-1 downto 0);
+ RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_ring.bus_w-1 downto 0);
+
-- pmbus
PMBUS_SC : INOUT STD_LOGIC;
PMBUS_SD : INOUT STD_LOGIC;
@@ -147,18 +142,15 @@ BEGIN
BCK_REF_CLK => BCK_REF_CLK,
-- back transceivers
- -- BCK_RX => BCK_RX,
- -- BCK_TX => BCK_TX,
-
- BCK_SDA => BCK_SDA,
- BCK_SCL => BCK_SCL,
- BCK_ERR => BCK_ERR,
+ BCK_RX => BCK_RX,
+ BCK_TX => BCK_TX,
-- ring transceivers
- -- RING_0_RX => RING_0_RX,
- -- RING_0_TX => RING_0_TX,
- -- RING_1_RX => RING_1_RX,
- -- RING_1_TX => RING_1_TX,
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
-- pmbus
PMBUS_SC => PMBUS_SC,
PMBUS_SD => PMBUS_SD,
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/hdllib.cfg
new file mode 100644
index 0000000000..a93f5ca758
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/hdllib.cfg
@@ -0,0 +1,115 @@
+hdl_lib_name = unb2c_test_ddr
+hdl_library_clause_name = unb2c_test_ddr_lib
+hdl_lib_uses_synth = common mm technology unb2c_board unb2c_test
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e2sg
+hdl_lib_include_ip =
+ # Comment all IP that is not used in this design
+ # DDR memory
+ ip_arria10_e2sg_ddr4_8g_1600
+
+synth_files =
+ unb2c_test_ddr.vhd
+
+test_bench_files =
+ tb_unb2c_test_ddr.vhd
+
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/hex hex
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ quartus .
+ ../../quartus .
+ ../../src/hex hex
+
+quartus_qsf_files =
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+
+quartus_sdc_pre_files =
+ quartus/unb2c_test_ddr.sdc
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
+
+quartus_sdc_files =
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+
+quartus_tcl_files =
+ quartus/unb2c_test_ddr_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/qsys_unb2c_test/qsys_unb2c_test.qip
+
+quartus_ip_files =
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dp_shiftram.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_unb_pmbus.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_unb_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+
+
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/quartus/unb2c_test_ddr.sdc b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/quartus/unb2c_test_ddr.sdc
new file mode 100644
index 0000000000..fbcc86fb1b
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/quartus/unb2c_test_ddr.sdc
@@ -0,0 +1 @@
+#set_false_path -from [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}] -to [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/quartus/unb2c_test_ddr_pins.tcl b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/quartus/unb2c_test_ddr_pins.tcl
new file mode 100644
index 0000000000..e659f0faff
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/quartus/unb2c_test_ddr_pins.tcl
@@ -0,0 +1,23 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_ddr_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd
new file mode 100644
index 0000000000..f8fe0e6bec
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd
@@ -0,0 +1,38 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, unb2c_test_lib;
+USE IEEE.std_logic_1164.ALL;
+
+
+ENTITY tb_unb2c_test_ddr IS
+END tb_unb2c_test_ddr;
+
+
+ARCHITECTURE tb OF tb_unb2c_test_ddr IS
+BEGIN
+ u_tb_unb2c_test : ENTITY unb2c_test_lib.tb_unb2c_test
+ GENERIC MAP (
+ g_design_name => "unb2c_test_ddr"
+ );
+END tb;
+
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd
new file mode 100644
index 0000000000..2d1abcaf36
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd
@@ -0,0 +1,146 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib, tech_ddr_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2c_board_lib.unb2c_board_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+
+
+ENTITY unb2c_test_ddr IS
+ GENERIC (
+ g_design_name : STRING := "unb2c_test_ddr";
+ g_design_note : STRING := "DDR: MB I and II";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := "" -- revision ID -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2c_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+
+ -- pmbus
+ PMBUS_SC : INOUT STD_LOGIC;
+ PMBUS_SD : INOUT STD_LOGIC;
+ PMBUS_ALERT : IN STD_LOGIC;
+
+ -- DDR reference clocks
+ MB_I_REF_CLK : IN STD_LOGIC; -- Reference clock for MB_I
+ MB_II_REF_CLK : IN STD_LOGIC; -- Reference clock for MB_II
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN : IN t_tech_ddr4_phy_in;
+ MB_I_IO : INOUT t_tech_ddr4_phy_io;
+ MB_I_OU : OUT t_tech_ddr4_phy_ou;
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN : IN t_tech_ddr4_phy_in;
+ MB_II_IO : INOUT t_tech_ddr4_phy_io;
+ MB_II_OU : OUT t_tech_ddr4_phy_ou;
+
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+ );
+END unb2c_test_ddr;
+
+
+ARCHITECTURE str OF unb2c_test_ddr IS
+
+BEGIN
+ u_revision : ENTITY unb2c_test_lib.unb2c_test
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
+END str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/hdllib.cfg
new file mode 100644
index 0000000000..91cf1a1fd7
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/hdllib.cfg
@@ -0,0 +1,112 @@
+hdl_lib_name = unb2c_test_heater
+hdl_library_clause_name = unb2c_test_heater_lib
+hdl_lib_uses_synth = common mm technology unb2c_board unb2c_test
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e2sg
+hdl_lib_include_ip =
+
+synth_files =
+ unb2c_test_heater.vhd
+
+test_bench_files =
+ tb_unb2c_test_heater.vhd
+
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/hex hex
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ quartus .
+ ../../quartus .
+ ../../src/hex hex
+
+quartus_qsf_files =
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+
+quartus_sdc_pre_files =
+ quartus/unb2c_test_heater.sdc
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
+
+quartus_sdc_files =
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+
+quartus_tcl_files =
+ quartus/unb2c_test_heater_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/qsys_unb2c_test/qsys_unb2c_test.qip
+
+quartus_ip_files =
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dp_shiftram.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_unb_pmbus.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_unb_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+
+
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/quartus/unb2c_test_heater.sdc b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/quartus/unb2c_test_heater.sdc
new file mode 100644
index 0000000000..fbcc86fb1b
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/quartus/unb2c_test_heater.sdc
@@ -0,0 +1 @@
+#set_false_path -from [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}] -to [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/quartus/unb2c_test_heater_pins.tcl b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/quartus/unb2c_test_heater_pins.tcl
new file mode 100644
index 0000000000..ae417258f8
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/quartus/unb2c_test_heater_pins.tcl
@@ -0,0 +1,22 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd
new file mode 100644
index 0000000000..f9765ad948
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd
@@ -0,0 +1,38 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, unb2c_test_lib;
+USE IEEE.std_logic_1164.ALL;
+
+
+ENTITY tb_unb2c_test_heater IS
+END tb_unb2c_test_heater;
+
+
+ARCHITECTURE tb OF tb_unb2c_test_heater IS
+BEGIN
+ u_tb_unb2c_test : ENTITY unb2c_test_lib.tb_unb2c_test
+ GENERIC MAP (
+ g_design_name => "unb2c_test_heater"
+ );
+END tb;
+
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd
new file mode 100644
index 0000000000..e5757d6e5e
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd
@@ -0,0 +1,117 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2c_board_lib.unb2c_board_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+
+
+ENTITY unb2c_test_heater IS
+ GENERIC (
+ g_design_name : STRING := "unb2c_test_heater";
+ g_design_note : STRING := "heater: none";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := "" -- revision ID -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2c_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+
+ -- pmbus
+ PMBUS_SC : INOUT STD_LOGIC;
+ PMBUS_SD : INOUT STD_LOGIC;
+ PMBUS_ALERT : IN STD_LOGIC;
+
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+ );
+END unb2c_test_heater;
+
+
+ARCHITECTURE str OF unb2c_test_heater IS
+
+BEGIN
+ u_revision : ENTITY unb2c_test_lib.unb2c_test
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ QSFP_LED => QSFP_LED
+ );
+END str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/hdllib.cfg
new file mode 100644
index 0000000000..f58ef84acd
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/hdllib.cfg
@@ -0,0 +1,112 @@
+hdl_lib_name = unb2c_test_jesd204b
+hdl_library_clause_name = unb2c_test_jesd204b_lib
+hdl_lib_uses_synth = common mm technology unb2c_board unb2c_test
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e2sg
+hdl_lib_include_ip =
+
+synth_files =
+ unb2c_test_jesd204b.vhd
+
+test_bench_files =
+ tb_unb2c_test_jesd204b.vhd
+
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/hex hex
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ quartus .
+ ../../quartus .
+ ../../src/hex hex
+
+quartus_qsf_files =
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+
+quartus_sdc_pre_files =
+ quartus/unb2c_test_jesd204b.sdc
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
+
+quartus_sdc_files =
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+
+quartus_tcl_files =
+ quartus/unb2c_test_jesd204b_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/qsys_unb2c_test/qsys_unb2c_test.qip
+
+quartus_ip_files =
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dp_shiftram.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_unb_pmbus.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_unb_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+
+
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/quartus/unb2c_test_jesd204b.sdc b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/quartus/unb2c_test_jesd204b.sdc
new file mode 100644
index 0000000000..fbcc86fb1b
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/quartus/unb2c_test_jesd204b.sdc
@@ -0,0 +1 @@
+#set_false_path -from [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}] -to [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/quartus/unb2c_test_jesd204b_pins.tcl b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/quartus/unb2c_test_jesd204b_pins.tcl
new file mode 100644
index 0000000000..face7edbab
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/quartus/unb2c_test_jesd204b_pins.tcl
@@ -0,0 +1,23 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_jesd204b_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd
new file mode 100644
index 0000000000..566cf243de
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd
@@ -0,0 +1,38 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, unb2c_test_lib;
+USE IEEE.std_logic_1164.ALL;
+
+
+ENTITY tb_unb2c_test_jesd204b IS
+END tb_unb2c_test_jesd204b;
+
+
+ARCHITECTURE tb OF tb_unb2c_test_jesd204b IS
+BEGIN
+ u_tb_unb2c_test : ENTITY unb2c_test_lib.tb_unb2c_test
+ GENERIC MAP (
+ g_design_name => "unb2c_test_jesd204b"
+ );
+END tb;
+
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd
new file mode 100644
index 0000000000..ec84b97512
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd
@@ -0,0 +1,117 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2c_board_lib.unb2c_board_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+
+
+ENTITY unb2c_test_jesd204b IS
+ GENERIC (
+ g_design_name : STRING := "unb2c_test_jesd204b";
+ g_design_note : STRING := "jesd204b: none";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := "" -- revision ID -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2c_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+
+ -- pmbus
+ PMBUS_SC : INOUT STD_LOGIC;
+ PMBUS_SD : INOUT STD_LOGIC;
+ PMBUS_ALERT : IN STD_LOGIC;
+
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+ );
+END unb2c_test_jesd204b;
+
+
+ARCHITECTURE str OF unb2c_test_jesd204b IS
+
+BEGIN
+ u_revision : ENTITY unb2c_test_lib.unb2c_test
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ QSFP_LED => QSFP_LED
+ );
+END str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
index cc65f82fea..99eb679928 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
@@ -57,7 +57,7 @@ ENTITY unb2c_test_minimal IS
SENS_SD : INOUT STD_LOGIC;
-- 1GbE Control Interface
- ETH_CLK : IN STD_LOGIC;
+ ETH_CLK : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
index 3bf0020794..0d6184b46b 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
@@ -128,6 +128,10 @@ ENTITY mmm_unb2c_test IS
reg_remu_mosi : OUT t_mem_mosi;
reg_remu_miso : IN t_mem_miso;
+ -- Heater
+ reg_heater_mosi : OUT t_mem_mosi;
+ reg_heater_miso : IN t_mem_miso;
+
-- block gen
ram_diag_bg_1GbE_mosi : OUT t_mem_mosi;
ram_diag_bg_1GbE_miso : IN t_mem_miso;
@@ -400,6 +404,10 @@ BEGIN
u_mm_file_reg_eth10g_back1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK1")
PORT MAP(mm_rst, mm_clk, reg_eth10g_back1_mosi, reg_eth10g_back1_miso);
+ u_mm_file_reg_heater : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HEATER")
+ PORT MAP(mm_rst, mm_clk, reg_heater_mosi, reg_heater_miso );
+
+
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
----------------------------------------------------------------------------
@@ -814,7 +822,16 @@ BEGIN
ram_diag_data_buffer_ddr_MB_II_write_export => ram_diag_data_buf_ddr_MB_II_mosi.wr,
ram_diag_data_buffer_ddr_MB_II_writedata_export => ram_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_diag_data_buffer_ddr_MB_II_read_export => ram_diag_data_buf_ddr_MB_II_mosi.rd,
- ram_diag_data_buffer_ddr_MB_II_readdata_export => ram_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w-1 DOWNTO 0)
+ ram_diag_data_buffer_ddr_MB_II_readdata_export => ram_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_heater_reset_export => OPEN,
+ reg_heater_clk_export => OPEN,
+ reg_heater_address_export => reg_heater_mosi.address(4 DOWNTO 0),
+ reg_heater_read_export => reg_heater_mosi.rd,
+ reg_heater_readdata_export => reg_heater_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_heater_write_export => reg_heater_mosi.wr,
+ reg_heater_writedata_export => reg_heater_mosi.wrdata(c_word_w-1 DOWNTO 0)
+
);
END GENERATE;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
index 29ed873843..c010c0ee05 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
@@ -20,7 +20,7 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2c_board_lib, unb2c_board_10gbe_lib, dp_lib, eth_lib, tr_10GbE_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib, tech_jesd204b_lib;
+LIBRARY IEEE, common_lib, unb2c_board_lib, unb2c_board_10gbe_lib, dp_lib, eth_lib, tr_10GbE_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib, tech_jesd204b_lib, util_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
@@ -35,6 +35,8 @@ USE diag_lib.diag_pkg.ALL;
USE eth_lib.eth_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
USE work.unb2c_test_pkg.ALL;
+USE util_lib.util_heater_pkg.ALL;
+
ENTITY unb2c_test IS
GENERIC (
@@ -68,7 +70,7 @@ ENTITY unb2c_test IS
SENS_SD : INOUT STD_LOGIC;
-- 1GbE Control Interface
- ETH_CLK : IN STD_LOGIC := '0';
+ ETH_CLK : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
@@ -150,6 +152,7 @@ ARCHITECTURE str OF unb2c_test IS
CONSTANT c_use_10GbE_back1 : BOOLEAN := c_revision_select.use_10GbE_back1;
CONSTANT c_use_10GbE : BOOLEAN := c_use_10GbE_qsfp OR c_use_10GbE_ring OR c_use_10GbE_back0 OR c_use_10GbE_back1;
CONSTANT c_use_jesd204b : BOOLEAN := c_revision_select.use_jesd204b;
+ CONSTANT c_use_heater : BOOLEAN := c_revision_select.use_heater;
CONSTANT c_use_MB_I : BOOLEAN := c_revision_select.use_MB_I;
CONSTANT c_use_MB_II : BOOLEAN := c_revision_select.use_MB_II;
CONSTANT c_ddr_MB_I : t_c_tech_ddr := c_revision_select.type_MB_I;
@@ -315,6 +318,10 @@ ARCHITECTURE str OF unb2c_test IS
SIGNAL jesd204b_mosi : t_mem_mosi;
SIGNAL jesd204b_miso : t_mem_miso;
+ -- Heater
+ SIGNAL reg_heater_mosi : t_mem_mosi;
+ SIGNAL reg_heater_miso : t_mem_miso;
+
-- 10GbE
SIGNAL i_serial_10G_tx_qsfp_ring_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO 0);
SIGNAL i_serial_10G_rx_qsfp_ring_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO 0);
@@ -333,8 +340,8 @@ ARCHITECTURE str OF unb2c_test IS
SIGNAL i_QSFP_RX : t_unb2c_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0);
SIGNAL i_RING_TX : t_unb2c_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
SIGNAL i_RING_RX : t_unb2c_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- -- SIGNAL i_BCK_TX : t_unb2c_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
- -- SIGNAL i_BCK_RX : t_unb2c_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ SIGNAL i_BCK_TX : t_unb2c_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ SIGNAL i_BCK_RX : t_unb2c_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
SIGNAL serial_10G_tx_back_arr : STD_LOGIC_VECTOR(c_nof_streams_back0+c_nof_streams_back1-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL serial_10G_rx_back_arr : STD_LOGIC_VECTOR(c_nof_streams_back0+c_nof_streams_back1-1 DOWNTO 0);
@@ -588,7 +595,7 @@ BEGIN
MB_I_REF_CLK => MB_I_REF_CLK,
MB_II_REF_CLK => MB_II_REF_CLK,
-- . 1GbE Control Interface
- ETH_CLK => ETH_CLK,
+ ETH_CLK => ETH_CLK(0),
ETH_SGIN => ETH_SGIN(0),
ETH_SGOUT => ETH_SGOUT(0)
);
@@ -684,6 +691,10 @@ BEGIN
reg_remu_mosi => reg_remu_mosi,
reg_remu_miso => reg_remu_miso,
+ -- heater:
+ reg_heater_mosi => reg_heater_mosi,
+ reg_heater_miso => reg_heater_miso,
+
-- block gen
ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
@@ -869,8 +880,8 @@ BEGIN
-- Clocks and reset
mm_rst => mm_rst, -- use reset from QSYS
mm_clk => mm_clk, -- use mm_clk direct
- eth_clk => xo_ethclk, -- 125 MHz clock
- --eth_clk => ETH_CLK1, -- try direct connection to the pin
+ --eth_clk => xo_ethclk, -- 125 MHz clock
+ eth_clk => ETH_CLK(1),
st_rst => dp_rst,
st_clk => dp_clk,
@@ -1112,6 +1123,7 @@ BEGIN
);
END GENERATE;
+
gen_jesd204b : IF c_use_jesd204b = TRUE GENERATE
u_jesd204b: ENTITY tech_jesd204b_lib.tech_jesd204b
GENERIC MAP(
@@ -1164,13 +1176,9 @@ BEGIN
-- Serial I/O
-- back transceivers
BCK_RX(0) => BCK_RX(c_nof_streams_back0-1 downto 0),
- BCK_TX(0) => BCK_TX(c_nof_streams_back0-1 downto 0),
- BCK_RX(1) => BCK_RX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
- BCK_TX(1) => BCK_TX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
-
- BCK_SDA => open,
- BCK_SCL => open,
- BCK_ERR => open
+ BCK_TX(0) => BCK_TX(c_nof_streams_back0-1 downto 0)
+ --BCK_RX(1) => BCK_RX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
+ --BCK_TX(1) => BCK_TX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0)
);
END GENERATE;
@@ -1190,11 +1198,7 @@ BEGIN
-- -- Serial I/O
-- -- back transceivers
-- BCK_RX(0) => BCK_RX(c_nof_streams_jesd204b-1 downto 0),
--- BCK_TX(0) => open,
---
--- BCK_SDA => BCK_SDA,
--- BCK_SCL => BCK_SCL,
--- BCK_ERR => BCK_ERR
+-- BCK_TX(0) => open
-- );
-- END GENERATE;
@@ -1415,5 +1419,29 @@ BEGIN
);
END GENERATE;
+ gen_heater : IF c_use_heater = TRUE GENERATE
+ u_heater : ENTITY util_lib.util_heater
+ GENERIC MAP (
+ g_technology => g_technology,
+ --g_nof_mac4 => 315 -- on Arria10 using 630 of 1518 DSP blocks
+ --g_nof_mac4 => 630 --
+ g_nof_mac4 => 736, -- max 736, 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
+ g_pipeline => 72, -- max 72
+ g_nof_ram => 4, -- max 4
+ g_nof_logic => 24 -- max 24
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ sla_in => reg_heater_mosi,
+ sla_out => reg_heater_miso
+ );
+ END GENERATE;
+
+
END str;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
index 72b312110e..3ccb2ad4fb 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
@@ -73,14 +73,16 @@ PACKAGE unb2c_test_pkg IS
use_jesd204b : BOOLEAN;
use_MB_I : BOOLEAN;
use_MB_II : BOOLEAN;
+ use_heater : BOOLEAN;
type_MB_I : t_c_tech_ddr;
type_MB_II : t_c_tech_ddr;
END RECORD;
- -- loop 1GbE 1GbE qsfp ring bk0 bk1 jesd DDR4 DDR4
- CONSTANT c_pinning : t_unb2c_test_config := ( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,FALSE, TRUE, TRUE, c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- CONSTANT c_pinning_jesd204b : t_unb2c_test_config := ( TRUE, TRUE, TRUE, TRUE, TRUE,FALSE,FALSE, TRUE, TRUE, TRUE, c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- CONSTANT c_test_minimal : t_unb2c_test_config := (FALSE, TRUE, TRUE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- CONSTANT c_test_all : t_unb2c_test_config := (FALSE, TRUE, TRUE, TRUE, TRUE,FALSE,FALSE,FALSE, TRUE, TRUE, c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ -- loop 1GbE 1GbE qsfp ring bk0 bk1 jesd DDR4 DDR4 heatr
+ CONSTANT c_test_minimal : t_unb2c_test_config := (FALSE, TRUE, TRUE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ CONSTANT c_test_10GbE : t_unb2c_test_config := (FALSE, TRUE, TRUE, TRUE, TRUE, TRUE,FALSE,FALSE,FALSE,FALSE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ CONSTANT c_test_ddr : t_unb2c_test_config := (FALSE, TRUE, TRUE,FALSE,FALSE,FALSE,FALSE,FALSE, TRUE, TRUE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ CONSTANT c_test_heater : t_unb2c_test_config := (FALSE, TRUE, TRUE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE, TRUE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ CONSTANT c_test_jesd204b : t_unb2c_test_config := (FALSE, TRUE, TRUE,FALSE,FALSE,FALSE,FALSE, TRUE,FALSE,FALSE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
-- Function to select the revision configuration.
FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_unb2c_test_config;
@@ -93,10 +95,11 @@ PACKAGE BODY unb2c_test_pkg IS
FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_unb2c_test_config IS
BEGIN
- IF g_design_name = "unb2c_test_pinning" THEN RETURN c_pinning;
- ELSIF g_design_name = "unb2c_test_pinning_jesd204b" THEN RETURN c_pinning_jesd204b;
- ELSIF g_design_name = "unb2c_test_minimal" THEN RETURN c_test_minimal;
- ELSIF g_design_name = "unb2c_test_all" THEN RETURN c_test_all;
+ IF g_design_name = "unb2c_test_minimal" THEN RETURN c_test_minimal;
+ ELSIF g_design_name = "unb2c_test_10GbE" THEN RETURN c_test_10GbE;
+ ELSIF g_design_name = "unb2c_test_ddr" THEN RETURN c_test_ddr;
+ ELSIF g_design_name = "unb2c_test_heater" THEN RETURN c_test_heater;
+ ELSIF g_design_name = "unb2c_test_jesd204b" THEN RETURN c_test_jesd204b;
ELSE RETURN c_test_minimal;
END IF;
END;
diff --git a/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_10GbE_pins.tcl b/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_10GbE_pins.tcl
index 50c27a5d3c..d0f3141ced 100644
--- a/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_10GbE_pins.tcl
+++ b/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_10GbE_pins.tcl
@@ -2054,27 +2054,8 @@ set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[11]
-
-#set_location_assignment PIN_BA25 -to PMBUS_SC
-#set_location_assignment PIN_BD25 -to PMBUS_SD
-#set_location_assignment PIN_BD26 -to PMBUS_ALERT
-#set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_SC
-#set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_SD
-#set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_ALERT
-
-
-
-
-#set_location_assignment PIN_R14 -to BCK_SCL[0]
-#set_location_assignment PIN_Y13 -to BCK_SCL[1]
-#set_location_assignment PIN_U14 -to BCK_SCL[2]
-#set_location_assignment PIN_P14 -to BCK_SDA[0]
-#set_location_assignment PIN_T12 -to BCK_SDA[1]
-#set_location_assignment PIN_V12 -to BCK_SDA[2]
-
set_location_assignment PIN_AT31 -to QSFP_RST
-# FIXME are they gone: ?
set_location_assignment PIN_AY33 -to QSFP_SCL[0]
set_location_assignment PIN_AY32 -to QSFP_SCL[1]
set_location_assignment PIN_AY30 -to QSFP_SCL[2]
@@ -2087,18 +2068,9 @@ set_location_assignment PIN_AP33 -to QSFP_SDA[2]
set_location_assignment PIN_AM33 -to QSFP_SDA[3]
set_location_assignment PIN_AK33 -to QSFP_SDA[4]
set_location_assignment PIN_AH32 -to QSFP_SDA[5]
-#set_location_assignment PIN_M13 -to BCK_ERR[0]
-#set_location_assignment PIN_R13 -to BCK_ERR[1]
-#set_location_assignment PIN_U12 -to BCK_ERR[2]
set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[5]
set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[5]
-#set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SDA[0]
-#set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SCL[0]
-#set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SDA[1]
-#set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SCL[1]
-#set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SDA[2]
-#set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_SCL[2]
set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[0]
@@ -2110,7 +2082,4 @@ set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[2]
set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[3]
set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[4]
set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_RST
-#set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_ERR[0]
-#set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_ERR[1]
-#set_instance_assignment -name IO_STANDARD "1.8 V" -to BCK_ERR[2]
diff --git a/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl b/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
index 909af5c9b9..9acaeb5391 100644
--- a/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+++ b/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
@@ -2,7 +2,6 @@
set_location_assignment PIN_K15 -to CLK
set_location_assignment PIN_J15 -to "CLK(n)"
-#set_location_assignment PIN_N12 -to ETH_CLK
set_location_assignment PIN_N12 -to ETH_CLK[0]
set_location_assignment PIN_AK33 -to ETH_CLK[1]
set_location_assignment PIN_H17 -to S10_ETH_CLK
@@ -31,13 +30,6 @@ set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to CLK
-
-# IO Standard Assignments from Gijs (excluding memory)
-#set_instance_assignment -name IO_STANDARD "1.8 V" -to ETH_CLK
-# Changed from "GLOBAL_CLOCK" due to Error 18694
-#set_instance_assignment -name GLOBAL_SIGNAL "OFF" -to ETH_CLK
-#set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL_CLOCK" -to ETH_CLK
-
set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[0]
set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGIN[0](n)"
set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[1]
@@ -50,18 +42,12 @@ set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGOUT[1](n)"
set_location_assignment PIN_K12 -to ETH_SGIN[0]
set_location_assignment PIN_J12 -to "ETH_SGIN[0](n)"
-# Try placing eth1 in the same block as eth0
-#set_location_assignment PIN_U12 -to ETH_SGIN[1]
-#set_location_assignment PIN_T12 -to "ETH_SGIN[1](n)"
set_location_assignment PIN_AF33 -to ETH_SGIN[1]
set_location_assignment PIN_AE33 -to "ETH_SGIN[1](n)"
set_location_assignment PIN_H13 -to ETH_SGOUT[0]
set_location_assignment PIN_H12 -to "ETH_SGOUT[0](n)"
-# Try placing eth1 in the same block as eth0
-#set_location_assignment PIN_G13 -to ETH_SGOUT[1]
-#set_location_assignment PIN_H14 -to "ETH_SGOUT[1](n)"
set_location_assignment PIN_AW31 -to ETH_SGOUT[1]
set_location_assignment PIN_AV31 -to "ETH_SGOUT[1](n)"
@@ -97,7 +83,6 @@ set_instance_assignment -name IO_STANDARD "1.8 V" -to VERSION[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to VERSION[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to WDI
-# locations changed 30 sept
set_location_assignment PIN_P16 -to ID[0]
set_location_assignment PIN_P15 -to ID[1]
set_location_assignment PIN_K13 -to ID[2]
@@ -167,5 +152,3 @@ set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[9]
set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[10]
set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_LED[11]
-
-
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd
index ba203e23b3..b9b3afc3e2 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd
@@ -34,11 +34,7 @@ ENTITY unb2c_board_back_io IS
-- back transceivers
BCK_RX : IN t_unb2c_board_back_bus_2arr(g_nof_back_bus-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
- BCK_TX : OUT t_unb2c_board_back_bus_2arr(g_nof_back_bus-1 DOWNTO 0);
-
- BCK_SDA : INOUT STD_LOGIC_VECTOR(c_unb2c_board_tr_back.i2c_w-1 DOWNTO 0);
- BCK_SCL : INOUT STD_LOGIC_VECTOR(c_unb2c_board_tr_back.i2c_w-1 DOWNTO 0);
- BCK_ERR : INOUT STD_LOGIC_VECTOR(c_unb2c_board_tr_back.i2c_w-1 DOWNTO 0)
+ BCK_TX : OUT t_unb2c_board_back_bus_2arr(g_nof_back_bus-1 DOWNTO 0)
);
END unb2c_board_back_io;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd
index 5d88daefc2..a81c212512 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd
@@ -38,8 +38,6 @@ ENTITY unb2c_board_front_io IS
QSFP_RX : IN t_unb2c_board_qsfp_bus_2arr(g_nof_qsfp_bus-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
QSFP_TX : OUT t_unb2c_board_qsfp_bus_2arr(g_nof_qsfp_bus-1 DOWNTO 0);
- --QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.i2c_w-1 downto 0);
- --QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.i2c_w-1 downto 0);
--QSFP_RST : INOUT STD_LOGIC;
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0)
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600.ip b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600.ip
index 39363aac32..687dad5c46 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600.ip
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600.ip
@@ -2794,7 +2794,7 @@
<ipxact:parameter parameterId="PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM" type="string">
<ipxact:name>PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM</ipxact:name>
<ipxact:displayName>PLL reference clock I/O standard</ipxact:displayName>
- <ipxact:value>IO_STD_LVDS</ipxact:value>
+ <ipxact:value>IO_STD_CMOS_12</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="PHY_DDR4_USER_RZQ_IO_STD_ENUM" type="string">
<ipxact:name>PHY_DDR4_USER_RZQ_IO_STD_ENUM</ipxact:name>
@@ -2859,7 +2859,7 @@
<ipxact:parameter parameterId="PHY_DDR4_PLL_REF_CLK_IO_STD_ENUM" type="string">
<ipxact:name>PHY_DDR4_PLL_REF_CLK_IO_STD_ENUM</ipxact:name>
<ipxact:displayName>PLL reference clock I/O standard</ipxact:displayName>
- <ipxact:value>IO_STD_LVDS</ipxact:value>
+ <ipxact:value>IO_STD_CMOS_12</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="PHY_DDR4_RZQ_IO_STD_ENUM" type="string">
<ipxact:name>PHY_DDR4_RZQ_IO_STD_ENUM</ipxact:name>
@@ -10307,27 +10307,6 @@
</consumedSystemInfos>
</value>
</entry>
- <entry>
- <key>ctrl_amm_avalon_slave_0</key>
- <value>
- <connectionPointName>ctrl_amm_avalon_slave_0</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='ctrl_amm_avalon_slave_0' start='0x0' end='0x240000000' datawidth='576' /&gt;&lt;/address-map&gt;</value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>34</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>576</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
<entry>
<key>ctrl_mmr_slave_0</key>
<value>
@@ -10349,27 +10328,6 @@
</consumedSystemInfos>
</value>
</entry>
- <entry>
- <key>ctrl_mmr_slave_avalon_slave_0</key>
- <value>
- <connectionPointName>ctrl_mmr_slave_avalon_slave_0</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='ctrl_mmr_slave_avalon_slave_0' start='0x0' end='0x1000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>12</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
<entry>
<key>emif_usr_clk</key>
<value>
@@ -10383,19 +10341,6 @@
</consumedSystemInfos>
</value>
</entry>
- <entry>
- <key>emif_usr_clk_clock_source</key>
- <value>
- <connectionPointName>emif_usr_clk_clock_source</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>200000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
</connPtSystemInfos>
</systemInfosDefinition></ipxact:value>
</ipxact:parameter>
--
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