diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
index 8876bd0fc5630af28aa0c2834091071ab5fefdd8..34b69bb9152dd49966f73533bc684efe27e9b389 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
@@ -23,21 +23,21 @@
-- WO write only (no VHDL present to access HW in read mode)
-- WE write event (=WO)
-- WR write control, read control
--- RW read status, write control
+-- RW read status, write control
-- RC read, clear on read
-- FR FIFO read
-- FW FIFO write
--
-- wi Bits R/W Name Default Description |REG_unb2c_BOARD_SYSTEM_INFO|
-- =============================================================================
--- 0 [31..0] RO info
+-- 0 [31..0] RO info
-- 1 [7..0] RO 0
-- 2 [31..0] RO design_name
-- . .. . ..
-- 9 [31..0] RO design name
-- 10 [31..0] RO date stamp (YYYYMMDD)
-- 11 [31..0] RO time stamp (HHMMSS)
--- 12 [31..0] RO SVN stamp
+-- 12 [31..0] RO SVN stamp
-- 13 [31..0] RO note
-- . . . ..
-- 20 [31..0] RO note
@@ -60,13 +60,13 @@ ENTITY unb2c_board_system_info_reg IS
);
PORT (
-- Clocks and reset
- mm_rst : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
-
- -- Memory Mapped Slave
- sla_in : IN t_mem_mosi;
- sla_out : OUT t_mem_miso;
-
+
+ -- Memory Mapped Slave
+ sla_in : IN t_mem_mosi;
+ sla_out : OUT t_mem_miso;
+
info : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0)
);
END unb2c_board_system_info_reg;
@@ -80,13 +80,20 @@ ARCHITECTURE rtl OF unb2c_board_system_info_reg IS
CONSTANT c_nof_revision_id_regs : NATURAL := 3; -- revision id, commit hash or id (hash: first 9 chars of the 40chars commit hash)
CONSTANT c_nof_design_note_regs : NATURAL := 13; -- note
- CONSTANT c_nof_regs : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs;
+ CONSTANT c_info_reg : NATURAL := 0;
+ CONSTANT c_use_phy_reg : NATURAL := 1;
+ CONSTANT c_design_name_offset : NATURAL := c_nof_fixed_regs;
+ CONSTANT c_stamp_date_offset : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs;
+ CONSTANT c_stamp_time_offset : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + 1;
+ CONSTANT c_revision_id_offset : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs;
+ CONSTANT c_design_note_offset : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs;
+ CONSTANT c_nof_regs : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs;
CONSTANT c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_nof_regs),
dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
nof_dat => c_nof_regs,
- init_sl => '0');
+ init_sl => '0');
CONSTANT c_use_phy_w : NATURAL := 8;
CONSTANT c_use_phy : STD_LOGIC_VECTOR(c_use_phy_w-1 DOWNTO 0) := (OTHERS=> '0'); -- Unused but keep for compatibillity
@@ -94,7 +101,7 @@ ARCHITECTURE rtl OF unb2c_board_system_info_reg IS
CONSTANT c_design_name : t_slv_32_arr(0 TO c_nof_design_name_regs-1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
CONSTANT c_revision_id : t_slv_32_arr(0 TO c_nof_revision_id_regs-1) := str_to_ascii_slv_32_arr(g_revision_id, c_nof_revision_id_regs);
CONSTANT c_design_note : t_slv_32_arr(0 TO c_nof_design_note_regs-1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
-
+
BEGIN
p_mm_reg : PROCESS (mm_rst, mm_clk)
@@ -106,34 +113,36 @@ BEGIN
ELSIF rising_edge(mm_clk) THEN
-- Read access defaults
sla_out.rdval <= '0';
-
+
-- Read access: get register value
IF sla_in.rd = '1' THEN
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
vA := TO_UINT(sla_in.address(c_mm_reg.adr_w-1 DOWNTO 0));
- IF vA = 0 THEN
+ IF vA = c_info_reg THEN
sla_out.rddata(c_word_w-1 DOWNTO 0) <= info;
-- Use bit 11 to indicate that we're using the MM bus (not the info SLV).
-- Using the MM bus enables user to also read use_phy, design_name etc.
sla_out.rddata(11) <= '1';
- ELSIF vA = 1 THEN
+
+ ELSIF vA = c_use_phy_reg THEN
sla_out.rddata(c_use_phy_w-1 DOWNTO 0) <= c_use_phy;
- ELSIF vA < c_nof_fixed_regs + c_nof_design_name_regs THEN
- sla_out.rddata(c_word_w-1 DOWNTO 0) <= c_design_name(vA-c_nof_fixed_regs);
- ELSIF vA = c_nof_fixed_regs + c_nof_design_name_regs THEN
+ ELSIF vA < c_design_name_offset + c_nof_design_name_regs THEN
+ sla_out.rddata(c_word_w-1 DOWNTO 0) <= c_design_name(vA - c_design_name_offset);
+
+ ELSIF vA = c_stamp_date_offset THEN
sla_out.rddata(c_word_w-1 DOWNTO 0) <= TO_UVEC(g_stamp_date, c_word_w);
- ELSIF vA = c_nof_fixed_regs + c_nof_design_name_regs+1 THEN
+ ELSIF vA = c_stamp_time_offset THEN
sla_out.rddata(c_word_w-1 DOWNTO 0) <= TO_UVEC(g_stamp_time, c_word_w);
- ELSIF vA < c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs THEN
- sla_out.rddata(c_word_w-1 DOWNTO 0) <= c_revision_id(vA-c_nof_fixed_regs-c_nof_design_name_regs-c_nof_stamp_regs);
+ ELSIF vA < c_revision_id_offset + c_nof_revision_id_regs THEN
+ sla_out.rddata(c_word_w-1 DOWNTO 0) <= c_revision_id(vA - c_revision_id_offset);
- ELSIF vA < c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs THEN
- sla_out.rddata(c_word_w-1 DOWNTO 0) <= c_design_note(vA-c_nof_fixed_regs-c_nof_design_name_regs-c_nof_stamp_regs-c_nof_revision_id_regs);
+ ELSIF vA < c_design_note_offset + c_nof_design_note_regs THEN
+ sla_out.rddata(c_word_w-1 DOWNTO 0) <= c_design_note(vA - c_design_note_offset);
END IF;
@@ -141,6 +150,6 @@ BEGIN
END IF;
END PROCESS;
-
+
END rtl;