diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd
index 6ebbfeabb29d293eb8673fb3f1bce043e25e7727..3e3ad8f0a410d0f6ed0ef8468630480dbc21b514 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd
@@ -26,7 +26,7 @@
-- Contains AIT input stage with WG, oversampled FSUB, XSUB, BF and RING, so without ADC JESD.
-LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
@@ -34,6 +34,9 @@ USE common_lib.common_mem_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
+USE wpfb_lib.wpfb_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+
ENTITY disturb2_unb2b_sdp_station_full_wg IS
GENERIC (
@@ -44,7 +47,9 @@ ENTITY disturb2_unb2b_sdp_station_full_wg IS
g_sim_node_nr : NATURAL := 0;
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : STRING := "" -- revision ID -- set by QSF
+ g_revision_id : STRING := ""; -- revision ID -- set by QSF
+ g_wpfb : t_wpfb := c_sdp_wpfb_subbands;
+ g_wpfb_complex : t_wpfb := c_sdp_wpfb_complex_subbands
);
PORT (
-- GENERAL
@@ -100,14 +105,16 @@ BEGIN
u_revision : ENTITY lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
GENERIC MAP (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_wpfb => g_wpfb,
+ g_wpfb_complex => g_wpfb_complex
)
PORT MAP (
-- GENERAL
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/hdllib.cfg
index 58d08abe19530ec2376e4f860c46ea299f245470..d0ccc47927d1d99d2b94926d955c1ce2c367fa2a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/hdllib.cfg
@@ -4,12 +4,14 @@ hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_sdp_station
hdl_lib_uses_sim = eth
hdl_lib_technology = ip_arria10_e1sg
- synth_files =
+synth_files =
disturb2_unb2b_sdp_station_full_wg.vhd
test_bench_files =
+ tb_disturb2_unb2b_sdp_station_full_wg.vhd
regression_test_vhdl =
+ tb_disturb2_unb2b_sdp_station_full_wg.vhd
[modelsim_project_file]
modelsim_copy_files =
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..75b4e33e6fbdbfa2086688217e442a54f89d438a
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd
@@ -0,0 +1,388 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Self-checking testbench for simulating disturb2_unb2b_sdp_station_wg using WG data.
+--
+-- Description:
+-- MM control actions:
+--
+-- 1) Enable calc mode for WG via reg_diag_wg with:
+-- 1.
+-- freq = 19.921875MHz (subband 102)
+-- ampl = 0.5 * 2**13
+-- 2.
+-- freg = 19.43359375 MHz (subband 99.5)
+-- ampl = 0.5 * 2**13
+--
+-- 2) Read current BSN from reg_bsn_scheduler_wg and write reg_bsn_scheduler_wg
+-- to trigger start of WG at BSN.
+--
+-- 3) Verify 10GbE output.
+--
+--
+-- Usage:
+-- > as 7 # default
+-- > as 12 # for detailed debugging
+-- > run -a
+-- Remark: TB based on tb_lofar2_unb2b_beamformer.vhd
+-------------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE wpfb_lib.wpfb_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+USE tech_pll_lib.tech_pll_component_pkg.ALL;
+
+ENTITY tb_disturb2_unb2b_sdp_station_full_wg IS
+END tb_disturb2_unb2b_sdp_station_full_wg;
+
+ARCHITECTURE tb OF tb_disturb2_unb2b_sdp_station_full_wg IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr : NATURAL := 0;
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
+
+ CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
+ CONSTANT c_ext_clk_period : TIME := 5 ns;
+ CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
+ CONSTANT c_sa_clk_period : TIME := tech_pll_clk_644_period; -- 644MHz
+ CONSTANT c_pps_period : NATURAL := 1000;
+
+ CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
+ CONSTANT c_cable_delay : TIME := 12 ns;
+
+ CONSTANT c_nof_block_per_sync : NATURAL := 16;
+ CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
+ CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
+ CONSTANT c_wpfb_complex_sim : t_wpfb := func_wpfb_map_real_input_wpfb_parameters_to_complex_input(c_wpfb_sim);
+
+ -- WG
+ CONSTANT c_full_scale_ampl : REAL := REAL(2**(c_sdp_W_adc-1)-1); -- = full scale of WG
+ CONSTANT c_bsn_start_wg : NATURAL := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ CONSTANT c_ampl_sp : NATURAL := 2**(c_sdp_W_adc-1) / 2; -- in number of lsb
+ CONSTANT c_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit/REAL(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
+ CONSTANT c_wg_freq_offset : REAL := 0.0/11.0; -- in freq_unit
+ CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ CONSTANT c_subband_sp_1 : REAL := 99.5; -- Select subband at index 99.5 = 99.5/1024 * 200MHz = 19.43359375 MHz
+ CONSTANT c_wg_ampl_lsb : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps
+ CONSTANT c_exp_wg_power_sp : REAL := REAL(c_ampl_sp**2)/2.0 * REAL(c_sdp_N_fft*c_nof_block_per_sync);
+
+ TYPE t_real_arr IS ARRAY (INTEGER RANGE <>) OF REAL;
+ TyPE t_slv_64_subbands_arr IS ARRAY (INTEGER RANGE <>) OF t_slv_64_arr(0 TO c_sdp_S_sub_bf);
+
+ -- MM
+ CONSTANT c_mm_file_reg_ppsh : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
+ CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
+ CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
+ CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
+ CONSTANT c_mm_file_reg_dp_xonoff : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DP_XONOFF";
+
+ -- Tb
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL sim_done : STD_LOGIC := '0';
+ SIGNAL tb_clk : STD_LOGIC := '0';
+ SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
+
+ -- WG
+ SIGNAL dbg_c_exp_wg_power_sp : REAL := c_exp_wg_power_sp;
+ SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+
+ -- 10GbE
+ CONSTANT c_exp_beamlet_index : NATURAL := NATURAL(c_subband_sp_0) * c_sdp_N_pol;
+ CONSTANT c_exp_beamlet_index_os : NATURAL := c_sdp_N_pol_bf * c_sdp_cep_nof_beamlets_per_block + NATURAL(ROUND(c_subband_sp_1)) * c_sdp_N_pol;
+ CONSTANT c_exp_beamlet_re : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"7F"; --Derived from simulation
+ CONSTANT c_exp_beamlet_im : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"81"; --Derived from simulation
+
+ SIGNAL dbg_beamlet_index_offset : NATURAL := 0;
+
+ SIGNAL beamlet_arr2_re : t_slv_8_arr(c_sdp_R_os * c_sdp_N_pol_bf * c_sdp_cep_nof_beamlets_per_block-1 DOWNTO 0);
+ SIGNAL beamlet_arr2_im : t_slv_8_arr(c_sdp_R_os * c_sdp_N_pol_bf * c_sdp_cep_nof_beamlets_per_block-1 DOWNTO 0);
+
+ SIGNAL tr_10GbE_src_out : t_dp_sosi;
+ SIGNAL tr_ref_clk_312 : STD_LOGIC := '0';
+ SIGNAL tr_ref_clk_156 : STD_LOGIC := '0';
+ SIGNAL tr_ref_rst_156 : STD_LOGIC := '0';
+
+ -- DUT
+ SIGNAL ext_clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL ext_pps : STD_LOGIC := '0';
+ SIGNAL pps_rst : STD_LOGIC := '1';
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+ SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+
+ SIGNAL sens_scl : STD_LOGIC;
+ SIGNAL sens_sda : STD_LOGIC;
+ SIGNAL pmbus_scl : STD_LOGIC;
+ SIGNAL pmbus_sda : STD_LOGIC;
+
+ SIGNAL SA_CLK : STD_LOGIC := '1';
+ SIGNAL si_lpbk_0 : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- System setup
+ ----------------------------------------------------------------------------
+ ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ SA_CLK <= NOT SA_CLK AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz)
+ pps_rst <= '0' AFTER c_ext_clk_period*2;
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ sens_scl <= 'H'; -- pull up
+ sens_sda <= 'H'; -- pull up
+ pmbus_scl <= 'H'; -- pull up
+ pmbus_sda <= 'H'; -- pull up
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(5, c_pps_period, '1', pps_rst, ext_clk, pps);
+ ext_pps <= pps;
+
+ ------------------------------------------------------------------------------
+ -- DUT
+ ------------------------------------------------------------------------------
+ u_disturb2_unb2b_sdp_station_full_wg : ENTITY work.disturb2_unb2b_sdp_station_full_wg
+ GENERIC MAP (
+ g_design_name => "disturb2_unb2b_sdp_station_full_wg",
+ g_design_note => "SIM Disturb2 SDP station full design WG",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_wpfb_complex => c_wpfb_complex_sim
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers
+ QSFP_1_RX => si_lpbk_0,
+ QSFP_1_TX => si_lpbk_0,
+
+ -- LEDs
+ QSFP_LED => open
+ );
+
+ u_unb2_board_clk644_pll : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
+ PORT MAP (
+ refclk_644 => SA_CLK,
+ rst_in => pps_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => OPEN
+ );
+
+ u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE
+ GENERIC MAP (
+ g_sim => TRUE,
+ g_sim_level => 1,
+ g_nof_macs => 1,
+ g_use_mdio => FALSE
+ )
+ PORT MAP (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+
+ -- MM interface
+ mm_rst => pps_rst,
+ mm_clk => tb_clk,
+
+ -- DP interface
+ dp_rst => pps_rst,
+ dp_clk => ext_clk,
+
+ serial_rx_arr(0) => si_lpbk_0(0),
+
+ src_out_arr(0) => tr_10GbE_src_out
+ );
+
+ ------------------------------------------------------------------------------
+ -- MM slave accesses via file IO
+ ------------------------------------------------------------------------------
+ tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock
+
+ p_mm_stimuli : PROCESS
+ VARIABLE v_bsn : NATURAL;
+ VARIABLE v_beamlet_index_offset : NATURAL;
+ BEGIN
+ -- Wait for DUT power up after reset
+ WAIT FOR 1 us;
+
+ proc_common_wait_until_hi_lo(ext_clk, ext_pps);
+
+ ----------------------------------------------------------------------------
+ -- Enable UDP offload (dp_xonoff) of beamset 0
+ ----------------------------------------------------------------------------
+ mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff,0 , 1, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff,2 , 1, tb_clk);
+
+ ----------------------------------------------------------------------------
+ -- Enable BS
+ ----------------------------------------------------------------------------
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 1, tb_clk); -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+
+ ----------------------------------------------------------------------------
+ -- Enable WG
+ ----------------------------------------------------------------------------
+ -- 0 : mode[7:0] --> off=0, calc=1, repeat=2, single=3)
+ -- nof_samples[31:16] --> <= c_ram_wg_size=1024
+ -- 1 : phase[15:0]
+ -- 2 : freq[30:0]
+ -- 3 : ampl[16:0]
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024*2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, INTEGER( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, INTEGER((c_subband_sp_0+c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk); -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, INTEGER(REAL(c_ampl_sp) * c_wg_ampl_lsb), tb_clk); -- ampl
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 8, 1024*2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 9, INTEGER( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 10, INTEGER((c_subband_sp_1+c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk); -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 11, INTEGER(REAL(c_ampl_sp) * c_wg_ampl_lsb), tb_clk); -- ampl
+
+ -- Read current BSN
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO 0), tb_clk);
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 1, current_bsn_wg(63 DOWNTO 32), tb_clk);
+ proc_common_wait_some_cycles(tb_clk, 1);
+
+ -- Write scheduler BSN to trigger start of WG at next block
+ v_bsn := TO_UINT(current_bsn_wg) + 2;
+ ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR;
+ v_bsn := c_bsn_start_wg;
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+
+ -- Wait for enough WG data and start of sync interval
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync*2, -- this is the wait until condition
+ c_sdp_T_sub, tb_clk);
+
+ ---------------------------------------------------------------------------
+ -- Read 10GbE Stream
+ ---------------------------------------------------------------------------
+ FOR BS IN 0 TO 2 LOOP -- Read 3 blocks to make sure we get 1 from each beamset. It can happen that two blocks (but not three) from the same beamset are received back to back.
+ proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.sop);
+ FOR I IN 0 TO 8 LOOP -- Packet header is 9.25 words wide, which can be discarded
+ IF I = 7 THEN
+ v_beamlet_index_offset := c_sdp_N_pol_bf * TO_UINT(tr_10GbE_src_out.data(39 DOWNTO 24)); -- Read beamlet index
+ dbg_beamlet_index_offset <= v_beamlet_index_offset;
+ END IF;
+ proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.valid);
+ proc_common_wait_some_cycles(ext_clk, 1);
+ END LOOP;
+
+ -- First word contains 3 beamlets + 1 header part
+ beamlet_arr2_re(v_beamlet_index_offset + 0) <= tr_10GbE_src_out.data(7 DOWNTO 0);
+ beamlet_arr2_im(v_beamlet_index_offset + 0) <= tr_10GbE_src_out.data(15 DOWNTO 8);
+ beamlet_arr2_re(v_beamlet_index_offset + 1) <= tr_10GbE_src_out.data(23 DOWNTO 16);
+ beamlet_arr2_im(v_beamlet_index_offset + 1) <= tr_10GbE_src_out.data(31 DOWNTO 24);
+ beamlet_arr2_re(v_beamlet_index_offset + 2) <= tr_10GbE_src_out.data(39 DOWNTO 32);
+ beamlet_arr2_im(v_beamlet_index_offset + 2) <= tr_10GbE_src_out.data(47 DOWNTO 40);
+ proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.valid);
+ proc_common_wait_some_cycles(ext_clk, 1);
+ FOR I IN 1 TO (c_sdp_N_pol_bf * c_sdp_cep_nof_beamlets_per_block/4)-1 LOOP
+ beamlet_arr2_re(v_beamlet_index_offset + I*4 -1) <= tr_10GbE_src_out.data(7 DOWNTO 0);
+ beamlet_arr2_im(v_beamlet_index_offset + I*4 -1) <= tr_10GbE_src_out.data(15 DOWNTO 8);
+ beamlet_arr2_re(v_beamlet_index_offset + I*4 +0) <= tr_10GbE_src_out.data(23 DOWNTO 16);
+ beamlet_arr2_im(v_beamlet_index_offset + I*4 +0) <= tr_10GbE_src_out.data(31 DOWNTO 24);
+ beamlet_arr2_re(v_beamlet_index_offset + I*4 +1) <= tr_10GbE_src_out.data(39 DOWNTO 32);
+ beamlet_arr2_im(v_beamlet_index_offset + I*4 +1) <= tr_10GbE_src_out.data(47 DOWNTO 40);
+ beamlet_arr2_re(v_beamlet_index_offset + I*4 +2) <= tr_10GbE_src_out.data(55 DOWNTO 48);
+ beamlet_arr2_im(v_beamlet_index_offset + I*4 +2) <= tr_10GbE_src_out.data(63 DOWNTO 56);
+ proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.valid);
+ proc_common_wait_some_cycles(ext_clk, 1);
+ END LOOP;
+
+ beamlet_arr2_re(v_beamlet_index_offset + c_sdp_N_pol_bf * c_sdp_cep_nof_beamlets_per_block-1) <= tr_10GbE_src_out.data(55 DOWNTO 48);
+ beamlet_arr2_im(v_beamlet_index_offset + c_sdp_N_pol_bf * c_sdp_cep_nof_beamlets_per_block-1) <= tr_10GbE_src_out.data(63 DOWNTO 56);
+ END LOOP;
+
+ ---------------------------------------------------------------------------
+ -- Verify 10GbE UDP offload
+ ---------------------------------------------------------------------------
+ ASSERT beamlet_arr2_re(c_exp_beamlet_index) = c_exp_beamlet_re REPORT "Wrong 10GbE output (re) on beamset 0" SEVERITY ERROR;
+ ASSERT beamlet_arr2_im(c_exp_beamlet_index) = c_exp_beamlet_im REPORT "Wrong 10GbE output (im) on beamset 0" SEVERITY ERROR;
+ ASSERT beamlet_arr2_re(c_exp_beamlet_index_os) = c_exp_beamlet_re REPORT "Wrong 10GbE output (re) on beamset 1 (shifted subbands)" SEVERITY ERROR;
+ ASSERT beamlet_arr2_im(c_exp_beamlet_index_os) = c_exp_beamlet_im REPORT "Wrong 10GbE output (im) on beamset 1 (shifted subbands)" SEVERITY ERROR;
+
+ ---------------------------------------------------------------------------
+ -- End Simulation
+ ---------------------------------------------------------------------------
+ sim_done <= '1';
+ proc_common_wait_some_cycles(ext_clk, 100);
+ proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+ WAIT;
+ END PROCESS;
+END tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index aebdb44fbc63e59491da5ef90addfce1354ed21d..3bbe9c203ef9726a41b99ea2576ebdebda0813be 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -56,6 +56,7 @@ ENTITY lofar2_unb2b_sdp_station IS
g_factory_image : BOOLEAN := FALSE;
g_protect_addr_range : BOOLEAN := FALSE;
g_wpfb : t_wpfb := c_sdp_wpfb_subbands;
+ g_wpfb_complex : t_wpfb := c_sdp_wpfb_complex_subbands;
g_bsn_nof_clk_per_sync : NATURAL := c_sdp_N_clk_per_sync; -- Default 200M, overide for short simulation
g_scope_selected_subband : NATURAL := 0
);
@@ -807,6 +808,7 @@ BEGIN
GENERIC MAP (
g_sim => g_sim,
g_wpfb => g_wpfb,
+ g_wpfb_complex => g_wpfb_complex,
g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
g_scope_selected_subband => g_scope_selected_subband,
g_no_jesd => c_revision_select.no_jesd,
diff --git a/doc/erko_howto_tools.txt b/doc/erko_howto_tools.txt
index b60d6352af82b88beb876c037f76562c963af792..de19be64d8555d84e375bd4030e9ba2f37b827ba 100755
--- a/doc/erko_howto_tools.txt
+++ b/doc/erko_howto_tools.txt
@@ -18,9 +18,11 @@
* Screen to run a terminal session without ssh connection
* Quartus Qsys IP files in GIT
* Quartus version
+* Quartus issues
* Linux
* ICT diensten
* Python
+* Numpy, matplotlib.pyplot
* Jupyter
* Graphana
* Zenodo DOI
@@ -170,10 +172,21 @@ run_rbf unb2b lofar2_unb2b_sdp_station_full_wg
*******************************************************************************
* scp from regtest
*******************************************************************************
+mkdir hdl_build_results/20230108
+scp -rp regtest@dop349:/home/regtest/quartus_build_images_cron.log hdl_build_results/20230108/
+scp -rp regtest@dop349:/home/regtest/git/hdl/build/unb2c/quartus/lofar2_unb2c_sdp_station_full hdl_build_results/20230108/
+scp -rp regtest@dop349:/home/regtest/git/hdl/build/unb2b/quartus/lofar2_unb2b_sdp_station_full_wg hdl_build_results/20230108/
+scp -rp regtest@dop349:/home/regtest/git/hdl/build/unb2c/quartus/disturb2_unb2b_sdp_station_full hdl_build_results/20230108/
+scp -rp regtest@dop349:/home/regtest/git/hdl/build/unb2c/quartus/disturb2_unb2b_sdp_station_full_wg hdl_build_results/20230108/
-scp -rp regtest@dop349:/home/regtest/quartus_build_images_cron.log 20221218/
-scp -rp regtest@dop349:/home/regtest/git/hdl/build/unb2c/quartus/lofar2_unb2c_sdp_station_full 20221218/
+scp -rp kooistra@dop436:/home/kooistra/git/hdl/build/unb2b/quartus/lofar2_unb2b_sdp_station_full_wg ~/hdl_build_result
+du -h -d 2
+df -h /home
+
+Synthesis neemt onegeveer 4GB voor Disturb image en 3GB voor SDP image, dus
+ongeveer 14GB / weekend. De regtest machine heeft nog 500GB vrij, dus we
+kunnen nog ongeveer 35x opslaan, voordat we moeten deleten.
*******************************************************************************
* Flash and reboot unb2
@@ -943,6 +956,62 @@ Quartus version meeting minutes 13 may 2020 (RW, LH JH, EK):
3) UniBoard2c IP was created using Q19.4 by Jonathan, but we need to reconsider going to the latest Quartus version and recreate the IP, when we continue with the pinning and test designs for UniBoard2c
+*******************************************************************************
+* Quartus issues
+*******************************************************************************
+
+1) run_quartus unb2b fails to start:
+
+quartus: /home/software/Altera/18.0/quartus/linux64/liblzma.so.5:
+no version information available (required by /lib/x86_64-linux-gnu/libsystemd.so.0)
+
+# Installing libpng12 did not help to fix this (because this libsystemd is only a warning):
+> sudo add-apt-repository ppa:linuxuprising/libpng12
+> sudo apt update
+> sudo apt install libpng12-0
+
+# Changing video driver via system settings did not help
+
+Linux video driver teruggezet naar xserver-xorg-video-nouveau (19 jan 2022)
+nvidia-driver-470
+Version 470.161.03-Oubuntu0.20.04.1
+NVIDEA driver metapackage
+
+change to
+
+xserver-xorg-video-nouveau (0pen source)
+Version 1:1.0.16-1
+X.Org X server - Nouveau display driver
+
+geeft:
+
+pk-client-error-quark: E: dpkg was interrupted, you must manually run 'dpkg --configure -a' to correct the problem. (281)
+
+na sudo dpkg --configure -a die de 470 uninstallde kon ik de driver terug zetten
+en werkte shutdown weer als shutdown ipv als suspend.
+
+# sudo ln -s /usr/lib/x86_64-linux-gnu/dri ./dri haalt een error weg, maar dan deze error:
+ libGL error: MESA-LOADER: failed to open iris: /home/software/Altera/18.0/quartus/linux64/libstdc++.so.6: version `GLIBCXX_3.4.22' not found (required by /usr/lib/x86_64-linux-gnu/libLLVM-12.so.1) (search paths /usr/lib/x86_64-linux-gnu/dri:\$${ORIGIN}/dri:/usr/lib/dri, suffix _dri)
+ libGL error: failed to load driver: iris
+ libGL error: MESA-LOADER: failed to open iris: /home/software/Altera/18.0/quartus/linux64/libstdc++.so.6: version `GLIBCXX_3.4.22' not found (required by /usr/lib/x86_64-linux-gnu/libLLVM-12.so.1) (search paths /usr/lib/x86_64-linux-gnu/dri:\$${ORIGIN}/dri:/usr/lib/dri, suffix _dri)
+ libGL error: failed to load driver: iris
+ libGL error: MESA-LOADER: failed to open swrast: /home/software/Altera/18.0/quartus/linux64/libstdc++.so.6: version `GLIBCXX_3.4.22' not found (required by /usr/lib/x86_64-linux-gnu/libLLVM-12.so.1) (search paths /usr/lib/x86_64-linux-gnu/dri:\$${ORIGIN}/dri:/usr/lib/dri, suffix _dri)
+ libGL error: failed to load driver: swrast
+
+kooistra@dop466:/dop466_0/kooistra/git/hdl$ find /usr -name libstdc++.so.6
+/usr/lib/x86_64-linux-gnu/libstdc++.so.6
+/usr/lib/i386-linux-gnu/libstdc++.so.6
+/usr/local/MATLAB/R2018a/sys/os/glnxa64/libstdc++.so.6
+
+ cd /home/software/Altera/18.0/quartus/linux64/
+ cp -p libstdc++.so.6 libstdc++.so.6.quartus
+ rm libstdc++.so.6
+ ln -s /usr/lib/x86_64-linux-gnu/libstdc++.so.6 libstdc++.so.6
+
+Dit werkt, oplossing komt uit:
+
+https://forum.step.esa.int/t/snap9-error-libegl-warning-mesa-loader-failed-to-open-swrast/36702/2
+
*******************************************************************************
* Linux
*******************************************************************************
@@ -1108,6 +1177,27 @@ numpy tutorial:
https://lwn.net/SubscriberLink/847039/3016fa7278000b77/
+*******************************************************************************
+* Numpy, matplotlib.pyplot
+*******************************************************************************
+
+a = 20
+plt.figure(figsize=(16, 6))
+plt.subplot(1, 2, 1)
+plt.plot(si_ampls[0:a], si_SSTs_dB[0:a])
+plt.title(f"SST as function of input sine amplitude [0:{a}>")
+plt.xlabel("si_ampl, ni_sigma [q]")
+plt.ylabel("SST [dB]")
+plt.grid()
+
+plt.subplot(1, 2, 2)
+plt.plot(si_ampls[a:], si_SSTs_dB[a:])
+plt.title(f"SST as function of input sine amplitude [{a}:{FS}>")
+plt.xlabel("si_ampl, ni_sigma [q]")
+plt.ylabel("SST [dB]")
+plt.grid()
+
+
*******************************************************************************
* Jupyter
*******************************************************************************
diff --git a/libraries/technology/flash/hdllib.cfg b/libraries/technology/flash/hdllib.cfg
index e3bf434a4ce1023b80a340f289c187e187f76432..e6dc1a8b05d98342086c5465e55946c9bea730cd 100644
--- a/libraries/technology/flash/hdllib.cfg
+++ b/libraries/technology/flash/hdllib.cfg
@@ -7,9 +7,9 @@ hdl_lib_uses_synth = technology
ip_arria10_e3sge3_asmi_parallel
ip_arria10_e3sge3_remote_update
ip_arria10_e1sg_asmi_parallel # modelsim crashes when asmi_parallel ip is used(segmentation violation)
- ip_arria10_e1sg_remote_update
- ip_arria10_e2sg_asmi_parallel
- ip_arria10_e2sg_remote_update
+ ip_arria10_e1sg_remote_update # modelsim crashes when asmi_parallel ip is used(segmentation violation)
+ ip_arria10_e2sg_asmi_parallel # modelsim crashes when asmi_parallel ip is used(segmentation violation)
+ ip_arria10_e2sg_remote_update # modelsim crashes when asmi_parallel ip is used(segmentation violation)
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -26,8 +26,8 @@ hdl_lib_disclose_library_clause_names =
synth_files =
tech_flash_component_pkg.vhd
- tech_flash_asmi_parallel.vhd #e1sg component is not instantiated in simulation
- tech_flash_remote_update.vhd
+ tech_flash_asmi_parallel.vhd #e1sg,e2sg component is not instantiated in simulation, only for synthesis
+ tech_flash_remote_update.vhd #e1sg,e2sg component is not instantiated in simulation, only for synthesis
test_bench_files =
diff --git a/libraries/technology/flash/tech_flash_asmi_parallel.vhd b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
index b91e7ee92f51a48fd18ed2595e63346228128711..7a0431e7b19f866832a42eae8f5a8713fbadd4bb 100644
--- a/libraries/technology/flash/tech_flash_asmi_parallel.vhd
+++ b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
@@ -32,7 +32,7 @@ LIBRARY ip_stratixiv_flash_lib;
LIBRARY ip_arria10_asmi_parallel_altera_asmi_parallel_150;
LIBRARY ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151;
--LIBRARY ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_180;
-LIBRARY ip_arria10_e2sg_asmi_parallel_altera_asmi_parallel_1910;
+--LIBRARY ip_arria10_e2sg_asmi_parallel_altera_asmi_parallel_1910;
ENTITY tech_flash_asmi_parallel IS
GENERIC (
diff --git a/libraries/technology/flash/tech_flash_remote_update.vhd b/libraries/technology/flash/tech_flash_remote_update.vhd
index e30a5affdb1aaabf0a90da230e54e3f9efe23928..4d097ce383ff615caf77ee8622b80291cbfc259f 100644
--- a/libraries/technology/flash/tech_flash_remote_update.vhd
+++ b/libraries/technology/flash/tech_flash_remote_update.vhd
@@ -31,8 +31,8 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_stratixiv_flash_lib;
LIBRARY ip_arria10_remote_update_altera_remote_update_150;
LIBRARY ip_arria10_e3sge3_remote_update_altera_remote_update_151;
-LIBRARY ip_arria10_e1sg_remote_update_altera_remote_update_180;
-LIBRARY ip_arria10_e2sg_remote_update_altera_remote_update_1910;
+--LIBRARY ip_arria10_e1sg_remote_update_altera_remote_update_180;
+--LIBRARY ip_arria10_e2sg_remote_update_altera_remote_update_1910;
ENTITY tech_flash_remote_update IS
GENERIC (
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/hdllib.cfg
index b55caa82d66dcb7b7741133b823c55b6ffaa1a7c..e12f81a5e5ffcaf9be45fd6668552b82c4dd0a11 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/hdllib.cfg
@@ -1,4 +1,5 @@
hdl_lib_name = ip_arria10_e2sg_altera_asmi_parallel_1910
+# Note, this library causes modelsim to crash!
hdl_library_clause_name = altera_asmi_parallel_1910
hdl_lib_uses_synth =
hdl_lib_uses_sim =
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl
index 4d9fd39c9c45b99d46a5e0e4fb06c73a7f3c6bc8..675f177c97873d239882fedfddd3daed5281cfd4 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl
@@ -41,9 +41,9 @@ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_d
# ddr4_16g_1600_72b
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_slbjghy_top.sv" -work altera_emif_arch_nf_191
- vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_slbjghy_io_aux.sv" -work altera_emif_arch_nf_191
- vcom "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_slbjghy.vhd" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_mqx4bea_top.sv" -work altera_emif_arch_nf_191
+ vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_mqx4bea_io_aux.sv" -work altera_emif_arch_nf_191
+ vcom "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_mqx4bea.vhd" -work altera_emif_arch_nf_191
# ddr4_8g_1600
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
@@ -161,5 +161,5 @@ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_d
vcom "$IP_DIR/../altera_emif_1910/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_1910_rvperma.vhd" -work altera_emif_1910
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
- vcom "$IP_DIR/../altera_emif_1910/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_1910_3t6zvqq.vhd" -work altera_emif_1910
+ vcom "$IP_DIR/../altera_emif_1910/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_1910_vq72fgq.vhd" -work altera_emif_1910
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/compile_ip.tcl
index 9b124aeee40aa003c243d361ed26215b2b3a0b39..13a78195a945f878b6b502e093c00fd70fc0870c 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-#vlib ./work/ ;# Assume library work already exist
+vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_remote_update/sim"
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/hdllib.cfg
index 83a19e1b246e72236be1eed67d13ec305050deaa..428e6c1871dce197004ef1b1d9344c2a3e948728 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/hdllib.cfg
@@ -1,4 +1,5 @@
hdl_lib_name = ip_arria10_e2sg_altera_remote_update_1910
+# Note, this library causes modelsim to crash!
hdl_library_clause_name = altera_remote_update_1910
hdl_lib_uses_synth =
hdl_lib_uses_sim = ip_arria10_e2sg_altera_remote_update_core_1910
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/compile_ip.tcl
index 41bea969d2a7353840feacfd2ed38f9bcc3d3143..006a7835bfd6063ecc7898382e6bc0d8640a6747 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-#vlib ./work/ ;# Assume library work already exist
+vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_remote_update/sim"
diff --git a/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/compile_ip.tcl
index d14407ec43819d25f028e97d1dd64f2497e1b21e..1ce4968f35431047637732f3bdd3bd62649b5233 100644
--- a/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/compile_ip.tcl
@@ -26,10 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-vlib ./work/ ;# Assume library work already exist
-
+#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_asmi_parallel/sim"
-
-
- vcom "$IP_DIR/ip_arria10_e2sg_asmi_parallel.vhd"
+ vcom "$IP_DIR/ip_arria10_e2sg_asmi_parallel.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/hdllib.cfg
index 474a468c1eb0fc088b5b0ebc0d330c1d91ffa92e..07ae00fb5840b2d978c0b2986dde9ec85f9994c2 100644
--- a/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/hdllib.cfg
@@ -1,9 +1,7 @@
hdl_lib_name = ip_arria10_e2sg_asmi_parallel
hdl_library_clause_name = ip_arria10_e2sg_asmi_parallel_altera_asmi_parallel_1910
hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-# Do not use this simulation library: it causes Modelsim to crash:
-#ip_arria10_e2sg_altera_asmi_parallel_1910
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_asmi_parallel_1910
hdl_lib_technology = ip_arria10_e2sg
synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/flash/remote_update/hdllib.cfg
index d699858547cda662671410e916de6b4c582272b5..662398ca5c0bda555b53a358a5c96aad79ce308d 100644
--- a/libraries/technology/ip_arria10_e2sg/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/flash/remote_update/hdllib.cfg
@@ -1,9 +1,7 @@
hdl_lib_name = ip_arria10_e2sg_remote_update
hdl_library_clause_name = ip_arria10_e2sg_remote_update_altera_remote_update_1910
hdl_lib_uses_synth =
-hdl_lib_uses_sim =
-# Do not use this simulation library: it causes Modelsim to crash:
-#ip_arria10_e2sg_altera_remote_update_1910
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_remote_update_1910
hdl_lib_technology = ip_arria10_e2sg
synth_files =