diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg
index c854fbb25961c387d6ba0ccfda5a233dab1bd38c..b45b48b74132a6b57e3dd8ea406b5e1f1c03d8be 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg
@@ -1,6 +1,6 @@
 hdl_lib_name = lofar2_unb2b_adc
 hdl_library_clause_name = lofar2_unb2b_adc_lib
-hdl_lib_uses_synth = common technology mm unb2b_board dp eth tech_tse tr_10GbE diagnostics diag aduh tech_jesd204b
+hdl_lib_uses_synth = common technology mm unb2b_board dp eth tech_tse tr_10GbE diagnostics diag aduh tech_jesd204b lofar2_sdp
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10_e1sg
 
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
index 63f99093742d281b74f83529b4545d4a3cd580a5..96e3c42900bd80357dc8c4f7ef22ca834fa67a6e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
@@ -26,7 +26,7 @@
 --   Contains all the signal processing blocks to receive and time the ADC input data
 --   See https://support.astron.nl/confluence/display/STAT/L5+SDPFW+DD%3A+ADC+data+input+and+timestamp
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib, lofar2_sdp_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
@@ -37,6 +37,7 @@ USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
 USE diag_lib.diag_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 USE work.lofar2_unb2b_adc_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
 
 ENTITY node_adc_input_and_timing IS
   GENERIC (
@@ -329,7 +330,7 @@ BEGIN
     g_buf_addr_w         => c_wg_buf_addr_w,
     g_calc_support       => TRUE,
     g_calc_gain_w        => 1,
-    g_calc_dat_w         => 14
+    g_calc_dat_w         => c_sdp_W_adc
   )
   PORT MAP (
     -- Memory-mapped clock domain
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
index ff826041cdbbc873b5c4be4567468ac13995bdf6..6b60e21f0ab95664410e5e844ebb2c187d442c36 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
@@ -458,7 +458,7 @@ BEGIN
     -- Read 10GbE Stream
     ---------------------------------------------------------------------------
     proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.sop);
-    FOR I IN 0 TO 8 LOOP -- Packet header
+    FOR I IN 0 TO 8 LOOP -- Packet header is 9.25 words wide, which can be discarded
       proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.valid);
       proc_common_wait_some_cycles(ext_clk, 1);
     END LOOP;