diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
index 46153425b4f8b6a7bad1f83ad2b1a8c4a7e11237..3c1ec3c57f7102adf17207bad48df86644ed92be 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
@@ -95,7 +95,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload IS
   CONSTANT c_eth_crc_size                 : NATURAL := 1; -- word
   CONSTANT c_eth_packet_size              : NATURAL := c_eth_header_size + c_eth_crc_size + (c_sdp_W_statistic / c_word_w) * c_sdp_S_pn * c_sdp_S_pn * c_nof_complex; -- 20 + 2 * 12 * 12 * 2 = 596 
   CONSTANT c_eth_check_nof_valid          : NATURAL := c_eth_check_nof_packets * c_eth_packet_size;  
-  CONSTANT c_eth_runtime_timeout          : TIME := 2 * c_nof_clk_per_sync * c_ext_clk_period;  -- eth statistics should be done at the second sync interval
+  CONSTANT c_eth_runtime_timeout          : TIME := 3 * c_nof_clk_per_sync * c_ext_clk_period;  -- eth statistics should be done at the third sync interval
   
   -- DUT
   SIGNAL ext_clk             : STD_LOGIC := '0';
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd
index 8a84a6fada42be3d8eea93fb4f284e94807a978f..8219a71f3fe2fbf6a0159224c884afb7a95321b9 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd
@@ -95,7 +95,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload IS
   CONSTANT c_eth_crc_size                 : NATURAL := 1; -- word
   CONSTANT c_eth_packet_size              : NATURAL := c_eth_header_size + c_eth_crc_size + (c_sdp_W_statistic / c_word_w) * c_sdp_S_pn * c_sdp_S_pn * c_nof_complex; -- 20 + 2 * 12 * 12 * 2 = 596 
   CONSTANT c_eth_check_nof_valid          : NATURAL := c_eth_check_nof_packets * c_eth_packet_size;  
-  CONSTANT c_eth_runtime_timeout          : TIME := 2 * c_nof_clk_per_sync * c_ext_clk_period;  -- eth statistics should be done at the second sync interval
+  CONSTANT c_eth_runtime_timeout          : TIME := 3 * c_nof_clk_per_sync * c_ext_clk_period;  -- eth statistics should be done at the third sync interval
   
   -- DUT
   SIGNAL ext_clk             : STD_LOGIC := '0';
diff --git a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
index 0b5a6f61f4899f666adf4930ca8728f089805daa..9985eb19c958972147fd60cfb547f6560d7d6e81 100644
--- a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
@@ -209,11 +209,25 @@ BEGIN
     proc_common_wait_until_low(dp_clk, dp_rst);
     proc_common_wait_some_cycles(mm_clk, 5);
 
-    -- Read stream enable bits, default '0' after power up
+    -- Read stream enable bits, default '1' after power up
     FOR I IN 0 TO c_nof_streams-1 LOOP
       proc_mem_mm_bus_rd(I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi);
       proc_mem_mm_bus_rd_latency(1, mm_clk);
-      ASSERT reg_bsn_align_cipo.rddata(0) = '0' REPORT "Wrong stream disable for output " & int_to_str(I) SEVERITY ERROR;
+      ASSERT reg_bsn_align_cipo.rddata(0) = '1' REPORT "Wrong stream disable for output " & int_to_str(I) SEVERITY ERROR;
+    END LOOP;
+
+    -- Write stream enable bits for stream_en_arr
+    FOR I IN 0 TO c_nof_streams-1 LOOP
+      proc_mem_mm_bus_wr(I, 0,  mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi);
+    END LOOP;
+    proc_common_wait_some_cycles(mm_clk, c_cross_clock_domain_latency);
+    proc_common_wait_some_cycles(dp_clk, c_cross_clock_domain_latency);
+
+    -- Read stream enable bits, should now be '0'
+    FOR I IN 0 TO c_nof_streams-1 LOOP
+      proc_mem_mm_bus_rd(I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi);
+      proc_mem_mm_bus_rd_latency(1, mm_clk);
+      ASSERT reg_bsn_align_cipo.rddata(0) = '0' REPORT "Wrong BSN align stream enable for output " & int_to_str(I) SEVERITY ERROR;
     END LOOP;
 
     -- Write stream enable bits for stream_en_arr