From 2c5af00b33c9990d4523304bed52af6a77088991 Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Mon, 16 Mar 2020 13:59:02 +0100
Subject: [PATCH] Used SISO/SOSI instead of kernel signals. Also made nof IPs
configurable with constants in top.vhd
---
.../ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd | 424 +++++++++---------
.../ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc.vhd | 36 +-
.../ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd | 34 +-
.../ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd | 171 ++++---
.../ta2_unb2b_bsp/hardware/unb2b/top.vhd | 254 ++++++-----
5 files changed, 451 insertions(+), 468 deletions(-)
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
index 34f7db0034..27f608901b 100644
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
@@ -57,28 +57,27 @@ USE technology_lib.technology_pkg.ALL;
USE common_lib.common_interface_layers_pkg.ALL;
USE tech_mac_10g_lib.tech_mac_10g_component_pkg.ALL;
-ENTITY ta2_unb2b_10GbE IS
+ENTITY ta2_unb2b_10GbE IS
+ GENERIC (
+ g_nof_mac : NATURAL
+ );
PORT (
- --config_clk : IN STD_LOGIC; -- 100MHz clk for reconfig block and status interface
- config_reset : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC; -- 100MHz clk for reconfig block and status interface
+ mm_rst : IN STD_LOGIC;
- clk_ref_r : IN STD_LOGIC; -- 644.53125MHz 10G MAC reference clock
+ clk_ref_r : IN STD_LOGIC; -- 644.53125MHz 10G MAC reference clock
- tx_serial_r : OUT STD_LOGIC; -- Serial TX lanes towards QSFP cage
- rx_serial_r : IN STD_LOGIC; -- Serial RX lanes from QSFP cage
+ tx_serial_r : OUT STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0); -- Serial TX lanes towards QSFP cage
+ rx_serial_r : IN STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0); -- Serial RX lanes from QSFP cage
- kernel_clk : IN STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
- kernel_reset : IN STD_LOGIC;
+ kernel_clk : IN STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
+ kernel_reset : IN STD_LOGIC;
- kernel_src_data : OUT STD_LOGIC_VECTOR(71 DOWNTO 0); -- RX Data to kernel
- kernel_src_valid : OUT STD_LOGIC; -- RX data valid signal to kernel
- kernel_src_ready : IN STD_LOGIC; -- Flow control from kernel
+ src_out_arr : OUT t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ src_in_arr : IN t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
+ snk_out_arr : OUT t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
+ snk_in_arr : IN t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0)
- kernel_snk_data : IN STD_LOGIC_VECTOR(71 DOWNTO 0); -- TX Data from kernel
- kernel_snk_valid : IN STD_LOGIC; -- TX data valid signal from kernel
- kernel_snk_ready : OUT STD_LOGIC; -- Flow control towards kernel
-
- rx_status : OUT STD_LOGIC -- RX status
);
END ta2_unb2b_10GbE;
@@ -87,8 +86,6 @@ ARCHITECTURE str OF ta2_unb2b_10GbE IS
CONSTANT c_sim : BOOLEAN := FALSE;
- CONSTANT c_nof_streams_qsfp : NATURAL := 1;
-
CONSTANT c_tx_fifo_fill : NATURAL := 1125; -- Largest frame is 9000 bytes = 1125
CONSTANT c_tx_fifo_size : NATURAL := 2048;
CONSTANT c_rx_fifo_size : NATURAL := 256; -- should be large enough
@@ -97,39 +94,36 @@ ARCHITECTURE str OF ta2_unb2b_10GbE IS
SIGNAL tr_ref_clk_156 : STD_LOGIC;
SIGNAL tr_ref_rst_156 : STD_LOGIC;
- SIGNAL unb2_board_front_io_serial_tx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL unb2_board_front_io_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0);
-
SIGNAL eth_ref_clk_644 : STD_LOGIC;
SIGNAL eth_ref_clk_312 : STD_LOGIC;
SIGNAL eth_ref_clk_156 : STD_LOGIC;
SIGNAL eth_ref_rst_156 : STD_LOGIC;
- SIGNAL eth_tx_clk_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0);
- SIGNAL eth_tx_rst_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0);
- SIGNAL eth_rx_clk_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0);
- SIGNAL eth_rx_rst_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0);
+ SIGNAL eth_tx_clk_arr : STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0);
+ SIGNAL eth_tx_rst_arr : STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0);
+ SIGNAL eth_rx_clk_arr : STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0);
+ SIGNAL eth_rx_rst_arr : STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0);
- SIGNAL dp_latency_adapter_tx_src_out : t_dp_sosi;
- SIGNAL dp_latency_adapter_tx_src_in : t_dp_siso;
+ SIGNAL dp_latency_adapter_tx_src_out_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL dp_latency_adapter_tx_src_in_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL dp_latency_adapter_tx_snk_in_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL dp_latency_adapter_tx_snk_out_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
- SIGNAL dp_latency_adapter_tx_snk_in : t_dp_sosi;
- SIGNAL dp_latency_adapter_tx_snk_out : t_dp_siso;
+ SIGNAL dp_fifo_fill_tx_src_out_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL dp_fifo_fill_tx_src_in_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
- SIGNAL dp_fifo_fill_tx_src_out_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0);
- SIGNAL dp_fifo_fill_tx_src_in_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0);
+ SIGNAL mac_10g_src_out_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL mac_10g_src_in_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
- SIGNAL mac_10g_src_out_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0);
- SIGNAL mac_10g_src_in_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0);
+ SIGNAL dp_fifo_dc_rx_src_out_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL dp_fifo_dc_rx_src_in_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
- SIGNAL dp_fifo_dc_rx_src_out : t_dp_sosi;
- SIGNAL dp_fifo_dc_rx_src_in : t_dp_siso;
+ SIGNAL dp_latency_adapter_rx_src_out_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL dp_latency_adapter_rx_src_in_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
- SIGNAL dp_latency_adapter_rx_src_out : t_dp_sosi;
- SIGNAL dp_latency_adapter_rx_src_in : t_dp_siso;
+ SIGNAL dp_xonoff_src_out_arr : t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ SIGNAL dp_xonoff_src_in_arr : t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
- SIGNAL dp_xonoff_src_out : t_dp_sosi;
- SIGNAL dp_xonoff_src_in : t_dp_siso;
BEGIN
--------
@@ -141,23 +135,21 @@ BEGIN
)
PORT MAP (
refclk_644 => clk_ref_r,
- rst_in => config_reset,
+ rst_in => mm_rst,
clk_156 => tr_ref_clk_156,
clk_312 => tr_ref_clk_312,
rst_156 => tr_ref_rst_156,
rst_312 => OPEN
);
-
---------------------------------------------------------------------------------------
-- Clocks and reset
---------------------------------------------------------------------------------------
-
-- Apply the clocks from top level down such that they have their rising_edge() aligned without any delta-delay
u_tech_eth_10g_clocks : ENTITY tech_eth_10g_lib.tech_eth_10g_clocks
GENERIC MAP (
g_technology => c_tech_arria10_e1sg,
- g_nof_channels => c_nof_streams_qsfp
+ g_nof_channels => g_nof_mac
)
PORT MAP (
-- Input clocks
@@ -183,196 +175,180 @@ BEGIN
eth_rx_rst_arr => eth_rx_rst_arr
);
-
- ----------------------------------------------------------------------------
- -- Data mapping
- ----------------------------------------------------------------------------
- -- Reverse byte order
- gen_tx_bytes: FOR I IN 0 TO 7 GENERATE
- dp_latency_adapter_tx_snk_in.data(8*(8-I) -1 DOWNTO 8*(7-I)) <= kernel_snk_data(8*(I+1) -1 DOWNTO 8*I);
- END GENERATE;
-
- -- Assign correct data fields to control signals.
- dp_latency_adapter_tx_snk_in.sop <= kernel_snk_data(64);
- dp_latency_adapter_tx_snk_in.eop <= kernel_snk_data(65);
- dp_latency_adapter_tx_snk_in.empty(2 DOWNTO 0) <= kernel_snk_data(71 DOWNTO 69);
-
- dp_latency_adapter_tx_snk_in.valid <= kernel_snk_valid;
- kernel_snk_ready <= dp_latency_adapter_tx_snk_out.ready; -- Flow control towards source (kernel)
-
- rx_status <= dp_xonoff_src_in.xon; -- use xonoff_src_in for status as xonoff_snk_out is always '1'
-
- tx_serial_r <= unb2_board_front_io_serial_tx_arr(0);
- unb2_board_front_io_serial_rx_arr(0) <= rx_serial_r;
-
- ----------------------------------------------------------------------------
- -- Latency adapter: adapt RL=0 (OpenCL kernel) to RL=1 (Downstream).
- ----------------------------------------------------------------------------
- u_dp_latency_adapter_tx : ENTITY dp_lib.dp_latency_adapter
- GENERIC MAP (
- g_in_latency => 0,
- g_out_latency => 1
- )
- PORT MAP (
- clk => kernel_clk,
- rst => kernel_reset,
-
- snk_in => dp_latency_adapter_tx_snk_in,
- snk_out => dp_latency_adapter_tx_snk_out,
-
- src_out => dp_latency_adapter_tx_src_out,
- src_in => dp_latency_adapter_tx_src_in
- );
+ gen_mac: FOR mac IN 0 TO g_nof_mac-1 GENERATE
+ ----------------------------------------------------------------------------
+ -- Data mapping
+ ----------------------------------------------------------------------------
+ -- Reverse byte order
+ gen_tx_bytes: FOR I IN 0 TO 7 GENERATE
+ dp_latency_adapter_tx_snk_in_arr(mac).data(8*(8-I) -1 DOWNTO 8*(7-I)) <= snk_in_arr(mac).data(8*(I+1) -1 DOWNTO 8*I);
+ END GENERATE;
+ -- Assign correct data fields to control signals.
+ dp_latency_adapter_tx_snk_in_arr(mac).sop <= snk_in_arr(mac).data(64);
+ dp_latency_adapter_tx_snk_in_arr(mac).eop <= snk_in_arr(mac).data(65);
+ dp_latency_adapter_tx_snk_in_arr(mac).empty(2 DOWNTO 0) <= snk_in_arr(mac).data(71 DOWNTO 69);
+ dp_latency_adapter_tx_snk_in_arr(mac).valid <= snk_in_arr(mac).valid;
+ snk_out_arr(mac).ready <= dp_latency_adapter_tx_snk_out_arr(mac).ready; -- Flow control towards source (kernel)
+ snk_out_arr(mac).xon <= dp_xonoff_src_in_arr(mac).xon; -- use xonoff_src_in for status as xonoff_snk_out is always '1'
+
+ ----------------------------------------------------------------------------
+ -- Latency adapter: adapt RL=0 (OpenCL kernel) to RL=1 (Downstream).
+ ----------------------------------------------------------------------------
+ u_dp_latency_adapter_tx : ENTITY dp_lib.dp_latency_adapter
+ GENERIC MAP (
+ g_in_latency => 0,
+ g_out_latency => 1
+ )
+ PORT MAP (
+ clk => kernel_clk,
+ rst => kernel_reset,
+
+ snk_in => dp_latency_adapter_tx_snk_in_arr(mac),
+ snk_out => dp_latency_adapter_tx_snk_out_arr(mac),
+
+ src_out => dp_latency_adapter_tx_src_out_arr(mac),
+ src_in => dp_latency_adapter_tx_src_in_arr(mac)
+ );
- -----------------------------------------------------------------------------
- -- RX XON frame control
- -----------------------------------------------------------------------------
-
- u_dp_xonoff : ENTITY dp_lib.dp_xonoff
- PORT MAP (
- rst => kernel_reset,
- clk => kernel_clk,
-
- in_siso => dp_latency_adapter_tx_src_in,
- in_sosi => dp_latency_adapter_tx_src_out,
-
- out_siso => dp_xonoff_src_in,
- out_sosi => dp_xonoff_src_out
- );
-
-
- ---------------------------------------------------------------------------------------
- -- FIFO FILL with fill level/eop trigger so we can deliver packets to the MAC fast enough
- ---------------------------------------------------------------------------------------
-
- u_dp_fifo_fill_tx_eop : ENTITY dp_lib.dp_fifo_fill_eop
- GENERIC MAP (
- g_technology => c_tech_arria10_e1sg,
- g_use_dual_clock => TRUE,
- g_data_w => c_xgmii_data_w,
- g_empty_w => c_tech_mac_10g_empty_w,
- g_use_empty => TRUE,
- g_fifo_fill => c_tx_fifo_fill,
- g_fifo_size => c_tx_fifo_size
- )
- PORT MAP (
- wr_rst => kernel_reset,
- wr_clk => kernel_clk,
- rd_rst => eth_tx_rst_arr(0),
- rd_clk => eth_tx_clk_arr(0),
-
- snk_out => dp_xonoff_src_in,
- snk_in => dp_xonoff_src_out,
-
- src_in => dp_fifo_fill_tx_src_in_arr(0),
- src_out => dp_fifo_fill_tx_src_out_arr(0)
- );
-
-
- ---------------------------------------------------------------------------------------
- -- ETH MAC + PHY
- ---------------------------------------------------------------------------------------
-
- u_tech_eth_10g : ENTITY tech_eth_10g_lib.tech_eth_10g
- GENERIC MAP (
- g_technology => c_tech_arria10_e1sg,
- g_sim => c_sim,
- g_sim_level => 1, -- 0 = use IP; 1 = use fast serdes model
- g_nof_channels => c_nof_streams_qsfp,
- g_direction => "TX_RX",
- g_pre_header_padding => FALSE
- )
- PORT MAP (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => eth_ref_clk_644, -- 644.531250 MHz for 10GBASE-R
- tr_ref_clk_312 => eth_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => eth_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => eth_ref_rst_156, -- for 10GBASE-R or for XAUI
+
+ -----------------------------------------------------------------------------
+ -- RX XON frame control
+ -----------------------------------------------------------------------------
+ u_dp_xonoff : ENTITY dp_lib.dp_xonoff
+ PORT MAP (
+ rst => kernel_reset,
+ clk => kernel_clk,
+
+ in_siso => dp_latency_adapter_tx_src_in_arr(mac),
+ in_sosi => dp_latency_adapter_tx_src_out_arr(mac),
+
+ out_siso => dp_xonoff_src_in_arr(mac),
+ out_sosi => dp_xonoff_src_out_arr(mac)
+ );
+
+ ---------------------------------------------------------------------------------------
+ -- FIFO FILL with fill level/eop trigger so we can deliver packets to the MAC fast enough
+ ---------------------------------------------------------------------------------------
+ u_dp_fifo_fill_tx_eop : ENTITY dp_lib.dp_fifo_fill_eop
+ GENERIC MAP (
+ g_technology => c_tech_arria10_e1sg,
+ g_use_dual_clock => TRUE,
+ g_data_w => c_xgmii_data_w,
+ g_empty_w => c_tech_mac_10g_empty_w,
+ g_use_empty => TRUE,
+ g_fifo_fill => c_tx_fifo_fill,
+ g_fifo_size => c_tx_fifo_size
+ )
+ PORT MAP (
+ wr_rst => kernel_reset,
+ wr_clk => kernel_clk,
+ rd_rst => eth_tx_rst_arr(mac),
+ rd_clk => eth_tx_clk_arr(mac),
+
+ snk_out => dp_xonoff_src_in_arr(mac),
+ snk_in => dp_xonoff_src_out_arr(mac),
+
+ src_in => dp_fifo_fill_tx_src_in_arr(mac),
+ src_out => dp_fifo_fill_tx_src_out_arr(mac)
+ );
+
+
+ ---------------------------------------------------------------------------------------
+ -- ETH MAC + PHY, use g_nof_mac duplicates of eth_10g with g_nof_channels = 1 to be most flexible
+ ---------------------------------------------------------------------------------------
+ u_tech_eth_10g : ENTITY tech_eth_10g_lib.tech_eth_10g
+ GENERIC MAP (
+ g_technology => c_tech_arria10_e1sg,
+ g_sim => c_sim,
+ g_sim_level => 1, -- 0 = use IP; 1 = use fast serdes model
+ g_nof_channels => 1,
+ g_direction => "TX_RX",
+ g_pre_header_padding => FALSE
+ )
+ PORT MAP (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => eth_ref_clk_644, -- 644.531250 MHz for 10GBASE-R
+ tr_ref_clk_312 => eth_ref_clk_312, -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_156 => eth_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => eth_ref_rst_156, -- for 10GBASE-R or for XAUI
+
+ -- MM
+ mm_clk => '0',
+ mm_rst => '0',
- -- MM
- mm_clk => '0',
- mm_rst => '0',
+ -- ST
+ tx_snk_in_arr => dp_fifo_fill_tx_src_out_arr(mac DOWNTO mac), -- 64 bit data @ 156 MHz
+ tx_snk_out_arr => dp_fifo_fill_tx_src_in_arr(mac DOWNTO mac),
+
+ rx_src_out_arr => mac_10g_src_out_arr(mac DOWNTO mac), -- 64 bit data @ 156 MHz
+ rx_src_in_arr => mac_10g_src_in_arr(mac DOWNTO mac),
+
+ -- PHY serial IO
+ -- . 10GBASE-R (single lane)
+ serial_tx_arr => tx_serial_r(mac DOWNTO mac),
+ serial_rx_arr => rx_serial_r(mac DOWNTO mac)
+ );
- -- ST
- tx_snk_in_arr => dp_fifo_fill_tx_src_out_arr, -- 64 bit data @ 156 MHz
- tx_snk_out_arr => dp_fifo_fill_tx_src_in_arr,
+ ---------------------------------------------------------------------------------------
+ -- RX FIFO: rx_clk -> dp_clk
+ ---------------------------------------------------------------------------------------
+ u_dp_fifo_dc_rx : ENTITY dp_lib.dp_fifo_dc
+ GENERIC MAP (
+ g_technology => c_tech_arria10_e1sg,
+ g_data_w => c_xgmii_data_w,
+ g_empty_w => c_tech_mac_10g_empty_w,
+ g_use_empty => TRUE,
+ g_fifo_size => c_rx_fifo_size
+ )
+ PORT MAP (
+ wr_rst => eth_rx_rst_arr(mac),
+ wr_clk => eth_rx_clk_arr(mac),
+ rd_rst => kernel_reset,
+ rd_clk => kernel_clk,
- rx_src_out_arr => mac_10g_src_out_arr, -- 64 bit data @ 156 MHz
- rx_src_in_arr => mac_10g_src_in_arr,
+ snk_out => mac_10g_src_in_arr(mac),
+ snk_in => mac_10g_src_out_arr(mac),
- -- PHY serial IO
- -- . 10GBASE-R (single lane)
- serial_tx_arr => unb2_board_front_io_serial_tx_arr,
- serial_rx_arr => unb2_board_front_io_serial_rx_arr
- );
-
-
-
- ---------------------------------------------------------------------------------------
- -- RX FIFO: rx_clk -> dp_clk
- ---------------------------------------------------------------------------------------
-
- u_dp_fifo_dc_rx : ENTITY dp_lib.dp_fifo_dc
- GENERIC MAP (
- g_technology => c_tech_arria10_e1sg,
- g_data_w => c_xgmii_data_w,
- g_empty_w => c_tech_mac_10g_empty_w,
- g_use_empty => TRUE,
- g_fifo_size => c_rx_fifo_size
- )
- PORT MAP (
- wr_rst => eth_rx_rst_arr(0),
- wr_clk => eth_rx_clk_arr(0),
- rd_rst => kernel_reset,
- rd_clk => kernel_clk,
+ src_in => dp_fifo_dc_rx_src_in_arr(mac),
+ src_out => dp_fifo_dc_rx_src_out_arr(mac)
+ );
- snk_out => mac_10g_src_in_arr(0),
- snk_in => mac_10g_src_out_arr(0),
+ ----------------------------------------------------------------------------
+ -- Latency adapter: adapt RL=1 (Upstream) to RL=0 (OpenCL kernel).
+ ----------------------------------------------------------------------------
+ u_dp_latency_adapter_rx : ENTITY dp_lib.dp_latency_adapter
+ GENERIC MAP (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ PORT MAP (
+ clk => kernel_clk,
+ rst => kernel_reset,
- src_in => dp_fifo_dc_rx_src_in,
- src_out => dp_fifo_dc_rx_src_out
- );
-
-
- ----------------------------------------------------------------------------
- -- Latency adapter: adapt RL=1 (Upstream) to RL=0 (OpenCL kernel).
- ----------------------------------------------------------------------------
- u_dp_latency_adapter_rx : ENTITY dp_lib.dp_latency_adapter
- GENERIC MAP (
- g_in_latency => 1,
- g_out_latency => 0
- )
- PORT MAP (
- clk => kernel_clk,
- rst => kernel_reset,
-
- snk_in => dp_fifo_dc_rx_src_out,
- snk_out => dp_fifo_dc_rx_src_in,
-
- src_out => dp_latency_adapter_rx_src_out,
- src_in => dp_latency_adapter_rx_src_in
- );
-
-
- ----------------------------------------------------------------------------
- -- Data mapping
- ----------------------------------------------------------------------------
- -- Reverse byte order
- gen_rx_bytes: FOR I IN 0 TO 7 GENERATE
- kernel_src_data(8*(8-I) -1 DOWNTO 8*(7-I)) <= dp_latency_adapter_rx_src_out.data(8*(I+1) -1 DOWNTO 8*I);
- END GENERATE;
-
- -- Assign control signals to correct data fields.
- kernel_src_data(64) <= dp_latency_adapter_rx_src_out.sop;
- kernel_src_data(65) <= dp_latency_adapter_rx_src_out.eop;
- kernel_src_data(71 DOWNTO 69) <= dp_latency_adapter_rx_src_out.empty(2 DOWNTO 0);
+ snk_in => dp_fifo_dc_rx_src_out_arr(mac),
+ snk_out => dp_fifo_dc_rx_src_in_arr(mac),
-
- kernel_src_valid <= dp_latency_adapter_rx_src_out.valid;
- dp_latency_adapter_rx_src_in.ready <= kernel_src_ready;
- dp_latency_adapter_rx_src_in.xon <= '1';
-
+ src_out => dp_latency_adapter_rx_src_out_arr(mac),
+ src_in => dp_latency_adapter_rx_src_in_arr(mac)
+ );
+
+ ----------------------------------------------------------------------------
+ -- Data mapping
+ ----------------------------------------------------------------------------
+ -- Reverse byte order
+ gen_rx_bytes: FOR I IN 0 TO 7 GENERATE
+ src_out_arr(mac).data(8*(8-I) -1 DOWNTO 8*(7-I)) <= dp_latency_adapter_rx_src_out_arr(mac).data(8*(I+1) -1 DOWNTO 8*I);
+ END GENERATE;
+
+ -- Assign control signals to correct data fields.
+ src_out_arr(mac).data(64) <= dp_latency_adapter_rx_src_out_arr(mac).sop;
+ src_out_arr(mac).data(65) <= dp_latency_adapter_rx_src_out_arr(mac).eop;
+ src_out_arr(mac).data(71 DOWNTO 69) <= dp_latency_adapter_rx_src_out_arr(mac).empty(2 DOWNTO 0);
+ src_out_arr(mac).valid <= dp_latency_adapter_rx_src_out_arr(mac).valid;
+ dp_latency_adapter_rx_src_in_arr(mac).ready <= src_in_arr(mac).ready;
+ dp_latency_adapter_rx_src_in_arr(mac).xon <= '1';
+ END GENERATE;
END str;
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc.vhd b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc.vhd
index 79c186c775..9e87d67520 100644
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc.vhd
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc.vhd
@@ -64,14 +64,10 @@ ENTITY ta2_unb2b_1GbE_mc IS
kernel_clk : IN STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
kernel_reset : IN STD_LOGIC;
- kernel_src_data : OUT STD_LOGIC_VECTOR(5*c_byte_w -1 DOWNTO 0); -- RX Data to kernel
- kernel_src_valid : OUT STD_LOGIC; -- RX data valid signal to kernel
- kernel_src_ready : IN STD_LOGIC; -- Flow control from kernel
-
- kernel_snk_data : IN STD_LOGIC_VECTOR(5*c_byte_w -1 DOWNTO 0); -- TX Data from kernel
- kernel_snk_valid : IN STD_LOGIC; -- TX data valid signal from kernel
- kernel_snk_ready : OUT STD_LOGIC -- Flow control towards kernel
-
+ src_out : OUT t_dp_sosi;
+ src_in : IN t_dp_siso;
+ snk_out : OUT t_dp_siso;
+ snk_in : IN t_dp_sosi
);
END ta2_unb2b_1GbE_mc;
@@ -109,16 +105,16 @@ BEGIN
----------------------------------------------------------------------------
-- Reverse byte order
gen_tx_bytes: FOR I IN 0 TO 3 GENERATE
- dp_latency_adapter_tx_snk_in.data(c_byte_w*(4-I) -1 DOWNTO c_byte_w*(3-I)) <= kernel_snk_data(c_byte_w*(I+1) -1 DOWNTO c_byte_w*I);
+ dp_latency_adapter_tx_snk_in.data(c_byte_w*(4-I) -1 DOWNTO c_byte_w*(3-I)) <= snk_in.data(c_byte_w*(I+1) -1 DOWNTO c_byte_w*I);
END GENERATE;
-- Assign correct data fields to control signals.
- dp_latency_adapter_tx_snk_in.sop <= kernel_snk_data(32);
- dp_latency_adapter_tx_snk_in.eop <= kernel_snk_data(33);
- dp_latency_adapter_tx_snk_in.empty(1 DOWNTO 0) <= kernel_snk_data(39 DOWNTO 38);
+ dp_latency_adapter_tx_snk_in.sop <= snk_in.data(32);
+ dp_latency_adapter_tx_snk_in.eop <= snk_in.data(33);
+ dp_latency_adapter_tx_snk_in.empty(1 DOWNTO 0) <= snk_in.data(39 DOWNTO 38);
- dp_latency_adapter_tx_snk_in.valid <= kernel_snk_valid;
- kernel_snk_ready <= dp_latency_adapter_tx_snk_out.ready; -- Flow control towards source (kernel)
+ dp_latency_adapter_tx_snk_in.valid <= snk_in.valid;
+ snk_out.ready <= dp_latency_adapter_tx_snk_out.ready; -- Flow control towards source (kernel)
----------------------------------------------------------------------------
-- Latency adapter: adapt RL=0 (OpenCL kernel) to RL=1 (Downstream).
@@ -234,17 +230,17 @@ BEGIN
----------------------------------------------------------------------------
-- Reverse byte order
gen_rx_bytes: FOR I IN 0 TO 3 GENERATE
- kernel_src_data(c_byte_w*(4-I) -1 DOWNTO c_byte_w*(3-I)) <= dp_latency_adapter_rx_src_out.data(c_byte_w*(I+1) -1 DOWNTO c_byte_w*I);
+ src_out.data(c_byte_w*(4-I) -1 DOWNTO c_byte_w*(3-I)) <= dp_latency_adapter_rx_src_out.data(c_byte_w*(I+1) -1 DOWNTO c_byte_w*I);
END GENERATE;
-- Assign control signals to correct data fields.
- kernel_src_data(32) <= dp_latency_adapter_rx_src_out.sop;
- kernel_src_data(33) <= dp_latency_adapter_rx_src_out.eop;
- kernel_src_data(39 DOWNTO 38) <= dp_latency_adapter_rx_src_out.empty(1 DOWNTO 0);
+ src_out.data(32) <= dp_latency_adapter_rx_src_out.sop;
+ src_out.data(33) <= dp_latency_adapter_rx_src_out.eop;
+ src_out.data(39 DOWNTO 38) <= dp_latency_adapter_rx_src_out.empty(1 DOWNTO 0);
- kernel_src_valid <= dp_latency_adapter_rx_src_out.valid;
- dp_latency_adapter_rx_src_in.ready <= kernel_src_ready;
+ src_out.valid <= dp_latency_adapter_rx_src_out.valid;
+ dp_latency_adapter_rx_src_in.ready <= src_in.ready;
dp_latency_adapter_rx_src_in.xon <= '1';
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
index 0bbee7f131..87962e2db3 100644
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
@@ -60,21 +60,21 @@ ENTITY ta2_unb2b_40GbE IS
g_nof_mac : NATURAL := 1
);
PORT (
- config_clk : IN STD_LOGIC; -- 100MHz clk for reconfig block and status interface
- config_reset : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC; -- 100MHz clk for reconfig block and status interface
+ mm_rst : IN STD_LOGIC;
- clk_ref_r : IN STD_LOGIC; -- 644.53125MHz 40G MAC reference clock
+ clk_ref_r : IN STD_LOGIC; -- 644.53125MHz 40G MAC reference clock
- tx_serial_r : OUT STD_LOGIC_VECTOR(4*g_nof_mac-1 DOWNTO 0); -- Serial TX lanes towards QSFP cage
- rx_serial_r : IN STD_LOGIC_VECTOR(4*g_nof_mac-1 DOWNTO 0); -- Serial RX lanes from QSFP cage
+ tx_serial_r : OUT STD_LOGIC_VECTOR(4*g_nof_mac-1 DOWNTO 0); -- Serial TX lanes towards QSFP cage
+ rx_serial_r : IN STD_LOGIC_VECTOR(4*g_nof_mac-1 DOWNTO 0); -- Serial RX lanes from QSFP cage
- kernel_clk : IN STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
- kernel_reset : IN STD_LOGIC;
+ kernel_clk : IN STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
+ kernel_reset : IN STD_LOGIC;
- src_out_arr : OUT t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
- src_in_arr : IN t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
- snk_out_arr : OUT t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
- snk_in_arr : IN t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0)
+ src_out_arr : OUT t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0);
+ src_in_arr : IN t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
+ snk_out_arr : OUT t_dp_siso_arr(g_nof_mac-1 DOWNTO 0);
+ snk_in_arr : IN t_dp_sosi_arr(g_nof_mac-1 DOWNTO 0)
);
END ta2_unb2b_40GbE;
@@ -381,7 +381,7 @@ BEGIN
u_arria10_40g_mac : arria10_40g_mac
PORT MAP (
- reset_async(0) => config_reset,
+ reset_async(0) => mm_rst,
clk_txmac(0) => clk_txmac_arr(mac), -- MAC + PCS clock - at least 312.5Mhz
clk_rxmac(0) => clk_rxmac_arr(mac), -- MAC + PCS clock - at least 312.5Mhz
clk_ref(0) => clk_ref_r,
@@ -390,8 +390,8 @@ BEGIN
tx_serial_clk => serial_clk_2arr(mac),
tx_pll_locked(0) => pll_locked_arr(mac),
- clk_status(0) => config_clk,
- reset_status(0) => config_reset,
+ clk_status(0) => mm_clk,
+ reset_status(0) => mm_rst,
status_addr => (OTHERS=>'0'),
status_read => (OTHERS=>'0'),
status_write => (OTHERS=>'0'),
@@ -400,8 +400,8 @@ BEGIN
-- status_read_timeout => status_read_timeout,
-- status_readdata_valid => status_readdata_valid_eth,
- reconfig_clk(0) => config_clk,
- reconfig_reset(0) => config_reset,
+ reconfig_clk(0) => mm_clk,
+ reconfig_reset(0) => mm_rst,
reconfig_write => (OTHERS=>'0'),
reconfig_read => (OTHERS=>'0'),
reconfig_address => (OTHERS=>'0'),
@@ -577,7 +577,7 @@ BEGIN
port map (
pll_cal_busy => OPEN,
pll_locked => pll_locked_arr(mac),
- pll_powerdown => config_reset,
+ pll_powerdown => mm_rst,
pll_refclk0 => clk_ref_r,
tx_serial_clk => serial_clk_arr(mac)
);
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
index 506ffc71d9..61a92c4c21 100644
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
@@ -50,9 +50,12 @@ USE technology_lib.technology_pkg.ALL;
USE common_lib.common_interface_layers_pkg.ALL;
ENTITY ta2_unb2b_jesd204b IS
+ GENERIC (
+ g_nof_streams : NATURAL := 12 -- can be 1-12
+ );
PORT (
- config_clk : IN STD_LOGIC; -- 100MHz clk for reconfig block and status interface
- config_reset : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC; -- 100MHz clk for reconfig block and status interface
+ mm_rst : IN STD_LOGIC;
-- MM Control
jesd204b_mosi : IN t_mem_mosi;
@@ -61,16 +64,15 @@ ENTITY ta2_unb2b_jesd204b IS
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
- serial_rx_arr : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
kernel_clk : IN STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
kernel_reset : IN STD_LOGIC;
- kernel_src_data : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- RX Data to kernel
- kernel_src_valid : OUT STD_LOGIC; -- RX data valid signal to kernel
- kernel_src_ready : IN STD_LOGIC -- Flow control from kernel
+ src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ src_in_arr : IN t_dp_siso_arr(g_nof_streams-1 DOWNTO 0)
);
END ta2_unb2b_jesd204b;
@@ -80,29 +82,27 @@ ARCHITECTURE str OF ta2_unb2b_jesd204b IS
CONSTANT c_sim : BOOLEAN := FALSE;
- CONSTANT c_nof_connected_streams_jesd204b: NATURAL := 1;
CONSTANT c_nof_streams_jesd204b : NATURAL := 12;
CONSTANT c_rx_fifo_size : NATURAL := 32; -- should be large enough
- SIGNAL dp_fifo_dc_rx_src_out : t_dp_sosi;
- SIGNAL dp_fifo_dc_rx_snk_in : t_dp_sosi := c_dp_sosi_rst;
- SIGNAL dp_fifo_dc_rx_src_in : t_dp_siso;
- SIGNAL dp_fifo_dc_rx_snk_out : t_dp_siso;
+ SIGNAL dp_fifo_dc_rx_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL dp_fifo_dc_rx_snk_in_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL dp_fifo_dc_rx_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL dp_fifo_dc_rx_snk_out_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL dp_latency_adapter_rx_src_out : t_dp_sosi;
- SIGNAL dp_latency_adapter_rx_src_in : t_dp_siso;
+ SIGNAL dp_latency_adapter_rx_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL dp_latency_adapter_rx_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL jesd204b_rx_src_out_arr : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
SIGNAL jesd204b_frame_clk : STD_LOGIC;
- SIGNAL jesd204b_rx_src_out_flat_w_sync : t_dp_sosi;
SIGNAL i_jesd204b_sync_n_arr : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
SIGNAL jesd204b_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
- jesd204b_sync_n_arr <= i_jesd204b_sync_n_arr(c_nof_connected_streams_jesd204b -1 DOWNTO 0);
- jesd204b_serial_rx_arr(c_nof_connected_streams_jesd204b -1 DOWNTO 0) <= serial_rx_arr;
+ jesd204b_sync_n_arr <= i_jesd204b_sync_n_arr(g_nof_streams -1 DOWNTO 0);
+ jesd204b_serial_rx_arr(g_nof_streams -1 DOWNTO 0) <= serial_rx_arr;
u_jesd204b: ENTITY tech_jesd204b_lib.tech_jesd204b
GENERIC MAP(
@@ -118,8 +118,8 @@ BEGIN
jesd204b_frame_clk => jesd204b_frame_clk,
-- MM
- mm_clk => config_clk,
- mm_rst => config_reset,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
jesd204b_mosi => jesd204b_mosi,
jesd204b_miso => jesd204b_miso,
@@ -129,73 +129,72 @@ BEGIN
serial_rx_arr => jesd204b_serial_rx_arr
);
-
- ---------------------------------------------------------------------------------------
- -- RX FIFO: adc_clk -> kernel_clk
- ---------------------------------------------------------------------------------------
-
- dp_fifo_dc_rx_snk_in.data(13 DOWNTO 0) <= jesd204b_rx_src_out_arr(0).data(15 DOWNTO 2);
- dp_fifo_dc_rx_snk_in.data(14) <= jesd204b_rx_src_out_arr(0).data(15);
- dp_fifo_dc_rx_snk_in.data(15) <= jesd204b_rx_src_out_arr(0).data(15);
- dp_fifo_dc_rx_snk_in.valid <= dp_fifo_dc_rx_snk_out.ready AND jesd204b_rx_src_out_arr(0).valid;
-
- u_dp_fifo_dc_rx : ENTITY dp_lib.dp_fifo_dc
- GENERIC MAP (
- g_technology => c_tech_arria10_e1sg,
- g_data_w => 16,
- g_empty_w => 1,
- g_use_empty => FALSE,
- g_use_ctrl => FALSE,
- g_fifo_size => c_rx_fifo_size
- )
- PORT MAP (
- wr_rst => kernel_reset,
- wr_clk => jesd204b_frame_clk,
- rd_rst => kernel_reset,
- rd_clk => kernel_clk,
-
- snk_out => dp_fifo_dc_rx_snk_out,
- snk_in => dp_fifo_dc_rx_snk_in,
-
- src_in => dp_fifo_dc_rx_src_in,
- src_out => dp_fifo_dc_rx_src_out
- );
-
-
- ----------------------------------------------------------------------------
- -- Latency adapter: adapt RL=1 (Upstream) to RL=0 (OpenCL kernel).
- ----------------------------------------------------------------------------
- u_dp_latency_adapter_rx : ENTITY dp_lib.dp_latency_adapter
- GENERIC MAP (
- g_in_latency => 1,
- g_out_latency => 0
- )
- PORT MAP (
- clk => kernel_clk,
- rst => kernel_reset,
-
- snk_in => dp_fifo_dc_rx_src_out,
- snk_out => dp_fifo_dc_rx_src_in,
-
- src_out => dp_latency_adapter_rx_src_out,
- src_in => dp_latency_adapter_rx_src_in
- );
-
-
- ----------------------------------------------------------------------------
- -- Data mapping
- ----------------------------------------------------------------------------
- -- Reverse byte order
- --gen_rx_bytes: FOR I IN 0 TO c_halfword_sz-1 GENERATE
- -- kernel_src_data(c_byte_w*(c_halfword_sz-I) -1 DOWNTO c_byte_w*(c_halfword_sz-1-I)) <= dp_latency_adapter_rx_src_out.data(c_byte_w*(I+1) -1 DOWNTO c_byte_w*I);
- --END GENERATE;
-
- kernel_src_data <= dp_latency_adapter_rx_src_out.data(15 DOWNTO 0);
-
- kernel_src_valid <= dp_latency_adapter_rx_src_out.valid;
- dp_latency_adapter_rx_src_in.ready <= kernel_src_ready;
- dp_latency_adapter_rx_src_in.xon <= '1';
-
+ gen_streams: FOR stream IN 0 TO g_nof_streams-1 GENERATE
+ ---------------------------------------------------------------------------------------
+ -- RX FIFO: adc_clk -> kernel_clk
+ ---------------------------------------------------------------------------------------
+
+ dp_fifo_dc_rx_snk_in_arr(stream).data(13 DOWNTO 0) <= jesd204b_rx_src_out_arr(stream).data(15 DOWNTO 2);
+ dp_fifo_dc_rx_snk_in_arr(stream).data(14) <= jesd204b_rx_src_out_arr(stream).data(15);
+ dp_fifo_dc_rx_snk_in_arr(stream).data(15) <= jesd204b_rx_src_out_arr(stream).data(15);
+ dp_fifo_dc_rx_snk_in_arr(stream).valid <= dp_fifo_dc_rx_snk_out_arr(stream).ready AND jesd204b_rx_src_out_arr(stream).valid;
+
+ u_dp_fifo_dc_rx : ENTITY dp_lib.dp_fifo_dc
+ GENERIC MAP (
+ g_technology => c_tech_arria10_e1sg,
+ g_data_w => 16,
+ g_empty_w => 1,
+ g_use_empty => FALSE,
+ g_use_ctrl => FALSE,
+ g_fifo_size => c_rx_fifo_size
+ )
+ PORT MAP (
+ wr_rst => kernel_reset,
+ wr_clk => jesd204b_frame_clk,
+ rd_rst => kernel_reset,
+ rd_clk => kernel_clk,
+
+ snk_out => dp_fifo_dc_rx_snk_out_arr(stream),
+ snk_in => dp_fifo_dc_rx_snk_in_arr(stream),
+
+ src_in => dp_fifo_dc_rx_src_in_arr(stream),
+ src_out => dp_fifo_dc_rx_src_out_arr(stream)
+ );
+
+
+ ----------------------------------------------------------------------------
+ -- Latency adapter: adapt RL=1 (Upstream) to RL=0 (OpenCL kernel).
+ ----------------------------------------------------------------------------
+ u_dp_latency_adapter_rx : ENTITY dp_lib.dp_latency_adapter
+ GENERIC MAP (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ PORT MAP (
+ clk => kernel_clk,
+ rst => kernel_reset,
+
+ snk_in => dp_fifo_dc_rx_src_out_arr(stream),
+ snk_out => dp_fifo_dc_rx_src_in_arr(stream),
+
+ src_out => dp_latency_adapter_rx_src_out_arr(stream),
+ src_in => dp_latency_adapter_rx_src_in_arr(stream)
+ );
+
+
+ ----------------------------------------------------------------------------
+ -- Data mapping
+ ----------------------------------------------------------------------------
+ -- Reverse byte order
+ --gen_rx_bytes: FOR I IN 0 TO c_halfword_sz-1 GENERATE
+ -- kernel_src_data(c_byte_w*(c_halfword_sz-I) -1 DOWNTO c_byte_w*(c_halfword_sz-1-I)) <= dp_latency_adapter_rx_src_out.data(c_byte_w*(I+1) -1 DOWNTO c_byte_w*I);
+ --END GENERATE;
+
+ src_out_arr(stream).data(15 DOWNTO 0) <= dp_latency_adapter_rx_src_out_arr(stream).data(15 DOWNTO 0);
+ src_out_arr(stream).valid <= dp_latency_adapter_rx_src_out_arr(stream).valid;
+ dp_latency_adapter_rx_src_in_arr(stream).ready <= src_in_arr(stream).ready;
+ dp_latency_adapter_rx_src_in_arr(stream).xon <= '1';
+ END GENERATE;
END str;
diff --git a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/top.vhd b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/top.vhd
index 42ce5312d6..e3cc0384ae 100644
--- a/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/top.vhd
+++ b/applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/top.vhd
@@ -101,25 +101,38 @@ END top;
ARCHITECTURE str OF top IS
-
- -- Firmware version x.y
- CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1);
- CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_100M;
-
- -- 1 GbE
- CONSTANT c_use_1GbE_udp_offload : BOOLEAN := TRUE;
- CONSTANT c_nof_streams_1GbE : NATURAL := 1;
-
- -- 10GbE
+ ---------------
+ -- Constants
+ ---------------
+ -- QSFP
CONSTANT c_nof_qsfp_bus : NATURAL := 2;
+ CONSTANT c_nof_streams_qsfp : NATURAL := c_unb2b_board_tr_qsfp.bus_w*c_nof_qsfp_bus;
+
+ -- RING
CONSTANT c_nof_ring_bus : NATURAL := 2;
CONSTANT c_ring_bus_w : NATURAL := c_unb2b_board_tr_ring.bus_w;
- CONSTANT c_nof_streams_qsfp : NATURAL := c_unb2b_board_tr_qsfp.bus_w*c_nof_qsfp_bus;
CONSTANT c_nof_streams_ring : NATURAL := c_unb2b_board_tr_ring.bus_w*c_nof_ring_bus;
-- 40GbE
CONSTANT c_nof_40GbE_IP : NATURAL := 3;
+ -- 10GbE
+ CONSTANT c_nof_10GbE_IP : NATURAL := 1;
+
+ -- 1 GbE
+ CONSTANT c_use_1GbE_udp_offload : BOOLEAN := TRUE;
+ CONSTANT c_nof_streams_1GbE : NATURAL := 1;
+
+ -- ADC
+ CONSTANT c_nof_ADC : NATURAL := 1;
+
+ -- Firmware version x.y
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1);
+ CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_100M;
+
+ ------------
+ -- Signals
+ ------------
-- System
SIGNAL cs_sim : STD_LOGIC;
SIGNAL xo_ethclk : STD_LOGIC;
@@ -202,16 +215,17 @@ ARCHITECTURE str OF top IS
SIGNAL reg_ta2_unb2b_jesd204b_mosi : t_mem_mosi;
SIGNAL reg_ta2_unb2b_jesd204b_miso : t_mem_miso;
- -- 10GbE
+ -- QSFP
SIGNAL i_QSFP_TX : t_unb2b_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0);
SIGNAL i_QSFP_RX : t_unb2b_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0);
+
+ SIGNAL unb2b_board_front_io_serial_tx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL unb2b_board_front_io_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0);
+ -- RING
SIGNAL i_RING_TX : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
SIGNAL i_RING_RX : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- SIGNAL unb2b_board_front_io_serial_tx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL unb2b_board_front_io_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0);
-
SIGNAL unb2b_board_ring_io_serial_tx_arr : STD_LOGIC_VECTOR(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL unb2b_board_ring_io_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_streams_ring-1 DOWNTO 0);
@@ -221,6 +235,7 @@ ARCHITECTURE str OF top IS
--SIGNAL unb2b_board_qsfp_leds_tx_src_in_arr : t_dp_siso_arr(c_nof_qsfp_bus*c_quad-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
SIGNAL unb2b_board_qsfp_leds_tx_src_in_arr : t_dp_siso_arr((c_nof_qsfp_bus+c_nof_qsfp_bus)*c_quad-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ -- Reset
SIGNAL i_reset_n : STD_LOGIC;
SIGNAL i_kernel_rst : STD_LOGIC;
@@ -258,24 +273,20 @@ ARCHITECTURE str OF top IS
SIGNAL ta2_unb2b_40GbE_tx_serial_r : STD_LOGIC_VECTOR(4*c_nof_40GbE_IP -1 DOWNTO 0);
SIGNAL ta2_unb2b_40GbE_rx_serial_r : STD_LOGIC_VECTOR(4*c_nof_40GbE_IP -1 DOWNTO 0);
- SIGNAL board_kernel_stream_src_10GbE_data : std_logic_vector(71 downto 0);
- SIGNAL board_kernel_stream_src_10GbE_valid : std_logic;
- SIGNAL board_kernel_stream_src_10GbE_ready : std_logic;
- SIGNAL board_kernel_stream_snk_10GbE_data : std_logic_vector(71 downto 0);
- SIGNAL board_kernel_stream_snk_10GbE_valid : std_logic;
- SIGNAL board_kernel_stream_snk_10GbE_ready : std_logic;
- SIGNAL ta2_unb2b_10gbe_rx_status_rx_status : std_logic; -- rx_status
-
- SIGNAL board_kernel_stream_src_1GbE_data : std_logic_vector(39 downto 0);
- SIGNAL board_kernel_stream_src_1GbE_valid : std_logic;
- SIGNAL board_kernel_stream_src_1GbE_ready : std_logic;
- SIGNAL board_kernel_stream_snk_1GbE_data : std_logic_vector(39 downto 0);
- SIGNAL board_kernel_stream_snk_1GbE_valid : std_logic;
- SIGNAL board_kernel_stream_snk_1GbE_ready : std_logic;
-
- SIGNAL board_kernel_stream_src_ADC_data : std_logic_vector(15 downto 0);
- SIGNAL board_kernel_stream_src_ADC_valid : std_logic;
- SIGNAL board_kernel_stream_src_ADC_ready : std_logic;
+ SIGNAL ta2_unb2b_10GbE_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_IP-1 DOWNTO 0);
+ SIGNAL ta2_unb2b_10GbE_src_in_arr : t_dp_siso_arr(c_nof_10GbE_IP-1 DOWNTO 0);
+ SIGNAL ta2_unb2b_10GbE_snk_out_arr : t_dp_siso_arr(c_nof_10GbE_IP-1 DOWNTO 0);
+ SIGNAL ta2_unb2b_10GbE_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_IP-1 DOWNTO 0);
+ SIGNAL ta2_unb2b_10GbE_tx_serial_r : STD_LOGIC_VECTOR(c_nof_10GbE_IP -1 DOWNTO 0);
+ SIGNAL ta2_unb2b_10GbE_rx_serial_r : STD_LOGIC_VECTOR(c_nof_10GbE_IP -1 DOWNTO 0);
+
+ SIGNAL ta2_unb2b_1GbE_src_out : t_dp_sosi;
+ SIGNAL ta2_unb2b_1GbE_src_in : t_dp_siso;
+ SIGNAL ta2_unb2b_1GbE_snk_out : t_dp_siso;
+ SIGNAL ta2_unb2b_1GbE_snk_in : t_dp_sosi;
+
+ SIGNAL ta2_unb2b_ADC_src_out_arr : t_dp_sosi_arr(c_nof_ADC-1 DOWNTO 0);
+ SIGNAL ta2_unb2b_ADC_src_in_arr : t_dp_siso_arr(c_nof_ADC-1 DOWNTO 0);
BEGIN
------------
@@ -309,7 +320,7 @@ BEGIN
------------------------
-- qsfp LEDs controller
------------------------
- unb2b_board_qsfp_leds_tx_src_in_arr(0).xon <= ta2_unb2b_10gbe_rx_status_rx_status;
+ unb2b_board_qsfp_leds_tx_src_in_arr(0).xon <= ta2_unb2b_10GbE_snk_out_arr(0).xon;
unb2b_board_qsfp_leds_tx_src_in_arr(4).xon <= ta2_unb2b_40GbE_snk_out_arr(0).xon;
-- ring LED indicator
unb2b_board_qsfp_leds_tx_src_in_arr(8).xon <= ta2_unb2b_40GbE_snk_out_arr(1).xon;
@@ -378,47 +389,51 @@ BEGIN
g_nof_mac => c_nof_40GbE_IP
)
PORT MAP (
- config_clk => mm_clk,
- config_reset => mm_rst,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- clk_ref_r => SA_CLK,
+ clk_ref_r => SA_CLK,
- tx_serial_r => ta2_unb2b_40GbE_tx_serial_r,
- rx_serial_r => ta2_unb2b_40GbE_rx_serial_r,
+ tx_serial_r => ta2_unb2b_40GbE_tx_serial_r,
+ rx_serial_r => ta2_unb2b_40GbE_rx_serial_r,
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
- src_out_arr => ta2_unb2b_40GbE_src_out_arr,
- src_in_arr => ta2_unb2b_40GbE_src_in_arr,
- snk_out_arr => ta2_unb2b_40GbE_snk_out_arr,
- snk_in_arr => ta2_unb2b_40GbE_snk_in_arr
+ src_out_arr => ta2_unb2b_40GbE_src_out_arr,
+ src_in_arr => ta2_unb2b_40GbE_src_in_arr,
+ snk_out_arr => ta2_unb2b_40GbE_snk_out_arr,
+ snk_in_arr => ta2_unb2b_40GbE_snk_in_arr
);
----------
-- 10GbE
----------
- u_ta2_unb2b_10GbE : ENTITY work.ta2_unb2b_10GbE
- PORT MAP (
- config_reset => mm_rst,
+ -- Front QSFP 0 10GbE Interface, IP index = 0
+ unb2b_board_front_io_serial_tx_arr(0) <= ta2_unb2b_10GbE_tx_serial_r(0);
+ ta2_unb2b_10GbE_rx_serial_r(0) <= unb2b_board_front_io_serial_rx_arr(0);
- clk_ref_r => SA_CLK,
- tx_serial_r => unb2b_board_front_io_serial_tx_arr(0),
- rx_serial_r => unb2b_board_front_io_serial_rx_arr(0),
-
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
+ u_ta2_unb2b_10GbE : ENTITY work.ta2_unb2b_10GbE
+ GENERIC MAP (
+ g_nof_mac => c_nof_10GbE_IP
+ )
+ PORT MAP (
+ mm_clk => '0', --mm_clk,
+ mm_rst => mm_rst,
- kernel_src_data => board_kernel_stream_src_10GbE_data,
- kernel_src_valid => board_kernel_stream_src_10GbE_valid,
- kernel_src_ready => board_kernel_stream_src_10GbE_ready,
+ clk_ref_r => SA_CLK,
+
+ tx_serial_r => ta2_unb2b_10GbE_tx_serial_r,
+ rx_serial_r => ta2_unb2b_10GbE_rx_serial_r,
- kernel_snk_data => board_kernel_stream_snk_10GbE_data,
- kernel_snk_valid => board_kernel_stream_snk_10GbE_valid,
- kernel_snk_ready => board_kernel_stream_snk_10GbE_ready,
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
- rx_status => ta2_unb2b_10gbe_rx_status_rx_status
+ src_out_arr => ta2_unb2b_10GbE_src_out_arr,
+ src_in_arr => ta2_unb2b_10GbE_src_in_arr,
+ snk_out_arr => ta2_unb2b_10GbE_snk_out_arr,
+ snk_in_arr => ta2_unb2b_10GbE_snk_in_arr
);
@@ -438,22 +453,22 @@ BEGIN
kernel_clk => board_kernel_clk_clk,
kernel_reset => i_kernel_rst,
- kernel_src_data => board_kernel_stream_src_1GbE_data,
- kernel_src_valid => board_kernel_stream_src_1GbE_valid,
- kernel_src_ready => board_kernel_stream_src_1GbE_ready,
- kernel_snk_data => board_kernel_stream_snk_1GbE_data,
- kernel_snk_valid => board_kernel_stream_snk_1GbE_valid,
- kernel_snk_ready => board_kernel_stream_snk_1GbE_ready
-
+ src_out => ta2_unb2b_1GbE_src_out,
+ src_in => ta2_unb2b_1GbE_src_in,
+ snk_out => ta2_unb2b_1GbE_snk_out,
+ snk_in => ta2_unb2b_1GbE_snk_in
);
----------
-- ADC
----------
u_ta2_unb2b_jesd204b : ENTITY work.ta2_unb2b_jesd204b
+ GENERIC MAP(
+ g_nof_streams => c_nof_ADC
+ )
PORT MAP(
- config_clk => mm_clk,
- config_reset => mm_rst,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
jesd204b_mosi => reg_ta2_unb2b_jesd204b_mosi,
jesd204b_miso => reg_ta2_unb2b_jesd204b_miso,
@@ -467,11 +482,9 @@ BEGIN
kernel_clk => board_kernel_clk_clk,
kernel_reset => i_kernel_rst,
-
- kernel_src_data => board_kernel_stream_src_ADC_data,
- kernel_src_valid => board_kernel_stream_src_ADC_valid,
- kernel_src_ready => board_kernel_stream_src_ADC_ready
-
+
+ src_out_arr => ta2_unb2b_ADC_src_out_arr,
+ src_in_arr => ta2_unb2b_ADC_src_in_arr
);
@@ -480,34 +493,34 @@ BEGIN
-----------------------------------------------------------------------------
freeze_wrapper_inst : freeze_wrapper
PORT MAP(
- board_kernel_clk_clk => board_kernel_clk_clk,
- board_kernel_clk2x_clk => board_kernel_clk2x_clk,
- board_kernel_reset_reset_n => board_kernel_reset_reset_n_in,
- board_kernel_irq_irq => board_kernel_irq_irq,
- board_kernel_cra_waitrequest => board_kernel_cra_waitrequest,
- board_kernel_cra_readdata => board_kernel_cra_readdata,
- board_kernel_cra_readdatavalid => board_kernel_cra_readdatavalid,
- board_kernel_cra_burstcount => board_kernel_cra_burstcount,
- board_kernel_cra_writedata => board_kernel_cra_writedata,
- board_kernel_cra_address => board_kernel_cra_address,
- board_kernel_cra_write => board_kernel_cra_write,
- board_kernel_cra_read => board_kernel_cra_read,
- board_kernel_cra_byteenable => board_kernel_cra_byteenable,
- board_kernel_cra_debugaccess => board_kernel_cra_debugaccess,
- board_kernel_register_mem_address => board_kernel_register_mem_address,
- board_kernel_register_mem_clken => board_kernel_register_mem_clken,
- board_kernel_register_mem_chipselect => board_kernel_register_mem_chipselect,
- board_kernel_register_mem_write => board_kernel_register_mem_write,
- board_kernel_register_mem_readdata => board_kernel_register_mem_readdata,
- board_kernel_register_mem_writedata => board_kernel_register_mem_writedata,
- board_kernel_register_mem_byteenable => board_kernel_register_mem_byteenable,
-
- board_kernel_stream_src_40GbE_data => ta2_unb2b_40GbE_src_out_arr(0).data(263 DOWNTO 0),
- board_kernel_stream_src_40GbE_valid => ta2_unb2b_40GbE_src_out_arr(0).valid,
- board_kernel_stream_src_40GbE_ready => ta2_unb2b_40GbE_src_in_arr(0).ready,
- board_kernel_stream_snk_40GbE_data => ta2_unb2b_40GbE_snk_in_arr(0).data(263 DOWNTO 0),
- board_kernel_stream_snk_40GbE_valid => ta2_unb2b_40GbE_snk_in_arr(0).valid,
- board_kernel_stream_snk_40GbE_ready => ta2_unb2b_40GbE_snk_out_arr(0).ready,
+ board_kernel_clk_clk => board_kernel_clk_clk,
+ board_kernel_clk2x_clk => board_kernel_clk2x_clk,
+ board_kernel_reset_reset_n => board_kernel_reset_reset_n_in,
+ board_kernel_irq_irq => board_kernel_irq_irq,
+ board_kernel_cra_waitrequest => board_kernel_cra_waitrequest,
+ board_kernel_cra_readdata => board_kernel_cra_readdata,
+ board_kernel_cra_readdatavalid => board_kernel_cra_readdatavalid,
+ board_kernel_cra_burstcount => board_kernel_cra_burstcount,
+ board_kernel_cra_writedata => board_kernel_cra_writedata,
+ board_kernel_cra_address => board_kernel_cra_address,
+ board_kernel_cra_write => board_kernel_cra_write,
+ board_kernel_cra_read => board_kernel_cra_read,
+ board_kernel_cra_byteenable => board_kernel_cra_byteenable,
+ board_kernel_cra_debugaccess => board_kernel_cra_debugaccess,
+ board_kernel_register_mem_address => board_kernel_register_mem_address,
+ board_kernel_register_mem_clken => board_kernel_register_mem_clken,
+ board_kernel_register_mem_chipselect => board_kernel_register_mem_chipselect,
+ board_kernel_register_mem_write => board_kernel_register_mem_write,
+ board_kernel_register_mem_readdata => board_kernel_register_mem_readdata,
+ board_kernel_register_mem_writedata => board_kernel_register_mem_writedata,
+ board_kernel_register_mem_byteenable => board_kernel_register_mem_byteenable,
+
+ board_kernel_stream_src_40GbE_data => ta2_unb2b_40GbE_src_out_arr(0).data(263 DOWNTO 0),
+ board_kernel_stream_src_40GbE_valid => ta2_unb2b_40GbE_src_out_arr(0).valid,
+ board_kernel_stream_src_40GbE_ready => ta2_unb2b_40GbE_src_in_arr(0).ready,
+ board_kernel_stream_snk_40GbE_data => ta2_unb2b_40GbE_snk_in_arr(0).data(263 DOWNTO 0),
+ board_kernel_stream_snk_40GbE_valid => ta2_unb2b_40GbE_snk_in_arr(0).valid,
+ board_kernel_stream_snk_40GbE_ready => ta2_unb2b_40GbE_snk_out_arr(0).ready,
board_kernel_stream_src_40GbE_ring_0_data => ta2_unb2b_40GbE_src_out_arr(1).data(263 DOWNTO 0),
board_kernel_stream_src_40GbE_ring_0_valid => ta2_unb2b_40GbE_src_out_arr(1).valid,
@@ -523,23 +536,23 @@ BEGIN
board_kernel_stream_snk_40GbE_ring_1_valid => ta2_unb2b_40GbE_snk_in_arr(2).valid,
board_kernel_stream_snk_40GbE_ring_1_ready => ta2_unb2b_40GbE_snk_out_arr(2).ready,
- board_kernel_stream_src_10GbE_data => board_kernel_stream_src_10GbE_data,
- board_kernel_stream_src_10GbE_valid => board_kernel_stream_src_10GbE_valid,
- board_kernel_stream_src_10GbE_ready => board_kernel_stream_src_10GbE_ready,
- board_kernel_stream_snk_10GbE_data => board_kernel_stream_snk_10GbE_data,
- board_kernel_stream_snk_10GbE_valid => board_kernel_stream_snk_10GbE_valid,
- board_kernel_stream_snk_10GbE_ready => board_kernel_stream_snk_10GbE_ready,
-
- board_kernel_stream_src_1GbE_data => board_kernel_stream_src_1GbE_data,
- board_kernel_stream_src_1GbE_valid => board_kernel_stream_src_1GbE_valid,
- board_kernel_stream_src_1GbE_ready => board_kernel_stream_src_1GbE_ready,
- board_kernel_stream_snk_1GbE_data => board_kernel_stream_snk_1GbE_data,
- board_kernel_stream_snk_1GbE_valid => board_kernel_stream_snk_1GbE_valid,
- board_kernel_stream_snk_1GbE_ready => board_kernel_stream_snk_1GbE_ready,
-
- board_kernel_stream_src_ADC_data => board_kernel_stream_src_ADC_data,
- board_kernel_stream_src_ADC_valid => board_kernel_stream_src_ADC_valid,
- board_kernel_stream_src_ADC_ready => board_kernel_stream_src_ADC_ready
+ board_kernel_stream_src_10GbE_data => ta2_unb2b_10GbE_src_out_arr(0).data(71 DOWNTO 0),
+ board_kernel_stream_src_10GbE_valid => ta2_unb2b_10GbE_src_out_arr(0).valid,
+ board_kernel_stream_src_10GbE_ready => ta2_unb2b_10GbE_src_in_arr(0).ready,
+ board_kernel_stream_snk_10GbE_data => ta2_unb2b_10GbE_snk_in_arr(0).data(71 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_valid => ta2_unb2b_10GbE_snk_in_arr(0).valid,
+ board_kernel_stream_snk_10GbE_ready => ta2_unb2b_10GbE_snk_out_arr(0).ready,
+
+ board_kernel_stream_src_1GbE_data => ta2_unb2b_1GbE_src_out.data(39 DOWNTO 0),
+ board_kernel_stream_src_1GbE_valid => ta2_unb2b_1GbE_src_out.valid,
+ board_kernel_stream_src_1GbE_ready => ta2_unb2b_1GbE_src_in.ready,
+ board_kernel_stream_snk_1GbE_data => ta2_unb2b_1GbE_snk_in.data(39 DOWNTO 0),
+ board_kernel_stream_snk_1GbE_valid => ta2_unb2b_1GbE_snk_in.valid,
+ board_kernel_stream_snk_1GbE_ready => ta2_unb2b_1GbE_snk_out.ready,
+
+ board_kernel_stream_src_ADC_data => ta2_unb2b_ADC_src_out_arr(0).data(15 DOWNTO 0),
+ board_kernel_stream_src_ADC_valid => ta2_unb2b_ADC_src_out_arr(0).valid,
+ board_kernel_stream_src_ADC_ready => ta2_unb2b_ADC_src_in_arr(0).ready
);
@@ -558,7 +571,6 @@ BEGIN
out_rst => board_kernel_reset_reset_n_in
);
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
--
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