diff --git a/boards/uniboard2/libraries/unb2_board/hdllib.cfg b/boards/uniboard2/libraries/unb2_board/hdllib.cfg
index 89b6c49020b519954e4c2d7896672db59e38df35..78a7e33886ea174d8a5b23da6ab731b69caffc20 100644
--- a/boards/uniboard2/libraries/unb2_board/hdllib.cfg
+++ b/boards/uniboard2/libraries/unb2_board/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = unb2_board
hdl_library_clause_name = unb2_board_lib
-hdl_lib_uses_synth = common dp diag uth ppsh i2c tr_nonbonded eth remu technology tech_clkbuf tech_pll tech_fractional_pll epcs tr_10GbE fpga_temp_sens
+hdl_lib_uses_synth = common dp diag uth ppsh i2c tr_nonbonded eth remu technology tech_clkbuf tech_pll tech_fractional_pll epcs tr_10GbE fpga_sense
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10
diff --git a/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf b/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
index 577051cd04ca496483104ac833348cdca94c10c4..d6735e3af94fbf909ec3c097569198267d33ca15 100644
--- a/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+++ b/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
@@ -27,6 +27,7 @@
# Device:
set_global_assignment -name FAMILY "Arria 10"
set_global_assignment -name DEVICE 10AX115U4F45I3SGES
+#set_global_assignment -name DEVICE 10AX115U4F45E3SG
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "1.8 V"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
#set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
index 3d9cc018ba0040d70417076ea59a67e4ca9fe951..e707ccbdad2eafe4db3952512fe9016e7fcaa7db 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
@@ -181,8 +181,10 @@ ENTITY ctrl_unb2_board IS
reg_unb_sens_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_unb_sens_miso : OUT t_mem_miso;
- reg_fpga_sens_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_fpga_sens_miso : OUT t_mem_miso;
+ reg_fpga_temp_sens_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_fpga_temp_sens_miso : OUT t_mem_miso;
+ reg_fpga_voltage_sens_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_fpga_voltage_sens_miso : OUT t_mem_miso;
reg_unb_pmbus_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_unb_pmbus_miso : OUT t_mem_miso;
@@ -709,8 +711,10 @@ BEGIN
mm_start => '1', -- this works
-- Memory-mapped clock domain
- reg_mosi => reg_fpga_sens_mosi,
- reg_miso => reg_fpga_sens_miso,
+ reg_temp_mosi => reg_fpga_temp_sens_mosi,
+ reg_temp_miso => reg_fpga_temp_sens_miso,
+ reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
+ reg_voltage_miso => reg_fpga_voltage_sens_miso,
-- Temperature alarm
temp_alarm => temp_alarm
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
index 1b288793365a7f486b2e95944cd911aa7c2415eb..2f2c4d9d581056ee7af8841887804039939d8dc5 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
@@ -42,8 +42,10 @@ ENTITY mms_unb2_fpga_sens IS
mm_start : IN STD_LOGIC;
-- Memory-mapped clock domain
- reg_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
- reg_miso : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
+ reg_temp_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
+ reg_temp_miso : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
+ reg_voltage_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- actual ranges defined by c_mm_reg
+ reg_voltage_miso : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
-- Temperature alarm output
temp_alarm : OUT STD_LOGIC
@@ -77,8 +79,10 @@ BEGIN
start => mm_start,
-- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ sla_temp_in => reg_temp_mosi,
+ sla_temp_out => reg_temp_miso,
+ sla_voltage_in => reg_voltage_mosi,
+ sla_voltage_out => reg_voltage_miso,
-- MM registers
--sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd
index 9e3fc7755e4b21a8e0b678ba99886089e022cddb..179be05dab124343bbccaaed2cd35aded8dde543 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd
@@ -157,14 +157,15 @@ PACKAGE unb2_board_peripherals_pkg IS
-- dp_offload
reg_dp_offload_tx_adr_w : NATURAL; -- = 1
- -- pi_unb_fpga_sens
- reg_fpga_sens_adr_w : NATURAL; -- = 3
+ -- pi_unb_fpga_sensors
+ reg_fpga_temp_sens_adr_w : NATURAL; -- = 3
+ reg_fpga_voltage_sens_adr_w : NATURAL; -- = 4
-- pi_unb_pmbus
reg_unb_pmbus_adr_w : NATURAL; -- = 3
END RECORD;
- CONSTANT c_unb2_board_peripherals_mm_reg_default : t_c_unb2_board_peripherals_mm_reg := (TRUE, 10, 4, 10, 5, 10, 1, 1, 3, 1, 1, 1, 1, 1, 3, 3, 3, 16, 4, 6, 2, 2, 1, 4, 3, 6, 13, 12, 2, 32, 8, 2, 8, 10, 16, 1024, 14, 5, 3, 11, 2, 3, 5, 16, 11, 3, 1, 3, 3);
+ CONSTANT c_unb2_board_peripherals_mm_reg_default : t_c_unb2_board_peripherals_mm_reg := (TRUE, 10, 4, 10, 5, 10, 1, 1, 3, 1, 1, 1, 1, 1, 3, 3, 3, 16, 4, 6, 2, 2, 1, 4, 3, 6, 13, 12, 2, 32, 8, 2, 8, 10, 16, 1024, 14, 5, 3, 11, 2, 3, 5, 16, 11, 3, 1, 3, 4, 3);
END unb2_board_peripherals_pkg;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd
index c7ae0a50379b3df39a963f8e1e8a517d0679fdd4..6be0a05095e7eba93f2f87b6d239b3ac9b5ae4ff 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd
@@ -22,7 +22,7 @@
-- Purpose: Provide MM slave register for unb2_fpga_sens
--
-LIBRARY IEEE, common_lib, fpga_temp_sens_lib;
+LIBRARY IEEE, common_lib, fpga_sense_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
@@ -81,8 +81,8 @@ BEGIN
reg_temp_mosi => sla_temp_in,
reg_temp_miso => sla_temp_out,
- reg_voltage_sense_mosi => sla_voltage_in,
- reg_voltage_sense_miso => sla_voltage_out
+ reg_voltage_store_mosi => sla_voltage_in,
+ reg_voltage_store_miso => sla_voltage_out
);
END str;