diff --git a/tools/oneclick/base/mmm_gen.py b/tools/oneclick/base/mmm_gen.py
index de5de5109c17dd82dcab763bb6ba531139934a58..3c635d2224990e1a192c1932b61bd5497c523eaa 100644
--- a/tools/oneclick/base/mmm_gen.py
+++ b/tools/oneclick/base/mmm_gen.py
@@ -148,14 +148,9 @@ class QsysEntity(vhdl.Entity):
             s_connect = ""
             if "_address_export" in s:  
                 s_reg_name = self.name_convert(s.split("_address_export")[0])
-                if s_reg_name[-1].isdigit():
-                    s_index    = s_reg_name.rsplit("_", 1)[1]
-                    s_reg_name = s_reg_name.rsplit("_", 1)[0]
-                    s_connect =  s_reg_name + "_mosi_arr(" + s_index + ").address("
-                else:
-                    s_connect =  s_reg_name + "_mosi.address("
-                    
+                s_connect =  s_reg_name + "_mosi.address("
                 span = self.find_span(s_reg_name, mmm_conf.peripherals) 
+                print s_reg_name
                 if span == 0: 
                     sys.exit('Error: No corresponding register in mmm.cfg for QSYS register: ' + s_reg_name)
                 if span == 1: 
@@ -165,39 +160,23 @@ class QsysEntity(vhdl.Entity):
             
             if "_read_export" in s:  
                 s_reg_name = self.name_convert(s.split("_read_export")[0])
-                if s_reg_name[-1].isdigit():
-                    s_index    = s_reg_name.rsplit("_", 1)[1]
-                    s_reg_name = s_reg_name.rsplit("_", 1)[0]
-                    s_connect =  s_reg_name + "_mosi_arr(" + s_index + ").rd,"
-                else:
-                    s_connect =  s_reg_name + "_mosi.rd,"
+                s_connect =  s_reg_name + "_mosi.rd,"
 
             if "_write_export" in s:  
                 s_reg_name = self.name_convert(s.split("_write_export")[0])
-                if s_reg_name[-1].isdigit():
-                    s_index    = s_reg_name.rsplit("_", 1)[1]
-                    s_reg_name = s_reg_name.rsplit("_", 1)[0]
-                    s_connect =  s_reg_name + "_mosi_arr(" + s_index + ").wr,"
-                else:
-                    s_connect =  s_reg_name + "_mosi.wr,"
+                s_connect =  s_reg_name + "_mosi.wr,"
 
             if "_readdata_export" in s:  
                 s_reg_name = self.name_convert(s.split("_readdata_export")[0])
-                if s_reg_name[-1].isdigit():
-                    s_index    = s_reg_name.rsplit("_", 1)[1]
-                    s_reg_name = s_reg_name.rsplit("_", 1)[0]
-                    s_connect =  s_reg_name + "_miso_arr(" + s_index + ").rddata(c_word_w-1 DOWNTO 0),"
-                else:
-                    s_connect =  s_reg_name + "_miso.rddata(c_word_w-1 DOWNTO 0),"
+                s_connect =  s_reg_name + "_miso.rddata(c_word_w-1 DOWNTO 0),"
 
             if "_writedata_export" in s:  
                 s_reg_name = self.name_convert(s.split("_writedata_export")[0])
-                if s_reg_name[-1].isdigit():
-                    s_index    = s_reg_name.rsplit("_", 1)[1]
-                    s_reg_name = s_reg_name.rsplit("_", 1)[0]
-                    s_connect =  s_reg_name + "_mosi_arr(" + s_index + ").wrdata(c_word_w-1 DOWNTO 0),"
-                else:
-                    s_connect =  s_reg_name + "_mosi.wrdata(c_word_w-1 DOWNTO 0),"
+                s_connect =  s_reg_name + "_mosi.wrdata(c_word_w-1 DOWNTO 0),"
+
+            if "_waitrequest_export" in s:  
+                s_reg_name = self.name_convert(s.split("_waitrequest_export")[0])
+                s_connect =  s_reg_name + "_miso.waitrequest,"
 
             if "_clk_export" in s:  
                 s_connect =  "OPEN,"
@@ -397,7 +376,8 @@ if __name__ == '__main__':
     # commented instantiation. 
     ###################################
     s_entity = ent_mmm.make_entity_definition_string()
-    s_instantiation = ent_mmm.comment(ent_mmm.make_instantiation_string())
+    s_instantiation = ent_mmm.comment(ent_mmm.make_instantiation_string()) 
+    s_signal_declarations = ent_mmm.comment(ent_mmm.make_signal_declarations_string(["t_mem_mosi", "t_mem_miso"]))
 
     ###################################    
     # Make the architecture header
@@ -440,7 +420,7 @@ if __name__ == '__main__':
     s_master = s_master_start + ent_qsys.apply_indend(s_inv_mm_rst + "\n" + ent_qsys.make_qsys_instance_string(mmm_conf), 2) + s_end_generate + "\n"
 
     s_arch_total = s_arch_begin + ent_qsys.apply_indend(s_file + s_master, 2) + s_arch_end
-    string_elements = [s_header, s_instantiation, s_libraries, s_entity, s_arch_header, s_arch_total ]
+    string_elements = [s_header, s_instantiation, s_signal_declarations, s_libraries, s_entity, s_arch_header, s_arch_total ]
     
     ###################################    
     # Write the whole string to a file