From 2b7c2abe67c7189261dd7fa1936dfa76a14f82fd Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Tue, 11 Apr 2023 14:10:21 +0200
Subject: [PATCH] added axi4 wrapper for eth_tester
---
libraries/io/eth/hdllib.cfg | 3 +-
.../eth/src/vhdl/eth_tester_axi4_wrapper.vhd | 601 ++++++++++++++++++
2 files changed, 603 insertions(+), 1 deletion(-)
create mode 100644 libraries/io/eth/src/vhdl/eth_tester_axi4_wrapper.vhd
diff --git a/libraries/io/eth/hdllib.cfg b/libraries/io/eth/hdllib.cfg
index ef29caf98d..94292b2cb6 100644
--- a/libraries/io/eth/hdllib.cfg
+++ b/libraries/io/eth/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = eth
hdl_library_clause_name = eth_lib
-hdl_lib_uses_synth = dp common diag tech_tse
+hdl_lib_uses_synth = dp common diag tech_tse axi4
hdl_lib_uses_sim =
hdl_lib_technology =
@@ -28,6 +28,7 @@ synth_files =
src/vhdl/eth_tester_tx.vhd
src/vhdl/eth_tester_rx.vhd
src/vhdl/eth_tester.vhd
+ src/vhdl/eth_tester_axi4_wrapper.vhd
test_bench_files =
src/vhdl/eth_statistics.vhd
diff --git a/libraries/io/eth/src/vhdl/eth_tester_axi4_wrapper.vhd b/libraries/io/eth/src/vhdl/eth_tester_axi4_wrapper.vhd
new file mode 100644
index 0000000000..51ea0649c3
--- /dev/null
+++ b/libraries/io/eth/src/vhdl/eth_tester_axi4_wrapper.vhd
@@ -0,0 +1,601 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib, diag_lib, axi4_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE dp_lib.dp_components_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE axi4_lib.axi4_stream_pkg.ALL;
+USE axi4_lib.axi4_lite_pkg.ALL;
+USE work.eth_pkg.ALL;
+USE work.eth_tester_pkg.ALL;
+
+ENTITY eth_tester_axi4_wrapper IS
+ PORT (
+ -- Clocks and reset
+ mm_clk : IN STD_LOGIC;
+ st_clk : IN STD_LOGIC;
+ st_pps : IN STD_LOGIC;
+ aresetn : IN STD_LOGIC;
+ -- UDP transmit interface
+ eth_src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
+ ip_src_addr : IN STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
+ udp_src_port : IN STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
+
+ tx_fifo_rd_emp_arr : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+
+ -- tx_udp
+ -- Source In and Sink Out
+ tx_udp_tready : IN STD_LOGIC;
+
+ -- Source Out and Sink In
+ tx_udp_tvalid : OUT STD_LOGIC;
+ tx_udp_tdata : OUT STD_LOGIC_VECTOR(c_axi4_stream_data_w-1 DOWNTO 0);
+ tx_udp_tstrb : OUT STD_LOGIC_VECTOR(c_axi4_stream_strb_w-1 DOWNTO 0);
+ tx_udp_tkeep : OUT STD_LOGIC_VECTOR(c_axi4_stream_keep_w-1 DOWNTO 0);
+ tx_udp_tlast : OUT STD_LOGIC;
+ tx_udp_tid : OUT STD_LOGIC_VECTOR(c_axi4_stream_tid_w-1 DOWNTO 0);
+ tx_udp_tdest : OUT STD_LOGIC_VECTOR(c_axi4_stream_dest_w-1 DOWNTO 0);
+ tx_udp_tuser : OUT STD_LOGIC_VECTOR(c_axi4_stream_user_w-1 DOWNTO 0);
+
+ -- rx_udp
+ -- Source In and Sink Out
+ rx_udp_tready : OUT STD_LOGIC;
+
+ -- Source Out and Sink In
+ rx_udp_tvalid : IN STD_LOGIC;
+ rx_udp_tdata : IN STD_LOGIC_VECTOR(c_axi4_stream_data_w-1 DOWNTO 0);
+ rx_udp_tstrb : IN STD_LOGIC_VECTOR(c_axi4_stream_strb_w-1 DOWNTO 0);
+ rx_udp_tkeep : IN STD_LOGIC_VECTOR(c_axi4_stream_keep_w-1 DOWNTO 0);
+ rx_udp_tlast : IN STD_LOGIC;
+ rx_udp_tid : IN STD_LOGIC_VECTOR(c_axi4_stream_tid_w-1 DOWNTO 0);
+ rx_udp_tdest : IN STD_LOGIC_VECTOR(c_axi4_stream_dest_w-1 DOWNTO 0);
+ rx_udp_tuser : IN STD_LOGIC_VECTOR(c_axi4_stream_user_w-1 DOWNTO 0);
+
+ -- reg_bg_ctrl
+ -- copi
+ reg_bg_ctrl_awaddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
+ reg_bg_ctrl_awprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
+ reg_bg_ctrl_awvalid : IN STD_LOGIC;
+ reg_bg_ctrl_wdata : IN STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
+ reg_bg_ctrl_wstrb : IN STD_LOGIC_VECTOR((c_axi4_lite_data_w/c_byte_w)-1 downto 0);
+ reg_bg_ctrl_wvalid : IN STD_LOGIC;
+ reg_bg_ctrl_bready : IN STD_LOGIC;
+ reg_bg_ctrl_araddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
+ reg_bg_ctrl_arprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
+ reg_bg_ctrl_arvalid : IN STD_LOGIC;
+ reg_bg_ctrl_rready : IN STD_LOGIC;
+ -- cipo
+ reg_bg_ctrl_awready : OUT STD_LOGIC;
+ reg_bg_ctrl_wready : OUT STD_LOGIC;
+ reg_bg_ctrl_bresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
+ reg_bg_ctrl_bvalid : OUT STD_LOGIC;
+ reg_bg_ctrl_arready : OUT STD_LOGIC;
+ reg_bg_ctrl_rdata : OUT STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
+ reg_bg_ctrl_rresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
+ reg_bg_ctrl_rvalid : OUT STD_LOGIC;
+
+ -- reg_hdr_dat
+ -- copi
+ reg_hdr_dat_awaddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
+ reg_hdr_dat_awprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
+ reg_hdr_dat_awvalid : IN STD_LOGIC;
+ reg_hdr_dat_wdata : IN STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
+ reg_hdr_dat_wstrb : IN STD_LOGIC_VECTOR((c_axi4_lite_data_w/c_byte_w)-1 downto 0);
+ reg_hdr_dat_wvalid : IN STD_LOGIC;
+ reg_hdr_dat_bready : IN STD_LOGIC;
+ reg_hdr_dat_araddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
+ reg_hdr_dat_arprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
+ reg_hdr_dat_arvalid : IN STD_LOGIC;
+ reg_hdr_dat_rready : IN STD_LOGIC;
+ -- cipo
+ reg_hdr_dat_awready : OUT STD_LOGIC;
+ reg_hdr_dat_wready : OUT STD_LOGIC;
+ reg_hdr_dat_bresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
+ reg_hdr_dat_bvalid : OUT STD_LOGIC;
+ reg_hdr_dat_arready : OUT STD_LOGIC;
+ reg_hdr_dat_rdata : OUT STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
+ reg_hdr_dat_rresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
+ reg_hdr_dat_rvalid : OUT STD_LOGIC;
+
+ -- reg_bsn_monitor_v2_tx
+ -- copi
+ reg_bsn_monitor_v2_tx_awaddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
+ reg_bsn_monitor_v2_tx_awprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
+ reg_bsn_monitor_v2_tx_awvalid : IN STD_LOGIC;
+ reg_bsn_monitor_v2_tx_wdata : IN STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
+ reg_bsn_monitor_v2_tx_wstrb : IN STD_LOGIC_VECTOR((c_axi4_lite_data_w/c_byte_w)-1 downto 0);
+ reg_bsn_monitor_v2_tx_wvalid : IN STD_LOGIC;
+ reg_bsn_monitor_v2_tx_bready : IN STD_LOGIC;
+ reg_bsn_monitor_v2_tx_araddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
+ reg_bsn_monitor_v2_tx_arprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
+ reg_bsn_monitor_v2_tx_arvalid : IN STD_LOGIC;
+ reg_bsn_monitor_v2_tx_rready : IN STD_LOGIC;
+ -- cipo
+ reg_bsn_monitor_v2_tx_awready : OUT STD_LOGIC;
+ reg_bsn_monitor_v2_tx_wready : OUT STD_LOGIC;
+ reg_bsn_monitor_v2_tx_bresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
+ reg_bsn_monitor_v2_tx_bvalid : OUT STD_LOGIC;
+ reg_bsn_monitor_v2_tx_arready : OUT STD_LOGIC;
+ reg_bsn_monitor_v2_tx_rdata : OUT STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
+ reg_bsn_monitor_v2_tx_rresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
+ reg_bsn_monitor_v2_tx_rvalid : OUT STD_LOGIC;
+
+ -- reg_strobe_total_count_tx
+ -- copi
+ reg_strobe_total_count_tx_awaddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
+ reg_strobe_total_count_tx_awprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
+ reg_strobe_total_count_tx_awvalid : IN STD_LOGIC;
+ reg_strobe_total_count_tx_wdata : IN STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
+ reg_strobe_total_count_tx_wstrb : IN STD_LOGIC_VECTOR((c_axi4_lite_data_w/c_byte_w)-1 downto 0);
+ reg_strobe_total_count_tx_wvalid : IN STD_LOGIC;
+ reg_strobe_total_count_tx_bready : IN STD_LOGIC;
+ reg_strobe_total_count_tx_araddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
+ reg_strobe_total_count_tx_arprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
+ reg_strobe_total_count_tx_arvalid : IN STD_LOGIC;
+ reg_strobe_total_count_tx_rready : IN STD_LOGIC;
+ -- cipo
+ reg_strobe_total_count_tx_awready : OUT STD_LOGIC;
+ reg_strobe_total_count_tx_wready : OUT STD_LOGIC;
+ reg_strobe_total_count_tx_bresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
+ reg_strobe_total_count_tx_bvalid : OUT STD_LOGIC;
+ reg_strobe_total_count_tx_arready : OUT STD_LOGIC;
+ reg_strobe_total_count_tx_rdata : OUT STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
+ reg_strobe_total_count_tx_rresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
+ reg_strobe_total_count_tx_rvalid : OUT STD_LOGIC;
+
+ -- reg_bsn_monitor_v2_rx
+ -- copi
+ reg_bsn_monitor_v2_rx_awaddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
+ reg_bsn_monitor_v2_rx_awprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
+ reg_bsn_monitor_v2_rx_awvalid : IN STD_LOGIC;
+ reg_bsn_monitor_v2_rx_wdata : IN STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
+ reg_bsn_monitor_v2_rx_wstrb : IN STD_LOGIC_VECTOR((c_axi4_lite_data_w/c_byte_w)-1 downto 0);
+ reg_bsn_monitor_v2_rx_wvalid : IN STD_LOGIC;
+ reg_bsn_monitor_v2_rx_bready : IN STD_LOGIC;
+ reg_bsn_monitor_v2_rx_araddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
+ reg_bsn_monitor_v2_rx_arprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
+ reg_bsn_monitor_v2_rx_arvalid : IN STD_LOGIC;
+ reg_bsn_monitor_v2_rx_rready : IN STD_LOGIC;
+ -- cipo
+ reg_bsn_monitor_v2_rx_awready : OUT STD_LOGIC;
+ reg_bsn_monitor_v2_rx_wready : OUT STD_LOGIC;
+ reg_bsn_monitor_v2_rx_bresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
+ reg_bsn_monitor_v2_rx_bvalid : OUT STD_LOGIC;
+ reg_bsn_monitor_v2_rx_arready : OUT STD_LOGIC;
+ reg_bsn_monitor_v2_rx_rdata : OUT STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
+ reg_bsn_monitor_v2_rx_rresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
+ reg_bsn_monitor_v2_rx_rvalid : OUT STD_LOGIC;
+
+ -- reg_strobe_total_count_rx
+ -- copi
+ reg_strobe_total_count_rx_awaddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
+ reg_strobe_total_count_rx_awprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
+ reg_strobe_total_count_rx_awvalid : IN STD_LOGIC;
+ reg_strobe_total_count_rx_wdata : IN STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
+ reg_strobe_total_count_rx_wstrb : IN STD_LOGIC_VECTOR((c_axi4_lite_data_w/c_byte_w)-1 downto 0);
+ reg_strobe_total_count_rx_wvalid : IN STD_LOGIC;
+ reg_strobe_total_count_rx_bready : IN STD_LOGIC;
+ reg_strobe_total_count_rx_araddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
+ reg_strobe_total_count_rx_arprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
+ reg_strobe_total_count_rx_arvalid : IN STD_LOGIC;
+ reg_strobe_total_count_rx_rready : IN STD_LOGIC;
+ -- cipo
+ reg_strobe_total_count_rx_awready : OUT STD_LOGIC;
+ reg_strobe_total_count_rx_wready : OUT STD_LOGIC;
+ reg_strobe_total_count_rx_bresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
+ reg_strobe_total_count_rx_bvalid : OUT STD_LOGIC;
+ reg_strobe_total_count_rx_arready : OUT STD_LOGIC;
+ reg_strobe_total_count_rx_rdata : OUT STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
+ reg_strobe_total_count_rx_rresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
+ reg_strobe_total_count_rx_rvalid : OUT STD_LOGIC
+
+ );
+END eth_tester_axi4_wrapper;
+
+
+ARCHITECTURE str OF eth_tester_axi4_wrapper IS
+ SIGNAL rx_udp_sosi_arr : t_dp_sosi_arr(0 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL rx_udp_siso_arr : t_dp_siso_arr(0 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ SIGNAL tx_udp_sosi_arr : t_dp_sosi_arr(0 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL tx_udp_siso_arr : t_dp_siso_arr(0 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+
+ SIGNAL rx_udp_axi4_sosi : t_axi4_sosi := c_axi4_sosi_rst;
+ SIGNAL rx_udp_axi4_siso : t_axi4_siso := c_axi4_siso_rst;
+ SIGNAL tx_udp_axi4_sosi : t_axi4_sosi := c_axi4_sosi_rst;
+ SIGNAL tx_udp_axi4_siso : t_axi4_siso := c_axi4_siso_rst;
+
+ SIGNAL reg_bg_ctrl_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bg_ctrl_cipo : t_mem_cipo;
+ SIGNAL reg_hdr_dat_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_hdr_dat_cipo : t_mem_cipo;
+ SIGNAL reg_bsn_monitor_v2_tx_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_tx_cipo : t_mem_cipo;
+ SIGNAL reg_strobe_total_count_tx_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_strobe_total_count_tx_cipo : t_mem_cipo;
+
+ SIGNAL reg_bsn_monitor_v2_rx_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_rx_cipo : t_mem_cipo;
+ SIGNAL reg_strobe_total_count_rx_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_strobe_total_count_rx_cipo : t_mem_cipo;
+
+
+ SIGNAL reg_bg_ctrl_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
+ SIGNAL reg_bg_ctrl_axi4_cipo : t_axi4_lite_cipo;
+ SIGNAL reg_hdr_dat_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
+ SIGNAL reg_hdr_dat_axi4_cipo : t_axi4_lite_cipo;
+ SIGNAL reg_bsn_monitor_v2_tx_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_tx_axi4_cipo : t_axi4_lite_cipo;
+ SIGNAL reg_strobe_total_count_tx_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
+ SIGNAL reg_strobe_total_count_tx_axi4_cipo : t_axi4_lite_cipo;
+
+ SIGNAL reg_bsn_monitor_v2_rx_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_rx_axi4_cipo : t_axi4_lite_cipo;
+ SIGNAL reg_strobe_total_count_rx_axi4_copi : t_axi4_lite_copi := c_axi4_lite_copi_rst;
+ SIGNAL reg_strobe_total_count_rx_axi4_cipo : t_axi4_lite_cipo;
+
+ SIGNAL mm_rst : STD_LOGIC := '0';
+ SIGNAL st_rst : STD_LOGIC := '0';
+
+BEGIN
+
+ u_eth_tester : ENTITY work.eth_tester
+ GENERIC MAP (
+ g_remove_crc => FALSE
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+ st_pps => st_pps,
+
+ -- UDP transmit interface
+ eth_src_mac => eth_src_mac,
+ ip_src_addr => ip_src_addr,
+ udp_src_port => udp_src_port,
+
+ tx_fifo_rd_emp_arr => tx_fifo_rd_emp_arr,
+
+ tx_udp_sosi_arr => tx_udp_sosi_arr,
+ tx_udp_siso_arr => tx_udp_siso_arr,
+
+ -- UDP receive interface
+ rx_udp_sosi_arr => rx_udp_sosi_arr,
+
+ -- Memory Mapped Slaves (one per stream)
+ reg_bg_ctrl_copi => reg_bg_ctrl_copi,
+ reg_bg_ctrl_cipo => reg_bg_ctrl_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_copi,
+ reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_cipo,
+ reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_copi,
+ reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_cipo,
+
+ reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_copi,
+ reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_cipo,
+ reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_copi,
+ reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
+ );
+
+ -- DP to AXI4
+ u_axi4_tx_udp : ENTITY axi4_lib.axi4_stream_dp_bridge
+ GENERIC MAP (
+ g_axi4_rl => 0,
+ g_dp_rl => 1,
+ g_active_low_rst => TRUE
+ )
+ PORT MAP (
+ in_clk => st_clk,
+ in_rst => aresetn,
+
+ dp_rst => st_rst,
+
+ dp_in_sosi => tx_udp_sosi_arr(0),
+ dp_in_siso => tx_udp_siso_arr(0),
+
+ axi4_out_sosi => tx_udp_axi4_sosi,
+ axi4_out_siso => tx_udp_axi4_siso
+ );
+
+ u_axi4_rx_udp : ENTITY axi4_lib.axi4_stream_dp_bridge
+ GENERIC MAP (
+ g_axi4_rl => 0,
+ g_dp_rl => 1,
+ g_active_low_rst => TRUE
+ )
+ PORT MAP (
+ in_clk => st_clk,
+ in_rst => aresetn,
+
+ axi4_in_sosi => rx_udp_axi4_sosi,
+ axi4_in_siso => rx_udp_axi4_siso,
+
+ dp_out_sosi => rx_udp_sosi_arr(0),
+ dp_out_siso => rx_udp_siso_arr(0)
+ );
+
+ -- AXI4 to MM
+ u_axi4_reg_bg_ctrl : ENTITY axi4_lib.axi4_lite_mm_bridge
+ GENERIC MAP (
+ g_active_low_rst => TRUE
+ )
+ PORT MAP (
+ in_clk => mm_clk,
+ in_rst => aresetn,
+
+ mm_rst => mm_rst,
+
+ axi4_in_copi => reg_bg_ctrl_axi4_copi,
+ axi4_in_cipo => reg_bg_ctrl_axi4_cipo,
+
+ mm_out_copi => reg_bg_ctrl_copi,
+ mm_out_cipo => reg_bg_ctrl_cipo
+ );
+
+ u_axi4_reg_hdr_dat : ENTITY axi4_lib.axi4_lite_mm_bridge
+ GENERIC MAP (
+ g_active_low_rst => TRUE
+ )
+ PORT MAP (
+ in_clk => mm_clk,
+ in_rst => aresetn,
+
+ axi4_in_copi => reg_hdr_dat_axi4_copi,
+ axi4_in_cipo => reg_hdr_dat_axi4_cipo,
+
+ mm_out_copi => reg_hdr_dat_copi,
+ mm_out_cipo => reg_hdr_dat_cipo
+ );
+
+
+ u_axi4_reg_bsn_monitor_v2_tx : ENTITY axi4_lib.axi4_lite_mm_bridge
+ GENERIC MAP (
+ g_active_low_rst => TRUE
+ )
+ PORT MAP (
+ in_clk => mm_clk,
+ in_rst => aresetn,
+
+ axi4_in_copi => reg_bsn_monitor_v2_tx_axi4_copi,
+ axi4_in_cipo => reg_bsn_monitor_v2_tx_axi4_cipo,
+
+ mm_out_copi => reg_bsn_monitor_v2_tx_copi,
+ mm_out_cipo => reg_bsn_monitor_v2_tx_cipo
+ );
+
+
+ u_axi4_reg_strobe_total_count_tx : ENTITY axi4_lib.axi4_lite_mm_bridge
+ GENERIC MAP (
+ g_active_low_rst => TRUE
+ )
+ PORT MAP (
+ in_clk => mm_clk,
+ in_rst => aresetn,
+
+ axi4_in_copi => reg_strobe_total_count_tx_axi4_copi,
+ axi4_in_cipo => reg_strobe_total_count_tx_axi4_cipo,
+
+ mm_out_copi => reg_strobe_total_count_tx_copi,
+ mm_out_cipo => reg_strobe_total_count_tx_cipo
+ );
+
+
+ u_axi4_reg_bsn_monitor_v2_rx : ENTITY axi4_lib.axi4_lite_mm_bridge
+ GENERIC MAP (
+ g_active_low_rst => TRUE
+ )
+ PORT MAP (
+ in_clk => mm_clk,
+ in_rst => aresetn,
+
+ axi4_in_copi => reg_bsn_monitor_v2_rx_axi4_copi,
+ axi4_in_cipo => reg_bsn_monitor_v2_rx_axi4_cipo,
+
+ mm_out_copi => reg_bsn_monitor_v2_rx_copi,
+ mm_out_cipo => reg_bsn_monitor_v2_rx_cipo
+ );
+
+ u_axi4_reg_strobe_total_count_rx : ENTITY axi4_lib.axi4_lite_mm_bridge
+ GENERIC MAP (
+ g_active_low_rst => TRUE
+ )
+ PORT MAP (
+ in_clk => mm_clk,
+ in_rst => aresetn,
+
+ axi4_in_copi => reg_strobe_total_count_rx_axi4_copi,
+ axi4_in_cipo => reg_strobe_total_count_rx_axi4_cipo,
+
+ mm_out_copi => reg_strobe_total_count_rx_copi,
+ mm_out_cipo => reg_strobe_total_count_rx_cipo
+ );
+
+ -- Wire Records to IN/OUT ports.
+
+ -- tx_udp
+ tx_udp_axi4_siso.tready <= tx_udp_tready;
+
+ tx_udp_tvalid <= tx_udp_axi4_sosi.tvalid;
+ tx_udp_tdata <= tx_udp_axi4_sosi.tdata;
+ tx_udp_tstrb <= tx_udp_axi4_sosi.tstrb;
+ tx_udp_tkeep <= tx_udp_axi4_sosi.tkeep;
+ tx_udp_tlast <= tx_udp_axi4_sosi.tlast;
+ tx_udp_tid <= tx_udp_axi4_sosi.tid;
+ tx_udp_tdest <= tx_udp_axi4_sosi.tdest;
+ tx_udp_tuser <= tx_udp_axi4_sosi.tuser;
+
+ -- rx_udp
+ rx_udp_tready <= rx_udp_axi4_siso.tready;
+
+ rx_udp_axi4_sosi.tvalid <= rx_udp_tvalid;
+ rx_udp_axi4_sosi.tdata <= rx_udp_tdata;
+ rx_udp_axi4_sosi.tstrb <= rx_udp_tstrb;
+ rx_udp_axi4_sosi.tkeep <= rx_udp_tkeep;
+ rx_udp_axi4_sosi.tlast <= rx_udp_tlast;
+ rx_udp_axi4_sosi.tid <= rx_udp_tid;
+ rx_udp_axi4_sosi.tdest <= rx_udp_tdest;
+ rx_udp_axi4_sosi.tuser <= rx_udp_tuser;
+
+ -- reg_bg_ctrl
+ -- copi
+ reg_bg_ctrl_axi4_copi.awaddr <= reg_bg_ctrl_awaddr;
+ reg_bg_ctrl_axi4_copi.awprot <= reg_bg_ctrl_awprot;
+ reg_bg_ctrl_axi4_copi.awvalid <= reg_bg_ctrl_awvalid;
+ reg_bg_ctrl_axi4_copi.wdata <= reg_bg_ctrl_wdata;
+ reg_bg_ctrl_axi4_copi.wstrb <= reg_bg_ctrl_wstrb;
+ reg_bg_ctrl_axi4_copi.wvalid <= reg_bg_ctrl_wvalid;
+ reg_bg_ctrl_axi4_copi.bready <= reg_bg_ctrl_bready;
+ reg_bg_ctrl_axi4_copi.araddr <= reg_bg_ctrl_araddr;
+ reg_bg_ctrl_axi4_copi.arprot <= reg_bg_ctrl_arprot;
+ reg_bg_ctrl_axi4_copi.arvalid <= reg_bg_ctrl_arvalid;
+ reg_bg_ctrl_axi4_copi.rready <= reg_bg_ctrl_rready;
+ -- cipo
+ reg_bg_ctrl_awready <= reg_bg_ctrl_axi4_cipo.awready;
+ reg_bg_ctrl_wready <= reg_bg_ctrl_axi4_cipo.wready;
+ reg_bg_ctrl_bresp <= reg_bg_ctrl_axi4_cipo.bresp;
+ reg_bg_ctrl_bvalid <= reg_bg_ctrl_axi4_cipo.bvalid;
+ reg_bg_ctrl_arready <= reg_bg_ctrl_axi4_cipo.arready;
+ reg_bg_ctrl_rdata <= reg_bg_ctrl_axi4_cipo.rdata;
+ reg_bg_ctrl_rresp <= reg_bg_ctrl_axi4_cipo.rresp;
+ reg_bg_ctrl_rvalid <= reg_bg_ctrl_axi4_cipo.rvalid;
+
+ -- reg_hdr_dat
+ -- copi
+ reg_hdr_dat_axi4_copi.awaddr <= reg_hdr_dat_awaddr;
+ reg_hdr_dat_axi4_copi.awprot <= reg_hdr_dat_awprot;
+ reg_hdr_dat_axi4_copi.awvalid <= reg_hdr_dat_awvalid;
+ reg_hdr_dat_axi4_copi.wdata <= reg_hdr_dat_wdata;
+ reg_hdr_dat_axi4_copi.wstrb <= reg_hdr_dat_wstrb;
+ reg_hdr_dat_axi4_copi.wvalid <= reg_hdr_dat_wvalid;
+ reg_hdr_dat_axi4_copi.bready <= reg_hdr_dat_bready;
+ reg_hdr_dat_axi4_copi.araddr <= reg_hdr_dat_araddr;
+ reg_hdr_dat_axi4_copi.arprot <= reg_hdr_dat_arprot;
+ reg_hdr_dat_axi4_copi.arvalid <= reg_hdr_dat_arvalid;
+ reg_hdr_dat_axi4_copi.rready <= reg_hdr_dat_rready;
+ -- cipo
+ reg_hdr_dat_awready <= reg_hdr_dat_axi4_cipo.awready;
+ reg_hdr_dat_wready <= reg_hdr_dat_axi4_cipo.wready;
+ reg_hdr_dat_bresp <= reg_hdr_dat_axi4_cipo.bresp;
+ reg_hdr_dat_bvalid <= reg_hdr_dat_axi4_cipo.bvalid;
+ reg_hdr_dat_arready <= reg_hdr_dat_axi4_cipo.arready;
+ reg_hdr_dat_rdata <= reg_hdr_dat_axi4_cipo.rdata;
+ reg_hdr_dat_rresp <= reg_hdr_dat_axi4_cipo.rresp;
+ reg_hdr_dat_rvalid <= reg_hdr_dat_axi4_cipo.rvalid;
+
+ -- reg_bsn_monitor_v2_tx
+ -- copi
+ reg_bsn_monitor_v2_tx_axi4_copi.awaddr <= reg_bsn_monitor_v2_tx_awaddr;
+ reg_bsn_monitor_v2_tx_axi4_copi.awprot <= reg_bsn_monitor_v2_tx_awprot;
+ reg_bsn_monitor_v2_tx_axi4_copi.awvalid <= reg_bsn_monitor_v2_tx_awvalid;
+ reg_bsn_monitor_v2_tx_axi4_copi.wdata <= reg_bsn_monitor_v2_tx_wdata;
+ reg_bsn_monitor_v2_tx_axi4_copi.wstrb <= reg_bsn_monitor_v2_tx_wstrb;
+ reg_bsn_monitor_v2_tx_axi4_copi.wvalid <= reg_bsn_monitor_v2_tx_wvalid;
+ reg_bsn_monitor_v2_tx_axi4_copi.bready <= reg_bsn_monitor_v2_tx_bready;
+ reg_bsn_monitor_v2_tx_axi4_copi.araddr <= reg_bsn_monitor_v2_tx_araddr;
+ reg_bsn_monitor_v2_tx_axi4_copi.arprot <= reg_bsn_monitor_v2_tx_arprot;
+ reg_bsn_monitor_v2_tx_axi4_copi.arvalid <= reg_bsn_monitor_v2_tx_arvalid;
+ reg_bsn_monitor_v2_tx_axi4_copi.rready <= reg_bsn_monitor_v2_tx_rready;
+ -- cipo
+ reg_bsn_monitor_v2_tx_awready <= reg_bsn_monitor_v2_tx_axi4_cipo.awready;
+ reg_bsn_monitor_v2_tx_wready <= reg_bsn_monitor_v2_tx_axi4_cipo.wready;
+ reg_bsn_monitor_v2_tx_bresp <= reg_bsn_monitor_v2_tx_axi4_cipo.bresp;
+ reg_bsn_monitor_v2_tx_bvalid <= reg_bsn_monitor_v2_tx_axi4_cipo.bvalid;
+ reg_bsn_monitor_v2_tx_arready <= reg_bsn_monitor_v2_tx_axi4_cipo.arready;
+ reg_bsn_monitor_v2_tx_rdata <= reg_bsn_monitor_v2_tx_axi4_cipo.rdata;
+ reg_bsn_monitor_v2_tx_rresp <= reg_bsn_monitor_v2_tx_axi4_cipo.rresp;
+ reg_bsn_monitor_v2_tx_rvalid <= reg_bsn_monitor_v2_tx_axi4_cipo.rvalid;
+
+ -- reg_strobe_total_count_tx
+ -- copi
+ reg_strobe_total_count_tx_axi4_copi.awaddr <= reg_strobe_total_count_tx_awaddr;
+ reg_strobe_total_count_tx_axi4_copi.awprot <= reg_strobe_total_count_tx_awprot;
+ reg_strobe_total_count_tx_axi4_copi.awvalid <= reg_strobe_total_count_tx_awvalid;
+ reg_strobe_total_count_tx_axi4_copi.wdata <= reg_strobe_total_count_tx_wdata;
+ reg_strobe_total_count_tx_axi4_copi.wstrb <= reg_strobe_total_count_tx_wstrb;
+ reg_strobe_total_count_tx_axi4_copi.wvalid <= reg_strobe_total_count_tx_wvalid;
+ reg_strobe_total_count_tx_axi4_copi.bready <= reg_strobe_total_count_tx_bready;
+ reg_strobe_total_count_tx_axi4_copi.araddr <= reg_strobe_total_count_tx_araddr;
+ reg_strobe_total_count_tx_axi4_copi.arprot <= reg_strobe_total_count_tx_arprot;
+ reg_strobe_total_count_tx_axi4_copi.arvalid <= reg_strobe_total_count_tx_arvalid;
+ reg_strobe_total_count_tx_axi4_copi.rready <= reg_strobe_total_count_tx_rready;
+ -- cipo
+ reg_strobe_total_count_tx_awready <= reg_strobe_total_count_tx_axi4_cipo.awready;
+ reg_strobe_total_count_tx_wready <= reg_strobe_total_count_tx_axi4_cipo.wready;
+ reg_strobe_total_count_tx_bresp <= reg_strobe_total_count_tx_axi4_cipo.bresp;
+ reg_strobe_total_count_tx_bvalid <= reg_strobe_total_count_tx_axi4_cipo.bvalid;
+ reg_strobe_total_count_tx_arready <= reg_strobe_total_count_tx_axi4_cipo.arready;
+ reg_strobe_total_count_tx_rdata <= reg_strobe_total_count_tx_axi4_cipo.rdata;
+ reg_strobe_total_count_tx_rresp <= reg_strobe_total_count_tx_axi4_cipo.rresp;
+ reg_strobe_total_count_tx_rvalid <= reg_strobe_total_count_tx_axi4_cipo.rvalid;
+
+ -- reg_bsn_monitor_v2_rx
+ -- copi
+ reg_bsn_monitor_v2_rx_axi4_copi.awaddr <= reg_bsn_monitor_v2_rx_awaddr;
+ reg_bsn_monitor_v2_rx_axi4_copi.awprot <= reg_bsn_monitor_v2_rx_awprot;
+ reg_bsn_monitor_v2_rx_axi4_copi.awvalid <= reg_bsn_monitor_v2_rx_awvalid;
+ reg_bsn_monitor_v2_rx_axi4_copi.wdata <= reg_bsn_monitor_v2_rx_wdata;
+ reg_bsn_monitor_v2_rx_axi4_copi.wstrb <= reg_bsn_monitor_v2_rx_wstrb;
+ reg_bsn_monitor_v2_rx_axi4_copi.wvalid <= reg_bsn_monitor_v2_rx_wvalid;
+ reg_bsn_monitor_v2_rx_axi4_copi.bready <= reg_bsn_monitor_v2_rx_bready;
+ reg_bsn_monitor_v2_rx_axi4_copi.araddr <= reg_bsn_monitor_v2_rx_araddr;
+ reg_bsn_monitor_v2_rx_axi4_copi.arprot <= reg_bsn_monitor_v2_rx_arprot;
+ reg_bsn_monitor_v2_rx_axi4_copi.arvalid <= reg_bsn_monitor_v2_rx_arvalid;
+ reg_bsn_monitor_v2_rx_axi4_copi.rready <= reg_bsn_monitor_v2_rx_rready;
+ -- cipo
+ reg_bsn_monitor_v2_rx_awready <= reg_bsn_monitor_v2_rx_axi4_cipo.awready;
+ reg_bsn_monitor_v2_rx_wready <= reg_bsn_monitor_v2_rx_axi4_cipo.wready;
+ reg_bsn_monitor_v2_rx_bresp <= reg_bsn_monitor_v2_rx_axi4_cipo.bresp;
+ reg_bsn_monitor_v2_rx_bvalid <= reg_bsn_monitor_v2_rx_axi4_cipo.bvalid;
+ reg_bsn_monitor_v2_rx_arready <= reg_bsn_monitor_v2_rx_axi4_cipo.arready;
+ reg_bsn_monitor_v2_rx_rdata <= reg_bsn_monitor_v2_rx_axi4_cipo.rdata;
+ reg_bsn_monitor_v2_rx_rresp <= reg_bsn_monitor_v2_rx_axi4_cipo.rresp;
+ reg_bsn_monitor_v2_rx_rvalid <= reg_bsn_monitor_v2_rx_axi4_cipo.rvalid;
+
+ -- reg_strobe_total_count_rx
+ -- copi
+ reg_strobe_total_count_rx_axi4_copi.awaddr <= reg_strobe_total_count_rx_awaddr;
+ reg_strobe_total_count_rx_axi4_copi.awprot <= reg_strobe_total_count_rx_awprot;
+ reg_strobe_total_count_rx_axi4_copi.awvalid <= reg_strobe_total_count_rx_awvalid;
+ reg_strobe_total_count_rx_axi4_copi.wdata <= reg_strobe_total_count_rx_wdata;
+ reg_strobe_total_count_rx_axi4_copi.wstrb <= reg_strobe_total_count_rx_wstrb;
+ reg_strobe_total_count_rx_axi4_copi.wvalid <= reg_strobe_total_count_rx_wvalid;
+ reg_strobe_total_count_rx_axi4_copi.bready <= reg_strobe_total_count_rx_bready;
+ reg_strobe_total_count_rx_axi4_copi.araddr <= reg_strobe_total_count_rx_araddr;
+ reg_strobe_total_count_rx_axi4_copi.arprot <= reg_strobe_total_count_rx_arprot;
+ reg_strobe_total_count_rx_axi4_copi.arvalid <= reg_strobe_total_count_rx_arvalid;
+ reg_strobe_total_count_rx_axi4_copi.rready <= reg_strobe_total_count_rx_rready;
+ -- cipo
+ reg_strobe_total_count_rx_awready <= reg_strobe_total_count_rx_axi4_cipo.awready;
+ reg_strobe_total_count_rx_wready <= reg_strobe_total_count_rx_axi4_cipo.wready;
+ reg_strobe_total_count_rx_bresp <= reg_strobe_total_count_rx_axi4_cipo.bresp;
+ reg_strobe_total_count_rx_bvalid <= reg_strobe_total_count_rx_axi4_cipo.bvalid;
+ reg_strobe_total_count_rx_arready <= reg_strobe_total_count_rx_axi4_cipo.arready;
+ reg_strobe_total_count_rx_rdata <= reg_strobe_total_count_rx_axi4_cipo.rdata;
+ reg_strobe_total_count_rx_rresp <= reg_strobe_total_count_rx_axi4_cipo.rresp;
+ reg_strobe_total_count_rx_rvalid <= reg_strobe_total_count_rx_axi4_cipo.rvalid;
+
+END str;
--
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