diff --git a/tools/oneclick/base/mmm_gen.py b/tools/oneclick/base/mmm_gen.py
index 0a2fa62429e0d404dc940ef6c844e32127aeb036..3ff135e23a2464853782d6162039069bdeaebf15 100644
--- a/tools/oneclick/base/mmm_gen.py
+++ b/tools/oneclick/base/mmm_gen.py
@@ -32,7 +32,7 @@ import os
import os.path
import shutil
import argparse
-import entity
+import vhdl
import hdl_config
s_header = """--------------------------------------------------------------------------------
@@ -88,11 +88,6 @@ s_fileio_start = "--------------------------------------------------------------
----------------------------------------------------------------------------\n\
gen_mm_file_io : IF g_sim = TRUE GENERATE\n"
-s_fileio_mm_clk = "mm_locked <= '0', '1' AFTER c_mm_clk_period*5;\n\
-i_mm_clk <= NOT i_mm_clk AFTER c_mm_clk_period/2;\n"
-
-s_fileio_dp_clk = "i_dp_clk <= NOT i_dp_clk AFTER c_dp_clk_period/2;\n"
-
s_fileio_eth_init = "----------------------------------------------------------------------------\n\
-- 1GbE setup sequence normally performed by unb_os@NIOS\n\
----------------------------------------------------------------------------\n\
@@ -141,9 +136,12 @@ peripherals_vhdl2python = { 'reg_wdi' : "reg_wdi",\
'reg_ppsh' : "pio_pps",\
'eth1g_reg' : "avs_eth_0_mms_reg"}
-class QsysEntity(entity.Entity):
+class QsysEntity(vhdl.Entity):
+
+ def __init__(self, name= ""):
+ vhdl.Entity.__init__(self, name)
- def make_qsys_instance(self, mmm_conf):
+ def make_qsys_instance_string(self, mmm_conf):
s_start = "u_" + self.name + " : " + self.name + "\n" + self.s_port_map_start
self.portNames.sort()
s_port_connects = ""
@@ -159,6 +157,8 @@ class QsysEntity(entity.Entity):
s_connect = s_reg_name + "_mosi.address("
span = self.find_span(s_reg_name, mmm_conf.peripherals)
+ if span == 0:
+ sys.exit('Error: No corresponding register in mmm.cfg for QSYS register: ' + s_reg_name)
if span == 1:
s_connect = s_connect + "0),"
else:
@@ -251,16 +251,21 @@ class QsysEntity(entity.Entity):
return new_name
def find_span(self, name, peripherals):
+ """Function find_span calculates te address span based on the values in column 1 and 2 of a peripheral entry.
+ Column 1 (C1) defines the number of instances.
+ Column 2 (C2) defines the address span of single instance.
+ The total address span is ceil_log2(C1) + C2.
+ """
span = 0
for i in range(len(peripherals)):
if peripherals[i][0] == name:
- span = int(peripherals[i][2])
+ span = cm.ceil_log2(int(peripherals[i][1])) + int(peripherals[i][2])
return span
-class MmmEntity(entity.Entity):
+class MmmEntity(vhdl.Entity):
def __init__(self, mmm_conf):
- entity.Entity.__init__(self, mmm_conf.mmmName)
+ vhdl.Entity.__init__(self, mmm_conf.mmmName)
# Add default generics
self.add_generic( "g_sim", "BOOLEAN", "FALSE")
self.add_generic( "g_sim_unb_nr", "NATURAL", "0")
@@ -272,7 +277,7 @@ class MmmEntity(entity.Entity):
self.add_port("mm_rst", "IN", "STD_LOGIC", "\'1\'")
# Add UNB1 board peripherals
- for s in mmm_conf.unb1_board_peripherals:
+ for s in mmm_conf.peripherals:
# Extra signals for ethernet peripheral
if(s[0] == "eth1g_ram"):
@@ -284,21 +289,9 @@ class MmmEntity(entity.Entity):
if(s[0] == "reg_wdi"):
self.add_port("pout_wdi", "OUT", "STD_LOGIC", "\'1\'")
- if(int(s[1]) == 1):
- self.add_port(s[0] + "_mosi", "OUT", "t_mem_mosi")
- self.add_port(s[0] + "_miso", "IN", "t_mem_miso", "c_mem_miso_rst")
- elif(int(s[1]) > 1):
- self.add_port(s[0] + "_mosi_arr", "OUT", "t_mem_mosi_arr(" + str(int(s[1])-1) + " DOWNTO 0)")
- self.add_port(s[0] + "_miso_arr", "IN", "t_mem_miso_arr(" + str(int(s[1])-1) + " DOWNTO 0)", "(others => c_mem_miso_rst)")
+ self.add_port(s[0] + "_mosi", "OUT", "t_mem_mosi")
+ self.add_port(s[0] + "_miso", "IN", "t_mem_miso", "c_mem_miso_rst")
- # Add custom peripherals
- for s in mmm_conf.custom_peripherals:
- if(int(s[1]) == 1):
- self.add_port(s[0] + "_mosi", "OUT", "t_mem_mosi")
- self.add_port(s[0] + "_miso", "IN", "t_mem_miso", "c_mem_miso_rst")
- elif(int(s[1]) > 1):
- self.add_port(s[0] + "_mosi_arr", "OUT", "t_mem_mosi_arr(" + str(int(s[1])-1) + " DOWNTO 0)")
- self.add_port(s[0] + "_miso_arr", "IN", "t_mem_miso_arr(" + str(int(s[1])-1) + " DOWNTO 0)", "(others => c_mem_miso_rst)")
class MmmGenerate:
@@ -317,29 +310,34 @@ class MmmGenerate:
name = self.mmm.get_key_value('mmm_name', d)
if name == mmmLibraryName:
self.mmm.remove_all_but_the_dict_from_list(d)
-
+
+ self.board_select = self.mmm.get_key_values('board_select')
+
+ if self.board_select == 'unb1':
+ self.board_peripherals_path = mmmRootDir + "/boards/uniboard1/libraries/unb1_board/unb1_board_peripherals.cfg"
+ elif self.board_select == 'unb2':
+ self.board_peripherals_path = mmmRootDir + "/boards/uniboard2/libraries/unb2_board/unb2_board_peripherals.cfg"
+
+ self.board_peripherals_dict = self.mmm.read_dict_file(self.board_peripherals_path , ' ')
+ self.board_peripherals = self.chunks(self.mmm.get_key_values('board_peripherals', dicts=self.board_peripherals_dict).split(), 3)
+
# Keep list of HDL library names
self.designName = self.mmm.get_key_values('mmm_name')
self.mmmName = "mmm_" + self.mmm.get_key_values('mmm_name')
- self.VhdlFilePath = self.mmm.filePaths[0] + '/../vhdl/'
+ self.VhdlOutputPath = cm.expand_file_path_name(self.mmm.get_key_values('vhdl_output_path'), self.mmm.filePaths[0])
self.VhdlFileName = self.mmmName + '.vhd'
self.QsysName = "qsys_" + self.designName
self.QsysFileName = self.QsysName + '.vhd'
self.input_clks = self.mmm.get_key_values('input_clks')
- self.output_clks = self.mmm.get_key_values('output_clks')
- self.unb1_board_peripherals_temp = self.mmm.get_key_values('unb1_board_peripherals').split()
- self.unb1_board_peripherals = self.chunks(self.unb1_board_peripherals_temp, 3)
self.custom_peripherals_temp = self.mmm.get_key_values('custom_peripherals').split()
self.custom_peripherals = self.chunks(self.custom_peripherals_temp, 3)
- self.peripherals = self.unb1_board_peripherals + self.custom_peripherals
- self.mm_clk_period = self.mmm.get_key_values('sim_mm_clk_period')
- self.dp_clk_period = self.mmm.get_key_values('sim_dp_clk_period')
+ self.peripherals = self.board_peripherals + self.custom_peripherals
def chunks(self, l, n):
n = max(1, n)
return [l[i:i + n] for i in range(0, len(l), n)]
- def make_mm_file_io_entry(self, peripheral):
+ def make_mm_file_io_entry_string(self, peripheral):
if peripheral[0] in peripherals_vhdl2python:
python_name = peripherals_vhdl2python[peripheral[0]].upper()
else:
@@ -368,7 +366,6 @@ if __name__ == '__main__':
sys.exit(1)
toolFileName = 'hdltool_' + arg_toolset + '.cfg'
-
designName = arg_library # "unb1_terminal_bg_mesh_db"
libRootDir = 'RADIOHDL'
mmmRootDir = os.environ['RADIOHDL']
@@ -380,70 +377,69 @@ if __name__ == '__main__':
QsysBuildDir = os.environ['RADIOHDL']+'/build/' + arg_toolset + '/quartus/' + designName +'/qsys_' + designName + '/simulation/'
###################################
- # Define the entity definitions
+ # Define the entity and architecture
###################################
- ent_qsys = QsysEntity()
ent_mmm = MmmEntity(mmm_conf)
- ent_mm_file = entity.Entity()
-
+ ent_qsys = QsysEntity()
+ ent_mm_file = vhdl.Entity()
+ arch_mmm = vhdl.Architecture(archName = "str", entityName = ent_mmm.name)
+
###################################
# Read the Qsys entity definition
###################################
ent_qsys.read_entity_from_file(QsysBuildDir, mmm_conf.QsysName)
ent_qsys.replace_std_logic_vector_with_std_logic()
- s_qsys_comp = ent_qsys.make_component_definition(indend = 0)
###################################
# Read the mm_file entity definition
###################################
ent_mm_file.read_entity_from_file(mm_dir, mm_file)
- s_mm_file_comp = ent_mm_file.make_component_definition(indend = 0)
###################################
# Make the entity definition and a
# commented instantiation.
###################################
- s_entity = ent_mmm.make_entity_definition()
- s_instantiation = ent_mmm.comment(ent_mmm.make_instantiation())
+ s_entity = ent_mmm.make_entity_definition_string()
+ s_instantiation = ent_mmm.comment(ent_mmm.make_instantiation_string())
###################################
# Make the architecture header
- ###################################
- s_arch_start = "ARCHITECTURE str OF "+ str(mmm_conf.mmmName) + " IS\n\n"
- s_arch_constants = ""
- s_arch_constants = s_arch_constants + "CONSTANT c_mm_clk_period : TIME := " + str(mmm_conf.mm_clk_period) + " ns;\n"
- s_arch_constants = s_arch_constants + "CONSTANT c_dp_clk_period : TIME := " + str(mmm_conf.dp_clk_period) + " ns;\n"
- s_arch_constants = s_arch_constants + "CONSTANT c_sim_node_type : STRING(1 TO 2):= sel_a_b(g_sim_node_nr<4, " + r'"FN", "BN"' + ");\n"
- s_arch_constants = s_arch_constants + "CONSTANT c_sim_node_nr : NATURAL := sel_a_b(c_sim_node_type=" + r'"BN"' +", g_sim_node_nr-4, g_sim_node_nr);\n"
-
- s_arch_constants = s_arch_constants + "CONSTANT c_sim_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X\"00228608\" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);"
- s_arch_constants = s_arch_constants + "CONSTANT c_sim_eth_control_rx_en : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en;"
-
- s_arch_signals = ""
- s_arch_signals = s_arch_signals + "SIGNAL sim_eth_mm_bus_switch : STD_LOGIC;\n"
- s_arch_signals = s_arch_signals + "SIGNAL sim_eth_psc_access : STD_LOGIC;\n"
- s_arch_signals = s_arch_signals + "SIGNAL i_eth1g_reg_mosi : t_mem_mosi;\n"
- s_arch_signals = s_arch_signals + "SIGNAL i_eth1g_reg_miso : t_mem_miso;\n"
- s_arch_signals = s_arch_signals + "SIGNAL sim_eth1g_reg_mosi : t_mem_mosi;\n"
+ ###################################
+ arch_constants = [['c_sim_node_type', 'STRING(1 TO 2)', "sel_a_b(g_sim_node_nr<4, " + r'"FN", "BN"' + ")"],
+ ['c_sim_node_nr', 'NATURAL', "sel_a_b(c_sim_node_type=" + r'"BN"' +", g_sim_node_nr-4, g_sim_node_nr)"],
+ ['c_sim_eth_src_mac', "STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE)", 'X\"00228608\" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w)'],
+ ['c_sim_eth_control_rx_en', 'NATURAL', '2**c_eth_mm_reg_control_bi.rx_en']]
+
+ arch_signals = [['sim_eth_mm_bus_switch', 'STD_LOGIC', ''],
+ ['sim_eth_psc_access', 'STD_LOGIC', ''],
+ ['i_eth1g_reg_mosi', 't_mem_mosi', ''],
+ ['i_eth1g_reg_miso', 't_mem_miso', ''],
+ ['sim_eth1g_reg_mosi', 't_mem_mosi', '']]
+
+ for s in arch_constants:
+ arch_mmm.add_constant(s[0], s[1], s[2])
+
+ for s in arch_signals:
+ arch_mmm.add_signal(s[0], s[1], s[2])
+
+ arch_mmm.add_component(ent_mm_file)
+ arch_mmm.add_component(ent_qsys)
- s_arch_components = s_mm_file_comp + s_qsys_comp
- s_arch_header = s_arch_start + ent_qsys.apply_indend(s_arch_constants + "\n" + s_arch_signals + "\n" + s_arch_components, 2)
+ s_arch_header = arch_mmm.make_arch_header_string()
###################################
# Make the architecture content
###################################
s_arch_file = ""
- for s in mmm_conf.unb1_board_peripherals:
- s_arch_file = s_arch_file + mmm_conf.make_mm_file_io_entry(s)
- for s in mmm_conf.custom_peripherals:
- s_arch_file = s_arch_file + mmm_conf.make_mm_file_io_entry(s)
+ for s in mmm_conf.peripherals:
+ s_arch_file = s_arch_file + mmm_conf.make_mm_file_io_entry_string(s)
# Make File I/O master
s_file = s_fileio_start + ent_qsys.apply_indend(s_arch_file + s_fileio_eth_init + s_fileio_poll, 2) + s_end_generate + "\n"
# Make QSYS master
s_master_start = s_master_header + "gen_" + ent_qsys.name + " : IF g_sim = FALSE GENERATE\n"
- s_master = s_master_start + ent_qsys.apply_indend(ent_qsys.make_qsys_instance(mmm_conf), 2) + s_end_generate + "\n"
+ s_master = s_master_start + ent_qsys.apply_indend(ent_qsys.make_qsys_instance_string(mmm_conf), 2) + s_end_generate + "\n"
s_arch_total = s_arch_begin + ent_qsys.apply_indend(s_file + s_master, 2) + s_arch_end
string_elements = [s_header, s_instantiation, s_libraries, s_entity, s_arch_header, s_arch_total ]
@@ -451,7 +447,7 @@ if __name__ == '__main__':
###################################
# Write the whole string to a file
###################################
- fileName = mmm_conf.VhdlFilePath + mmm_conf.VhdlFileName
+ fileName = mmm_conf.VhdlOutputPath + mmm_conf.VhdlFileName
f = file(fileName, "w")
for s in string_elements:
f.write(s)