From 2af82b8de997ec327b5e38417ff135092bf7ee55 Mon Sep 17 00:00:00 2001 From: Reinier van der Walle <walle@astron.nl> Date: Mon, 4 Oct 2021 18:53:14 +0200 Subject: [PATCH] added ring_lane --- libraries/base/ring/src/vhdl/ring_lane.vhd | 178 +++++++++++++++++++++ 1 file changed, 178 insertions(+) create mode 100644 libraries/base/ring/src/vhdl/ring_lane.vhd diff --git a/libraries/base/ring/src/vhdl/ring_lane.vhd b/libraries/base/ring/src/vhdl/ring_lane.vhd new file mode 100644 index 0000000000..b6d9a7bbef --- /dev/null +++ b/libraries/base/ring/src/vhdl/ring_lane.vhd @@ -0,0 +1,178 @@ +------------------------------------------------------------------------------- +-- +-- Copyright 2021 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- +-- Author: R. van der Walle + +-- Purpose: Implement the function of a complete ring lane by combining ring_lane/tx. +-- Description: See https://support.astron.nl/confluence/x/jyu7Ag +-- Remark: +-- . Note that the dp_fifo_fill_eop in dp_block_validate_err cannot handle +-- continues stream of blocks without a gap between blocks the dp_fifo_fill_eop +-- needs 1 cycle to process a block. Streaming without gaps may cause the fifo +-- to overflow. Bursts of blocks can be handled by increasing gvalidate_err_fifo_size. + +------------------------------------------------------------------------------- + +LIBRARY IEEE, common_lib, mm_lib, dp_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE common_lib.common_pkg.ALL; +USE common_lib.common_mem_pkg.ALL; +USE common_lib.common_field_pkg.ALL; +USE dp_lib.dp_stream_pkg.ALL; +USE work.ring_pkg.ALL; + +ENTITY ring_lane IS + GENERIC ( + g_lane_direction : NATURAL := 1; + g_lane_data_w : NATURAL := 64; + g_lane_packet_length : NATURAL := 1024; + g_use_dp_layer : BOOLEAN := TRUE; + g_nof_rx_monitors : NATURAL := 0; + g_nof_tx_monitors : NATURAL := 1; + g_err_bi : NATURAL := 0; -- ring_rx bit index in sosi.err field to set for wrongly sized packets + g_nof_err_counts : NATURAL := 1; -- nof counters to count the set err bits in range sosi.err(g_nof_err_counts-1 DOWNTO 0) + g_validate_err_fifo_size : NATURAL := 1536; -- should be >= g_lane_packet_length + g_bsn_at_sync_check_channel : NATURAL := 1; -- on which channel should the bsn be checked + g_validate_channel : BOOLEAN := TRUE; + g_validate_channel_mode : STRING := ">" + ); + PORT ( + -- Clocks and reset + mm_rst : IN STD_LOGIC; + mm_clk : IN STD_LOGIC; + + dp_clk : IN STD_LOGIC; + dp_rst : IN STD_LOGIC; + + from_lane_sosi : OUT t_dp_sosi; + to_lane_sosi : IN t_dp_sosi; + lane_rx_cable_sosi : IN t_dp_sosi; + lane_rx_board_sosi : IN t_dp_sosi; + lane_tx_cable_sosi : OUT t_dp_sosi; + lane_tx_board_sosi : OUT t_dp_sosi; + bs_sosi : IN t_dp_sosi; + + reg_ring_lane_info_copi : IN t_mem_copi; + reg_ring_lane_info_cipo : OUT t_mem_cipo; + reg_bsn_monitor_v2_ring_rx_copi : IN t_mem_copi; + reg_bsn_monitor_v2_ring_rx_cipo : OUT t_mem_cipo; + reg_bsn_monitor_v2_ring_tx_copi : IN t_mem_copi; + reg_bsn_monitor_v2_ring_tx_cipo : OUT t_mem_cipo; + reg_dp_block_validate_err_copi : IN t_mem_copi; + reg_dp_block_validate_err_cipo : OUT t_mem_cipo; + reg_dp_block_validate_bsn_at_sync_copi : IN t_mem_copi; + reg_dp_block_validate_bsn_at_sync_cipo : OUT t_mem_cipo; + + ref_sync : IN STD_LOGIC; + this_rn : IN STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0); + N_rn : IN STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0) + ); +END ring_lane; + +ARCHITECTURE str OF ring_lane IS + + CONSTANT c_lane_direction : STD_LOGIC := sel_a_b(g_lane_direction, '1', '0'); + SIGNAL lane_info : t_lane_info; + +BEGIN + + u_ring_lane_info : ENTITY work.ring_lane_info + PORT MAP ( + dp_rst => dp_rst, + dp_clk => dp_clk, + + mm_rst => mm_rst, + mm_clk => mm_clk, + + reg_mosi => reg_ring_lane_info_copi, + reg_miso => reg_ring_lane_info_cipo, + + lane_direction => c_lane_direction, + lane_info => lane_info + ); + + + u_ring_rx : ENTITY work.ring_rx + GENERIC MAP ( + g_use_dp_layer => g_use_dp_layer, + g_lane_direction => g_lane_direction, + g_data_w => g_lane_data_w, + g_nof_rx_monitors => g_nof_rx_monitors, + g_err_bi => g_err_bi, + g_block_size => g_lane_packet_length, + g_nof_err_counts => g_nof_err_counts, + g_fifo_size => g_validate_err_fifo_size, + g_check_channel => g_bsn_at_sync_check_channel + ) + PORT MAP ( + mm_rst => mm_rst, + mm_clk => mm_clk, + dp_clk => dp_clk, + dp_rst => dp_rst, + + from_lane_sosi => from_lane_sosi, + lane_rx_cable_sosi => lane_rx_cable_sosi, + lane_rx_board_sosi => lane_rx_board_sosi, + bs_sosi => bs_sosi, + + reg_bsn_monitor_v2_copi => reg_bsn_monitor_v2_ring_rx_copi, + reg_bsn_monitor_v2_cipo => reg_bsn_monitor_v2_ring_rx_cipo, + reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi, + reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo, + reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi, + reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo, + + ref_sync => ref_sync, -- bs_sosi.sync? + rx_select => lane_info.rx_select, + this_rn => this_rn, + N_rn => N_rn + ); + + u_ring_tx : ENTITY work.ring_tx + GENERIC MAP ( + g_use_dp_layer => g_use_dp_layer, + g_lane_direction => g_lane_direction, + g_data_w => g_lane_data_w, + g_nof_tx_monitors => g_nof_tx_monitors, + g_validate_channel=> g_validate_channel, + g_mode => g_validate_channel_mode + ) + PORT MAP ( + mm_rst => mm_rst, + mm_clk => mm_clk, + dp_clk => dp_clk, + dp_rst => dp_rst, + + to_lane_sosi => to_lane_sosi, + lane_tx_cable_sosi => lane_tx_cable_sosi, + lane_tx_board_sosi => lane_tx_board_sosi, + + reg_bsn_monitor_v2_copi => reg_bsn_monitor_v2_ring_tx_copi, + reg_bsn_monitor_v2_cipo => reg_bsn_monitor_v2_ring_tx_cipo, + + tx_select => lane_info.tx_select, + remove_channel => lane_info.transport_nof_hops, + this_rn => this_rn, + N_rn => N_rn + ); + +END str; -- GitLab