From 2abcabfc830fb1dd6e237d393469b6401776f483 Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Tue, 22 Aug 2023 09:56:14 +0200
Subject: [PATCH] added missing file paths

---
 libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl       | 4 ++++
 libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl  | 2 ++
 libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2.tcl  | 2 ++
 libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2a.tcl | 2 ++
 libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl | 4 ++++
 libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl | 4 ++++
 6 files changed, 18 insertions(+)

diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
index 78cfca72bd..5f7d3f0c82 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
@@ -42,6 +42,8 @@ set_fileset_property quartus_synth ENABLE_RELATIVE_INCLUDE_PATHS false
 set_fileset_property quartus_synth ENABLE_FILE_OVERWRITE_MODE false
 add_fileset_file avs2_eth_coe.vhd VHDL PATH avs2_eth_coe.vhd TOP_LEVEL_FILE
 add_fileset_file common_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_pkg.vhd
+add_fileset_file common_str_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_str_pkg.vhd
+add_fileset_file common_field_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_field_pkg.vhd
 add_fileset_file dp_stream_pkg.vhd VHDL PATH ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd
 add_fileset_file tech_tse_pkg.vhd VHDL PATH ../../../../technology/tse/tech_tse_pkg.vhd
 add_fileset_file eth_pkg.vhd VHDL PATH eth_pkg.vhd
@@ -52,6 +54,8 @@ set_fileset_property sim_vhdl ENABLE_RELATIVE_INCLUDE_PATHS false
 set_fileset_property sim_vhdl ENABLE_FILE_OVERWRITE_MODE false
 add_fileset_file avs2_eth_coe.vhd VHDL PATH avs2_eth_coe.vhd
 add_fileset_file common_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_pkg.vhd
+add_fileset_file common_str_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_str_pkg.vhd
+add_fileset_file common_field_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_field_pkg.vhd
 add_fileset_file dp_stream_pkg.vhd VHDL PATH ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd
 add_fileset_file tech_tse_pkg.vhd VHDL PATH ../../../../technology/tse/tech_tse_pkg.vhd
 add_fileset_file eth_pkg.vhd VHDL PATH eth_pkg.vhd
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl
index 9e7b8318d1..9aa4532295 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl
@@ -55,6 +55,8 @@ set_module_property FIX_110_VIP_PATH false
 # |               RadioHDL/trunk/libraries/io/eth/src/vhdl/
 add_file avs2_eth_coe.vhd {SYNTHESIS SIMULATION}
 add_file ../../../../base/common/src/vhdl/common_pkg.vhd {SYNTHESIS SIMULATION}
+add_file ../../../../base/common/src/vhdl/common_str_pkg.vhd {SYNTHESIS SIMULATION}
+add_file ../../../../base/common/src/vhdl/common_field_pkg.vhd {SYNTHESIS SIMULATION}
 add_file ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd {SYNTHESIS SIMULATION}
 add_file ../../../../technology/tse/tech_tse_pkg.vhd {SYNTHESIS SIMULATION}
 add_file eth_pkg.vhd {SYNTHESIS SIMULATION}
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2.tcl
index 9e7b8318d1..9aa4532295 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2.tcl
@@ -55,6 +55,8 @@ set_module_property FIX_110_VIP_PATH false
 # |               RadioHDL/trunk/libraries/io/eth/src/vhdl/
 add_file avs2_eth_coe.vhd {SYNTHESIS SIMULATION}
 add_file ../../../../base/common/src/vhdl/common_pkg.vhd {SYNTHESIS SIMULATION}
+add_file ../../../../base/common/src/vhdl/common_str_pkg.vhd {SYNTHESIS SIMULATION}
+add_file ../../../../base/common/src/vhdl/common_field_pkg.vhd {SYNTHESIS SIMULATION}
 add_file ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd {SYNTHESIS SIMULATION}
 add_file ../../../../technology/tse/tech_tse_pkg.vhd {SYNTHESIS SIMULATION}
 add_file eth_pkg.vhd {SYNTHESIS SIMULATION}
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2a.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2a.tcl
index 9e7b8318d1..9aa4532295 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2a.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2a.tcl
@@ -55,6 +55,8 @@ set_module_property FIX_110_VIP_PATH false
 # |               RadioHDL/trunk/libraries/io/eth/src/vhdl/
 add_file avs2_eth_coe.vhd {SYNTHESIS SIMULATION}
 add_file ../../../../base/common/src/vhdl/common_pkg.vhd {SYNTHESIS SIMULATION}
+add_file ../../../../base/common/src/vhdl/common_str_pkg.vhd {SYNTHESIS SIMULATION}
+add_file ../../../../base/common/src/vhdl/common_field_pkg.vhd {SYNTHESIS SIMULATION}
 add_file ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd {SYNTHESIS SIMULATION}
 add_file ../../../../technology/tse/tech_tse_pkg.vhd {SYNTHESIS SIMULATION}
 add_file eth_pkg.vhd {SYNTHESIS SIMULATION}
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl
index 78cfca72bd..5f7d3f0c82 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl
@@ -42,6 +42,8 @@ set_fileset_property quartus_synth ENABLE_RELATIVE_INCLUDE_PATHS false
 set_fileset_property quartus_synth ENABLE_FILE_OVERWRITE_MODE false
 add_fileset_file avs2_eth_coe.vhd VHDL PATH avs2_eth_coe.vhd TOP_LEVEL_FILE
 add_fileset_file common_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_pkg.vhd
+add_fileset_file common_str_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_str_pkg.vhd
+add_fileset_file common_field_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_field_pkg.vhd
 add_fileset_file dp_stream_pkg.vhd VHDL PATH ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd
 add_fileset_file tech_tse_pkg.vhd VHDL PATH ../../../../technology/tse/tech_tse_pkg.vhd
 add_fileset_file eth_pkg.vhd VHDL PATH eth_pkg.vhd
@@ -52,6 +54,8 @@ set_fileset_property sim_vhdl ENABLE_RELATIVE_INCLUDE_PATHS false
 set_fileset_property sim_vhdl ENABLE_FILE_OVERWRITE_MODE false
 add_fileset_file avs2_eth_coe.vhd VHDL PATH avs2_eth_coe.vhd
 add_fileset_file common_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_pkg.vhd
+add_fileset_file common_str_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_str_pkg.vhd
+add_fileset_file common_field_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_field_pkg.vhd
 add_fileset_file dp_stream_pkg.vhd VHDL PATH ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd
 add_fileset_file tech_tse_pkg.vhd VHDL PATH ../../../../technology/tse/tech_tse_pkg.vhd
 add_fileset_file eth_pkg.vhd VHDL PATH eth_pkg.vhd
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl
index 78cfca72bd..5f7d3f0c82 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl
@@ -42,6 +42,8 @@ set_fileset_property quartus_synth ENABLE_RELATIVE_INCLUDE_PATHS false
 set_fileset_property quartus_synth ENABLE_FILE_OVERWRITE_MODE false
 add_fileset_file avs2_eth_coe.vhd VHDL PATH avs2_eth_coe.vhd TOP_LEVEL_FILE
 add_fileset_file common_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_pkg.vhd
+add_fileset_file common_str_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_str_pkg.vhd
+add_fileset_file common_field_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_field_pkg.vhd
 add_fileset_file dp_stream_pkg.vhd VHDL PATH ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd
 add_fileset_file tech_tse_pkg.vhd VHDL PATH ../../../../technology/tse/tech_tse_pkg.vhd
 add_fileset_file eth_pkg.vhd VHDL PATH eth_pkg.vhd
@@ -52,6 +54,8 @@ set_fileset_property sim_vhdl ENABLE_RELATIVE_INCLUDE_PATHS false
 set_fileset_property sim_vhdl ENABLE_FILE_OVERWRITE_MODE false
 add_fileset_file avs2_eth_coe.vhd VHDL PATH avs2_eth_coe.vhd
 add_fileset_file common_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_pkg.vhd
+add_fileset_file common_str_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_str_pkg.vhd
+add_fileset_file common_field_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_field_pkg.vhd
 add_fileset_file dp_stream_pkg.vhd VHDL PATH ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd
 add_fileset_file tech_tse_pkg.vhd VHDL PATH ../../../../technology/tse/tech_tse_pkg.vhd
 add_fileset_file eth_pkg.vhd VHDL PATH eth_pkg.vhd
-- 
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