diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_tbuf_one/tb_lofar2_unb2c_sdp_station_tbuf_one.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_tbuf_one/tb_lofar2_unb2c_sdp_station_tbuf_one.vhd index bbee27df24723c76d0b29015a0889376ae8d9271..eb5c1cda093d2a3796a355e2a2b59d8381b48bd8 100644 --- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_tbuf_one/tb_lofar2_unb2c_sdp_station_tbuf_one.vhd +++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_tbuf_one/tb_lofar2_unb2c_sdp_station_tbuf_one.vhd @@ -86,7 +86,7 @@ entity tb_lofar2_unb2c_sdp_station_tbuf_one is g_tb_index : natural := 0; g_use_bf : boolean := false; g_processing_enable_toggle : boolean := false; - g_verify_crc_error : boolean := true; -- false for correct CRC, true to cause CRC error for all read pages + g_verify_crc_error : boolean := false; -- false for correct CRC, true to cause CRC error for all read pages g_verify_rsn_error : boolean := false; -- false for correct RSN, true to cause RSN error for all read pages g_sp : natural := 13; -- signal path (SP) index in range(S_pn = 12) for WG sinus, >= 12 -- for DC at g_sp @@ -272,12 +272,41 @@ architecture tb of tb_lofar2_unb2c_sdp_station_tbuf_one is constant c_mm_file_reg_dp_xonoff_tbuf : string := c_mmf_prefix & "REG_DP_XONOFF_TBUF"; constant c_mm_file_reg_nw_10gbe_mac : string := c_mmf_prefix & "REG_NW_10GBE_MAC"; + procedure proc_read_ddr4_wr_fifo_status(signal tb_clk : in std_logic; + signal rd_data : inout std_logic_vector(c_32 - 1 downto 0); + signal ddr_wr_fifo_used : inout natural; + signal ddr_wr_fifo_full : inout std_logic) is + begin + mmf_mm_bus_rd(c_mm_file_reg_io_ddr_mb_i, 2, rd_data, tb_clk); + ddr_wr_fifo_used <= to_uint(rd_data); + mmf_mm_bus_rd(c_mm_file_reg_io_ddr_mb_i, 3, rd_data, tb_clk); + ddr_wr_fifo_full <= rd_data(0); + proc_common_wait_some_cycles(tb_clk, 1); + print_str(c_tb_str & "ddr_wr_fifo_full = " & sl_to_str(ddr_wr_fifo_full)); + print_str(c_tb_str & "ddr_wr_fifo_used = " & int_to_str(ddr_wr_fifo_used)); + end procedure; + + procedure proc_read_ddr4_rd_fifo_status(signal tb_clk : in std_logic; + signal rd_data : inout std_logic_vector(c_32 - 1 downto 0); + signal ddr_rd_fifo_used : inout natural; + signal ddr_rd_fifo_full : inout std_logic) is + begin + mmf_mm_bus_rd(c_mm_file_reg_io_ddr_mb_i, 1, rd_data, tb_clk); + ddr_rd_fifo_used <= to_uint(rd_data); + mmf_mm_bus_rd(c_mm_file_reg_io_ddr_mb_i, 3, rd_data, tb_clk); + ddr_rd_fifo_full <= rd_data(0); + proc_common_wait_some_cycles(tb_clk, 1); + print_str(c_tb_str & "ddr_rd_fifo_full = " & sl_to_str(ddr_rd_fifo_full)); + print_str(c_tb_str & "ddr_rd_fifo_used = " & int_to_str(ddr_rd_fifo_used)); + end procedure; + signal wg_started : std_logic := '0'; signal rx_done : std_logic := '0'; signal tb_almost_end : std_logic := '0'; signal i_tb_end : std_logic := '0'; signal tb_clk : std_logic := '0'; signal rd_data_setup : std_logic_vector(c_32 - 1 downto 0); + signal rd_data_fifo : std_logic_vector(c_32 - 1 downto 0); signal rd_data_control : std_logic_vector(c_32 - 1 downto 0); signal rd_data_monitor : std_logic_vector(c_32 - 1 downto 0); signal rd_data_bsn : std_logic_vector(c_32 - 1 downto 0); @@ -298,7 +327,11 @@ architecture tb of tb_lofar2_unb2c_sdp_station_tbuf_one is signal rd_cep_udp_src_port : std_logic_vector(15 downto 0); signal rd_cep_udp_dst_port : std_logic_vector(15 downto 0); - signal rd_ddr_status : std_logic_vector(31 downto 0); + signal ddr_status : std_logic_vector(31 downto 0); + signal ddr_wr_fifo_used : natural; + signal ddr_rd_fifo_used : natural; + signal ddr_wr_fifo_full : std_logic; + signal ddr_rd_fifo_full : std_logic; signal ddr_dvr_done : std_logic := '0'; signal ddr_ctlr_nof_bytes_per_word : natural; @@ -733,18 +766,18 @@ begin -- Read DDR4 memory status ---------------------------------------------------------------------------- mmf_mm_bus_rd(c_mm_file_reg_io_ddr_mb_i, 0, rd_data_setup, tb_clk); - rd_ddr_status <= rd_data_setup; + ddr_status <= rd_data_setup; proc_common_wait_some_cycles(tb_clk, 1); -- . verify dvr_done for calibration ok - ddr_dvr_done <= rd_ddr_status(0); + ddr_dvr_done <= ddr_status(0); proc_common_wait_some_cycles(tb_clk, 1); assert ddr_dvr_done = '1' report c_tb_str & "Wrong no DDR MB_I" severity ERROR; -- . verify ddr_ctlr_nof_bytes_per_word - ddr_ctlr_nof_bytes_per_word <= TO_UINT(rd_ddr_status(15 downto 8)); + ddr_ctlr_nof_bytes_per_word <= TO_UINT(ddr_status(15 downto 8)); proc_common_wait_some_cycles(tb_clk, 1); assert ddr_ctlr_nof_bytes_per_word = c_exp_ddr_ctlr_nof_bytes_per_word report c_tb_str & "Wrong read ddr_ctlr_nof_bytes_per_word" @@ -811,7 +844,7 @@ begin mmf_mm_wait_until_value( c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low part "UNSIGNED", rd_data_bsn, ">=", c_bsn_start_wg, -- this is the wait until condition - c_T_bs_period, tb_clk); + c_T_bs_period, ext_clk); -- WG started wg_started <= '1'; @@ -871,6 +904,12 @@ begin -- Wait for DUT power up after reset wait for 200 ns; + ---------------------------------------------------------------------------- + -- Read DDR4 FIFOs status + ---------------------------------------------------------------------------- + proc_read_ddr4_wr_fifo_status(tb_clk, rd_data_fifo, ddr_wr_fifo_used, ddr_wr_fifo_full); + proc_read_ddr4_rd_fifo_status(tb_clk, rd_data_fifo, ddr_rd_fifo_used, ddr_rd_fifo_full); + ---------------------------------------------------------------------------- -- Record all antennas ---------------------------------------------------------------------------- @@ -929,6 +968,9 @@ begin -- Recording proc_common_wait_some_cycles(ext_clk, g_rs_block_size * g_rs_record_nof_block); + -- Read DDR4 write FIFO status + proc_read_ddr4_wr_fifo_status(tb_clk, rd_data_fifo, ddr_wr_fifo_used, ddr_wr_fifo_full); + -- Read BSN monitor for recording data mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_tbuf, 1, rd_data_monitor, tb_clk); -- bsn at sync recording_rsn_at_sync <= to_uint(rd_data_monitor); @@ -992,12 +1034,15 @@ begin mmf_mm_wait_until_value( c_mm_file_reg_tbuf, 18, -- read record_busy "UNSIGNED", rd_data_record_busy, "=", 0, -- this is the wait until condition - c_T_rd_interval, tb_clk); + c_T_rd_interval, ext_clk); tbuf_registers_ro.record_busy <= rd_data_record_busy(0); proc_common_wait_some_cycles(tb_clk, 1); print_str(c_tb_str & "tbuf_registers_rd.record_enable = " & sl_to_str(tbuf_registers_rd.record_enable)); print_str(c_tb_str & "tbuf_registers_ro.record_busy = " & sl_to_str(tbuf_registers_ro.record_busy)); + -- Read DDR4 write FIFO status + proc_read_ddr4_wr_fifo_status(tb_clk, rd_data_fifo, ddr_wr_fifo_used, ddr_wr_fifo_full); + -- Read number of recorded pages mmf_mm_bus_rd(c_mm_file_reg_tbuf, 4, rd_data_control, tb_clk); tbuf_registers_ro.recorded_nof_pages <= to_uint(rd_data_control); @@ -1104,13 +1149,17 @@ begin severity ERROR; print_str(c_tb_str & "tbuf_registers_rd.dump_enables = " & slv_to_str(tbuf_registers_rd.dump_enables)); + -- Read DDR4 read FIFO status + proc_common_wait_some_cycles(ext_clk, 10); + proc_read_ddr4_rd_fifo_status(tb_clk, rd_data_fifo, ddr_rd_fifo_used, ddr_rd_fifo_full); + ---------------------------------------------------------------------------- -- Wait until dump is done ---------------------------------------------------------------------------- mmf_mm_wait_until_value( c_mm_file_reg_tbuf, 17, -- read dump_done "UNSIGNED", rd_data_dump_done, "=", 1, -- this is the wait until condition - c_T_rd_interval, tb_clk); + c_T_rd_interval, ext_clk); tbuf_registers_ro.dump_done <= rd_data_dump_done(0); proc_common_wait_some_cycles(tb_clk, 1); @@ -1135,6 +1184,9 @@ begin proc_common_wait_some_cycles(ext_clk, g_rs_block_size * 4); rx_done <= '1'; + -- Read DDR4 read FIFO status + proc_read_ddr4_rd_fifo_status(tb_clk, rd_data_fifo, ddr_rd_fifo_used, ddr_rd_fifo_full); + -- Read strobe_total_counts mmf_mm_bus_rd(c_mm_file_reg_strobe_total_count_tbuf, 0, rd_data_strobe, tb_clk); tbuf_strobe_total_counts.memory_read_nof_packets <= to_uint(rd_data_strobe);