diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
index 74776150ed3d99824cde735d1f16483cae61616b..f1cb421361ec169273350ebb245464ff46541d32 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
@@ -32,10 +32,6 @@
-- after the fifo has been filled sufficiently, a frame is also available when
-- the in_eop has been received earlier than the specified g_fifo_fill. For
-- more details, please consult the description of dp_fill_fifo_core.
--- Remark:
--- . dp_fifo_fill_eop needs 1 clock cycle gap between eop and sop to process
--- the block. Therefore it cannot handle contious streams without gaps. It
--- can handle bursts by increasing g_fifo_size.
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, technology_lib;
@@ -48,6 +44,7 @@ USE technology_lib.technology_select_pkg.ALL;
ENTITY dp_fifo_fill_eop IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
+ g_note_is_ful : BOOLEAN := TRUE;
g_use_dual_clock : BOOLEAN := FALSE;
g_data_w : NATURAL := 16;
g_bsn_w : NATURAL := 1;
@@ -99,16 +96,12 @@ ARCHITECTURE rtl OF dp_fifo_fill_eop IS
CONSTANT c_use_ctrl : BOOLEAN := TRUE;
-- Define t_state as slv to avoid Modelsim warning "Nonresolved signal 'nxt_state' may have multiple sources". Due to that g_fifo_rl = 0 or 1 ar both supported.
- --TYPE t_state IS (s_idle, s_fill, s_output, s_xoff);
- CONSTANT s_idle : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
- CONSTANT s_fill : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
- CONSTANT s_output : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
- CONSTANT s_xoff : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
+ TYPE t_state IS (s_fill, s_output, s_xoff);
CONSTANT c_nof_spulse : NATURAL := 3;
- SIGNAL state : STD_LOGIC_VECTOR(1 DOWNTO 0); -- t_state
- SIGNAL nxt_state : STD_LOGIC_VECTOR(1 DOWNTO 0); -- t_state
+ SIGNAL state : t_state;
+ SIGNAL nxt_state : t_state;
SIGNAL xon_reg : STD_LOGIC;
SIGNAL nxt_xon_reg : STD_LOGIC;
@@ -150,106 +143,50 @@ BEGIN
-- Control FIFO fill level
wr_usedw_32b <= RESIZE_UVEC(wr_fifo_usedw, c_word_w);
rd_usedw_32b <= RESIZE_UVEC(rd_fifo_usedw, c_word_w);
-
rd_fill_ctrl <= rd_fill_32b(c_fifo_size_w-1 DOWNTO 0);
- gen_dp_fifo_sc : IF g_use_dual_clock=FALSE GENERATE
- u_dp_fifo_sc : ENTITY work.dp_fifo_sc
- GENERIC MAP (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_ctrl => c_use_ctrl,
- g_use_complex => g_use_complex,
- g_fifo_size => c_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_rl => c_fifo_rl
- )
- PORT MAP (
- rst => rd_rst,
- clk => rd_clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- usedw => rd_fifo_usedw,
- rd_emp => rd_emp,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => rd_siso, -- for RL = 0 rd_siso.ready acts as read acknowledge, for RL = 1 rd_siso.ready acts as read request
- src_out => rd_sosi
- );
-
- wr_fifo_usedw <= rd_fifo_usedw;
-
- -- No need to transfer eop counter across clock domains
- rd_eop_cnt <= wr_eop_cnt;
- rd_eop_new <= '1';
- p_sc: PROCESS(wr_clk, wr_rst)
- BEGIN
- IF wr_rst='1' THEN
- wr_eop_cnt <= 0;
- ELSIF rising_edge(wr_clk) THEN
- IF snk_in.eop = '1' THEN
- wr_eop_cnt <= 1;
- ELSE
- wr_eop_cnt <= 0;
- END IF;
- END IF;
- END PROCESS;
-
+ u_dp_fifo_core : ENTITY work.dp_fifo_core
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_note_is_ful => g_note_is_ful,
+ g_use_dual_clock => g_use_dual_clock,
+ g_data_w => g_data_w,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_ctrl => c_use_ctrl,
+ g_use_complex => g_use_complex,
+ g_fifo_size => c_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_rl => c_fifo_rl
+ )
+ PORT MAP (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => wr_fifo_usedw,
+ rd_usedw => rd_fifo_usedw,
+ rd_emp => rd_emp,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => rd_siso, -- for RL = 0 rd_siso.ready acts as read acknowledge, -- for RL = 1 rd_siso.ready acts as read request
+ src_out => rd_sosi
+ );
- END GENERATE;
-
+ -- Transfer eop counter across clock domains for dual clock
gen_dp_fifo_dc : IF g_use_dual_clock=TRUE GENERATE
- u_dp_fifo_dc : ENTITY work.dp_fifo_dc
- GENERIC MAP (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_ctrl => c_use_ctrl,
- --g_use_complex => g_use_complex,
- g_fifo_size => c_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_rl => c_fifo_rl
- )
- PORT MAP (
- wr_rst => wr_rst,
- wr_clk => wr_clk,
- rd_rst => rd_rst,
- rd_clk => rd_clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => wr_fifo_usedw,
- rd_usedw => rd_fifo_usedw,
- rd_emp => rd_emp,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => rd_siso, -- for RL = 0 rd_siso.ready acts as read acknowledge, -- for RL = 1 rd_siso.ready acts as read request
- src_out => rd_sosi
- );
-
- -- Transfer eop counter across clock domains
reg_wr_eop_cnt <= TO_UVEC(wr_eop_cnt, c_word_w);
- rd_eop_cnt <= TO_UINT(reg_rd_eop_cnt);
u_common_reg_cross_domain : ENTITY common_lib.common_reg_cross_domain
PORT MAP (
in_rst => wr_rst,
@@ -262,38 +199,60 @@ BEGIN
out_dat => reg_rd_eop_cnt,
out_new => rd_eop_new
);
+ END GENERATE;
+
+ -- No need to transfer eop counter across clock domains for single clock
+ gen_dp_fifo_sc : IF g_use_dual_clock=FALSE GENERATE
+ wr_fifo_usedw <= rd_fifo_usedw;
+ rd_eop_new <= '1';
+ END GENERATE;
- p_dc: PROCESS(wr_clk, wr_rst)
- VARIABLE v_wr_eop_cnt: NATURAL;
- BEGIN
- IF wr_rst='1' THEN
- wr_eop_busy <= '0';
- wr_eop_cnt <= 0;
- wr_eop_new <= '0';
- ELSIF rising_edge(wr_clk) THEN
+ rd_eop_cnt <= TO_UINT(reg_rd_eop_cnt) WHEN g_use_dual_clock ELSE wr_eop_cnt;
+
+ p_eop_cnt: PROCESS(wr_clk, wr_rst)
+ VARIABLE v_wr_eop_cnt: NATURAL;
+ BEGIN
+ IF wr_rst='1' THEN
+ wr_eop_busy <= '0';
+ wr_eop_cnt <= 0;
+ wr_eop_new <= '0';
+ ELSIF rising_edge(wr_clk) THEN
+ IF g_use_dual_clock THEN -- transfer eop counter accross clock domains
v_wr_eop_cnt := wr_eop_cnt;
IF wr_eop_done = '1' THEN
wr_eop_busy <= '0';
END IF;
-
+
IF wr_eop_busy = '0' THEN
wr_eop_busy <= '1';
wr_eop_new <= '1';
END IF;
-
+
IF wr_eop_new = '1' THEN
wr_eop_new <= '0';
v_wr_eop_cnt := 0;
END IF;
-
+
IF snk_in.eop = '1' THEN
v_wr_eop_cnt := v_wr_eop_cnt + 1;
END IF;
wr_eop_cnt <= v_wr_eop_cnt;
+
+ ELSE -- No need to transfer eop counter across clock domains for single clock
+ IF wr_rst='1' THEN
+ wr_eop_cnt <= 0;
+ ELSIF rising_edge(wr_clk) THEN
+ IF snk_in.eop = '1' THEN
+ wr_eop_cnt <= 1;
+ ELSE
+ wr_eop_cnt <= 0;
+ END IF;
+ END IF;
END IF;
- END PROCESS;
- END GENERATE;
-
+ END IF;
+ END PROCESS;
+
+
no_fill : IF g_fifo_fill=0 GENERATE
rd_siso <= src_in; -- SISO
src_out <= rd_sosi; -- SOSI
@@ -307,7 +266,7 @@ BEGIN
BEGIN
IF rd_rst='1' THEN
xon_reg <= '0';
- state <= s_idle;
+ state <= s_fill;
i_src_out <= c_dp_sosi_rst;
eop_cnt <= 0;
ELSIF rising_edge(rd_clk) THEN
@@ -320,77 +279,6 @@ BEGIN
nxt_xon_reg <= src_in.xon; -- register xon to easy timing closure
- gen_rl_0 : IF g_fifo_rl=0 GENERATE
- p_state : PROCESS(state, rd_sosi, src_in, xon_reg, rd_fifo_usedw, rd_fill_ctrl, rd_eop_cnt, eop_cnt, rd_eop_new)
- BEGIN
- nxt_state <= state;
- rd_siso <= src_in; -- default acknowledge (RL=1) this input when output is ready
-
- -- The output register stage increase RL=0 to 1, so it matches RL = 1 for src_in.ready
- nxt_src_out <= rd_sosi;
- nxt_src_out.valid <= '0'; -- default no output
- nxt_src_out.sop <= '0';
- nxt_src_out.eop <= '0';
- nxt_src_out.sync <= '0';
- nxt_eop_cnt <= eop_cnt;
- IF rd_eop_new = '1' THEN
- nxt_eop_cnt <= eop_cnt + rd_eop_cnt;
- END IF;
-
- CASE state IS
- WHEN s_idle =>
- IF xon_reg='0' THEN
- nxt_state <= s_xoff;
- ELSE
- -- read the FIFO until the sop is pending at the output, so discard any valid data between eop and sop
- IF rd_sosi.sop='0' THEN
- rd_siso <= c_dp_siso_rdy; -- acknowledge (RL=0) this input independent of output ready
- ELSE
- rd_siso <= c_dp_siso_hold; -- stop the input, hold the rd_sosi.sop at FIFO output (RL=0)
- nxt_state <= s_fill;
- END IF;
- END IF;
- WHEN s_fill =>
- IF xon_reg='0' THEN
- nxt_state <= s_xoff;
- ELSE
- -- stop reading until the FIFO has been filled sufficiently
- IF UNSIGNED(rd_fifo_usedw)<UNSIGNED(rd_fill_ctrl) AND eop_cnt <= 0 THEN
- rd_siso <= c_dp_siso_hold; -- stop the input, hold the pend_src_out.sop
- ELSE
- -- if the output is ready, then start outputting the frame
- IF src_in.ready='1' THEN
- nxt_src_out <= rd_sosi; -- output sop that is still at FIFO output (RL=0)
- nxt_state <= s_output;
- IF rd_eop_new = '1' THEN
- nxt_eop_cnt <= eop_cnt + rd_eop_cnt - 1;
- ELSE
- nxt_eop_cnt <= eop_cnt -1;
- END IF;
- END IF;
- END IF;
- END IF;
- WHEN s_output =>
- -- if the output is ready continue outputting the frame, ignore xon_reg during this frame
- IF src_in.ready='1' THEN
- nxt_src_out <= rd_sosi; -- output valid
- IF rd_sosi.eop='1' THEN
- nxt_state <= s_idle; -- output eop, so stop reading the FIFO
- END IF;
- END IF;
- WHEN OTHERS => -- s_xoff
- -- Flush the fill FIFO when xon='0'
- rd_siso <= c_dp_siso_flush;
- IF xon_reg='1' THEN
- nxt_state <= s_idle;
- END IF;
- END CASE;
-
- -- Pass on frame level flow control
- rd_siso.xon <= src_in.xon;
- END PROCESS;
- END GENERATE; -- gen_rl_0
-
gen_rl_1 : IF g_fifo_rl=1 GENERATE
-- Use dp_hold_input to get equivalent implementation with default RL=1 FIFO.
@@ -408,42 +296,40 @@ BEGIN
pend_src_out => pend_src_out,
src_out_reg => i_src_out
);
+ END GENERATE;
+
+ gen_rl_0 : IF g_fifo_rl=0 GENERATE
+ pend_src_out <= rd_sosi;
+ rd_siso <= hold_src_in;
+ END GENERATE;
- p_state : PROCESS(state, src_in, xon_reg, pend_src_out, rd_fifo_usedw, rd_fill_ctrl, rd_eop_cnt, eop_cnt, rd_eop_new)
- BEGIN
- nxt_state <= state;
+
+ p_state : PROCESS(state, src_in, xon_reg, pend_src_out, rd_fifo_usedw, rd_fill_ctrl, rd_eop_cnt, eop_cnt, rd_eop_new)
+ BEGIN
+ nxt_state <= state;
- hold_src_in <= src_in; -- default request (RL=1) new input when output is ready
-
- -- The output register stage matches RL = 1 for src_in.ready
- nxt_src_out <= pend_src_out;
- nxt_src_out.valid <= '0'; -- default no output
- nxt_src_out.sop <= '0';
- nxt_src_out.eop <= '0';
- nxt_src_out.sync <= '0';
- nxt_eop_cnt <= eop_cnt;
- IF rd_eop_new = '1' THEN
- nxt_eop_cnt <= eop_cnt + rd_eop_cnt;
- END IF;
+ hold_src_in <= src_in; -- default request (RL=1) new input when output is ready
+
+ -- The output register stage matches RL = 1 for src_in.ready
+ nxt_src_out <= pend_src_out;
+ nxt_src_out.valid <= '0'; -- default no output
+ nxt_src_out.sop <= '0';
+ nxt_src_out.eop <= '0';
+ nxt_src_out.sync <= '0';
+ nxt_eop_cnt <= eop_cnt;
+ IF rd_eop_new = '1' THEN
+ nxt_eop_cnt <= eop_cnt + rd_eop_cnt;
+ END IF;
- CASE state IS
- WHEN s_idle =>
- IF xon_reg='0' THEN
- nxt_state <= s_xoff;
- ELSE
- -- read the FIFO until the sop is pending at the output, so discard any valid data between eop and sop
- IF pend_src_out.sop='0' THEN
- hold_src_in <= c_dp_siso_rdy; -- request (RL=1) new input independent of output ready
- ELSE
- hold_src_in <= c_dp_siso_hold; -- stop the input, hold the pend_src_out.sop in dp_hold_input
- nxt_state <= s_fill;
- END IF;
- END IF;
- WHEN s_fill =>
- IF xon_reg='0' THEN
- nxt_state <= s_xoff;
+ CASE state IS
+ WHEN s_fill =>
+ IF xon_reg='0' THEN
+ nxt_state <= s_xoff;
+ ELSE
+ -- read the FIFO until the sop is pending at the output, so discard any valid data between eop and sop
+ IF pend_src_out.sop='0' THEN
+ hold_src_in <= c_dp_siso_rdy; -- request (RL=1) new input independent of output ready
ELSE
- -- stop reading until the FIFO has been filled sufficiently
IF UNSIGNED(rd_fifo_usedw)<UNSIGNED(rd_fill_ctrl) AND eop_cnt <= 0 THEN
hold_src_in <= c_dp_siso_hold; -- stop the input, hold the pend_src_out.sop
ELSE
@@ -459,26 +345,26 @@ BEGIN
END IF;
END IF;
END IF;
- WHEN s_output =>
- -- if the output is ready continue outputting the input frame, ignore xon_reg during this frame
- IF src_in.ready='1' THEN
- nxt_src_out <= pend_src_out; -- output valid
- IF pend_src_out.eop='1' THEN
- nxt_state <= s_idle; -- output eop, so stop reading the FIFO
- END IF;
+ END IF;
+ WHEN s_output =>
+ -- if the output is ready continue outputting the input frame, ignore xon_reg during this frame
+ IF src_in.ready='1' THEN
+ nxt_src_out <= pend_src_out; -- output valid
+ IF pend_src_out.eop='1' THEN
+ nxt_state <= s_fill; -- output eop, so stop reading the FIFO
END IF;
- WHEN OTHERS => -- s_xon
- -- Flush the fill FIFO when xon='0'
- hold_src_in <= c_dp_siso_flush;
- IF xon_reg='1' THEN
- nxt_state <= s_idle;
- END IF;
- END CASE;
+ END IF;
+ WHEN OTHERS => -- s_xoff
+ -- Flush the fill FIFO when xon='0'
+ hold_src_in <= c_dp_siso_flush;
+ IF xon_reg='1' THEN
+ nxt_state <= s_fill;
+ END IF;
+ END CASE;
- -- Pass on frame level flow control
- hold_src_in.xon <= src_in.xon;
- END PROCESS;
- END GENERATE; -- gen_rl_1
+ -- Pass on frame level flow control
+ hold_src_in.xon <= src_in.xon;
+ END PROCESS;
END GENERATE; -- gen_fill
END rtl;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd
index f4b4106cbc87fedc54cf9fafefc95f3ee48d8af9..0eb35ac9ecdc66c4964758a7d66e242c0bf822ed 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd
@@ -46,7 +46,9 @@ ARCHITECTURE tb OF tb_tb_dp_fifo_fill_eop IS
SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
BEGIN
-- Try FIFO settings : GENERIC MAP (g_dut_use_dual_clock, g_dut_use_bsn, g_dut_use_empty, g_dut_use_channel, g_dut_use_sync, g_dut_fifo_rl, g_dut_fifo_size, g_dut_fifo_fill, g_dut_use_rd_fill_32b)
- u_dut_sc : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => FALSE);
- u_dut_dc : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => TRUE);
+ u_dut_sc_1 : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => FALSE, g_dut_fifo_rl => 1);
+ u_dut_dc_1 : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => TRUE, g_dut_fifo_rl => 1);
+ u_dut_sc_0 : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => FALSE, g_dut_fifo_rl => 0);
+ u_dut_dc_0 : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => TRUE, g_dut_fifo_rl => 0);
END tb;