From 2a32f406375c23936d04a2938bfc416066406649 Mon Sep 17 00:00:00 2001
From: donker <donker@astron.nl>
Date: Tue, 12 Nov 2019 09:50:57 +0100
Subject: [PATCH] updated sim dir
---
boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd | 2 +-
.../unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd | 2 +-
.../unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd | 2 +-
.../unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd | 2 +-
.../uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd | 2 +-
.../unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd | 2 +-
.../designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd | 2 +-
.../src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd | 2 +-
boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd | 2 +-
.../designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd | 2 +-
boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd | 2 +-
.../designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd | 2 +-
.../designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd | 2 +-
.../uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd | 2 +-
.../designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd | 2 +-
.../designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd | 2 +-
.../uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd | 2 +-
.../designs/unb2c_heater/src/vhdl/mmm_unb2c_heater.vhd | 2 +-
.../designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd | 2 +-
.../uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd | 2 +-
.../dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd | 2 +-
libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd | 2 +-
.../designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd | 2 +-
.../io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd | 2 +-
24 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
index 7a27dbfa21..9c2a5cefd3 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
@@ -160,7 +160,7 @@ BEGIN
cal_clk <= i_cal_clk;
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
index b22bc96ef6..18f4514907 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
@@ -167,7 +167,7 @@ BEGIN
cal_clk <= i_cal_clk;
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
index 1bbf679a9b..3d5bd6df8e 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
@@ -133,7 +133,7 @@ BEGIN
mm_clk <= i_mm_clk;
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
index 48b37524cc..3799af2d93 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
@@ -146,7 +146,7 @@ BEGIN
eth1g_tse_clk <= i_tse_clk;
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
index bb47b661ed..adbd2679ab 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
@@ -122,7 +122,7 @@ BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
index 96883ccde9..61a2baef4a 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
@@ -122,7 +122,7 @@ ARCHITECTURE str OF mmm_unb1_minimal_qsys_wo_pll IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
index 2c0fee9797..a518c6b0cb 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
@@ -151,7 +151,7 @@ BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
index bd3dee21cc..52d2499977 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
@@ -268,7 +268,7 @@ ARCHITECTURE str OF mmm_unb1_terminal_bg_mesh_db IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
index 7fd9b5198b..e8c27dfe23 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
@@ -257,7 +257,7 @@ ARCHITECTURE str OF mmm_unb1_test IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
index db4628496d..2c1f0c7f90 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
@@ -111,7 +111,7 @@ ARCHITECTURE str OF mmm_unb2_minimal IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
index a9226f63e6..38dd414bf3 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
@@ -284,7 +284,7 @@ ARCHITECTURE str OF mmm_unb2_test IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
index 7d97a93016..6870c7a570 100644
--- a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
@@ -115,7 +115,7 @@ ARCHITECTURE str OF mmm_unb2a_heater IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
index 3388784703..a7548b0735 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
@@ -111,7 +111,7 @@ ARCHITECTURE str OF mmm_unb2a_minimal IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
index 7f07f1f7f3..06f8aeedc7 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
@@ -287,7 +287,7 @@ ARCHITECTURE str OF mmm_unb2a_test IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
index 782748e7d4..98475ca460 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
@@ -115,7 +115,7 @@ ARCHITECTURE str OF mmm_unb2b_heater IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
index c482ecfc35..9c99f381a3 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
@@ -111,7 +111,7 @@ ARCHITECTURE str OF mmm_unb2b_minimal IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
index 301f25db6d..842561e71f 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
@@ -287,7 +287,7 @@ ARCHITECTURE str OF mmm_unb2b_test IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2c/designs/unb2c_heater/src/vhdl/mmm_unb2c_heater.vhd b/boards/uniboard2c/designs/unb2c_heater/src/vhdl/mmm_unb2c_heater.vhd
index f405ed1f61..6fb087f033 100644
--- a/boards/uniboard2c/designs/unb2c_heater/src/vhdl/mmm_unb2c_heater.vhd
+++ b/boards/uniboard2c/designs/unb2c_heater/src/vhdl/mmm_unb2c_heater.vhd
@@ -115,7 +115,7 @@ ARCHITECTURE str OF mmm_unb2c_heater IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
index 1491593920..4f3f7b17ee 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
@@ -111,7 +111,7 @@ ARCHITECTURE str OF mmm_unb2c_minimal IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
index 6c752d86c0..e175ad0640 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
@@ -287,7 +287,7 @@ ARCHITECTURE str OF mmm_unb2c_test IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
index f5dd5eccc8..5bc3ecf934 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
@@ -176,7 +176,7 @@ BEGIN
dp_clk <= i_dp_clk;
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
index aeff190347..33be7018ca 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
@@ -169,7 +169,7 @@ BEGIN
eth1g_tse_clk <= i_tse_clk;
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
index c43cbeca4f..48ca14509e 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
+++ b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
@@ -198,7 +198,7 @@ BEGIN
mm_clk <= i_mm_clk;
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
index d48b4e138b..3504584981 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
+++ b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
@@ -419,7 +419,7 @@ ARCHITECTURE str OF mmm_unb1_eth_10g IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
--
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