diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
index 7a27dbfa212ce9fc6f38a7f1463d59354c6b4862..9c2a5cefd3b87cb296d0673e1fc9fadfcc48f7de 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
@@ -160,7 +160,7 @@ BEGIN
   cal_clk       <= i_cal_clk;
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
index b22bc96ef6876c494d0f5959118f569732f3daaf..18f4514907bed8b19a2151ae7eb6f4e3153338a1 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
@@ -167,7 +167,7 @@ BEGIN
   cal_clk       <= i_cal_clk;
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
index 1bbf679a9b2be2030f0f4d4d3f20ccfb801d3259..3d5bd6df8e1330930a40abedada557b2f4b20ac7 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
@@ -133,7 +133,7 @@ BEGIN
   mm_clk <= i_mm_clk;
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
index 48b37524cc93f255f3a4479aba797b50df15aabc..3799af2d9301feaf9798d11f3bcfed6435accb82 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
@@ -146,7 +146,7 @@ BEGIN
   eth1g_tse_clk <= i_tse_clk;
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
index bb47b661ed4d6abbaa0974821036d3669adc6479..adbd2679ab8321b3672e88ce7129ce5f5d22e343 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
@@ -122,7 +122,7 @@ BEGIN
 
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
index 96883ccde9b40f852b8bd541ccd5948b839cc74c..61a2baef4a5b7cf427a59a245158178c2be433d8 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
@@ -122,7 +122,7 @@ ARCHITECTURE str OF mmm_unb1_minimal_qsys_wo_pll IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
index 2c0fee9797b0edc7eb88bc91077cced153f16be9..a518c6b0cbd334a271934ee19123ba6d4b181a98 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
@@ -151,7 +151,7 @@ BEGIN
 
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
index bd3dee21cce9a4163932f7d00ec78c4ab3d1cadd..52d2499977120295d334bfc915bb7e30abb4f392 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
@@ -268,7 +268,7 @@ ARCHITECTURE str OF mmm_unb1_terminal_bg_mesh_db IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
     u_mm_file_reg_wdi  :  mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
index 7fd9b5198b0b5bae433650aa53e8b847c17365a8..e8c27dfe23e1306903e4a5123f234abdec492ac7 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
@@ -257,7 +257,7 @@ ARCHITECTURE str OF mmm_unb1_test IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
index db4628496d5407dcebe64cc739e0371b8220c88e..2c1f0c7f90cc18aef2845c7461d3e5de4ae4e27b 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
@@ -111,7 +111,7 @@ ARCHITECTURE str OF mmm_unb2_minimal IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
index a9226f63e6109e91ed3663c7f3b489139345f023..38dd414bf32dceb289966d3dd9f6c503f7b43fca 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
@@ -284,7 +284,7 @@ ARCHITECTURE str OF mmm_unb2_test IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
index 7d97a930169989f621da500a586be25d11782034..6870c7a570c70a47bf8b19a8a513fe91460e4baf 100644
--- a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
@@ -115,7 +115,7 @@ ARCHITECTURE str OF mmm_unb2a_heater IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
index 338878470393169081645cc7eb20659a0bc95803..a7548b0735eb816d2ecf80840555ed2f1604525e 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
@@ -111,7 +111,7 @@ ARCHITECTURE str OF mmm_unb2a_minimal IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
index 7f07f1f7f3ed4e55110b774aa62bbd87d13794b1..06f8aeedc793134557ebebb2f146f11ddb8529f7 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
@@ -287,7 +287,7 @@ ARCHITECTURE str OF mmm_unb2a_test IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
index 782748e7d4e2e3d4b6e5ec42794552666401f6cb..98475ca46038674446a0ad90053a8cacfab96856 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
@@ -115,7 +115,7 @@ ARCHITECTURE str OF mmm_unb2b_heater IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
index c482ecfc35216fce386e1b046dbe31d06d33f429..9c99f381a3f76fc1e91acafddabb8b3b63e9fede 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
@@ -111,7 +111,7 @@ ARCHITECTURE str OF mmm_unb2b_minimal IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
index 301f25db6d31f29d02654c220272a3cdbbaeeea8..842561e71fc06414b7f1c7a7bdb8fadccd5cb7a6 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
@@ -287,7 +287,7 @@ ARCHITECTURE str OF mmm_unb2b_test IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard2c/designs/unb2c_heater/src/vhdl/mmm_unb2c_heater.vhd b/boards/uniboard2c/designs/unb2c_heater/src/vhdl/mmm_unb2c_heater.vhd
index f405ed1f61cd85877eade8cc87693d49cb77a479..6fb087f03365456d8022c8f12ee1253b15831733 100644
--- a/boards/uniboard2c/designs/unb2c_heater/src/vhdl/mmm_unb2c_heater.vhd
+++ b/boards/uniboard2c/designs/unb2c_heater/src/vhdl/mmm_unb2c_heater.vhd
@@ -115,7 +115,7 @@ ARCHITECTURE str OF mmm_unb2c_heater IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
index 149159392034a6d9dbfdba12ac063c5ac2ebca65..4f3f7b17ee743180825b03b5f5ef177e4f654b5a 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
@@ -111,7 +111,7 @@ ARCHITECTURE str OF mmm_unb2c_minimal IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
index 6c752d86c0e20fa1f7d3b925c845bb6e85ae5d01..e175ad064068c0b2f7c1591ed2135389278d418e 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
@@ -287,7 +287,7 @@ ARCHITECTURE str OF mmm_unb2c_test IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
index f5dd5eccc8c00cccbdc16cbffe8c61f4adace468..5bc3ecf934cdc0a2d15ffee6e91e3b9e7fa5390a 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
@@ -176,7 +176,7 @@ BEGIN
   dp_clk        <= i_dp_clk;
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
index aeff190347ba10b63d455fdba7fd03f3f7089899..33be7018ca91af729653e4b5ea6a906d2dd60e22 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
@@ -169,7 +169,7 @@ BEGIN
   eth1g_tse_clk <= i_tse_clk;
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
index c43cbeca4faa08defe29a5f662848ba3475f00ee..48ca14509ed8e369f8bdae0dbdb1157cdd1cd30b 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
+++ b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
@@ -198,7 +198,7 @@ BEGIN
   mm_clk   <= i_mm_clk;
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
diff --git a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
index d48b4e138bc67ad1cf28af1fc924b441e98c0526..3504584981f117150c4db5ccc850942864c3d729 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
+++ b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
@@ -419,7 +419,7 @@ ARCHITECTURE str OF mmm_unb1_eth_10g IS
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
     u_mm_file_reg_wdi  :  mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")