From 296743e2f7bdd75c7be362997f156741baec8c03 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Mon, 28 Nov 2022 15:36:45 +0100
Subject: [PATCH] Rename 1GbE-I into eth_0 and II into eth_1.
---
.../unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd | 2 +-
.../unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd | 2 +-
.../unb2c_test/src/vhdl/mmm_unb2c_test.vhd | 450 +++++++++---------
.../unb2c_test/src/vhdl/unb2c_test.vhd | 314 ++++++------
4 files changed, 384 insertions(+), 384 deletions(-)
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
index 8fe2c8d809..5934694d5e 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
@@ -35,7 +35,7 @@ USE technology_lib.technology_pkg.ALL;
ENTITY unb2c_test_1GbE_I IS
GENERIC (
g_design_name : STRING := "unb2c_test_1GbE_I";
- g_design_note : STRING := "Uses only Eth0";
+ g_design_note : STRING := "Uses only eth_0";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd
index 8448d4f316..d23b4d0257 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd
@@ -35,7 +35,7 @@ USE technology_lib.technology_pkg.ALL;
ENTITY unb2c_test_1GbE_II IS
GENERIC (
g_design_name : STRING := "unb2c_test_1GbE_II";
- g_design_note : STRING := "Use Eth0 and Eth1";
+ g_design_note : STRING := "Use eth_0 and eth_1";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
index 2b921773c0..7b42c2b491 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
@@ -79,52 +79,52 @@ ENTITY mmm_unb2c_test IS
reg_ppsh_miso : IN t_mem_miso;
-- eth1g ch0
- eth1g_eth0_mm_rst : OUT STD_LOGIC;
- eth1g_eth0_tse_mosi : OUT t_mem_mosi;
- eth1g_eth0_tse_miso : IN t_mem_miso;
- eth1g_eth0_reg_mosi : OUT t_mem_mosi;
- eth1g_eth0_reg_miso : IN t_mem_miso;
- eth1g_eth0_reg_interrupt : IN STD_LOGIC;
- eth1g_eth0_ram_mosi : OUT t_mem_mosi;
- eth1g_eth0_ram_miso : IN t_mem_miso;
-
- reg_eth1g_I_bg_ctrl_copi : OUT t_mem_copi;
- reg_eth1g_I_bg_ctrl_cipo : IN t_mem_cipo;
- reg_eth1g_I_hdr_dat_copi : OUT t_mem_copi;
- reg_eth1g_I_hdr_dat_cipo : IN t_mem_cipo;
- reg_eth1g_I_bsn_monitor_v2_tx_copi : OUT t_mem_copi;
- reg_eth1g_I_bsn_monitor_v2_tx_cipo : IN t_mem_cipo;
- reg_eth1g_I_strobe_total_count_tx_copi : OUT t_mem_copi;
- reg_eth1g_I_strobe_total_count_tx_cipo : IN t_mem_cipo;
-
- reg_eth1g_I_bsn_monitor_v2_rx_copi : OUT t_mem_copi;
- reg_eth1g_I_bsn_monitor_v2_rx_cipo : IN t_mem_cipo;
- reg_eth1g_I_strobe_total_count_rx_copi : OUT t_mem_copi;
- reg_eth1g_I_strobe_total_count_rx_cipo : IN t_mem_cipo;
+ eth_0_mm_rst : OUT STD_LOGIC;
+ eth_0_tse_mosi : OUT t_mem_mosi;
+ eth_0_tse_miso : IN t_mem_miso;
+ eth_0_reg_mosi : OUT t_mem_mosi;
+ eth_0_reg_miso : IN t_mem_miso;
+ eth_0_reg_interrupt : IN STD_LOGIC;
+ eth_0_ram_mosi : OUT t_mem_mosi;
+ eth_0_ram_miso : IN t_mem_miso;
+
+ reg_diag_bg_eth_0_copi : OUT t_mem_copi;
+ reg_diag_bg_eth_0_cipo : IN t_mem_cipo;
+ reg_hdr_dat_eth_0_copi : OUT t_mem_copi;
+ reg_hdr_dat_eth_0_cipo : IN t_mem_cipo;
+ reg_bsn_monitor_v2_tx_eth_0_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_tx_eth_0_cipo : IN t_mem_cipo;
+ reg_strobe_total_count_tx_eth_0_copi : OUT t_mem_copi;
+ reg_strobe_total_count_tx_eth_0_cipo : IN t_mem_cipo;
+
+ reg_bsn_monitor_v2_rx_eth_0_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_rx_eth_0_cipo : IN t_mem_cipo;
+ reg_strobe_total_count_rx_eth_0_copi : OUT t_mem_copi;
+ reg_strobe_total_count_rx_eth_0_cipo : IN t_mem_cipo;
-- eth1g ch1
- eth1g_eth1_mm_rst : OUT STD_LOGIC;
- eth1g_eth1_tse_mosi : OUT t_mem_mosi;
- eth1g_eth1_tse_miso : IN t_mem_miso;
- eth1g_eth1_reg_mosi : OUT t_mem_mosi;
- eth1g_eth1_reg_miso : IN t_mem_miso;
- eth1g_eth1_reg_interrupt : IN STD_LOGIC;
- eth1g_eth1_ram_mosi : OUT t_mem_mosi;
- eth1g_eth1_ram_miso : IN t_mem_miso;
-
- reg_eth1g_II_bg_ctrl_copi : OUT t_mem_copi;
- reg_eth1g_II_bg_ctrl_cipo : IN t_mem_cipo;
- reg_eth1g_II_hdr_dat_copi : OUT t_mem_copi;
- reg_eth1g_II_hdr_dat_cipo : IN t_mem_cipo;
- reg_eth1g_II_bsn_monitor_v2_tx_copi : OUT t_mem_copi;
- reg_eth1g_II_bsn_monitor_v2_tx_cipo : IN t_mem_cipo;
- reg_eth1g_II_strobe_total_count_tx_copi : OUT t_mem_copi;
- reg_eth1g_II_strobe_total_count_tx_cipo : IN t_mem_cipo;
-
- reg_eth1g_II_bsn_monitor_v2_rx_copi : OUT t_mem_copi;
- reg_eth1g_II_bsn_monitor_v2_rx_cipo : IN t_mem_cipo;
- reg_eth1g_II_strobe_total_count_rx_copi : OUT t_mem_copi;
- reg_eth1g_II_strobe_total_count_rx_cipo : IN t_mem_cipo;
+ eth_1_mm_rst : OUT STD_LOGIC;
+ eth_1_tse_mosi : OUT t_mem_mosi;
+ eth_1_tse_miso : IN t_mem_miso;
+ eth_1_reg_mosi : OUT t_mem_mosi;
+ eth_1_reg_miso : IN t_mem_miso;
+ eth_1_reg_interrupt : IN STD_LOGIC;
+ eth_1_ram_mosi : OUT t_mem_mosi;
+ eth_1_ram_miso : IN t_mem_miso;
+
+ reg_diag_bg_eth_1_copi : OUT t_mem_copi;
+ reg_diag_bg_eth_1_cipo : IN t_mem_cipo;
+ reg_hdr_dat_eth_1_copi : OUT t_mem_copi;
+ reg_hdr_dat_eth_1_cipo : IN t_mem_cipo;
+ reg_bsn_monitor_v2_tx_eth_1_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_tx_eth_1_cipo : IN t_mem_cipo;
+ reg_strobe_total_count_tx_eth_1_copi : OUT t_mem_copi;
+ reg_strobe_total_count_tx_eth_1_cipo : IN t_mem_cipo;
+
+ reg_bsn_monitor_v2_rx_eth_1_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_rx_eth_1_cipo : IN t_mem_cipo;
+ reg_strobe_total_count_rx_eth_1_copi : OUT t_mem_copi;
+ reg_strobe_total_count_rx_eth_1_cipo : IN t_mem_cipo;
-- EPCS read
reg_dpmm_data_mosi : OUT t_mem_mosi;
@@ -267,13 +267,13 @@ ARCHITECTURE str OF mmm_unb2c_test IS
SIGNAL sim_eth_mm_bus_switch : STD_LOGIC;
SIGNAL sim_eth_psc_access : STD_LOGIC;
- SIGNAL i_eth1g_eth0_reg_mosi : t_mem_mosi;
- SIGNAL i_eth1g_eth0_reg_miso : t_mem_miso;
- SIGNAL i_eth1g_eth1_reg_mosi : t_mem_mosi;
- SIGNAL i_eth1g_eth1_reg_miso : t_mem_miso;
+ SIGNAL i_eth_0_reg_mosi : t_mem_mosi;
+ SIGNAL i_eth_0_reg_miso : t_mem_miso;
+ SIGNAL i_eth_1_reg_mosi : t_mem_mosi;
+ SIGNAL i_eth_1_reg_miso : t_mem_miso;
- SIGNAL sim_eth1g_eth0_reg_mosi : t_mem_mosi;
- SIGNAL sim_eth1g_eth1_reg_mosi : t_mem_mosi;
+ SIGNAL sim_eth_0_reg_mosi : t_mem_mosi;
+ SIGNAL sim_eth_1_reg_mosi : t_mem_mosi;
SIGNAL i_reset_n : STD_LOGIC;
BEGIN
@@ -283,8 +283,8 @@ BEGIN
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
- eth1g_eth0_mm_rst <= mm_rst;
- eth1g_eth1_mm_rst <= mm_rst;
+ eth_0_mm_rst <= mm_rst;
+ eth_1_mm_rst <= mm_rst;
u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
@@ -345,15 +345,15 @@ BEGIN
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
-- . 1GbE_I with TSE setup by NiosII
- u_mm_file_reg_eth0_tse : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_TSE")
- PORT MAP(mm_rst, mm_clk, eth1g_eth0_tse_mosi, eth1g_eth0_tse_miso);
- u_mm_file_reg_eth0_reg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_REG")
- PORT MAP(mm_rst, mm_clk, i_eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
- u_mm_file_reg_eth0_ram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_RAM")
- PORT MAP(mm_rst, mm_clk, eth1g_eth0_ram_mosi, eth1g_eth0_ram_miso);
+ u_mm_file_reg_eth_0_tse : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_TSE")
+ PORT MAP(mm_rst, mm_clk, eth_0_tse_mosi, eth_0_tse_miso);
+ u_mm_file_reg_eth_0_reg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_REG")
+ PORT MAP(mm_rst, mm_clk, i_eth_0_reg_mosi, eth_0_reg_miso);
+ u_mm_file_reg_eth_0_ram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_RAM")
+ PORT MAP(mm_rst, mm_clk, eth_0_ram_mosi, eth_0_ram_miso);
-- . 1GbE_II with TSE setup in VHDL
- u_mm_file_reg_eth1_tse : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_TSE")
- PORT MAP(mm_rst, mm_clk, eth1g_eth1_tse_mosi, eth1g_eth1_tse_miso);
+ u_mm_file_reg_eth_1_tse : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_TSE")
+ PORT MAP(mm_rst, mm_clk, eth_1_tse_mosi, eth_1_tse_miso);
u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
@@ -370,31 +370,31 @@ BEGIN
u_mm_file_ram_scrap : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
PORT MAP(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
- u_mm_file_reg_eth1g_I_bg_ctrl : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_I_BG_CTRL")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_I_bg_ctrl_copi, reg_eth1g_I_bg_ctrl_cipo );
- u_mm_file_reg_eth1g_I_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_I_HDR_DAT")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_I_hdr_dat_copi, reg_eth1g_I_hdr_dat_cipo );
- u_mm_file_reg_eth1g_I_bsn_monitor_v2_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_I_BSN_MONITOR_V2_TX")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_I_bsn_monitor_v2_tx_copi, reg_eth1g_I_bsn_monitor_v2_tx_cipo );
- u_mm_file_reg_eth1g_I_strobe_total_count_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_I_STROBE_TOTAL_COUNT_TX")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_I_strobe_total_count_tx_copi, reg_eth1g_I_strobe_total_count_tx_cipo );
- u_mm_file_reg_eth1g_I_bsn_monitor_v2_rx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_I_BSN_MONITOR_V2_RX")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_I_bsn_monitor_v2_rx_copi, reg_eth1g_I_bsn_monitor_v2_rx_cipo );
- u_mm_file_reg_eth1g_I_strobe_total_count_rx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_I_STROBE_TOTAL_COUNT_RX")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_I_strobe_total_count_rx_copi, reg_eth1g_I_strobe_total_count_rx_cipo );
-
- u_mm_file_reg_eth1g_II_bg_ctrl : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_II_BG_CTRL")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_II_bg_ctrl_copi, reg_eth1g_II_bg_ctrl_cipo );
- u_mm_file_reg_eth1g_II_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_II_HDR_DAT")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_II_hdr_dat_copi, reg_eth1g_II_hdr_dat_cipo );
- u_mm_file_reg_eth1g_II_bsn_monitor_v2_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_II_BSN_MONITOR_V2_TX")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_II_bsn_monitor_v2_tx_copi, reg_eth1g_II_bsn_monitor_v2_tx_cipo );
- u_mm_file_reg_eth1g_II_strobe_total_count_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_II_STROBE_TOTAL_COUNT_TX")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_II_strobe_total_count_tx_copi, reg_eth1g_II_strobe_total_count_tx_cipo );
- u_mm_file_reg_eth1g_II_bsn_monitor_v2_rx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_II_BSN_MONITOR_V2_RX")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_II_bsn_monitor_v2_rx_copi, reg_eth1g_II_bsn_monitor_v2_rx_cipo );
- u_mm_file_reg_eth1g_II_strobe_total_count_rx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH1G_II_STROBE_TOTAL_COUNT_RX")
- PORT MAP(mm_rst, mm_clk, reg_eth1g_II_strobe_total_count_rx_copi, reg_eth1g_II_strobe_total_count_rx_cipo );
+ u_mm_file_reg_reg_diag_bg_eth_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_ETH_0")
+ PORT MAP(mm_rst, mm_clk, reg_diag_bg_eth_0_copi, reg_diag_bg_eth_0_cipo );
+ u_mm_file_reg_hdr_dat_eth_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT_ETH_0")
+ PORT MAP(mm_rst, mm_clk, reg_hdr_dat_eth_0_copi, reg_hdr_dat_eth_0_cipo );
+ u_mm_file_reg_bsn_monitor_v2_tx_eth_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX_ETH_0")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_eth_0_copi, reg_bsn_monitor_v2_tx_eth_0_cipo );
+ u_mm_file_reg_strobe_total_count_tx_eth_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_TX_ETH_0")
+ PORT MAP(mm_rst, mm_clk, reg_strobe_total_count_tx_eth_0_copi, reg_strobe_total_count_tx_eth_0_cipo );
+ u_mm_file_reg_bsn_monitor_v2_rx_eth_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ETH_0")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_eth_0_copi, reg_bsn_monitor_v2_rx_eth_0_cipo );
+ u_mm_file_reg_strobe_total_count_rx_eth_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_RX_ETH_0")
+ PORT MAP(mm_rst, mm_clk, reg_strobe_total_count_rx_eth_0_copi, reg_strobe_total_count_rx_eth_0_cipo );
+
+ u_mm_file_reg_reg_diag_bg_eth_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_ETH_1")
+ PORT MAP(mm_rst, mm_clk, reg_diag_bg_eth_1_copi, reg_diag_bg_eth_1_cipo );
+ u_mm_file_reg_hdr_dat_eth_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT_ETH_1")
+ PORT MAP(mm_rst, mm_clk, reg_hdr_dat_eth_1_copi, reg_hdr_dat_eth_1_cipo );
+ u_mm_file_reg_bsn_monitor_v2_tx_eth_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX_ETH_1")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_eth_1_copi, reg_bsn_monitor_v2_tx_eth_1_cipo );
+ u_mm_file_reg_strobe_total_count_tx_eth_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_TX_ETH_1")
+ PORT MAP(mm_rst, mm_clk, reg_strobe_total_count_tx_eth_1_copi, reg_strobe_total_count_tx_eth_1_cipo );
+ u_mm_file_reg_bsn_monitor_v2_rx_eth_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ETH_1")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_eth_1_copi, reg_bsn_monitor_v2_rx_eth_1_cipo );
+ u_mm_file_reg_strobe_total_count_rx_eth_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_RX_ETH_1")
+ PORT MAP(mm_rst, mm_clk, reg_strobe_total_count_rx_eth_1_copi, reg_strobe_total_count_rx_eth_1_cipo );
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -403,25 +403,25 @@ BEGIN
BEGIN
sim_eth_mm_bus_switch <= '1';
- eth1g_eth0_tse_mosi.wr <= '0';
- eth1g_eth0_tse_mosi.rd <= '0';
+ eth_0_tse_mosi.wr <= '0';
+ eth_0_tse_mosi.rd <= '0';
WAIT FOR 400 ns;
WAIT UNTIL rising_edge(mm_clk);
- proc_tech_tse_setup(c_tech_arria10_e1sg, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_eth0_tse_miso, eth1g_eth0_tse_mosi);
+ proc_tech_tse_setup(c_tech_arria10_e1sg, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth_0_tse_miso, eth_0_tse_mosi);
-- Enable RX
- proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, mm_clk, eth1g_eth0_reg_miso, sim_eth1g_eth0_reg_mosi); -- control rx en
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, mm_clk, eth_0_reg_miso, sim_eth_0_reg_mosi); -- control rx en
sim_eth_mm_bus_switch <= '0';
WAIT;
END PROCESS;
- p_switch : PROCESS(sim_eth_mm_bus_switch, sim_eth1g_eth0_reg_mosi, i_eth1g_eth0_reg_mosi)
+ p_switch : PROCESS(sim_eth_mm_bus_switch, sim_eth_0_reg_mosi, i_eth_0_reg_mosi)
BEGIN
IF sim_eth_mm_bus_switch = '1' THEN
- eth1g_eth0_reg_mosi <= sim_eth1g_eth0_reg_mosi;
+ eth_0_reg_mosi <= sim_eth_0_reg_mosi;
ELSE
- eth1g_eth0_reg_mosi <= i_eth1g_eth0_reg_mosi;
+ eth_0_reg_mosi <= i_eth_0_reg_mosi;
END IF;
END PROCESS;
@@ -449,45 +449,45 @@ BEGIN
-- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2c_board.
pio_wdi_external_connection_export => pout_wdi,
- avs_eth_0_reset_export => eth1g_eth0_mm_rst,
+ avs_eth_0_reset_export => eth_0_mm_rst,
avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_eth0_tse_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
- avs_eth_0_tse_write_export => eth1g_eth0_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_eth0_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_eth0_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_0_tse_readdata_export => eth1g_eth0_tse_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_0_tse_waitrequest_export => eth1g_eth0_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_eth0_reg_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
- avs_eth_0_reg_write_export => eth1g_eth0_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_eth0_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_eth0_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_0_reg_readdata_export => eth1g_eth0_reg_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_0_ram_address_export => eth1g_eth0_ram_mosi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
- avs_eth_0_ram_write_export => eth1g_eth0_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_eth0_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_eth0_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_0_ram_readdata_export => eth1g_eth0_ram_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_0_irq_export => eth1g_eth0_reg_interrupt,
-
- avs2_eth_coe_1_reset_export => eth1g_eth1_mm_rst,
- avs2_eth_coe_1_clk_export => OPEN,
- avs2_eth_coe_1_tse_address_export => eth1g_eth1_tse_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
- avs2_eth_coe_1_tse_write_export => eth1g_eth1_tse_mosi.wr,
- avs2_eth_coe_1_tse_read_export => eth1g_eth1_tse_mosi.rd,
- avs2_eth_coe_1_tse_writedata_export => eth1g_eth1_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs2_eth_coe_1_tse_readdata_export => eth1g_eth1_tse_miso.rddata(c_word_w-1 DOWNTO 0),
- avs2_eth_coe_1_tse_waitrequest_export => eth1g_eth1_tse_miso.waitrequest,
- avs2_eth_coe_1_reg_address_export => eth1g_eth1_reg_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
- avs2_eth_coe_1_reg_write_export => eth1g_eth1_reg_mosi.wr,
- avs2_eth_coe_1_reg_read_export => eth1g_eth1_reg_mosi.rd,
- avs2_eth_coe_1_reg_writedata_export => eth1g_eth1_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs2_eth_coe_1_reg_readdata_export => eth1g_eth1_reg_miso.rddata(c_word_w-1 DOWNTO 0),
- avs2_eth_coe_1_ram_address_export => eth1g_eth1_ram_mosi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
- avs2_eth_coe_1_ram_write_export => eth1g_eth1_ram_mosi.wr,
- avs2_eth_coe_1_ram_read_export => eth1g_eth1_ram_mosi.rd,
- avs2_eth_coe_1_ram_writedata_export => eth1g_eth1_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs2_eth_coe_1_ram_readdata_export => eth1g_eth1_ram_miso.rddata(c_word_w-1 DOWNTO 0),
- avs2_eth_coe_1_irq_export => eth1g_eth1_reg_interrupt,
+ avs_eth_0_tse_address_export => eth_0_tse_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ avs_eth_0_tse_write_export => eth_0_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth_0_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth_0_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_tse_readdata_export => eth_0_tse_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_tse_waitrequest_export => eth_0_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth_0_reg_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_reg_write_export => eth_0_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth_0_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth_0_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_reg_readdata_export => eth_0_reg_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_ram_address_export => eth_0_ram_mosi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_ram_write_export => eth_0_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth_0_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth_0_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_ram_readdata_export => eth_0_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_irq_export => eth_0_reg_interrupt,
+
+ avs_eth_1_reset_export => eth_1_mm_rst,
+ avs_eth_1_clk_export => OPEN,
+ avs_eth_1_tse_address_export => eth_1_tse_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ avs_eth_1_tse_write_export => eth_1_tse_mosi.wr,
+ avs_eth_1_tse_read_export => eth_1_tse_mosi.rd,
+ avs_eth_1_tse_writedata_export => eth_1_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_1_tse_readdata_export => eth_1_tse_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_1_tse_waitrequest_export => eth_1_tse_miso.waitrequest,
+ avs_eth_1_reg_address_export => eth_1_reg_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ avs_eth_1_reg_write_export => eth_1_reg_mosi.wr,
+ avs_eth_1_reg_read_export => eth_1_reg_mosi.rd,
+ avs_eth_1_reg_writedata_export => eth_1_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_1_reg_readdata_export => eth_1_reg_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_1_ram_address_export => eth_1_ram_mosi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ avs_eth_1_ram_write_export => eth_1_ram_mosi.wr,
+ avs_eth_1_ram_read_export => eth_1_ram_mosi.rd,
+ avs_eth_1_ram_writedata_export => eth_1_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_1_ram_readdata_export => eth_1_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_1_irq_export => eth_1_reg_interrupt,
reg_fpga_temp_sens_reset_export => OPEN,
reg_fpga_temp_sens_clk_export => OPEN,
@@ -739,101 +739,101 @@ BEGIN
ram_diag_data_buffer_ddr_MB_II_read_export => ram_diag_data_buf_ddr_MB_II_mosi.rd,
ram_diag_data_buffer_ddr_MB_II_readdata_export => ram_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_eth1g_I_bg_ctrl_reset_export => OPEN,
- reg_eth1g_I_bg_ctrl_clk_export => OPEN,
- reg_eth1g_I_bg_ctrl_address_export => reg_eth1g_I_bg_ctrl_copi.address(4 downto 0),
- reg_eth1g_I_bg_ctrl_write_export => reg_eth1g_I_bg_ctrl_copi.wr,
- reg_eth1g_I_bg_ctrl_writedata_export => reg_eth1g_I_bg_ctrl_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_I_bg_ctrl_read_export => reg_eth1g_I_bg_ctrl_copi.rd,
- reg_eth1g_I_bg_ctrl_readdata_export => reg_eth1g_I_bg_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_eth1g_I_hdr_dat_reset_export => OPEN,
- reg_eth1g_I_hdr_dat_clk_export => OPEN,
- reg_eth1g_I_hdr_dat_address_export => reg_eth1g_I_hdr_dat_copi.address(6 downto 0),
- reg_eth1g_I_hdr_dat_write_export => reg_eth1g_I_hdr_dat_copi.wr,
- reg_eth1g_I_hdr_dat_writedata_export => reg_eth1g_I_hdr_dat_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_I_hdr_dat_read_export => reg_eth1g_I_hdr_dat_copi.rd,
- reg_eth1g_I_hdr_dat_readdata_export => reg_eth1g_I_hdr_dat_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_eth1g_I_bsn_monitor_v2_tx_reset_export => OPEN,
- reg_eth1g_I_bsn_monitor_v2_tx_clk_export => OPEN,
- reg_eth1g_I_bsn_monitor_v2_tx_address_export => reg_eth1g_I_bsn_monitor_v2_tx_copi.address(4 downto 0),
- reg_eth1g_I_bsn_monitor_v2_tx_write_export => reg_eth1g_I_bsn_monitor_v2_tx_copi.wr,
- reg_eth1g_I_bsn_monitor_v2_tx_writedata_export => reg_eth1g_I_bsn_monitor_v2_tx_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_I_bsn_monitor_v2_tx_read_export => reg_eth1g_I_bsn_monitor_v2_tx_copi.rd,
- reg_eth1g_I_bsn_monitor_v2_tx_readdata_export => reg_eth1g_I_bsn_monitor_v2_tx_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_eth1g_I_strobe_total_count_tx_reset_export => OPEN,
- reg_eth1g_I_strobe_total_count_tx_clk_export => OPEN,
- reg_eth1g_I_strobe_total_count_tx_address_export => reg_eth1g_I_strobe_total_count_tx_copi.address(6 downto 0),
- reg_eth1g_I_strobe_total_count_tx_write_export => reg_eth1g_I_strobe_total_count_tx_copi.wr,
- reg_eth1g_I_strobe_total_count_tx_writedata_export => reg_eth1g_I_strobe_total_count_tx_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_I_strobe_total_count_tx_read_export => reg_eth1g_I_strobe_total_count_tx_copi.rd,
- reg_eth1g_I_strobe_total_count_tx_readdata_export => reg_eth1g_I_strobe_total_count_tx_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_eth1g_I_bsn_monitor_v2_rx_reset_export => OPEN,
- reg_eth1g_I_bsn_monitor_v2_rx_clk_export => OPEN,
- reg_eth1g_I_bsn_monitor_v2_rx_address_export => reg_eth1g_I_bsn_monitor_v2_rx_copi.address(4 downto 0),
- reg_eth1g_I_bsn_monitor_v2_rx_write_export => reg_eth1g_I_bsn_monitor_v2_rx_copi.wr,
- reg_eth1g_I_bsn_monitor_v2_rx_writedata_export => reg_eth1g_I_bsn_monitor_v2_rx_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_I_bsn_monitor_v2_rx_read_export => reg_eth1g_I_bsn_monitor_v2_rx_copi.rd,
- reg_eth1g_I_bsn_monitor_v2_rx_readdata_export => reg_eth1g_I_bsn_monitor_v2_rx_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_eth1g_I_strobe_total_count_rx_reset_export => OPEN,
- reg_eth1g_I_strobe_total_count_rx_clk_export => OPEN,
- reg_eth1g_I_strobe_total_count_rx_address_export => reg_eth1g_I_strobe_total_count_rx_copi.address(6 downto 0),
- reg_eth1g_I_strobe_total_count_rx_write_export => reg_eth1g_I_strobe_total_count_rx_copi.wr,
- reg_eth1g_I_strobe_total_count_rx_writedata_export => reg_eth1g_I_strobe_total_count_rx_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_I_strobe_total_count_rx_read_export => reg_eth1g_I_strobe_total_count_rx_copi.rd,
- reg_eth1g_I_strobe_total_count_rx_readdata_export => reg_eth1g_I_strobe_total_count_rx_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_eth1g_II_bg_ctrl_reset_export => OPEN,
- reg_eth1g_II_bg_ctrl_clk_export => OPEN,
- reg_eth1g_II_bg_ctrl_address_export => reg_eth1g_II_bg_ctrl_copi.address(2 downto 0),
- reg_eth1g_II_bg_ctrl_write_export => reg_eth1g_II_bg_ctrl_copi.wr,
- reg_eth1g_II_bg_ctrl_writedata_export => reg_eth1g_II_bg_ctrl_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_II_bg_ctrl_read_export => reg_eth1g_II_bg_ctrl_copi.rd,
- reg_eth1g_II_bg_ctrl_readdata_export => reg_eth1g_II_bg_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_eth1g_II_hdr_dat_reset_export => OPEN,
- reg_eth1g_II_hdr_dat_clk_export => OPEN,
- reg_eth1g_II_hdr_dat_address_export => reg_eth1g_II_hdr_dat_copi.address(4 downto 0),
- reg_eth1g_II_hdr_dat_write_export => reg_eth1g_II_hdr_dat_copi.wr,
- reg_eth1g_II_hdr_dat_writedata_export => reg_eth1g_II_hdr_dat_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_II_hdr_dat_read_export => reg_eth1g_II_hdr_dat_copi.rd,
- reg_eth1g_II_hdr_dat_readdata_export => reg_eth1g_II_hdr_dat_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_eth1g_II_bsn_monitor_v2_tx_reset_export => OPEN,
- reg_eth1g_II_bsn_monitor_v2_tx_clk_export => OPEN,
- reg_eth1g_II_bsn_monitor_v2_tx_address_export => reg_eth1g_II_bsn_monitor_v2_tx_copi.address(2 downto 0),
- reg_eth1g_II_bsn_monitor_v2_tx_write_export => reg_eth1g_II_bsn_monitor_v2_tx_copi.wr,
- reg_eth1g_II_bsn_monitor_v2_tx_writedata_export => reg_eth1g_II_bsn_monitor_v2_tx_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_II_bsn_monitor_v2_tx_read_export => reg_eth1g_II_bsn_monitor_v2_tx_copi.rd,
- reg_eth1g_II_bsn_monitor_v2_tx_readdata_export => reg_eth1g_II_bsn_monitor_v2_tx_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_eth1g_II_strobe_total_count_tx_reset_export => OPEN,
- reg_eth1g_II_strobe_total_count_tx_clk_export => OPEN,
- reg_eth1g_II_strobe_total_count_tx_address_export => reg_eth1g_II_strobe_total_count_tx_copi.address(4 downto 0),
- reg_eth1g_II_strobe_total_count_tx_write_export => reg_eth1g_II_strobe_total_count_tx_copi.wr,
- reg_eth1g_II_strobe_total_count_tx_writedata_export => reg_eth1g_II_strobe_total_count_tx_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_II_strobe_total_count_tx_read_export => reg_eth1g_II_strobe_total_count_tx_copi.rd,
- reg_eth1g_II_strobe_total_count_tx_readdata_export => reg_eth1g_II_strobe_total_count_tx_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_eth1g_II_bsn_monitor_v2_rx_reset_export => OPEN,
- reg_eth1g_II_bsn_monitor_v2_rx_clk_export => OPEN,
- reg_eth1g_II_bsn_monitor_v2_rx_address_export => reg_eth1g_II_bsn_monitor_v2_rx_copi.address(2 downto 0),
- reg_eth1g_II_bsn_monitor_v2_rx_write_export => reg_eth1g_II_bsn_monitor_v2_rx_copi.wr,
- reg_eth1g_II_bsn_monitor_v2_rx_writedata_export => reg_eth1g_II_bsn_monitor_v2_rx_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_II_bsn_monitor_v2_rx_read_export => reg_eth1g_II_bsn_monitor_v2_rx_copi.rd,
- reg_eth1g_II_bsn_monitor_v2_rx_readdata_export => reg_eth1g_II_bsn_monitor_v2_rx_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_eth1g_II_strobe_total_count_rx_reset_export => OPEN,
- reg_eth1g_II_strobe_total_count_rx_clk_export => OPEN,
- reg_eth1g_II_strobe_total_count_rx_address_export => reg_eth1g_II_strobe_total_count_rx_copi.address(4 downto 0),
- reg_eth1g_II_strobe_total_count_rx_write_export => reg_eth1g_II_strobe_total_count_rx_copi.wr,
- reg_eth1g_II_strobe_total_count_rx_writedata_export => reg_eth1g_II_strobe_total_count_rx_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_eth1g_II_strobe_total_count_rx_read_export => reg_eth1g_II_strobe_total_count_rx_copi.rd,
- reg_eth1g_II_strobe_total_count_rx_readdata_export => reg_eth1g_II_strobe_total_count_rx_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_bg_eth_0_reset_export => OPEN,
+ reg_diag_bg_eth_0_clk_export => OPEN,
+ reg_diag_bg_eth_0_address_export => reg_diag_bg_eth_0_copi.address(4 downto 0),
+ reg_diag_bg_eth_0_write_export => reg_diag_bg_eth_0_copi.wr,
+ reg_diag_bg_eth_0_writedata_export => reg_diag_bg_eth_0_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_bg_eth_0_read_export => reg_diag_bg_eth_0_copi.rd,
+ reg_diag_bg_eth_0_readdata_export => reg_diag_bg_eth_0_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_hdr_dat_eth_0_reset_export => OPEN,
+ reg_hdr_dat_eth_0_clk_export => OPEN,
+ reg_hdr_dat_eth_0_address_export => reg_hdr_dat_eth_0_copi.address(6 downto 0),
+ reg_hdr_dat_eth_0_write_export => reg_hdr_dat_eth_0_copi.wr,
+ reg_hdr_dat_eth_0_writedata_export => reg_hdr_dat_eth_0_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_hdr_dat_eth_0_read_export => reg_hdr_dat_eth_0_copi.rd,
+ reg_hdr_dat_eth_0_readdata_export => reg_hdr_dat_eth_0_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_tx_eth_0_reset_export => OPEN,
+ reg_bsn_monitor_v2_tx_eth_0_clk_export => OPEN,
+ reg_bsn_monitor_v2_tx_eth_0_address_export => reg_bsn_monitor_v2_tx_eth_0_copi.address(4 downto 0),
+ reg_bsn_monitor_v2_tx_eth_0_write_export => reg_bsn_monitor_v2_tx_eth_0_copi.wr,
+ reg_bsn_monitor_v2_tx_eth_0_writedata_export => reg_bsn_monitor_v2_tx_eth_0_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_tx_eth_0_read_export => reg_bsn_monitor_v2_tx_eth_0_copi.rd,
+ reg_bsn_monitor_v2_tx_eth_0_readdata_export => reg_bsn_monitor_v2_tx_eth_0_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_strobe_total_count_tx_eth_0_reset_export => OPEN,
+ reg_strobe_total_count_tx_eth_0_clk_export => OPEN,
+ reg_strobe_total_count_tx_eth_0_address_export => reg_strobe_total_count_tx_eth_0_copi.address(6 downto 0),
+ reg_strobe_total_count_tx_eth_0_write_export => reg_strobe_total_count_tx_eth_0_copi.wr,
+ reg_strobe_total_count_tx_eth_0_writedata_export => reg_strobe_total_count_tx_eth_0_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_strobe_total_count_tx_eth_0_read_export => reg_strobe_total_count_tx_eth_0_copi.rd,
+ reg_strobe_total_count_tx_eth_0_readdata_export => reg_strobe_total_count_tx_eth_0_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_rx_eth_0_reset_export => OPEN,
+ reg_bsn_monitor_v2_rx_eth_0_clk_export => OPEN,
+ reg_bsn_monitor_v2_rx_eth_0_address_export => reg_bsn_monitor_v2_rx_eth_0_copi.address(4 downto 0),
+ reg_bsn_monitor_v2_rx_eth_0_write_export => reg_bsn_monitor_v2_rx_eth_0_copi.wr,
+ reg_bsn_monitor_v2_rx_eth_0_writedata_export => reg_bsn_monitor_v2_rx_eth_0_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_rx_eth_0_read_export => reg_bsn_monitor_v2_rx_eth_0_copi.rd,
+ reg_bsn_monitor_v2_rx_eth_0_readdata_export => reg_bsn_monitor_v2_rx_eth_0_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_strobe_total_count_rx_eth_0_reset_export => OPEN,
+ reg_strobe_total_count_rx_eth_0_clk_export => OPEN,
+ reg_strobe_total_count_rx_eth_0_address_export => reg_strobe_total_count_rx_eth_0_copi.address(6 downto 0),
+ reg_strobe_total_count_rx_eth_0_write_export => reg_strobe_total_count_rx_eth_0_copi.wr,
+ reg_strobe_total_count_rx_eth_0_writedata_export => reg_strobe_total_count_rx_eth_0_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_strobe_total_count_rx_eth_0_read_export => reg_strobe_total_count_rx_eth_0_copi.rd,
+ reg_strobe_total_count_rx_eth_0_readdata_export => reg_strobe_total_count_rx_eth_0_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_diag_bg_eth_1_reset_export => OPEN,
+ reg_diag_bg_eth_1_clk_export => OPEN,
+ reg_diag_bg_eth_1_address_export => reg_diag_bg_eth_1_copi.address(2 downto 0),
+ reg_diag_bg_eth_1_write_export => reg_diag_bg_eth_1_copi.wr,
+ reg_diag_bg_eth_1_writedata_export => reg_diag_bg_eth_1_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_bg_eth_1_read_export => reg_diag_bg_eth_1_copi.rd,
+ reg_diag_bg_eth_1_readdata_export => reg_diag_bg_eth_1_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_hdr_dat_eth_1_reset_export => OPEN,
+ reg_hdr_dat_eth_1_clk_export => OPEN,
+ reg_hdr_dat_eth_1_address_export => reg_hdr_dat_eth_1_copi.address(4 downto 0),
+ reg_hdr_dat_eth_1_write_export => reg_hdr_dat_eth_1_copi.wr,
+ reg_hdr_dat_eth_1_writedata_export => reg_hdr_dat_eth_1_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_hdr_dat_eth_1_read_export => reg_hdr_dat_eth_1_copi.rd,
+ reg_hdr_dat_eth_1_readdata_export => reg_hdr_dat_eth_1_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_tx_eth_1_reset_export => OPEN,
+ reg_bsn_monitor_v2_tx_eth_1_clk_export => OPEN,
+ reg_bsn_monitor_v2_tx_eth_1_address_export => reg_bsn_monitor_v2_tx_eth_1_copi.address(2 downto 0),
+ reg_bsn_monitor_v2_tx_eth_1_write_export => reg_bsn_monitor_v2_tx_eth_1_copi.wr,
+ reg_bsn_monitor_v2_tx_eth_1_writedata_export => reg_bsn_monitor_v2_tx_eth_1_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_tx_eth_1_read_export => reg_bsn_monitor_v2_tx_eth_1_copi.rd,
+ reg_bsn_monitor_v2_tx_eth_1_readdata_export => reg_bsn_monitor_v2_tx_eth_1_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_strobe_total_count_tx_eth_1_reset_export => OPEN,
+ reg_strobe_total_count_tx_eth_1_clk_export => OPEN,
+ reg_strobe_total_count_tx_eth_1_address_export => reg_strobe_total_count_tx_eth_1_copi.address(4 downto 0),
+ reg_strobe_total_count_tx_eth_1_write_export => reg_strobe_total_count_tx_eth_1_copi.wr,
+ reg_strobe_total_count_tx_eth_1_writedata_export => reg_strobe_total_count_tx_eth_1_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_strobe_total_count_tx_eth_1_read_export => reg_strobe_total_count_tx_eth_1_copi.rd,
+ reg_strobe_total_count_tx_eth_1_readdata_export => reg_strobe_total_count_tx_eth_1_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_rx_eth_1_reset_export => OPEN,
+ reg_bsn_monitor_v2_rx_eth_1_clk_export => OPEN,
+ reg_bsn_monitor_v2_rx_eth_1_address_export => reg_bsn_monitor_v2_rx_eth_1_copi.address(2 downto 0),
+ reg_bsn_monitor_v2_rx_eth_1_write_export => reg_bsn_monitor_v2_rx_eth_1_copi.wr,
+ reg_bsn_monitor_v2_rx_eth_1_writedata_export => reg_bsn_monitor_v2_rx_eth_1_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_rx_eth_1_read_export => reg_bsn_monitor_v2_rx_eth_1_copi.rd,
+ reg_bsn_monitor_v2_rx_eth_1_readdata_export => reg_bsn_monitor_v2_rx_eth_1_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_strobe_total_count_rx_eth_1_reset_export => OPEN,
+ reg_strobe_total_count_rx_eth_1_clk_export => OPEN,
+ reg_strobe_total_count_rx_eth_1_address_export => reg_strobe_total_count_rx_eth_1_copi.address(4 downto 0),
+ reg_strobe_total_count_rx_eth_1_write_export => reg_strobe_total_count_rx_eth_1_copi.wr,
+ reg_strobe_total_count_rx_eth_1_writedata_export => reg_strobe_total_count_rx_eth_1_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_strobe_total_count_rx_eth_1_read_export => reg_strobe_total_count_rx_eth_1_copi.rd,
+ reg_strobe_total_count_rx_eth_1_readdata_export => reg_strobe_total_count_rx_eth_1_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_heater_reset_export => OPEN,
reg_heater_clk_export => OPEN,
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
index 69aecc3a18..7a5dcff23a 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
@@ -135,8 +135,8 @@ ARCHITECTURE str OF unb2c_test IS
-- Revision controlled constants
CONSTANT c_revision_select : t_unb2c_test_config := func_sel_revision_rec(g_design_name);
CONSTANT c_use_loopback : BOOLEAN := c_revision_select.use_loopback;
- CONSTANT c_use_1GbE_I_UDP : BOOLEAN := c_revision_select.use_1GbE_I_UDP; -- Enable the UDP offload ports on eth0, eth0 is always enabled for control
- CONSTANT c_use_1GbE_II : BOOLEAN := c_revision_select.use_1GbE_II; -- Enable the second 1GbE eth1
+ CONSTANT c_use_eth_0_UDP : BOOLEAN := c_revision_select.use_1GbE_I_UDP; -- Enable the UDP offload ports on 1GbE-I = eth_0, eth_0 is always enabled for control
+ CONSTANT c_use_eth_1 : BOOLEAN := c_revision_select.use_1GbE_II; -- Enable the second 1GbE-II = eth_1
CONSTANT c_use_10GbE_qsfp : BOOLEAN := c_revision_select.use_10GbE_qsfp;
CONSTANT c_use_10GbE_ring : BOOLEAN := c_revision_select.use_10GbE_ring;
CONSTANT c_use_10GbE_back0 : BOOLEAN := c_revision_select.use_10GbE_back0;
@@ -155,10 +155,10 @@ ARCHITECTURE str OF unb2c_test IS
CONSTANT c_nof_jesd204b : NATURAL := c_unb2c_board_tr_jesd204b.nof_bus * c_unb2c_board_tr_jesd204b.bus_w;
-- 1GbE
- CONSTANT c_nof_udp_streams_1GbE_I : NATURAL := 4; -- <= c_eth_nof_udp_ports = 4, shared with M&C stream
- CONSTANT c_nof_udp_streams_1GbE_I_w : NATURAL := 2; -- = true_log2(c_nof_udp_streams_1GbE_I), fixed reserve 2 bit extra MM address space
- CONSTANT c_nof_udp_streams_1GbE_II : NATURAL := 1; -- fixed 1 UDP stream, so no need for dp_mux
- CONSTANT c_nof_udp_streams_1GbE_II_w : NATURAL := 0; -- = true_log2(c_nof_udp_streams_1GbE_II), fixed reserve no extra MM address space
+ CONSTANT c_nof_udp_streams_eth_0 : NATURAL := 4; -- <= c_eth_nof_udp_ports = 4, shared with M&C stream
+ CONSTANT c_nof_udp_streams_eth_0_w : NATURAL := 2; -- = true_log2(c_nof_udp_streams_eth_0), fixed reserve 2 bit extra MM address space
+ CONSTANT c_nof_udp_streams_eth_1 : NATURAL := 1; -- fixed 1 UDP stream, so no need for dp_mux
+ CONSTANT c_nof_udp_streams_eth_1_w : NATURAL := 0; -- = true_log2(c_nof_udp_streams_eth_1), fixed reserve no extra MM address space
CONSTANT c_base_mac : STD_LOGIC_VECTOR(32-1 DOWNTO 0) := c_eth_tester_eth_src_mac_47_16; -- = X"00228608"
CONSTANT c_base_ip : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := c_eth_tester_ip_src_addr_31_16; -- = X"0A63"
CONSTANT c_base_udp : STD_LOGIC_VECTOR(8-1 DOWNTO 0) := c_eth_tester_udp_src_port_15_8; -- = X"E0"
@@ -259,19 +259,19 @@ ARCHITECTURE str OF unb2c_test IS
SIGNAL reg_fpga_voltage_sens_miso : t_mem_miso;
-- eth1g ch0
- SIGNAL eth1g_eth0_mm_rst : STD_LOGIC;
- SIGNAL eth1g_eth0_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
- SIGNAL eth1g_eth0_tse_miso : t_mem_miso;
- SIGNAL eth1g_eth0_reg_mosi : t_mem_mosi; -- ETH control and status registers
- SIGNAL eth1g_eth0_reg_miso : t_mem_miso;
- SIGNAL eth1g_eth0_reg_interrupt : STD_LOGIC; -- Interrupt
- SIGNAL eth1g_eth0_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
- SIGNAL eth1g_eth0_ram_miso : t_mem_miso;
+ SIGNAL eth_0_mm_rst : STD_LOGIC;
+ SIGNAL eth_0_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ SIGNAL eth_0_tse_miso : t_mem_miso;
+ SIGNAL eth_0_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ SIGNAL eth_0_reg_miso : t_mem_miso;
+ SIGNAL eth_0_reg_interrupt : STD_LOGIC; -- Interrupt
+ SIGNAL eth_0_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ SIGNAL eth_0_ram_miso : t_mem_miso;
-- eth1g ch1 (eth_stream only has MM for TSE MAC)
- SIGNAL eth1g_eth1_mm_rst : STD_LOGIC;
- SIGNAL eth1g_eth1_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
- SIGNAL eth1g_eth1_tse_miso : t_mem_miso;
+ SIGNAL eth_1_mm_rst : STD_LOGIC;
+ SIGNAL eth_1_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ SIGNAL eth_1_tse_miso : t_mem_miso;
-- EPCS read
SIGNAL reg_dpmm_data_mosi : t_mem_mosi;
@@ -355,37 +355,37 @@ ARCHITECTURE str OF unb2c_test IS
SIGNAL reg_eth10g_back0_mosi : t_mem_mosi;
SIGNAL reg_eth10g_back0_miso : t_mem_miso;
- -- 1GbE I eth_tester (c_nof_udp_streams_1GbE_I_w = 2 bit)
+ -- 1GbE I eth_tester (c_nof_udp_streams_eth_0_w = 2 bit)
-- . Tx
- SIGNAL reg_eth1g_I_bg_ctrl_copi : t_mem_copi := c_mem_copi_rst; -- c_diag_bg_reg_adr_w = 3 --> w = 5
- SIGNAL reg_eth1g_I_bg_ctrl_cipo : t_mem_cipo;
- SIGNAL reg_eth1g_I_hdr_dat_copi : t_mem_copi := c_mem_copi_rst; -- c_eth_tester_reg_hdr_dat_addr_w = 5 --> w = 7
- SIGNAL reg_eth1g_I_hdr_dat_cipo : t_mem_cipo;
- SIGNAL reg_eth1g_I_bsn_monitor_v2_tx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 5
- SIGNAL reg_eth1g_I_bsn_monitor_v2_tx_cipo : t_mem_cipo;
- SIGNAL reg_eth1g_I_strobe_total_count_tx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 7
- SIGNAL reg_eth1g_I_strobe_total_count_tx_cipo : t_mem_cipo;
+ SIGNAL reg_diag_bg_eth_0_copi : t_mem_copi := c_mem_copi_rst; -- c_diag_bg_reg_adr_w = 3 --> w = 5
+ SIGNAL reg_diag_bg_eth_0_cipo : t_mem_cipo;
+ SIGNAL reg_hdr_dat_eth_0_copi : t_mem_copi := c_mem_copi_rst; -- c_eth_tester_reg_hdr_dat_addr_w = 5 --> w = 7
+ SIGNAL reg_hdr_dat_eth_0_cipo : t_mem_cipo;
+ SIGNAL reg_bsn_monitor_v2_tx_eth_0_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 5
+ SIGNAL reg_bsn_monitor_v2_tx_eth_0_cipo : t_mem_cipo;
+ SIGNAL reg_strobe_total_count_tx_eth_0_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 7
+ SIGNAL reg_strobe_total_count_tx_eth_0_cipo : t_mem_cipo;
-- . Rx
- SIGNAL reg_eth1g_I_bsn_monitor_v2_rx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 5
- SIGNAL reg_eth1g_I_bsn_monitor_v2_rx_cipo : t_mem_cipo;
- SIGNAL reg_eth1g_I_strobe_total_count_rx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 7
- SIGNAL reg_eth1g_I_strobe_total_count_rx_cipo : t_mem_cipo;
+ SIGNAL reg_bsn_monitor_v2_rx_eth_0_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 5
+ SIGNAL reg_bsn_monitor_v2_rx_eth_0_cipo : t_mem_cipo;
+ SIGNAL reg_strobe_total_count_rx_eth_0_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 7
+ SIGNAL reg_strobe_total_count_rx_eth_0_cipo : t_mem_cipo;
- -- 1GbE II eth_tester (c_nof_udp_streams_1GbE_I_w = 0 bit)
+ -- 1GbE II eth_tester (c_nof_udp_streams_eth_1_w = 0 bit)
-- . Tx
- SIGNAL reg_eth1g_II_bg_ctrl_copi : t_mem_copi := c_mem_copi_rst; -- c_diag_bg_reg_adr_w = 3 --> w = 3
- SIGNAL reg_eth1g_II_bg_ctrl_cipo : t_mem_cipo;
- SIGNAL reg_eth1g_II_hdr_dat_copi : t_mem_copi := c_mem_copi_rst; -- c_eth_tester_reg_hdr_dat_addr_w = 5 --> w = 5
- SIGNAL reg_eth1g_II_hdr_dat_cipo : t_mem_cipo;
- SIGNAL reg_eth1g_II_bsn_monitor_v2_tx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 3
- SIGNAL reg_eth1g_II_bsn_monitor_v2_tx_cipo : t_mem_cipo;
- SIGNAL reg_eth1g_II_strobe_total_count_tx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 5
- SIGNAL reg_eth1g_II_strobe_total_count_tx_cipo : t_mem_cipo;
+ SIGNAL reg_diag_bg_eth_1_copi : t_mem_copi := c_mem_copi_rst; -- c_diag_bg_reg_adr_w = 3 --> w = 3
+ SIGNAL reg_diag_bg_eth_1_cipo : t_mem_cipo;
+ SIGNAL reg_hdr_dat_eth_1_copi : t_mem_copi := c_mem_copi_rst; -- c_eth_tester_reg_hdr_dat_addr_w = 5 --> w = 5
+ SIGNAL reg_hdr_dat_eth_1_cipo : t_mem_cipo;
+ SIGNAL reg_bsn_monitor_v2_tx_eth_1_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 3
+ SIGNAL reg_bsn_monitor_v2_tx_eth_1_cipo : t_mem_cipo;
+ SIGNAL reg_strobe_total_count_tx_eth_1_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 5
+ SIGNAL reg_strobe_total_count_tx_eth_1_cipo : t_mem_cipo;
-- . Rx
- SIGNAL reg_eth1g_II_bsn_monitor_v2_rx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 3
- SIGNAL reg_eth1g_II_bsn_monitor_v2_rx_cipo : t_mem_cipo;
- SIGNAL reg_eth1g_II_strobe_total_count_rx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 5
- SIGNAL reg_eth1g_II_strobe_total_count_rx_cipo : t_mem_cipo;
+ SIGNAL reg_bsn_monitor_v2_rx_eth_1_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 3
+ SIGNAL reg_bsn_monitor_v2_rx_eth_1_cipo : t_mem_cipo;
+ SIGNAL reg_strobe_total_count_rx_eth_1_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 5
+ SIGNAL reg_strobe_total_count_rx_eth_1_cipo : t_mem_cipo;
-- 10GbE
SIGNAL reg_diag_bg_10GbE_mosi : t_mem_mosi;
@@ -442,25 +442,25 @@ ARCHITECTURE str OF unb2c_test IS
SIGNAL ram_diag_data_buf_ddr_MB_II_miso : t_mem_miso;
-- UDP streaming ports for 1GbE I and 1GbE II
- -- . 1GbE I
+ -- . eth_0 = 1GbE I
SIGNAL gn_eth_src_mac_I : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
SIGNAL gn_ip_src_addr_I : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
SIGNAL gn_udp_src_port_I : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
- SIGNAL eth1g_I_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_1GbE_I-1 DOWNTO 0);
- SIGNAL eth1g_I_udp_tx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_1GbE_I-1 DOWNTO 0);
- SIGNAL eth1g_I_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_1GbE_I-1 DOWNTO 0);
- SIGNAL eth1g_I_udp_rx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_1GbE_I-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ SIGNAL eth_0_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_eth_0-1 DOWNTO 0);
+ SIGNAL eth_0_udp_tx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_eth_0-1 DOWNTO 0);
+ SIGNAL eth_0_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_eth_0-1 DOWNTO 0);
+ SIGNAL eth_0_udp_rx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_eth_0-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
- -- . 1GbE II
+ -- . eth_1 = 1GbE II
SIGNAL gn_eth_src_mac_II : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
SIGNAL gn_ip_src_addr_II : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
SIGNAL gn_udp_src_port_II : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
- SIGNAL eth1g_II_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_1GbE_II-1 DOWNTO 0);
- SIGNAL eth1g_II_udp_tx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_1GbE_II-1 DOWNTO 0);
- SIGNAL eth1g_II_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_1GbE_II-1 DOWNTO 0);
- SIGNAL eth1g_II_udp_rx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_1GbE_II-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ SIGNAL eth_1_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_eth_1-1 DOWNTO 0);
+ SIGNAL eth_1_udp_tx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_eth_1-1 DOWNTO 0);
+ SIGNAL eth_1_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_eth_1-1 DOWNTO 0);
+ SIGNAL eth_1_udp_rx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_eth_1-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
-- QSFP leds
SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.nof_bus-1 DOWNTO 0);
@@ -489,8 +489,8 @@ BEGIN
g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
g_aux => c_unb2c_board_aux,
g_base_ip => c_base_ip, -- = X"0A63" is base IP address used by unb_osy: 10.99.xx.yy
- g_udp_offload => c_use_1GbE_I_UDP,
- g_udp_offload_nof_streams => c_nof_udp_streams_1GbE_I,
+ g_udp_offload => c_use_eth_0_UDP,
+ g_udp_offload_nof_streams => c_nof_udp_streams_eth_0,
g_factory_image => g_factory_image,
g_protect_addr_range => g_protect_addr_range
)
@@ -561,20 +561,20 @@ BEGIN
reg_ppsh_miso => reg_ppsh_miso,
-- eth1g ch0
- eth1g_mm_rst => eth1g_eth0_mm_rst,
- eth1g_tse_mosi => eth1g_eth0_tse_mosi,
- eth1g_tse_miso => eth1g_eth0_tse_miso,
- eth1g_reg_mosi => eth1g_eth0_reg_mosi,
- eth1g_reg_miso => eth1g_eth0_reg_miso,
- eth1g_reg_interrupt => eth1g_eth0_reg_interrupt,
- eth1g_ram_mosi => eth1g_eth0_ram_mosi,
- eth1g_ram_miso => eth1g_eth0_ram_miso,
+ eth1g_mm_rst => eth_0_mm_rst,
+ eth1g_tse_mosi => eth_0_tse_mosi,
+ eth1g_tse_miso => eth_0_tse_miso,
+ eth1g_reg_mosi => eth_0_reg_mosi,
+ eth1g_reg_miso => eth_0_reg_miso,
+ eth1g_reg_interrupt => eth_0_reg_interrupt,
+ eth1g_ram_mosi => eth_0_ram_mosi,
+ eth1g_ram_miso => eth_0_ram_miso,
-- eth1g UDP streaming ports
- udp_tx_sosi_arr => eth1g_I_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth1g_I_udp_tx_siso_arr,
- udp_rx_sosi_arr => eth1g_I_udp_rx_sosi_arr,
- udp_rx_siso_arr => eth1g_I_udp_rx_siso_arr,
+ udp_tx_sosi_arr => eth_0_udp_tx_sosi_arr,
+ udp_tx_siso_arr => eth_0_udp_tx_siso_arr,
+ udp_rx_sosi_arr => eth_0_udp_rx_sosi_arr,
+ udp_rx_siso_arr => eth_0_udp_rx_siso_arr,
-- scrap ram
ram_scrap_mosi => ram_scrap_mosi,
@@ -643,53 +643,53 @@ BEGIN
reg_ppsh_mosi => reg_ppsh_mosi,
reg_ppsh_miso => reg_ppsh_miso,
- -- eth1g ch0 = 1GbE_I
- eth1g_eth0_mm_rst => eth1g_eth0_mm_rst,
- eth1g_eth0_tse_mosi => eth1g_eth0_tse_mosi,
- eth1g_eth0_tse_miso => eth1g_eth0_tse_miso,
- eth1g_eth0_reg_mosi => eth1g_eth0_reg_mosi,
- eth1g_eth0_reg_miso => eth1g_eth0_reg_miso,
- eth1g_eth0_reg_interrupt => eth1g_eth0_reg_interrupt,
- eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
- eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
-
- reg_eth1g_I_bg_ctrl_copi => reg_eth1g_I_bg_ctrl_copi,
- reg_eth1g_I_bg_ctrl_cipo => reg_eth1g_I_bg_ctrl_cipo,
- reg_eth1g_I_hdr_dat_copi => reg_eth1g_I_hdr_dat_copi,
- reg_eth1g_I_hdr_dat_cipo => reg_eth1g_I_hdr_dat_cipo,
- reg_eth1g_I_bsn_monitor_v2_tx_copi => reg_eth1g_I_bsn_monitor_v2_tx_copi,
- reg_eth1g_I_bsn_monitor_v2_tx_cipo => reg_eth1g_I_bsn_monitor_v2_tx_cipo,
- reg_eth1g_I_strobe_total_count_tx_copi => reg_eth1g_I_strobe_total_count_tx_copi,
- reg_eth1g_I_strobe_total_count_tx_cipo => reg_eth1g_I_strobe_total_count_tx_cipo,
-
- reg_eth1g_I_bsn_monitor_v2_rx_copi => reg_eth1g_I_bsn_monitor_v2_rx_copi,
- reg_eth1g_I_bsn_monitor_v2_rx_cipo => reg_eth1g_I_bsn_monitor_v2_rx_cipo,
- reg_eth1g_I_strobe_total_count_rx_copi => reg_eth1g_I_strobe_total_count_rx_copi,
- reg_eth1g_I_strobe_total_count_rx_cipo => reg_eth1g_I_strobe_total_count_rx_cipo,
-
- -- eth1g ch1 = 1GbE_II
- eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
- eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
- eth1g_eth1_tse_miso => eth1g_eth1_tse_miso,
- eth1g_eth1_reg_mosi => OPEN,
- eth1g_eth1_reg_miso => c_mem_cipo_rst,
- eth1g_eth1_reg_interrupt => '0',
- eth1g_eth1_ram_mosi => OPEN,
- eth1g_eth1_ram_miso => c_mem_cipo_rst,
-
- reg_eth1g_II_bg_ctrl_copi => reg_eth1g_II_bg_ctrl_copi,
- reg_eth1g_II_bg_ctrl_cipo => reg_eth1g_II_bg_ctrl_cipo,
- reg_eth1g_II_hdr_dat_copi => reg_eth1g_II_hdr_dat_copi,
- reg_eth1g_II_hdr_dat_cipo => reg_eth1g_II_hdr_dat_cipo,
- reg_eth1g_II_bsn_monitor_v2_tx_copi => reg_eth1g_II_bsn_monitor_v2_tx_copi,
- reg_eth1g_II_bsn_monitor_v2_tx_cipo => reg_eth1g_II_bsn_monitor_v2_tx_cipo,
- reg_eth1g_II_strobe_total_count_tx_copi => reg_eth1g_II_strobe_total_count_tx_copi,
- reg_eth1g_II_strobe_total_count_tx_cipo => reg_eth1g_II_strobe_total_count_tx_cipo,
-
- reg_eth1g_II_bsn_monitor_v2_rx_copi => reg_eth1g_II_bsn_monitor_v2_rx_copi,
- reg_eth1g_II_bsn_monitor_v2_rx_cipo => reg_eth1g_II_bsn_monitor_v2_rx_cipo,
- reg_eth1g_II_strobe_total_count_rx_copi => reg_eth1g_II_strobe_total_count_rx_copi,
- reg_eth1g_II_strobe_total_count_rx_cipo => reg_eth1g_II_strobe_total_count_rx_cipo,
+ -- eth1g ch0
+ eth_0_mm_rst => eth_0_mm_rst,
+ eth_0_tse_mosi => eth_0_tse_mosi,
+ eth_0_tse_miso => eth_0_tse_miso,
+ eth_0_reg_mosi => eth_0_reg_mosi,
+ eth_0_reg_miso => eth_0_reg_miso,
+ eth_0_reg_interrupt => eth_0_reg_interrupt,
+ eth_0_ram_mosi => eth_0_ram_mosi,
+ eth_0_ram_miso => eth_0_ram_miso,
+
+ reg_diag_bg_eth_0_copi => reg_diag_bg_eth_0_copi,
+ reg_diag_bg_eth_0_cipo => reg_diag_bg_eth_0_cipo,
+ reg_hdr_dat_eth_0_copi => reg_hdr_dat_eth_0_copi,
+ reg_hdr_dat_eth_0_cipo => reg_hdr_dat_eth_0_cipo,
+ reg_bsn_monitor_v2_tx_eth_0_copi => reg_bsn_monitor_v2_tx_eth_0_copi,
+ reg_bsn_monitor_v2_tx_eth_0_cipo => reg_bsn_monitor_v2_tx_eth_0_cipo,
+ reg_strobe_total_count_tx_eth_0_copi => reg_strobe_total_count_tx_eth_0_copi,
+ reg_strobe_total_count_tx_eth_0_cipo => reg_strobe_total_count_tx_eth_0_cipo,
+
+ reg_bsn_monitor_v2_rx_eth_0_copi => reg_bsn_monitor_v2_rx_eth_0_copi,
+ reg_bsn_monitor_v2_rx_eth_0_cipo => reg_bsn_monitor_v2_rx_eth_0_cipo,
+ reg_strobe_total_count_rx_eth_0_copi => reg_strobe_total_count_rx_eth_0_copi,
+ reg_strobe_total_count_rx_eth_0_cipo => reg_strobe_total_count_rx_eth_0_cipo,
+
+ -- eth1g ch1
+ eth_1_mm_rst => eth_1_mm_rst,
+ eth_1_tse_mosi => eth_1_tse_mosi,
+ eth_1_tse_miso => eth_1_tse_miso,
+ eth_1_reg_mosi => OPEN,
+ eth_1_reg_miso => c_mem_cipo_rst,
+ eth_1_reg_interrupt => '0',
+ eth_1_ram_mosi => OPEN,
+ eth_1_ram_miso => c_mem_cipo_rst,
+
+ reg_diag_bg_eth_1_copi => reg_diag_bg_eth_1_copi,
+ reg_diag_bg_eth_1_cipo => reg_diag_bg_eth_1_cipo,
+ reg_hdr_dat_eth_1_copi => reg_hdr_dat_eth_1_copi,
+ reg_hdr_dat_eth_1_cipo => reg_hdr_dat_eth_1_cipo,
+ reg_bsn_monitor_v2_tx_eth_1_copi => reg_bsn_monitor_v2_tx_eth_1_copi,
+ reg_bsn_monitor_v2_tx_eth_1_cipo => reg_bsn_monitor_v2_tx_eth_1_cipo,
+ reg_strobe_total_count_tx_eth_1_copi => reg_strobe_total_count_tx_eth_1_copi,
+ reg_strobe_total_count_tx_eth_1_cipo => reg_strobe_total_count_tx_eth_1_cipo,
+
+ reg_bsn_monitor_v2_rx_eth_1_copi => reg_bsn_monitor_v2_rx_eth_1_copi,
+ reg_bsn_monitor_v2_rx_eth_1_cipo => reg_bsn_monitor_v2_rx_eth_1_cipo,
+ reg_strobe_total_count_rx_eth_1_copi => reg_strobe_total_count_rx_eth_1_copi,
+ reg_strobe_total_count_rx_eth_1_cipo => reg_strobe_total_count_rx_eth_1_cipo,
-- EPCS read
reg_dpmm_data_mosi => reg_dpmm_data_mosi,
@@ -799,7 +799,7 @@ BEGIN
);
- gen_udp_stream_1GbE : IF c_use_1GbE_I_UDP = TRUE GENERATE
+ gen_eth_0_udp : IF c_use_eth_0_UDP = TRUE GENERATE
-- Derive MAC/IP/UDP from gn_index
gn_eth_src_mac_I <= c_base_mac & func_eth_tester_gn_index_to_mac_15_0(gn_index, 0);
gn_ip_src_addr_I <= c_base_ip & func_eth_tester_gn_index_to_ip_15_0(gn_index, 0);
@@ -808,7 +808,7 @@ BEGIN
-- Generate UDP Tx and monitor UDP Rx
u_eth_tester_I : ENTITY eth_lib.eth_tester
GENERIC MAP (
- g_nof_streams => c_nof_udp_streams_1GbE_I,
+ g_nof_streams => c_nof_udp_streams_eth_0,
g_bg_sync_timeout => c_eth_tester_sync_timeout, -- BG sync interval < 11 s
g_remove_crc => TRUE -- use TRUE when using TSE link interface
)
@@ -827,38 +827,38 @@ BEGIN
tx_fifo_rd_emp_arr => OPEN,
- tx_udp_sosi_arr => eth1g_I_udp_tx_sosi_arr,
- tx_udp_siso_arr => eth1g_I_udp_tx_siso_arr,
+ tx_udp_sosi_arr => eth_0_udp_tx_sosi_arr,
+ tx_udp_siso_arr => eth_0_udp_tx_siso_arr,
-- UDP receive interface
- rx_udp_sosi_arr => eth1g_I_udp_rx_sosi_arr,
+ rx_udp_sosi_arr => eth_0_udp_rx_sosi_arr,
-- Memory Mapped Slaves (one per stream)
-- . Tx
- reg_bg_ctrl_copi => reg_eth1g_I_bg_ctrl_copi,
- reg_bg_ctrl_cipo => reg_eth1g_I_bg_ctrl_cipo,
- reg_hdr_dat_copi => reg_eth1g_I_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_eth1g_I_hdr_dat_cipo,
- reg_bsn_monitor_v2_tx_copi => reg_eth1g_I_bsn_monitor_v2_tx_copi,
- reg_bsn_monitor_v2_tx_cipo => reg_eth1g_I_bsn_monitor_v2_tx_cipo,
- reg_strobe_total_count_tx_copi => reg_eth1g_I_strobe_total_count_tx_copi,
- reg_strobe_total_count_tx_cipo => reg_eth1g_I_strobe_total_count_tx_cipo,
+ reg_bg_ctrl_copi => reg_diag_bg_eth_0_copi,
+ reg_bg_ctrl_cipo => reg_diag_bg_eth_0_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_eth_0_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_eth_0_cipo,
+ reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_eth_0_copi,
+ reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_eth_0_cipo,
+ reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_eth_0_copi,
+ reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_eth_0_cipo,
-- . Rx
- reg_bsn_monitor_v2_rx_copi => reg_eth1g_I_bsn_monitor_v2_rx_copi,
- reg_bsn_monitor_v2_rx_cipo => reg_eth1g_I_bsn_monitor_v2_rx_cipo,
- reg_strobe_total_count_rx_copi => reg_eth1g_I_strobe_total_count_rx_copi,
- reg_strobe_total_count_rx_cipo => reg_eth1g_I_strobe_total_count_rx_cipo
+ reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_eth_0_copi,
+ reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_eth_0_cipo,
+ reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_eth_0_copi,
+ reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_eth_0_cipo
);
-- Uses eth.vhd with ETH/TSE interface with UDP streams in ctrl_unb2c_board
- -- to stream UDP data via eth0 = 1GbE-I.
+ -- to stream UDP data via eth_0 = 1GbE-I.
END GENERATE;
-- Instantiate a second 1GbE-II to check pinning and to test UDP data via a
-- dedicated 1GbE port, instead of multiplexed with M&C
- gen_eth_II: IF c_use_1GbE_II = TRUE GENERATE
- -- Derive eth1 MAC/IP/UDP from eth0
+ gen_eth_1: IF c_use_eth_1 = TRUE GENERATE
+ -- Derive eth_1 MAC/IP/UDP from eth_0
gn_eth_src_mac_II <= c_base_mac & func_eth_tester_gn_index_to_mac_15_0(gn_index, 1);
gn_ip_src_addr_II <= c_base_ip & func_eth_tester_gn_index_to_ip_15_0(gn_index, 1);
gn_udp_src_port_II <= c_base_udp & func_eth_tester_gn_index_to_udp_7_0(gn_index, 1);
@@ -866,7 +866,7 @@ BEGIN
-- Generate UDP Tx and monitor UDP Rx
u_eth_tester_II : ENTITY eth_lib.eth_tester
GENERIC MAP (
- g_nof_streams => c_nof_udp_streams_1GbE_II,
+ g_nof_streams => c_nof_udp_streams_eth_1,
g_bg_sync_timeout => c_eth_tester_sync_timeout, -- BG sync interval < 11 s
g_remove_crc => TRUE -- use TRUE when using TSE link interface
)
@@ -885,31 +885,31 @@ BEGIN
tx_fifo_rd_emp_arr => OPEN,
- tx_udp_sosi_arr => eth1g_II_udp_tx_sosi_arr,
- tx_udp_siso_arr => eth1g_II_udp_tx_siso_arr,
+ tx_udp_sosi_arr => eth_1_udp_tx_sosi_arr,
+ tx_udp_siso_arr => eth_1_udp_tx_siso_arr,
-- UDP receive interface
- rx_udp_sosi_arr => eth1g_II_udp_rx_sosi_arr,
+ rx_udp_sosi_arr => eth_1_udp_rx_sosi_arr,
-- Memory Mapped Slaves (one per stream)
-- . Tx
- reg_bg_ctrl_copi => reg_eth1g_II_bg_ctrl_copi,
- reg_bg_ctrl_cipo => reg_eth1g_II_bg_ctrl_cipo,
- reg_hdr_dat_copi => reg_eth1g_II_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_eth1g_II_hdr_dat_cipo,
- reg_bsn_monitor_v2_tx_copi => reg_eth1g_II_bsn_monitor_v2_tx_copi,
- reg_bsn_monitor_v2_tx_cipo => reg_eth1g_II_bsn_monitor_v2_tx_cipo,
- reg_strobe_total_count_tx_copi => reg_eth1g_II_strobe_total_count_tx_copi,
- reg_strobe_total_count_tx_cipo => reg_eth1g_II_strobe_total_count_tx_cipo,
+ reg_bg_ctrl_copi => reg_diag_bg_eth_1_copi,
+ reg_bg_ctrl_cipo => reg_diag_bg_eth_1_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_eth_1_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_eth_1_cipo,
+ reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_eth_1_copi,
+ reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_eth_1_cipo,
+ reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_eth_1_copi,
+ reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_eth_1_cipo,
-- . Rx
- reg_bsn_monitor_v2_rx_copi => reg_eth1g_II_bsn_monitor_v2_rx_copi,
- reg_bsn_monitor_v2_rx_cipo => reg_eth1g_II_bsn_monitor_v2_rx_cipo,
- reg_strobe_total_count_rx_copi => reg_eth1g_II_strobe_total_count_rx_copi,
- reg_strobe_total_count_rx_cipo => reg_eth1g_II_strobe_total_count_rx_cipo
+ reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_eth_1_copi,
+ reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_eth_1_cipo,
+ reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_eth_1_copi,
+ reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_eth_1_cipo
);
-- Use eth_stream with ETH/TSE interface for UDP port g_rx_udp_port to
- -- stream UDP data via eth1 = 1GbE-II
+ -- stream UDP data via eth_1 = 1GbE-II
u_eth_stream : ENTITY eth_lib.eth_stream
GENERIC MAP (
g_technology => g_technology,
@@ -920,7 +920,7 @@ BEGIN
)
PORT MAP (
-- Clocks and reset
- mm_rst => mm_rst, -- eth1g_eth1_mm_rst
+ mm_rst => mm_rst, -- eth_1_mm_rst
mm_clk => mm_clk,
eth_clk => ETH_CLK(1),
st_rst => dp_rst,
@@ -931,16 +931,16 @@ BEGIN
setup_done => OPEN,
-- UDP transmit interface
- udp_tx_snk_in => eth1g_II_udp_tx_sosi_arr(0),
- udp_tx_snk_out => eth1g_II_udp_tx_siso_arr(0),
+ udp_tx_snk_in => eth_1_udp_tx_sosi_arr(0),
+ udp_tx_snk_out => eth_1_udp_tx_siso_arr(0),
-- UDP receive interface
udp_rx_src_in => c_dp_siso_rdy,
- udp_rx_src_out => eth1g_II_udp_rx_sosi_arr(0),
+ udp_rx_src_out => eth_1_udp_rx_sosi_arr(0),
-- Memory Mapped Slaves
- tse_ctlr_copi => eth1g_eth1_tse_mosi,
- tse_ctlr_cipo => eth1g_eth1_tse_miso,
+ tse_ctlr_copi => eth_1_tse_mosi,
+ tse_ctlr_cipo => eth_1_tse_miso,
-- PHY interface
eth_txp => ETH_SGOUT(1),
--
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