diff --git a/libraries/io/eth/eth.peripheral.yaml b/libraries/io/eth/eth.peripheral.yaml
index 321706436eb9bc52210d67d1da407f3fb5c71fb5..70a08c66a5e67f5aa879316710547f24db4e75ca 100644
--- a/libraries/io/eth/eth.peripheral.yaml
+++ b/libraries/io/eth/eth.peripheral.yaml
@@ -25,14 +25,641 @@ peripherals:
# MM port for registers in the TSE IP [1]
- mm_port_name: AVS_ETH_0_TSE
mm_port_type: REG
+ mm_port_span: 1024 * MM_BUS_SIZE # = c_tech_tse_byte_addr_w in tech_tse_pkg.vhd
mm_port_description: "Registers in the TSE IP [1], handled by the Nios microprocessor."
fields:
- - - field_name: registers
- field_description: ""
- number_of_fields: 1024 # = c_tech_tse_byte_addr_w in tech_tse_pkg.vhd
- address_offset: 0x0
+ - - field_name: rev
+ field_description: |
+ ". Bits[15:0]—Set to the current version of the IP.
+ . Bits[31:16]—Customer specific revision, specified by the
+ CUST_VERSION parameter defined in the top-level file
+ generated for the instance of the IP. These bits are set to
+ 0 during the configuration of the IP."
+ address_offset: 0x00 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: scratch
+ field_description: |
+ "Scratch register. Provides a memory location for you to test
+ the device memory operation."
+ address_offset: 0x01 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: command_config
+ field_description: |
+ "MAC configuration register. Use this register to control and
+ configure the MAC function. The MAC function starts
+ operation as soon as the transmit and receive enable bits in
+ this register are turned on. Intel, therefore, recommends
+ that you configure this register last."
+ address_offset: 0x02 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: mac_0
+ field_description: |
+ "6-byte MAC primary address. The first four most significant
+ bytes of the MAC address occupy mac_0 in reverse order.
+ The last two bytes of the MAC address occupy the two least
+ significant bytes of mac_1 in reverse order.
+ For example, if the MAC address is 00-1C-23-17-4A-CB, the
+ following assignments are made:
+ mac_0 = 0x17231c00
+ mac_1 = 0x0000CB4a
+ Ensure that you configure these registers with a valid MAC
+ address if you disable the promiscuous mode (PROMIS_EN
+ bit in command_config = 0)"
+ address_offset: 0x03 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: mac_1
+ field_description: |
+ "see mac_0"
+ address_offset: 0x04 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: frm_length
+ field_description: |
+ ". Bits[15:0]—16-bit maximum frame length in bytes. The
+ IP checks the length of receive frames against this value.
+ Typical value is 1518.
+ In the 10/100 Mbps and 1000 Mbps small MAC
+ variations, this register is RO and the maximum frame
+ length is fixed to 1518.
+ . Bits[31:16]—unused."
+ address_offset: 0x05 * MM_BUS_SIZE
access_mode: RW
+ - - field_name: pause_quant
+ field_description: |
+ ". Bits[15:0]—16-bit pause quanta. Use this register to
+ specify the pause quanta to be sent to remote devices
+ when the local device is congested. The IP sets the
+ pause quanta (P1, P2) field in pause frames to the value
+ of this register.
+ The 10/100 Mbps and 1000 Mbps small MAC variations
+ do not support flow control.
+ . Bits[31:16]—unused."
+ address_offset: 0x06 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: rx_section_empty
+ field_description: |
+ "Variable-length section-empty threshold of the receive FIFO
+ buffer. Use the depth of your FIFO buffer to determine this
+ threshold. This threshold is typically set to (FIFO Depth –
+ 16)."
+ address_offset: 0x07 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: rx_section_full
+ field_description: |
+ "Variable-length section-full threshold of the receive FIFO
+ buffer. Use the depth of your FIFO buffer to determine this
+ threshold."
+ address_offset: 0x08 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: tx_section_empty
+ field_description: |
+ "Variable-length section-empty threshold of the transmit
+ FIFO buffer. Use the depth of your FIFO buffer to determine
+ this threshold. This threshold is typically set to (FIFO Depth
+ – 16)."
+ address_offset: 0x09 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: tx_section_full
+ field_description: |
+ "Variable-length section-full threshold of the transmit FIFO
+ buffer. Use the depth of your FIFO buffer to determine this
+ threshold."
+ address_offset: 0x0A * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: rx_almost_empty
+ field_description: |
+ "Variable-length almost-empty threshold of the receive FIFO
+ buffer. Use the depth of your FIFO buffer to determine this
+ threshold."
+ address_offset: 0x0B * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: rx_almost_full
+ field_description: |
+ "Variable-length almost-full threshold of the receive FIFO
+ buffer. Use the depth of your FIFO buffer to determine this
+ threshold."
+ address_offset: 0x0C * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: tx_almost_empty
+ field_description: |
+ "Variable-length almost-empty threshold of the transmit FIFO
+ buffer. Use the depth of your FIFO buffer to determine this
+ threshold."
+ address_offset: 0x0D * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: tx_almost_full
+ field_description: |
+ "Variable-length almost-full threshold of the transmit FIFO
+ buffer. Use the depth of your FIFO buffer to determine this
+ threshold."
+ address_offset: 0x0E * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: mdio_addr0
+ field_description: |
+ ". Bits[4:0]—5-bit PHY address. Set these registers to the
+ addresses of any connected PHY devices you want to
+ access. The mdio_addr0 and mdio_addr1 registers
+ contain the addresses of the PHY whose registers are
+ mapped to MDIO Space 0 and MDIO Space 1
+ respectively.
+ . Bits[31:5]—unused. Set to read-only value of 0."
+ address_offset: 0x0F * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: mdio_addr1
+ field_description: |
+ "see mdio_addr0"
+ address_offset: 0x10 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: holdoff_quant
+ field_description: |
+ ". Bit[15:0]—16-bit holdoff quanta. When you enable the
+ flow control, use this register to specify the gap between
+ consecutive XOFF requests.
+ . Bits[31:16]—unused."
+ address_offset: 0x11 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: tx_ipg_length
+ field_description: |
+ ". Bits[4:0]—minimum IPG. Valid values are between 8 and
+ 26 byte-times. If this register is set to an invalid value,
+ the MAC still maintains a typical minimum IPG value of
+ 12 bytes between packets, although a read back to the
+ register reflects the invalid value written.
+ In the 10/100 Mbps and 1000 Mbps small MAC
+ variations, this register is RO and the register is set to a
+ fixed value of 12.
+ . Bits[31:5]—unused. Set to read-only value 0"
+ address_offset: 0x17 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: aMacID
+ field_description: |
+ "The MAC address. This register is wired to the primary MAC address
+ in the mac_0 and mac_1 registers."
+ address_offset: 0x18 * MM_BUS_SIZE
+ access_mode: RO
+ user_width: 64
+ radix: uint64
+
+ - - field_name: aFramesTransmittedOK
+ field_description: |
+ "The number of frames that are successfully transmitted including the
+ pause frames."
+ address_offset: 0x1A * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: aFramesReceivedOK
+ field_description: |
+ "The number of frames that are successfully received including the
+ pause frames."
+ address_offset: 0x1B * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: aFrameCheckSequenceErrors
+ field_description: |
+ "The number of receive frames with CRC error."
+ address_offset: 0x1C * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: aAlignmentErrors
+ field_description: |
+ "The number of receive frames with alignment error."
+ address_offset: 0x1D * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: aOctetsTransmittedOK
+ field_description: |
+ "The number of data and padding octets that are successfully
+ transmitted"
+ address_offset: 0x1E * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: aOctetsReceivedOK
+ field_description: |
+ "The number of data and padding octets that are successfully
+ received, including pause frames."
+ address_offset: 0x1F * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: aTxPAUSEMACCtrlFrames
+ field_description: |
+ "The number of pause frames transmitted."
+ address_offset: 0x20 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: aRxPAUSEMACCtrlFrames
+ field_description: |
+ "The number received pause frames received."
+ address_offset: 0x21 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: ifInErrors
+ field_description: |
+ "The number of errored frames received."
+ address_offset: 0x22 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: ifOutErrors
+ field_description: |
+ "The number of transmit frames with one the following errors:
+ . FIFO overflow error
+ . FIFO underflow error
+ . Frames that encounter late or excessive collision occasions
+ . Errors defined by the user application"
+ address_offset: 0x23 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: ifInUcastPkts
+ field_description: |
+ "The number of valid unicast frames received."
+ address_offset: 0x24 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: ifInMulticastPkts
+ field_description: |
+ "The number of valid multicast frames received. The count does not
+ include pause frames."
+ address_offset: 0x25 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: ifInBroadcastPkts
+ field_description: |
+ "The number of valid broadcast frames received."
+ address_offset: 0x26 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: ifOutUcastPkts
+ field_description: |
+ "The number of valid unicast and erroneous frames transmitted, as
+ well as unicast frames transmitted during late and excessive collision
+ occasions."
+ address_offset: 0x28 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: ifOutMulticastPkts
+ field_description: |
+ "The number of valid multicast frames transmitted, as well as
+ multicast frames transmitted during late and excessive collision
+ occasions, excluding pause frames."
+ address_offset: 0x29 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: ifOutBroadcastPkts
+ field_description: |
+ "The number of valid and erroneous broadcast frames transmitted, as
+ well as broadcast frames transmitted during late and excessive
+ collision occasions."
+ address_offset: 0x2A * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsDropEvents
+ field_description: |
+ "The number of frames that are dropped due to MAC internal errors
+ when FIFO buffer overflow persists."
+ address_offset: 0x2B * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsOctets
+ field_description: |
+ "The total number of octets received. This count includes both good
+ and errored frames."
+ address_offset: 0x2C * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsPkts
+ field_description: |
+ "The total number of good and errored frames received."
+ address_offset: 0x2D * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsUndersizePkts
+ field_description: |
+ "The number of frames received with length less than 64 bytes,
+ including pause frames. This count does not include errored frames."
+ address_offset: 0x2E * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsOversizePkts
+ field_description: |
+ "The number of frames received that are longer than the value
+ configured in the frm_length register. This count does not include
+ errored frames."
+ address_offset: 0x2F * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsPkts64Octets
+ field_description: |
+ "The number of 64-byte frames received. This count includes good and
+ errored frames"
+ address_offset: 0x30 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsPkts65to127Octets
+ field_description: |
+ "The number of received good and errored frames between the length
+ of 65 and 127 bytes."
+ address_offset: 0x31 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsPkts128to255Octets
+ field_description: |
+ "The number of received good and errored frames between the length
+ of 128 and 255 bytes."
+ address_offset: 0x32 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsPkts256to511Octets
+ field_description: |
+ "The number of received good and errored frames between the length
+ of 256 and 511 bytes."
+ address_offset: 0x33 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsPkts512to1023Octets
+ field_description: |
+ "The number of received good and errored frames between the length
+ of 512 and 1023 bytes."
+ address_offset: 0x34 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsPkts1024to1518Octets
+ field_description: |
+ "The number of received good and errored frames between the length
+ of 1024 and 1518 bytes."
+ address_offset: 0x35 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsPkts1519toXOctets
+ field_description: |
+ "The number of received good and errored frames between the length
+ of 1519 and the maximum frame length configured in the
+ frm_length register."
+ address_offset: 0x36 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsJabbers
+ field_description: |
+ "Too long frames with CRC error."
+ address_offset: 0x37 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsFragments
+ field_description: |
+ "Too short frames with CRC error."
+ address_offset: 0x38 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: tx_cmd_stat
+ field_description: |
+ "Specifies how the MAC function processes transmit frames. When you
+ turn on the Align packet headers to 32-bit boundaries option."
+ address_offset: 0x3A * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: rx_cmd_stat
+ field_description: |
+ "Specifies how the MAC function processes receive frames. When you
+ turn on the Align packet headers to 32-bit boundaries option"
+ address_offset: 0x3B * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: msb_aOctetsTransmittedOK
+ field_description: |
+ "Upper 32 bits of the respective statistics counters. By default all
+ statistics counters are 32 bits wide. These statistics counters can be
+ extended to 64 bits by turning on the Enable 64-bit byte counters
+ parameter.
+ To read the counter, read the lower 32 bits first, then followed by the
+ extended statistic counter bits"
+ address_offset: 0x3C * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: msb_aOctetsReceivedOK
+ field_description: |
+ "see msb_aOctetsTransmittedOK"
+ address_offset: 0x3D * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: msb_etherStatsOctets
+ field_description: |
+ "see msb_aOctetsTransmittedOK"
+ address_offset: 0x3E * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: pcs_control
+ field_description: |
+ "PCS control register. Use this register to control and
+ configure the PCS function."
+ address_offset: ( 0x80 + 0x00 ) * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RW
+
+ - - field_name: pcs_status
+ field_description: |
+ "Status register. Provides information on the operation of the
+ PCS function."
+ address_offset: ( 0x80 + 0x01 ) * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RO
+
+ - - field_name: pcs_phy_identifier_msb
+ field_description: |
+ "32-bit PHY identification register. This register is set to the
+ value of the PHY ID parameter. Bits 31:16 are written to
+ word offset 0x02. Bits 15:0 are written to word offset 0x03."
+ address_offset: ( 0x80 + 0x02 ) * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RO
+
+ - - field_name: pcs_phy_identifier_lsb
+ field_description: |
+ "see pcs_phy_identifier_msb"
+ address_offset: ( 0x80 + 0x03 ) * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RO
+
+ - - field_name: pcs_dev_ability
+ field_description: |
+ "Use this register to advertise the device abilities to a link
+ partner during auto-negotiation. In SGMII MAC mode, the
+ PHY does not use this register during auto-negotiation."
+ address_offset: ( 0x80 + 0x04 ) * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RW
+
+ - - field_name: pcs_partner_ability
+ field_description: |
+ "Contains the device abilities advertised by the link partner
+ during auto-negotiation."
+ address_offset: ( 0x80 + 0x05 ) * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RO
+
+ - - field_name: pcs_an_expansion
+ field_description: |
+ "Auto-negotiation expansion register. Contains the PCS
+ function capability and auto-negotiation status."
+ address_offset: ( 0x80 + 0x06 ) * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RO
+
+ - - field_name: pcs_scratch
+ field_description: |
+ "Scratch register. Provides a memory location to test register
+ read and write operations."
+ address_offset: ( 0x80 + 0x10 ) * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RW
+
+ - - field_name: pcs_rev
+ field_description: |
+ "The PCS function revision. Always set to the current version
+ of the IP."
+ address_offset: ( 0x80 + 0x11 ) * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RO
+
+ - - field_name: pcs_link_timer_lsb
+ field_description: |
+ "21-bit auto-negotiation link timer. Set the link timer value
+ from 0 to 16 ms in 8 ns steps (125 MHz clock periods). The
+ reset value sets the link timer to 10 ms.
+ . Bits 15:0 are written to word offset 0x12. Bit 0 of word
+ offset 0x12 is always set to 0, thus any value written to
+ it is ignored.
+ . Bits 20:16 are written to word offset 0x13. The
+ remaining bits are reserved and always set to 0."
+ address_offset: ( 0x80 + 0x12 ) * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RW
+
+ - - field_name: pcs_link_timer_msb
+ field_description: |
+ "see pcs_link_timer_lsb"
+ address_offset: ( 0x80 + 0x13 ) * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RW
+
+ - - field_name: pcs_if_mode
+ field_description: |
+ "Interface mode. Use this register to specify the operating
+ mode of the PCS function; 1000BASE-X or SGMII."
+ address_offset: ( 0x80 + 0x14 ) * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RW
+
+ - - field_name: tx_period
+ field_description: |
+ "Clock period for timestamp adjustment on the transmit
+ datapath. The period register is multiplied by the number of
+ stages separating actual timestamp and the GMII bus.
+ . Bits 0 to 15: Period in fractional nanoseconds
+ (TX_PERIOD_FNS).
+ . Bits 16 to 24: Period in nanoseconds (TX_PERIOD_NS).
+ . Bits 25 to 31: Not used.
+ The default value for the period is 0. For 125 MHz clock, set this
+ register to 8 ns."
+ address_offset: 0xD0 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: tx_adjust_fns
+ field_description: |
+ "Timing adjustment in fractional nanoseconds"
+ address_offset: 0xD1 * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RW
+
+ - - field_name: tx_adjust_ns
+ field_description: |
+ "Timing adjustment in nanoseconds."
+ address_offset: 0xD2 * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RW
+
+ - - field_name: rx_period
+ field_description: |
+ "Clock period for timestamp adjustment on the receive datapath.
+ The period register is multiplied by the number of stages
+ separating actual timestamp and the GMII bus.
+ . Bits 0 to 15: Period in fractional nanoseconds
+ (RX_PERIOD_FNS).
+ . Bits 16 to 24: Period in nanoseconds (RX_PERIOD_NS).
+ . Bits 25 to 31: Not used.
+ The default value for the period is 0. For 125 MHz clock, set this
+ register to 8 ns."
+ address_offset: 0xD3 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: rx_adjust_fns
+ field_description: |
+ "Timing adjustment in fractional nanoseconds."
+ address_offset: 0xD4 * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RW
+
+ - - field_name: rx_adjust_ns
+ field_description: |
+ "Timing adjustment in nanoseconds."
+ address_offset: 0xD5 * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RW
+
+ - - field_name: measure_valid
+ field_description: |
+ "Indicates whether the DL measurement values are
+ valid. 0: Not valid, 1: Valid"
+ address_offset: 0xE1 * MM_BUS_SIZE
+ mm_width: 1
+ bit_offset: 0
+ access_mode: RO
+
+ - - field_name: dl_reset
+ field_description: |
+ "Deterministic latency (DL) soft reset."
+ address_offset: 0xE1 * MM_BUS_SIZE
+ mm_width: 1
+ bit_offset: 1
+ access_mode: RW
+
+ - - field_name: tx_delay
+ field_description: |
+ "TX datapath latency.
+ Displays the TX datapath DL measurement values
+ measured in the i_dl_sampling_clk cycles.
+ measure_valid must be set prior taking the
+ measurement."
+ address_offset: 0xE2 * MM_BUS_SIZE
+ mm_width: 21
+ access_mode: RO
+
+ - - field_name: rx_delay
+ field_description: |
+ "RX datapath latency
+ Displays the RX datapath DL measurement values
+ measured in the i_dl_sampling_clk cycles.
+ measure_valid must be set prior taking the
+ measurement"
+ address_offset: 0xE3 * MM_BUS_SIZE
+ mm_width: 21
+ access_mode: RO
+
# MM port for registers in eth_mm_registers.vhd in the ETH module [2]
- mm_port_name: AVS_ETH_0_REG
mm_port_type: REG
diff --git a/libraries/technology/tse/tb_tech_tse_pkg.vhd b/libraries/technology/tse/tb_tech_tse_pkg.vhd
index 43c6110b8d7c4950ef1ec1c7c5eff8bd2b689097..0fcdd7b5527b2bf548414facfad482fd50b627b0 100644
--- a/libraries/technology/tse/tb_tech_tse_pkg.vhd
+++ b/libraries/technology/tse/tb_tech_tse_pkg.vhd
@@ -113,6 +113,10 @@ PACKAGE BODY tb_tech_tse_pkg IS
RETURN pcs_addr * 2 + c_tech_tse_byte_addr_pcs_offset;
END func_map_pcs_addr;
+ FUNCTION func_map_pcs_addr_arria10(pcs_addr : NATURAL) RETURN NATURAL IS
+ BEGIN
+ RETURN pcs_addr + c_tech_tse_reg_addr_pcs_offset;
+ END func_map_pcs_addr_arria10;
------------------------------------------------------------------------------
-- GLOBAL ITEMS
@@ -252,7 +256,7 @@ PACKAGE BODY tb_tech_tse_pkg IS
WAIT UNTIL rising_edge(mm_clk);
END proc_tech_tse_setup_stratixiv;
- -- It is noticed that the arria10 variant needs longer setup time.
+ -- It is noticed that the arria10 variant needs longer setup time and uses the mac register space with offset 0x80 to access the PCS registers.
PROCEDURE proc_tech_tse_setup_arria10(CONSTANT c_promis_en : IN BOOLEAN;
CONSTANT c_tse_tx_fifo_depth : IN NATURAL;
CONSTANT c_tse_rx_fifo_depth : IN NATURAL;
@@ -262,8 +266,94 @@ PACKAGE BODY tb_tech_tse_pkg IS
SIGNAL mm_clk : IN STD_LOGIC;
SIGNAL mm_miso : IN t_mem_miso;
SIGNAL mm_mosi : OUT t_mem_mosi) IS
- BEGIN
- proc_tech_tse_setup_stratixiv(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi);
+ CONSTANT c_mac0 : INTEGER := TO_SINT(hton(src_mac(47 DOWNTO 16), 4));
+ CONSTANT c_mac1 : INTEGER := TO_SINT(hton(src_mac(15 DOWNTO 0), 2));
+ BEGIN
+ -- PSC control
+ psc_access <= '1';
+ proc_mem_mm_bus_rd(func_map_pcs_addr_arria10(16#11#), mm_clk, mm_miso, mm_mosi); -- REV --> 0x0901
+ proc_mem_mm_bus_wr(func_map_pcs_addr_arria10(16#14#), 16#0008#, mm_clk, mm_miso, mm_mosi); -- IF_MODE <-- Force 1GbE, no autonegatiation
+ proc_mem_mm_bus_rd(func_map_pcs_addr_arria10(16#00#), mm_clk, mm_miso, mm_mosi); -- CONTROL --> 0x1140
+ proc_mem_mm_bus_rd(func_map_pcs_addr_arria10(16#01#), mm_clk, mm_miso, mm_mosi); -- STATUS --> 0x000D
+ proc_mem_mm_bus_wr(func_map_pcs_addr_arria10(16#00#), 16#0140#, mm_clk, mm_miso, mm_mosi); -- CONTROL <-- Auto negotiate disable
+ psc_access <= '0';
+
+ -- MAC control
+ proc_mem_mm_bus_rd(16#000#, mm_clk, mm_miso, mm_mosi); -- REV --> CUST_VERSION & 0x0901
+ IF c_promis_en=FALSE THEN
+ proc_mem_mm_bus_wr(16#002#, 16#0100004B#, mm_clk, mm_miso, mm_mosi);
+ ELSE
+ proc_mem_mm_bus_wr(16#002#, 16#0100005B#, mm_clk, mm_miso, mm_mosi);
+ END IF;
+ -- COMMAND_CONFIG <--
+ -- Only the bits relevant to UniBoard are explained here, others are 0
+ -- [ 0] = TX_ENA = 1, enable tx datapath
+ -- [ 1] = RX_ENA = 1, enable rx datapath
+ -- [ 2] = XON_GEN = 0
+ -- [ 3] = ETH_SPEED = 1, enable 1GbE operation
+ -- [ 4] = PROMIS_EN = 0, when 1 then receive all frames
+ -- [ 5] = PAD_EN = 0, when 1 enable receive padding removal (requires ethertype=payload length)
+ -- [ 6] = CRC_FWD = 1, enable receive CRC forward
+ -- [ 7] = PAUSE_FWD = 0
+ -- [ 8] = PAUSE_IGNORE = 0
+ -- [ 9] = TX_ADDR_INS = 0, when 1 then MAX overwrites tx SRC MAC with mac_0,1 or one of the supplemental mac
+ -- [ 10] = HD_ENA = 0
+ -- [ 11] = EXCESS_COL = 0
+ -- [ 12] = LATE_COL = 0
+ -- [ 13] = SW_RESET = 0, when 1 MAC disables tx and rx, clear statistics and flushes receive FIFO
+ -- [ 14] = MHAS_SEL = 0, select multicast address resolutions hash-code mode
+ -- [ 15] = LOOP_ENA = 0
+ -- [18-16] = TX_ADDR_SEL[2:0] = 000, TX_ADDR_INS insert mac_0,1 or one of the supplemental mac
+ -- [ 19] = MAGIC_EN = 0
+ -- [ 20] = SLEEP = 0
+ -- [ 21] = WAKEUP = 0
+ -- [ 22] = XOFF_GEN = 0
+ -- [ 23] = CNT_FRM_ENA = 0
+ -- [ 24] = NO_LGTH_CHECK = 1, when 0 then check payload length of received frames (requires ethertype=payload length)
+ -- [ 25] = ENA_10 = 0
+ -- [ 26] = RX_ERR_DISC = 0, when 1 then discard erroneous frames (requires store and forward mode, so rx_section_full=0)
+ -- when 0 then pass on with rx_err[0]=1
+ -- [ 27] = DISABLE_RD_TIMEOUT = 0
+ -- [30-28] = RSVD = 000
+ -- [ 31] = CNT_RESET = 0, when 1 clear statistics
+ proc_mem_mm_bus_wr(16#03#, c_mac0, mm_clk, mm_miso, mm_mosi); -- MAC_0
+ proc_mem_mm_bus_wr(16#04#, c_mac1, mm_clk, mm_miso, mm_mosi); -- MAC_1 <-- SRC_MAC = 12-34-56-78-9A-BC
+ proc_mem_mm_bus_wr(16#17#, 16#0000000C#, mm_clk, mm_miso, mm_mosi); -- TX_IPG_LENGTH <-- interpacket gap = 12
+ --proc_mem_mm_bus_wr(16#05#, 16#000005EE#, mm_clk, mm_miso, mm_mosi); -- FRM_LENGTH <-- receive max frame length = 1518
+ proc_mem_mm_bus_wr(16#05#, 16#0000233A#, mm_clk, mm_miso, mm_mosi); -- FRM_LENGTH <-- receive max frame length = 9018
+
+ -- FIFO legenda:
+ -- . Tx section full = There is enough data in the FIFO to start reading it, when 0 then store and forward.
+ -- . Rx section full = There is enough data in the FIFO to start reading it, when 0 then store and forward.
+ -- . Tx section empty = There is not much empty space anymore in the FIFO, warn user via ff_tx_septy
+ -- . Rx section empty = There is not much empty space anymore in the FIFO, inform remote device via XOFF flow control
+ -- . Tx almost full = Assert ff_tx_a_full and deassert ff_tx_rdy. Furthermore TX_ALMOST_FULL = c_tx_ready_latency+3,
+ -- so choose 3 for zero tx ready latency
+ -- . Rx almost full = Assert ff_rx_a_full and if the user is not ready ff_rx_rdy then:
+ -- --> break off the reception with an error to avoid FIFO overflow
+ -- . Tx almost empty = Assert ff_tx_a_empty and if the FIFO does not contain a eop yet then:
+ -- --> break off the transmission with an error to avoid FIFO underflow
+ -- . Rx almost empty = Assert ff_rx_a_empty
+ -- Typical FIFO values:
+ -- . TX_SECTION_FULL = 16 > 8 = TX_ALMOST_EMPTY
+ -- . RX_SECTION_FULL = 16 > 8 = RX_ALMOST_EMPTY
+ -- . TX_SECTION_EMPTY = D-16 < D-3 = Tx FIFO depth - TX_ALMOST_FULL
+ -- . RX_SECTION_EMPTY = D-16 < D-8 = Rx FIFO depth - RX_ALMOST_FULL
+ -- . c_tse_tx_fifo_depth = 1 M9K = 256*32b = 1k * 8b is sufficient when the Tx user respects ff_tx_rdy, to store a complete
+ -- ETH packet would require 1518 byte, so 2 M9K = 2k * 8b
+ -- . c_tse_rx_fifo_depth = 1 M9K = 256*32b = 1k * 8b is sufficient when the Rx user ff_rx_rdy is sufficiently active
+ proc_mem_mm_bus_wr(16#07#, c_tse_rx_fifo_depth-16, mm_clk, mm_miso, mm_mosi); -- RX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ proc_mem_mm_bus_wr(16#08#, 16, mm_clk, mm_miso, mm_mosi); -- RX_SECTION_FULL <-- default 16
+ proc_mem_mm_bus_wr(16#09#, c_tse_tx_fifo_depth-16, mm_clk, mm_miso, mm_mosi); -- TX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ proc_mem_mm_bus_wr(16#0A#, 16, mm_clk, mm_miso, mm_mosi); -- TX_SECTION_FULL <-- default 16, >~ 8 otherwise no tx
+ proc_mem_mm_bus_wr(16#0B#, 8, mm_clk, mm_miso, mm_mosi); -- RX_ALMOST_EMPTY <-- default 8
+ proc_mem_mm_bus_wr(16#0C#, 8, mm_clk, mm_miso, mm_mosi); -- RX_ALMOST_FULL <-- default 8
+ proc_mem_mm_bus_wr(16#0D#, 8, mm_clk, mm_miso, mm_mosi); -- TX_ALMOST_EMPTY <-- default 8
+ proc_mem_mm_bus_wr(16#0E#, c_tx_ready_latency+3, mm_clk, mm_miso, mm_mosi); -- TX_ALMOST_FULL <-- default 3
+
+ proc_mem_mm_bus_rd(16#3A#, mm_clk, mm_miso, mm_mosi); -- TX_CMD_STAT --> 0x00040000 : [18]=1 TX_SHIFT16, [17]=0 OMIT_CRC
+ proc_mem_mm_bus_rd(16#3B#, mm_clk, mm_miso, mm_mosi); -- RX_CMD_STAT --> 0x02000000 : [25]=1 RX_SHIFT16
+
WAIT FOR 10 us;
WAIT UNTIL rising_edge(mm_clk);
END proc_tech_tse_setup_arria10;
diff --git a/libraries/technology/tse/tech_tse_arria10.vhd b/libraries/technology/tse/tech_tse_arria10.vhd
index f1d26d696964e6a0934c4dfa4dc796f72784ed8c..b95a8454fffb5d67dbe3aa17a1bd122ca2b5dc16 100644
--- a/libraries/technology/tse/tech_tse_arria10.vhd
+++ b/libraries/technology/tse/tech_tse_arria10.vhd
@@ -140,7 +140,7 @@ BEGIN
reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
-- MM control interface
clk => mm_clk,
- reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+ reg_addr => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
reg_rd => mm_sla_in.rd,
reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
@@ -216,7 +216,7 @@ BEGIN
reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
-- MM control interface
clk => mm_clk,
- reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+ reg_addr => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
reg_rd => mm_sla_in.rd,
reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
diff --git a/libraries/technology/tse/tech_tse_arria10_e1sg.vhd b/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
index 664f3f85ecbc4e6a2d853b9a02bfb9ae635dfc07..e688dd3948effe51993c366bf847bd3d817e066e 100644
--- a/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
+++ b/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
@@ -140,7 +140,7 @@ BEGIN
reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
-- MM control interface
clk => mm_clk,
- reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+ reg_addr => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
reg_rd => mm_sla_in.rd,
reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
@@ -216,7 +216,7 @@ BEGIN
reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
-- MM control interface
clk => mm_clk,
- reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+ reg_addr => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
reg_rd => mm_sla_in.rd,
reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
diff --git a/libraries/technology/tse/tech_tse_arria10_e2sg.vhd b/libraries/technology/tse/tech_tse_arria10_e2sg.vhd
index d3e5752dbc20f3c24d4bc9c96441dd738a4c378e..43ce8e3667bd7f1258b3e6fd53fe3ac5f8dc74d4 100644
--- a/libraries/technology/tse/tech_tse_arria10_e2sg.vhd
+++ b/libraries/technology/tse/tech_tse_arria10_e2sg.vhd
@@ -140,7 +140,7 @@ BEGIN
reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
-- MM control interface
clk => mm_clk,
- reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+ reg_addr => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
reg_rd => mm_sla_in.rd,
reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
@@ -216,7 +216,7 @@ BEGIN
reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
-- MM control interface
clk => mm_clk,
- reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+ reg_addr => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
reg_rd => mm_sla_in.rd,
reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
diff --git a/libraries/technology/tse/tech_tse_arria10_e3sge3.vhd b/libraries/technology/tse/tech_tse_arria10_e3sge3.vhd
index ed5297387bfbddf8f28a4fca964b7349bff04d5b..d548b22f664c3f22c5b600c2535e1135714ac74f 100644
--- a/libraries/technology/tse/tech_tse_arria10_e3sge3.vhd
+++ b/libraries/technology/tse/tech_tse_arria10_e3sge3.vhd
@@ -140,7 +140,7 @@ BEGIN
reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
-- MM control interface
clk => mm_clk,
- reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+ reg_addr => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
reg_rd => mm_sla_in.rd,
reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
@@ -216,7 +216,7 @@ BEGIN
reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
-- MM control interface
clk => mm_clk,
- reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+ reg_addr => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
reg_rd => mm_sla_in.rd,
reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
diff --git a/libraries/technology/tse/tech_tse_pkg.vhd b/libraries/technology/tse/tech_tse_pkg.vhd
index 603b85d225dce42779499ad9cf2bfc7619493795..2f4a8327c3c3e2d1b7c44f18ce3bd241d6544c10 100644
--- a/libraries/technology/tse/tech_tse_pkg.vhd
+++ b/libraries/technology/tse/tech_tse_pkg.vhd
@@ -28,6 +28,7 @@ PACKAGE tech_tse_pkg IS
CONSTANT c_tech_tse_reg_addr_w : NATURAL := 8; -- = max 256 MAC registers
CONSTANT c_tech_tse_byte_addr_w : NATURAL := c_tech_tse_reg_addr_w + 2;
+ CONSTANT c_tech_tse_reg_addr_pcs_offset : NATURAL := 16#80#; -- table 4.8, 4.9 in ug_ethernet.pdf
CONSTANT c_tech_tse_byte_addr_pcs_offset : NATURAL := 16#200#; -- table 4.8, 4.9 in ug_ethernet.pdf
CONSTANT c_tech_tse_data_w : NATURAL := c_word_w; -- = 32