diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/lofar2_unb2b_adc.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_adc/lofar2_unb2b_adc.fpga.yaml
index f2e2c0667939a5a81e493dc9aaef0509a40bba71..373f67c336f362db51b0f2c07bb4ad4119d930d5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/lofar2_unb2b_adc.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/lofar2_unb2b_adc.fpga.yaml
@@ -11,10 +11,10 @@ peripherals:
# Factory / minimal (from ctrl_unb2b_board.vhd)
#############################################################################
- peripheral_name: unb2b_board/system_info
+ lock_base_address: 0x10000
mm_port_names:
- ROM_SYSTEM_INFO
- PIO_SYSTEM_INFO
- lock_base_address: 0x10000
- peripheral_name: unb2b_board/wdi
mm_port_names:
@@ -79,7 +79,7 @@ peripherals:
- peripheral_name: dp/dp_bsn_source
parameter_overrides:
- - { name: g_nof_block_per_sync, value: 195313 } # 390625 = 2 * 195312, to have integer number of blocks in 2 s sync interval
+ - { name: g_nof_block_per_sync, value: 390625 } # EK: TODO temporarily use 390625 = 2 * 195312.5, to have integer number of blocks in 2 s sync interval, TODO: remove when REG_BSN_SOURCE_V2 is used
mm_port_names:
- REG_BSN_SOURCE
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
index 15c8d9491520943af0974a751f9a88452407ecdf..674f5ceb675cef28356a62c13099580c279a810f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
@@ -31,17 +31,17 @@ parameters:
- { name: c_W_beamlet_resolution, value: 0 - 15 } # EK: FIXME support passing on negative values, workaround use 0 - positive
- { name: c_W_beamlet, value: 8 }
- { name: c_nof_clk_per_pps, value: c_f_adc_MHz * 10**6 } # = 200000000
- - { name: c_nof_block_per_sync, value: 195313 } # TBD temporarily use 390625 = 2 * 195312, to have integer number of blocks in 2 s sync interval, TODO: remove when REG_BSN_SOURCE_V2 is used
+ - { name: c_nof_block_per_sync, value: 390625 } # EK: TODO temporarily use 390625 = 2 * 195312.5, to have integer number of blocks in 2 s sync interval, TODO: remove when REG_BSN_SOURCE_V2 is used
peripherals:
#############################################################################
# Factory / minimal (see ctrl_unb2b_board.vhd)
#############################################################################
- peripheral_name: unb2b_board/system_info
+ lock_base_address: 0x10000
mm_port_names:
- ROM_SYSTEM_INFO
- PIO_SYSTEM_INFO
- lock_base_address: 0x10000
- peripheral_name: unb2b_board/wdi
mm_port_names:
@@ -51,39 +51,39 @@ peripherals:
mm_port_names:
- REG_FPGA_TEMP_SENS
- REG_FPGA_VOLTAGE_SENS
-
+
- peripheral_name: unb2b_board/ram_scrap
mm_port_names:
- RAM_SCRAP
-
+
- peripheral_name: eth/eth
mm_port_names:
- AVS_ETH_0_TSE
- AVS_ETH_0_REG
- AVS_ETH_0_RAM
-
+
- peripheral_name: ppsh/ppsh
mm_port_names:
- PIO_PPS
-
+
- peripheral_name: epcs/epcs
mm_port_names:
- REG_EPCS
-
+
- peripheral_name: dp/dpmm
mm_port_names:
- REG_DPMM_CTRL
- REG_DPMM_DATA
-
+
- peripheral_name: dp/mmdp
mm_port_names:
- REG_MMDP_CTRL
- REG_MMDP_DATA
-
+
- peripheral_name: remu/remu
mm_port_names:
- REG_REMU
-
+
#############################################################################
# AIT = ADC Input and Timing (see node_adc_input_and_timing.vhd)
#############################################################################
@@ -172,9 +172,12 @@ peripherals:
- peripheral_name: filter/fil_ppf_w
parameter_overrides:
- - { name: g_nof_taps, value: c_N_taps }
- - { name: g_nof_bands, value: c_N_fft }
- - { name: g_coef_dat_w, value: c_W_fir_coef }
+ - { name: g_fil_ppf.wb_factor, value: 1 } # process at sample rate
+ - { name: g_fil_ppf.nof_chan, value: 0 } # process at sample rate
+ - { name: g_fil_ppf.nof_bands, value: c_N_fft }
+ - { name: g_fil_ppf.nof_taps, value: c_N_taps }
+ - { name: g_fil_ppf.nof_streams, value: 1 }
+ - { name: g_fil_ppf.coef_dat_w, value: c_W_fir_coef }
mm_port_names:
- RAM_FIL_COEFS
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.mmap.gold b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.mmap.gold
new file mode 100644
index 0000000000000000000000000000000000000000..c92f08599cc8e1bc8974564f4843ca59843095d4
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.mmap.gold
@@ -0,0 +1,474 @@
+fpga_name = lofar2_unb2b_beamformer
+number_of_columns = 11
+# There can be multiple lines with a single key. The host should ignore unknown keys.
+# The lines with columns follow after the number_of_columns keys. The host should ignore
+# the extra columns in case the mmap contains more columns than the host expects.
+#
+# col 1: mm_port_name, if - then it is part of previous MM port.
+# col 2: number of peripherals, if - then it is part of previous peripheral.
+# col 3: number of mm_ports, if - then it is part of previous MM port.
+# col 4: mm_port_type, if - then it is part of previous MM port.
+# col 5: field_name
+# col 6: field start address (in MM words)
+# col 7: number of fields, if - then it is part of previous field_name.
+# col 8: field access_mode, if - then it is part of previous field_name.
+# col 9: field radix, if - then it is part of previous field_name.
+# col 10: field mm_mask
+# col 11: field user_mask, if - then it is same as mm_mask
+#
+# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11
+# ------------------------ ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ----------
+ ROM_SYSTEM_INFO 1 1 RAM data 0x00000000 32768 RO char8 b[31:0] b[7:0]
+ PIO_SYSTEM_INFO 1 1 REG info 0x00008000 1 RO uint32 b[31:0] -
+ - - - - info_gn_index 0x00008000 1 RO uint32 b[7:0] -
+ - - - - info_hw_version 0x00008000 1 RO uint32 b[9:8] -
+ - - - - info_cs_sim 0x00008000 1 RO uint32 b[10:10] -
+ - - - - info_fw_version_major 0x00008000 1 RO uint32 b[19:16] -
+ - - - - info_fw_version_minor 0x00008000 1 RO uint32 b[23:20] -
+ - - - - info_rom_version 0x00008000 1 RO uint32 b[26:24] -
+ - - - - info_technology 0x00008000 1 RO uint32 b[31:27] -
+ - - - - use_phy 0x00008001 1 RO uint32 b[7:0] -
+ - - - - design_name 0x00008002 52 RO char8 b[31:0] b[7:0]
+ - - - - stamp_date 0x0000800f 1 RO uint32 b[31:0] -
+ - - - - stamp_time 0x00008010 1 RO uint32 b[31:0] -
+ - - - - stamp_commit 0x00008011 3 RO uint32 b[31:0] -
+ - - - - design_note 0x00008014 52 RO char8 b[31:0] b[7:0]
+ PIO_WDI 1 1 REG wdi_override 0x0000a000 1 WO uint32 b[31:0] -
+ REG_FPGA_TEMP_SENS 1 1 REG temp 0x0000c000 1 RO uint32 b[31:0] -
+ REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x0000c000 6 RO uint32 b[31:0] -
+ RAM_SCRAP 1 1 RAM data 0x0000e000 512 RW uint32 b[31:0] -
+ AVS_ETH_0_TSE 1 1 REG status 0x00010000 1024 RO uint32 b[31:0] -
+ AVS_ETH_0_REG 1 1 REG status 0x00010000 12 RO uint32 b[31:0] -
+ AVS_ETH_0_RAM 1 1 RAM data 0x00010400 1024 RW uint32 b[31:0] -
+ PIO_PPS 1 1 REG capture_cnt 0x00012000 1 RO uint32 b[29:0] -
+ - - - - stable 0x00012000 1 RO uint32 b[30:30] -
+ - - - - toggle 0x00012000 1 RO uint32 b[31:31] -
+ - - - - expected_cnt 0x00012001 1 RW uint32 b[27:0] -
+ - - - - edge 0x00012001 1 RW uint32 b[31:31] -
+ - - - - offset_cnt 0x00012002 1 RO uint32 b[27:0] -
+ REG_EPCS 1 1 REG addr 0x00014000 1 WO uint32 b[23:0] -
+ - - - - rden 0x00014001 1 WO uint32 b[0:0] -
+ - - - - read_bit 0x00014002 1 WO uint32 b[0:0] -
+ - - - - write_bit 0x00014003 1 WO uint32 b[0:0] -
+ - - - - sector_erase 0x00014004 1 WO uint32 b[0:0] -
+ - - - - busy 0x00014005 1 RO uint32 b[0:0] -
+ - - - - unprotect 0x00014006 1 WO uint32 b[31:0] -
+ REG_DPMM_CTRL 1 1 REG rd_usedw 0x00016000 1 RO uint32 b[31:0] -
+ REG_DPMM_DATA 1 1 FIFO data 0x00016400 1 RO uint32 b[31:0] -
+ REG_MMDP_CTRL 1 1 REG wr_usedw 0x00018000 1 RO uint32 b[31:0] -
+ - - - - wr_availw 0x00018001 1 RO uint32 b[31:0] -
+ REG_MMDP_DATA 1 1 FIFO data 0x00018400 1 WO uint32 b[31:0] -
+ REG_REMU 1 1 REG reconfigure 0x0001a000 1 WO uint32 b[31:0] -
+ - - - - param 0x0001a001 1 WO uint32 b[2:0] -
+ - - - - read_param 0x0001a002 1 WO uint32 b[0:0] -
+ - - - - write_param 0x0001a003 1 WO uint32 b[0:0] -
+ - - - - data_out 0x0001a004 1 RO uint32 b[23:0] -
+ - - - - data_in 0x0001a005 1 WO uint32 b[23:0] -
+ - - - - busy 0x0001a006 1 RO uint32 b[0:0] -
+ PIO_JESD_CTRL 1 1 REG enable 0x0001c000 1 RW uint32 b[30:0] -
+ - - - - reset 0x0001c000 1 RW uint32 b[31:31] -
+ JESD204B 1 1 REG rx_dll_ctrl 0x0001e014 1 RW uint32 b[16:0] -
+ - - - - rx_syncn_sysref_ctrl 0x0001e015 1 RW uint32 b[24:0] -
+ - - - - rx_csr_sysref_always_on 0x0001e015 1 RW uint32 b[1:1] -
+ - - - - rx_csr_rbd_offset 0x0001e015 1 RW uint32 b[10:3] -
+ - - - - rx_csr_lmfc_offset 0x0001e015 1 RW uint32 b[19:12] -
+ - - - - rx_err0 0x0001e018 1 RW uint32 b[8:0] -
+ - - - - rx_err1 0x0001e019 1 RW uint32 b[9:0] -
+ - - - - csr_dev_syncn 0x0001e020 1 RO uint32 b[0:0] -
+ - - - - csr_rbd_count 0x0001e020 1 RO uint32 b[10:3] -
+ - - - - rx_status1 0x0001e021 1 RW uint32 b[23:0] -
+ - - - - rx_status2 0x0001e022 1 RW uint32 b[23:0] -
+ - - - - rx_status3 0x0001e023 1 RW uint32 b[7:0] -
+ - - - - rx_ilas_csr_l 0x0001e025 1 RW uint32 b[4:0] -
+ - - - - rx_ilas_csr_f 0x0001e025 1 RW uint32 b[15:8] -
+ - - - - rx_ilas_csr_k 0x0001e025 1 RW uint32 b[20:16] -
+ - - - - rx_ilas_csr_m 0x0001e025 1 RW uint32 b[31:24] -
+ - - - - rx_ilas_csr_n 0x0001e026 1 RW uint32 b[4:0] -
+ - - - - rx_ilas_csr_cs 0x0001e026 1 RW uint32 b[7:6] -
+ - - - - rx_ilas_csr_np 0x0001e026 1 RW uint32 b[12:8] -
+ - - - - rx_ilas_csr_subclassv 0x0001e026 1 RW uint32 b[15:13] -
+ - - - - rx_ilas_csr_s 0x0001e026 1 RW uint32 b[20:16] -
+ - - - - rx_ilas_csr_jesdv 0x0001e026 1 RW uint32 b[23:21] -
+ - - - - rx_ilas_csr_cf 0x0001e026 1 RW uint32 b[28:24] -
+ - - - - rx_ilas_csr_hd 0x0001e026 1 RW uint32 b[31:31] -
+ - - - - rx_status4 0x0001e03c 1 RW uint32 b[15:0] -
+ - - - - rx_status5 0x0001e03d 1 RW uint32 b[15:0] -
+ - - - - rx_status6 0x0001e03e 1 RW uint32 b[23:0] -
+ - - - - rx_status7 0x0001e03f 1 RO uint32 b[31:0] -
+ REG_DP_SHIFTRAM 1 12 REG shift 0x00020000 1 RW uint32 b[11:0] -
+ REG_BSN_SOURCE 1 1 REG dp_on 0x00022000 1 RW uint32 b[0:0] -
+ - - - - dp_on_pps 0x00022000 1 RW uint32 b[1:1] -
+ - - - - nof_block_per_sync 0x00022001 1 RW uint32 b[31:0] -
+ - - - - bsn 0x00022002 1 RW uint64 b[31:0] b[31:0]
+ - - - - - 0x00022003 - - - b[31:0] b[63:32]
+ REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x00024000 1 RW uint64 b[31:0] b[31:0]
+ - - - - - 0x00024001 - - - b[31:0] b[63:32]
+ REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00026000 1 RO uint32 b[0:0] -
+ - - - - ready_stable 0x00026000 1 RO uint32 b[1:1] -
+ - - - - sync_timeout 0x00026000 1 RO uint32 b[2:2] -
+ - - - - bsn_at_sync 0x00026001 1 RO uint64 b[31:0] b[31:0]
+ - - - - - 0x00026002 - - - b[31:0] b[63:32]
+ - - - - nof_sop 0x00026003 1 RO uint32 b[31:0] -
+ - - - - nof_valid 0x00026004 1 RO uint32 b[31:0] -
+ - - - - nof_err 0x00026005 1 RO uint32 b[31:0] -
+ - - - - bsn_first 0x00026006 1 RO uint64 b[31:0] b[31:0]
+ - - - - - 0x00026007 - - - b[31:0] b[63:32]
+ - - - - bsn_first_cycle_cnt 0x00026008 1 RO uint32 b[31:0] -
+ REG_DIAG_WG 1 12 REG mode 0x00028000 1 RW uint32 b[7:0] -
+ - - - - nof_samples 0x00028000 1 RW uint32 b[31:16] -
+ - - - - phase 0x00028001 1 RW uint32 b[15:0] -
+ - - - - freq 0x00028002 1 RW uint32 b[30:0] -
+ - - - - ampl 0x00028003 1 RW uint32 b[16:0] -
+ RAM_DIAG_WG 1 12 RAM data 0x0002c000 1024 RW uint32 b[17:0] -
+ REG_ADUH_MON 1 12 REG mean_sum_lo 0x00030000 1 RO uint32 b[31:0] -
+ - - - - mean_sum_hi 0x00030001 1 RO uint32 b[31:0] -
+ - - - - power_sum_lo 0x00030002 1 RO uint32 b[31:0] -
+ - - - - power_sum_hi 0x00030003 1 RO uint32 b[31:0] -
+ REG_DIAG_DATA_BUF_BSN 1 12 REG sync_cnt 0x00032000 1 RO uint32 b[31:0] -
+ - - - - word_cnt 0x00032001 1 RO uint32 b[31:0] -
+ RAM_DIAG_DATA_BUF_BSN 1 12 RAM data 0x00034000 1024 RW uint32 b[15:0] -
+ REG_SI 1 1 REG enable 0x00038000 1 RW uint32 b[0:0] -
+ RAM_FIL_COEFS 1 16 RAM data 0x0003c000 1024 RW uint32 b[15:0] -
+ RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] -
+ REG_DP_SELECTOR 1 1 REG input_select 0x00042000 1 RW uint32 b[0:0] -
+ RAM_ST_SST 1 6 RAM data 0x00044000 2048 RW uint64 b[31:0] b[31:0]
+ - - - - - 0x00042001 - - - b[21:0] b[53:32]
+ REG_STAT_ENABLE 1 1 REG enable 0x00048000 1 RW uint32 b[0:0] -
+ REG_STAT_HDR_INFO 1 1 REG bsn 0x0004a000 1 RW uint64 b[31:0] b[31:0]
+ - - - - - 0x0004a001 - - - b[31:0] b[63:32]
+ - - - - block_period 0x0004a002 1 RW uint32 b[15:0] -
+ - - - - nof_statistics_per_packet 0x0004a003 1 RW uint32 b[15:0] -
+ - - - - nof_bytes_per_statistic 0x0004a004 1 RW uint32 b[7:0] -
+ - - - - nof_signal_inputs 0x0004a005 1 RW uint32 b[7:0] -
+ - - - - data_id 0x0004a006 1 RW uint32 b[31:0] -
+ - - - - data_id_sst_signal_input_index 0x0004a006 1 RW uint32 b[7:0] -
+ - - - - data_id_sst_reserved 0x0004a006 1 RW uint32 b[31:8] -
+ - - - - integration_interval 0x0004a007 1 RW uint32 b[23:0] -
+ - - - - reserved 0x0004a008 1 RW uint32 b[7:0] -
+ - - - - source_info 0x0004a009 1 RW uint32 b[15:0] -
+ - - - - source_info_gn_index 0x0004a009 1 RW uint32 b[4:0] -
+ - - - - source_info_reserved 0x0004a009 1 RW uint32 b[7:5] -
+ - - - - source_info_subband_calibrated_flag 0x0004a009 1 RW uint32 b[8:8] -
+ - - - - source_info_beam_repositioning_flag 0x0004a009 1 RW uint32 b[9:9] -
+ - - - - source_info_payload_error 0x0004a009 1 RW uint32 b[10:10] -
+ - - - - source_info_fsub_type 0x0004a009 1 RW uint32 b[11:11] -
+ - - - - source_info_f_adc 0x0004a009 1 RW uint32 b[12:12] -
+ - - - - source_info_nyquist_zone_index 0x0004a009 1 RW uint32 b[14:13] -
+ - - - - source_info_antenna_band_index 0x0004a009 1 RW uint32 b[15:15] -
+ - - - - station_id 0x0004a00a 1 RW uint32 b[15:0] -
+ - - - - observation_id 0x0004a00b 1 RW uint32 b[31:0] -
+ - - - - version_id 0x0004a00c 1 RO uint32 b[7:0] -
+ - - - - marker 0x0004a00d 1 RO uint32 b[7:0] -
+ - - - - udp_checksum 0x0004a00e 1 RW uint32 b[15:0] -
+ - - - - udp_length 0x0004a00f 1 RW uint32 b[15:0] -
+ - - - - udp_destination_port 0x0004a010 1 RW uint32 b[15:0] -
+ - - - - udp_source_port 0x0004a011 1 RW uint32 b[15:0] -
+ - - - - ip_destination_address 0x0004a012 1 RW uint32 b[31:0] -
+ - - - - ip_source_address 0x0004a013 1 RW uint32 b[31:0] -
+ - - - - ip_header_checksum 0x0004a014 1 RW uint32 b[15:0] -
+ - - - - ip_protocol 0x0004a015 1 RW uint32 b[7:0] -
+ - - - - ip_time_to_live 0x0004a016 1 RW uint32 b[7:0] -
+ - - - - ip_fragment_offset 0x0004a017 1 RW uint32 b[12:0] -
+ - - - - ip_flags 0x0004a018 1 RW uint32 b[2:0] -
+ - - - - ip_identification 0x0004a019 1 RW uint32 b[15:0] -
+ - - - - ip_total_length 0x0004a01a 1 RW uint32 b[15:0] -
+ - - - - ip_services 0x0004a01b 1 RW uint32 b[7:0] -
+ - - - - ip_header_length 0x0004a01c 1 RW uint32 b[3:0] -
+ - - - - ip_version 0x0004a01d 1 RW uint32 b[3:0] -
+ - - - - eth_type 0x0004a01e 1 RO uint32 b[15:0] -
+ - - - - eth_source_mac 0x0004a01f 1 RO uint64 b[31:0] b[31:0]
+ - - - - - 0x0004a020 - - - b[15:0] b[47:32]
+ - - - - eth_destination_mac 0x0004a021 1 RW uint64 b[31:0] b[31:0]
+ - - - - - 0x0004a022 - - - b[15:0] b[47:32]
+ - - - - word_align 0x0004a023 1 RW uint32 b[15:0] -
+ REG_SDP_INFO 1 1 REG station_id 0x0004c000 1 RW uint32 b[15:0] -
+ - - - - antenna_band_index 0x0004c001 1 RO uint32 b[0:0] -
+ - - - - observation_id 0x0004c002 1 RW uint32 b[31:0] -
+ - - - - nyquist_zone_index 0x0004c003 1 RW uint32 b[1:0] -
+ - - - - f_adc 0x0004c004 1 RO uint32 b[0:0] -
+ - - - - fsub_type 0x0004c005 1 RO uint32 b[0:0] -
+ - - - - beam_repositioning_flag 0x0004c006 1 RW uint32 b[0:0] -
+ - - - - subband_calibrated_flag 0x0004c007 1 RW uint32 b[0:0] -
+ - - - - o_si 0x0004c008 1 RW uint32 b[7:0] -
+ - - - - n_si 0x0004c009 1 RW uint32 b[7:0] -
+ - - - - o_rn 0x0004c00a 1 RW uint32 b[7:0] -
+ - - - - n_rn 0x0004c00b 1 RW uint32 b[7:0] -
+ - - - - block_period 0x0004c00c 1 RO uint32 b[15:0] -
+ - - - - beamlet_scale 0x0004c00d 1 RW uint32 b[15:0] -
+ RAM_SS_SS_WIDE 2 6 RAM data 0x0004e000 976 RW uint32 b[9:0] -
+ RAM_BF_WEIGHTS 2 12 RAM data 0x00054000 976 RW cint16_ir b[31:0] -
+ REG_BF_SCALE 2 1 REG scale 0x0005c000 1 RW uint32 b[15:0] -
+ - - - - unused 0x0005c001 1 RW uint32 b[31:0] -
+ REG_HDR_DAT 2 1 REG bsn 0x0005e000 1 RW uint64 b[31:0] b[31:0]
+ - - - - - 0x0005e001 - - - b[31:0] b[63:32]
+ - - - - block_period 0x0005e002 1 RW uint32 b[15:0] -
+ - - - - nof_beamlets_per_block 0x0005e003 1 RW uint32 b[15:0] -
+ - - - - nof_blocks_per_packet 0x0005e004 1 RW uint32 b[7:0] -
+ - - - - beamlet_index 0x0005e005 1 RW uint32 b[15:0] -
+ - - - - beamlet_scale 0x0005e006 1 RW uint32 b[15:0] -
+ - - - - reserved 0x0005e007 1 RW uint64 b[31:0] b[31:0]
+ - - - - - 0x0005e008 - - - b[7:0] b[39:32]
+ - - - - source_info 0x0005e009 1 RW uint32 b[15:0] -
+ - - - - source_info_gn_index 0x0005e009 1 RW uint32 b[4:0] -
+ - - - - source_info_beamlet_width 0x0005e009 1 RW uint32 b[7:5] -
+ - - - - source_info_repositioning_flag 0x0005e009 1 RW uint32 b[9:9] -
+ - - - - source_info_payload_error 0x0005e009 1 RW uint32 b[10:10] -
+ - - - - source_info_fsub_type 0x0005e009 1 RW uint32 b[11:11] -
+ - - - - source_info_f_adc 0x0005e009 1 RW uint32 b[12:12] -
+ - - - - source_info_nyquist_zone_index 0x0005e009 1 RW uint32 b[14:13] -
+ - - - - source_info_antenna_band_index 0x0005e009 1 RW uint32 b[15:15] -
+ - - - - station_id 0x0005e00a 1 RW uint32 b[15:0] -
+ - - - - observation_id 0x0005e00b 1 RW uint32 b[31:0] -
+ - - - - version_id 0x0005e00c 1 RO uint32 b[7:0] -
+ - - - - marker 0x0005e00d 1 RO uint32 b[7:0] -
+ - - - - udp_checksum 0x0005e00e 1 RW uint32 b[15:0] -
+ - - - - udp_length 0x0005e00f 1 RW uint32 b[15:0] -
+ - - - - udp_destination_port 0x0005e010 1 RW uint32 b[15:0] -
+ - - - - udp_source_port 0x0005e011 1 RW uint32 b[15:0] -
+ - - - - ip_destination_address 0x0005e012 1 RW uint32 b[31:0] -
+ - - - - ip_source_address 0x0005e013 1 RW uint32 b[31:0] -
+ - - - - ip_header_checksum 0x0005e014 1 RW uint32 b[15:0] -
+ - - - - ip_protocol 0x0005e015 1 RW uint32 b[7:0] -
+ - - - - ip_time_to_live 0x0005e016 1 RW uint32 b[7:0] -
+ - - - - ip_fragment_offset 0x0005e017 1 RW uint32 b[12:0] -
+ - - - - ip_flags 0x0005e018 1 RW uint32 b[2:0] -
+ - - - - ip_identification 0x0005e019 1 RW uint32 b[15:0] -
+ - - - - ip_total_length 0x0005e01a 1 RW uint32 b[15:0] -
+ - - - - ip_services 0x0005e01b 1 RW uint32 b[7:0] -
+ - - - - ip_header_length 0x0005e01c 1 RW uint32 b[3:0] -
+ - - - - ip_version 0x0005e01d 1 RW uint32 b[3:0] -
+ - - - - eth_type 0x0005e01e 1 RO uint32 b[15:0] -
+ - - - - eth_source_mac 0x0005e01f 1 RO uint64 b[31:0] b[31:0]
+ - - - - - 0x0005e020 - - - b[15:0] b[47:32]
+ - - - - eth_destination_mac 0x0005e021 1 RW uint64 b[31:0] b[31:0]
+ - - - - - 0x0005e022 - - - b[15:0] b[47:32]
+ REG_DP_XONOFF 2 1 REG enable_stream 0x00060000 1 RW uint32 b[0:0] -
+ RAM_ST_BST 2 1 RAM data 0x00062000 1952 RW uint64 b[31:0] b[31:0]
+ - - - - - 0x00060001 - - - b[21:0] b[53:32]
+ REG_STAT_ENABLE_BST 1 1 REG enable 0x00064000 1 RW uint32 b[0:0] -
+ REG_STAT_HDR_INFO_BST 1 1 REG bsn 0x00066000 1 RW uint64 b[31:0] b[31:0]
+ - - - - - 0x00066001 - - - b[31:0] b[63:32]
+ - - - - block_period 0x00066002 1 RW uint32 b[15:0] -
+ - - - - nof_statistics_per_packet 0x00066003 1 RW uint32 b[15:0] -
+ - - - - nof_bytes_per_statistic 0x00066004 1 RW uint32 b[7:0] -
+ - - - - nof_signal_inputs 0x00066005 1 RW uint32 b[7:0] -
+ - - - - data_id 0x00066006 1 RW uint32 b[31:0] -
+ - - - - data_id_bst_beamlet_index 0x00066006 1 RW uint32 b[15:0] -
+ - - - - data_id_bst_reserved 0x00066006 1 RW uint32 b[31:16] -
+ - - - - integration_interval 0x00066007 1 RW uint32 b[23:0] -
+ - - - - reserved 0x00066008 1 RW uint32 b[7:0] -
+ - - - - source_info 0x00066009 1 RW uint32 b[15:0] -
+ - - - - source_info_gn_index 0x00066009 1 RW uint32 b[4:0] -
+ - - - - source_info_reserved 0x00066009 1 RW uint32 b[7:5] -
+ - - - - source_info_subband_calibrated_flag 0x00066009 1 RW uint32 b[8:8] -
+ - - - - source_info_beam_repositioning_flag 0x00066009 1 RW uint32 b[9:9] -
+ - - - - source_info_payload_error 0x00066009 1 RW uint32 b[10:10] -
+ - - - - source_info_fsub_type 0x00066009 1 RW uint32 b[11:11] -
+ - - - - source_info_f_adc 0x00066009 1 RW uint32 b[12:12] -
+ - - - - source_info_nyquist_zone_index 0x00066009 1 RW uint32 b[14:13] -
+ - - - - source_info_antenna_band_index 0x00066009 1 RW uint32 b[15:15] -
+ - - - - station_id 0x0006600a 1 RW uint32 b[15:0] -
+ - - - - observation_id 0x0006600b 1 RW uint32 b[31:0] -
+ - - - - version_id 0x0006600c 1 RO uint32 b[7:0] -
+ - - - - marker 0x0006600d 1 RO uint32 b[7:0] -
+ - - - - udp_checksum 0x0006600e 1 RW uint32 b[15:0] -
+ - - - - udp_length 0x0006600f 1 RW uint32 b[15:0] -
+ - - - - udp_destination_port 0x00066010 1 RW uint32 b[15:0] -
+ - - - - udp_source_port 0x00066011 1 RW uint32 b[15:0] -
+ - - - - ip_destination_address 0x00066012 1 RW uint32 b[31:0] -
+ - - - - ip_source_address 0x00066013 1 RW uint32 b[31:0] -
+ - - - - ip_header_checksum 0x00066014 1 RW uint32 b[15:0] -
+ - - - - ip_protocol 0x00066015 1 RW uint32 b[7:0] -
+ - - - - ip_time_to_live 0x00066016 1 RW uint32 b[7:0] -
+ - - - - ip_fragment_offset 0x00066017 1 RW uint32 b[12:0] -
+ - - - - ip_flags 0x00066018 1 RW uint32 b[2:0] -
+ - - - - ip_identification 0x00066019 1 RW uint32 b[15:0] -
+ - - - - ip_total_length 0x0006601a 1 RW uint32 b[15:0] -
+ - - - - ip_services 0x0006601b 1 RW uint32 b[7:0] -
+ - - - - ip_header_length 0x0006601c 1 RW uint32 b[3:0] -
+ - - - - ip_version 0x0006601d 1 RW uint32 b[3:0] -
+ - - - - eth_type 0x0006601e 1 RO uint32 b[15:0] -
+ - - - - eth_source_mac 0x0006601f 1 RO uint64 b[31:0] b[31:0]
+ - - - - - 0x00066020 - - - b[15:0] b[47:32]
+ - - - - eth_destination_mac 0x00066021 1 RW uint64 b[31:0] b[31:0]
+ - - - - - 0x00066022 - - - b[15:0] b[47:32]
+ - - - - word_align 0x00066023 1 RW uint32 b[15:0] -
+ REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00068000 1 RW uint32 b[0:0] -
+ - - - - rx_transfer_status 0x00068001 1 RO uint32 b[0:0] -
+ - - - - tx_transfer_control 0x00068002 1 RW uint32 b[0:0] -
+ - - - - rx_padcrc_control 0x00068040 1 RW uint32 b[1:0] -
+ - - - - rx_crccheck_control 0x00068080 1 RW uint32 b[1:0] -
+ - - - - rx_pktovrflow_error 0x000680c0 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x000680c1 - - - b[31:0] b[31:0]
+ - - - - rx_pktovrflow_etherstatsdropevents 0x000680c2 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x000680c3 - - - b[31:0] b[31:0]
+ - - - - rx_lane_decoder_preamble_control 0x00068100 1 RW uint32 b[0:0] -
+ - - - - rx_preamble_inserter_control 0x00068140 1 RW uint32 b[0:0] -
+ - - - - rx_frame_control 0x00068800 1 RW uint32 b[19:0] -
+ - - - - rx_frame_maxlength 0x00068801 1 RW uint32 b[15:0] -
+ - - - - rx_frame_addr0 0x00068802 1 RW uint32 b[15:0] -
+ - - - - rx_frame_addr1 0x00068803 1 RW uint32 b[15:0] -
+ - - - - rx_frame_spaddr0_0 0x00068804 1 RW uint32 b[15:0] -
+ - - - - rx_frame_spaddr0_1 0x00068805 1 RW uint32 b[15:0] -
+ - - - - rx_frame_spaddr1_0 0x00068806 1 RW uint32 b[15:0] -
+ - - - - rx_frame_spaddr1_1 0x00068807 1 RW uint32 b[15:0] -
+ - - - - rx_frame_spaddr2_0 0x00068808 1 RW uint32 b[15:0] -
+ - - - - rx_frame_spaddr2_1 0x00068809 1 RW uint32 b[15:0] -
+ - - - - rx_frame_spaddr3_0 0x0006880a 1 RW uint32 b[15:0] -
+ - - - - rx_frame_spaddr3_1 0x0006880b 1 RW uint32 b[15:0] -
+ - - - - rx_pfc_control 0x00068818 1 RW uint32 b[16:0] -
+ - - - - rx_stats_clr 0x00068c00 1 RW uint32 b[0:0] -
+ - - - - rx_stats_framesok 0x00068c02 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c03 - - - b[31:0] b[31:0]
+ - - - - rx_stats_frameserr 0x00068c04 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c05 - - - b[31:0] b[31:0]
+ - - - - rx_stats_framescrcerr 0x00068c06 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c07 - - - b[31:0] b[31:0]
+ - - - - rx_stats_octetsok 0x00068c08 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c09 - - - b[31:0] b[31:0]
+ - - - - rx_stats_pausemacctrl_frames 0x00068c0a 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c0b - - - b[31:0] b[31:0]
+ - - - - rx_stats_iferrors 0x00068c0c 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c0d - - - b[31:0] b[31:0]
+ - - - - rx_stats_unicast_framesok 0x00068c0e 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c0f - - - b[31:0] b[31:0]
+ - - - - rx_stats_unicast_frameserr 0x00068c10 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c11 - - - b[31:0] b[31:0]
+ - - - - rx_stats_multicastframesok 0x00068c12 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c13 - - - b[31:0] b[31:0]
+ - - - - rx_stats_multicast_frameserr 0x00068c14 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c15 - - - b[31:0] b[31:0]
+ - - - - rx_stats_broadcastframesok 0x00068c16 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c17 - - - b[31:0] b[31:0]
+ - - - - rx_stats_broadcast_frameserr 0x00068c18 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c19 - - - b[31:0] b[31:0]
+ - - - - rx_stats_etherstatsoctets 0x00068c1a 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c1b - - - b[31:0] b[31:0]
+ - - - - rx_stats_etherstatspkts 0x00068c1c 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c1d - - - b[31:0] b[31:0]
+ - - - - rx_stats_etherstats_undersizepkts 0x00068c1e 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c1f - - - b[31:0] b[31:0]
+ - - - - rx_stats_etherstats_oversizepkts 0x00068c20 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c21 - - - b[31:0] b[31:0]
+ - - - - rx_stats_etherstats_pkts64octets 0x00068c22 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c23 - - - b[31:0] b[31:0]
+ - - - - rx_stats_etherstats_pkts65to127octets 0x00068c24 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c25 - - - b[31:0] b[31:0]
+ - - - - rx_stats_etherstats_pkts128to255octets 0x00068c26 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c27 - - - b[31:0] b[31:0]
+ - - - - rx_stats_etherstats_pkts256to511octets 0x00068c28 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c29 - - - b[31:0] b[31:0]
+ - - - - rx_stats_etherstats_pkts512to1023octets 0x00068c2a 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c2b - - - b[31:0] b[31:0]
+ - - - - rx_stats_etherstat_pkts1024to1518octets 0x00068c2c 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c2d - - - b[31:0] b[31:0]
+ - - - - rx_stats_etherstats_pkts1519toxoctets 0x00068c2e 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c2f - - - b[31:0] b[31:0]
+ - - - - rx_stats_etherstats_fragments 0x00068c30 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c31 - - - b[31:0] b[31:0]
+ - - - - rx_stats_etherstats_jabbers 0x00068c32 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c33 - - - b[31:0] b[31:0]
+ - - - - rx_stats_etherstatscrcerr 0x00068c34 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c35 - - - b[31:0] b[31:0]
+ - - - - rx_stats_unicastmacctrlframes 0x00068c36 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c37 - - - b[31:0] b[31:0]
+ - - - - rx_stats_multicastmac_ctrlframes 0x00068c38 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c39 - - - b[31:0] b[31:0]
+ - - - - rx_stats_broadcastmac_ctrlframes 0x00068c3a 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c3b - - - b[31:0] b[31:0]
+ - - - - rx_stats_pfcmacctrlframes 0x00068c3c 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00068c3d - - - b[31:0] b[31:0]
+ - - - - tx_transfer_status 0x00069001 1 RO uint32 b[0:0] -
+ - - - - tx_padins_control 0x00069040 1 RW uint32 b[0:0] -
+ - - - - tx_crcins_control 0x00069080 1 RW uint32 b[1:0] -
+ - - - - tx_pktunderflow_error 0x000690c0 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x000690c1 - - - b[31:0] b[31:0]
+ - - - - tx_preamble_control 0x00069100 1 RW uint32 b[0:0] -
+ - - - - tx_pauseframe_control 0x00069140 1 RW uint32 b[1:0] -
+ - - - - tx_pauseframe_quanta 0x00069141 1 RW uint32 b[15:0] -
+ - - - - tx_pauseframe_enable 0x00069142 1 RW uint32 b[0:0] -
+ - - - - pfc_pause_quanta_0 0x00069180 1 RW uint32 b[31:0] -
+ - - - - pfc_pause_quanta_1 0x00069181 1 RW uint32 b[31:0] -
+ - - - - pfc_pause_quanta_2 0x00069182 1 RW uint32 b[31:0] -
+ - - - - pfc_pause_quanta_3 0x00069183 1 RW uint32 b[31:0] -
+ - - - - pfc_pause_quanta_4 0x00069184 1 RW uint32 b[31:0] -
+ - - - - pfc_pause_quanta_5 0x00069185 1 RW uint32 b[31:0] -
+ - - - - pfc_pause_quanta_6 0x00069186 1 RW uint32 b[31:0] -
+ - - - - pfc_pause_quanta_7 0x00069187 1 RW uint32 b[31:0] -
+ - - - - pfc_holdoff_quanta_0 0x00069190 1 RW uint32 b[31:0] -
+ - - - - pfc_holdoff_quanta_1 0x00069191 1 RW uint32 b[31:0] -
+ - - - - pfc_holdoff_quanta_2 0x00069192 1 RW uint32 b[31:0] -
+ - - - - pfc_holdoff_quanta_3 0x00069193 1 RW uint32 b[31:0] -
+ - - - - pfc_holdoff_quanta_4 0x00069194 1 RW uint32 b[31:0] -
+ - - - - pfc_holdoff_quanta_5 0x00069195 1 RW uint32 b[31:0] -
+ - - - - pfc_holdoff_quanta_6 0x00069196 1 RW uint32 b[31:0] -
+ - - - - pfc_holdoff_quanta_7 0x00069197 1 RW uint32 b[31:0] -
+ - - - - tx_pfc_priority_enable 0x000691a0 1 RW uint32 b[7:0] -
+ - - - - tx_addrins_control 0x00069200 1 RW uint32 b[0:0] -
+ - - - - tx_addrins_macaddr0 0x00069201 1 RW uint32 b[31:0] -
+ - - - - tx_addrins_macaddr1 0x00069202 1 RW uint32 b[15:0] -
+ - - - - tx_frame_maxlength 0x00069801 1 RW uint32 b[15:0] -
+ - - - - tx_stats_clr 0x00069c00 1 RW uint32 b[0:0] -
+ - - - - tx_stats_framesok 0x00069c02 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c03 - - - b[31:0] b[31:0]
+ - - - - tx_stats_frameserr 0x00069c04 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c05 - - - b[31:0] b[31:0]
+ - - - - tx_stats_framescrcerr 0x00069c06 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c07 - - - b[31:0] b[31:0]
+ - - - - tx_stats_octetsok 0x00069c08 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c09 - - - b[31:0] b[31:0]
+ - - - - tx_stats_pausemacctrl_frames 0x00069c0a 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c0b - - - b[31:0] b[31:0]
+ - - - - tx_stats_iferrors 0x00069c0c 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c0d - - - b[31:0] b[31:0]
+ - - - - tx_stats_unicast_framesok 0x00069c0e 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c0f - - - b[31:0] b[31:0]
+ - - - - tx_stats_unicast_frameserr 0x00069c10 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c11 - - - b[31:0] b[31:0]
+ - - - - tx_stats_multicastframesok 0x00069c12 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c13 - - - b[31:0] b[31:0]
+ - - - - tx_stats_multicast_frameserr 0x00069c14 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c15 - - - b[31:0] b[31:0]
+ - - - - tx_stats_broadcastframesok 0x00069c16 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c17 - - - b[31:0] b[31:0]
+ - - - - tx_stats_broadcast_frameserr 0x00069c18 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c19 - - - b[31:0] b[31:0]
+ - - - - tx_stats_etherstatsoctets 0x00069c1a 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c1b - - - b[31:0] b[31:0]
+ - - - - tx_stats_etherstatspkts 0x00069c1c 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c1d - - - b[31:0] b[31:0]
+ - - - - tx_stats_etherstats_undersizepkts 0x00069c1e 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c1f - - - b[31:0] b[31:0]
+ - - - - tx_stats_etherstats_oversizepkts 0x00069c20 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c21 - - - b[31:0] b[31:0]
+ - - - - tx_stats_etherstats_pkts64octets 0x00069c22 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c23 - - - b[31:0] b[31:0]
+ - - - - tx_stats_etherstats_pkts65to127octets 0x00069c24 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c25 - - - b[31:0] b[31:0]
+ - - - - tx_stats_etherstats_pkts128to255octets 0x00069c26 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c27 - - - b[31:0] b[31:0]
+ - - - - tx_stats_etherstats_pkts256to511octets 0x00069c28 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c29 - - - b[31:0] b[31:0]
+ - - - - tx_stats_etherstats_pkts512to1023octets 0x00069c2a 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c2b - - - b[31:0] b[31:0]
+ - - - - tx_stats_etherstat_pkts1024to1518octets 0x00069c2c 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c2d - - - b[31:0] b[31:0]
+ - - - - tx_stats_etherstats_pkts1519toxoctets 0x00069c2e 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c2f - - - b[31:0] b[31:0]
+ - - - - tx_stats_etherstats_fragments 0x00069c30 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c31 - - - b[31:0] b[31:0]
+ - - - - tx_stats_etherstats_jabbers 0x00069c32 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c33 - - - b[31:0] b[31:0]
+ - - - - tx_stats_etherstatscrcerr 0x00069c34 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c35 - - - b[31:0] b[31:0]
+ - - - - tx_stats_unicastmacctrlframes 0x00069c36 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c37 - - - b[31:0] b[31:0]
+ - - - - tx_stats_multicastmac_ctrlframes 0x00069c38 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c39 - - - b[31:0] b[31:0]
+ - - - - tx_stats_broadcastmac_ctrlframes 0x00069c3a 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c3b - - - b[31:0] b[31:0]
+ - - - - tx_stats_pfcmacctrlframes 0x00069c3c 1 RO uint64 b[3:0] b[35:32]
+ - - - - - 0x00069c3d - - - b[31:0] b[31:0]
+ REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x0006a000 1 RO uint32 b[0:0] -
+ - - - - xgmii_tx_ready 0x0006a000 1 RO uint32 b[1:1] -
+ - - - - xgmii_link_status 0x0006a000 1 RO uint32 b[3:2] -
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/lofar2_unb2b_filterbank.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_filterbank/lofar2_unb2b_filterbank.fpga.yaml
index 8913b3d218334598cac6e04fa4428ffba9c867ed..b9b96a2c4acb2059c6cce74b2e31e4453fbb1031 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/lofar2_unb2b_filterbank.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/lofar2_unb2b_filterbank.fpga.yaml
@@ -11,10 +11,10 @@ peripherals:
# Factory / minimal (see ctrl_unb2b_board.vhd)
#############################################################################
- peripheral_name: unb2b_board/system_info
+ lock_base_address: 0x10000
mm_port_names:
- ROM_SYSTEM_INFO
- PIO_SYSTEM_INFO
- lock_base_address: 0x10000
- peripheral_name: unb2b_board/wdi
mm_port_names:
@@ -79,7 +79,7 @@ peripherals:
- peripheral_name: dp/dp_bsn_source
parameter_overrides:
- - { name: g_nof_block_per_sync, value: 195313 } # 390625 = 2 * 195312, to have integer number of blocks in 2 s sync interval
+ - { name: g_nof_block_per_sync, value: 390625 } # EK: TODO temporarily use 390625 = 2 * 195312.5, to have integer number of blocks in 2 s sync interval, TODO: remove when REG_BSN_SOURCE_V2 is used
mm_port_names:
- REG_BSN_SOURCE
@@ -145,13 +145,15 @@ peripherals:
- peripheral_name: filter/fil_ppf_w
parameter_overrides:
- - { name: g_wb_factor, value: 1 }
- - { name: g_nof_taps, value: 16 } # = N_taps
- - { name: g_nof_bands, value: 1024 } # = N_fft
- - { name: g_coef_dat_w, value: 16 } # = W_fir_coef
+ - { name: g_fil_ppf.wb_factor, value: 1 } # process at sample rate
+ - { name: g_fil_ppf.nof_chan, value: 0 } # process at sample rate
+ - { name: g_fil_ppf.nof_bands, value: 1024 } # = N_fft
+ - { name: g_fil_ppf.nof_taps, value: 16 } # = N_taps
+ - { name: g_fil_ppf.nof_streams, value: 1 }
+ - { name: g_fil_ppf.coef_dat_w, value: 16 } # = W_fir_coef
mm_port_names:
- RAM_FIL_COEFS
-
+
- peripheral_name: sdp/sdp_subband_equalizer
mm_port_names:
- RAM_EQUALIZER_GAINS
diff --git a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
index dc9b8b805a4c6f04e9da0b69b7b019340f280c6d..166db254179b429d95f53754422cea9b4f937c21 100644
--- a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
+++ b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
@@ -11,26 +11,26 @@ peripherals:
mm_ports:
# MM port for sdp_info.vhd
- mm_port_name: REG_SDP_INFO
+ mm_port_type: REG
mm_port_description: |
"The SDP info contains central SDP information. The station_id applies to the entire station.
The other info fields apply per antenna band (low band or high band). An FPGA node only
participates in one band."
- mm_port_type: REG
fields:
- - - { field_name: station_id, width: 16, access_mode: RW, address_offset: 0x0 }
- - - { field_name: antenna_band_index, width: 1, access_mode: RO, address_offset: 0x4 }
- - - { field_name: observation_id, width: 32, access_mode: RW, address_offset: 0x8 }
- - - { field_name: nyquist_zone_index, width: 2, access_mode: RW, address_offset: 0xC }
- - - { field_name: f_adc, width: 1, access_mode: RO, address_offset: 0x10 }
- - - { field_name: fsub_type, width: 1, access_mode: RO, address_offset: 0x14 }
- - - { field_name: beam_repositioning_flag, width: 1, access_mode: RW, address_offset: 0x18 }
- - - { field_name: subband_calibrated_flag, width: 1, access_mode: RW, address_offset: 0x1C }
- - - { field_name: O_si, width: 8, access_mode: RW, address_offset: 0x20 }
- - - { field_name: N_si, width: 8, access_mode: RW, address_offset: 0x24 }
- - - { field_name: O_rn, width: 8, access_mode: RW, address_offset: 0x28 }
- - - { field_name: N_rn, width: 8, access_mode: RW, address_offset: 0x2C }
- - - { field_name: block_period, width: 16, access_mode: RO, address_offset: 0x30 }
- - - { field_name: beamlet_scale, width: 16, access_mode: RW, address_offset: 0x34 }
+ - - { field_name: station_id, mm_width: 16, access_mode: RW, address_offset: 0x0 }
+ - - { field_name: antenna_band_index, mm_width: 1, access_mode: RO, address_offset: 0x4 }
+ - - { field_name: observation_id, mm_width: 32, access_mode: RW, address_offset: 0x8 }
+ - - { field_name: nyquist_zone_index, mm_width: 2, access_mode: RW, address_offset: 0xC }
+ - - { field_name: f_adc, mm_width: 1, access_mode: RO, address_offset: 0x10 }
+ - - { field_name: fsub_type, mm_width: 1, access_mode: RO, address_offset: 0x14 }
+ - - { field_name: beam_repositioning_flag, mm_width: 1, access_mode: RW, address_offset: 0x18 }
+ - - { field_name: subband_calibrated_flag, mm_width: 1, access_mode: RW, address_offset: 0x1C }
+ - - { field_name: O_si, mm_width: 8, access_mode: RW, address_offset: 0x20 }
+ - - { field_name: N_si, mm_width: 8, access_mode: RW, address_offset: 0x24 }
+ - - { field_name: O_rn, mm_width: 8, access_mode: RW, address_offset: 0x28 }
+ - - { field_name: N_rn, mm_width: 8, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: block_period, mm_width: 16, access_mode: RO, address_offset: 0x30 }
+ - - { field_name: beamlet_scale, mm_width: 16, access_mode: RW, address_offset: 0x34 }
- peripheral_name: sdp_subband_equalizer # pi_sdp_subband_equalizer.py
@@ -41,6 +41,7 @@ peripherals:
mm_ports:
# MM port for sdp_subband_equalizer.vhd
- mm_port_name: RAM_EQUALIZER_GAINS
+ mm_port_type: RAM
mm_port_description: |
"The subband weigths are stored in g_nof_instances = P_pfb = S_pn / Q_fft = 6 blocks of
Q_fft * N_sub = 2 * 512 = 1024 complex coefficients as:
@@ -48,17 +49,16 @@ peripherals:
(cint16)subband_weights[S_pn/Q_fft]_[Q_fft][N_sub]
where S_pn = 12, Q_fft = 2 and N_sub = 512 are defined in sdp_pkg.vhd."
- mm_port_type: RAM
number_of_mm_ports: g_nof_instances
fields:
- - field_name: coef
field_description: |
"Complex coefficient to calibrate the gain and phase per subband. Packed as imaginary in high part,
- real in low part of width = N_complex * W_sub_weight = 2 * 16 = 32 bit."
- width: 32 # = N_complex * W_sub_weight
- address_offset: 0x0
+ real in low part of mm_width = N_complex * W_sub_weight = 2 * 16 = 32 bit."
number_of_fields: 1024 # = Q_fft * N_sub = 2 signal inputs * 512 subbands
- radix: complx
+ address_offset: 0x0
+ mm_width: 32 # = N_complex * W_sub_weight
+ radix: cint16_ir
- peripheral_name: sdp_bf_weights # pi_sdp_bf_weights.py
@@ -70,6 +70,7 @@ peripherals:
mm_ports:
# MM port for sdp_beamformer_local.vhd / sdp_bf_weights.vhd / mms_dp_gain_serial_arr.vhd
- mm_port_name: RAM_BF_WEIGHTS
+ mm_port_type: RAM
mm_port_description: |
"The beamlet weigths are stored in g_nof_instances = N_pol_bf * P_pfb = 2 * 6 = 12, where
P_pfb = S_pn / Q_fft = 6. Per instance there is a block of Q_fft * S_sub_bf =
@@ -96,17 +97,16 @@ peripherals:
when index of N_pol_bf and index of N_pol are the same. The cross-polarization BF
weights (XY, YX) are set when index of N_pol_bf and index of N_pol are different. If
no cross-polarization weighting is needed, then these weights can be kept 0."
- mm_port_type: RAM
number_of_mm_ports: g_nof_instances
fields:
- - field_name: coef
field_description: |
"Complex weight per subband. Packed as imaginary in high part, real in low part
- of width = N_complex * W_bf_weight = 2 * 16 = 32 bit."
- width: 32 # = N_complex * W_bf_weight
- address_offset: 0x0
+ of mm_width = N_complex * W_bf_weight = 2 * 16 = 32 bit."
number_of_fields: g_nof_gains
- radix: complx
+ address_offset: 0x0
+ mm_width: 32 # = N_complex * W_bf_weight
+ radix: cint16_ir
- peripheral_name: sdp_bf_scale # pi_sdp_bf_scale.py
@@ -118,6 +118,7 @@ peripherals:
mm_ports:
# MM port for node_sdp_beamformer.vhd / mms_dp_scale.vhd / mms_dp_gain.vhd / mms_dp_gain_arr.vhd
- mm_port_name: REG_BF_SCALE
+ mm_port_type: REG
mm_port_description: |
"The beamlet scale function scales the beamlet sum with a real scale factor and then
requantizes the result to beamlet data output with less bits.
@@ -129,16 +130,15 @@ peripherals:
. 2**11 rounds the lowest 4 bits, selects the next 8 bits of the beamlet sum and clips
the highest 6 bits,
. 2**5 rounds the lowest 10 bits and selects the highest 8 bits of the beamlet sum."
- mm_port_type: REG
fields:
- - field_name: scale
field_description: ""
- width: g_gain_w
- address_offset: 0x0
number_of_fields: 1
- radix: unsigned
- #radix_width: g_gain_w
- radix_resolution: 0 - g_lsb_w
+ address_offset: 0x0
+ mm_width: g_gain_w
+ #user_width: g_gain_w # EK TODO check parameter passing to user_width
+ radix: uint32 # scale factor is unsigned value
+ resolution_w: 0 - g_lsb_w
- - field_name: unused
field_description: "Not used."
address_offset: 0x4
@@ -149,6 +149,7 @@ peripherals:
mm_ports:
# MM port for sdp_beamformer_output.vhd / dp_offload_tx_v3.vhd
- mm_port_name: REG_DP_OFFLOAD_TX_HDR_DAT
+ mm_port_type: REG
mm_port_description: |
"The ETH/IP/UDP/application header fields for the beamlet data output offload UDP packets.
@@ -161,64 +162,63 @@ peripherals:
range (h downto 0) where the first header field (eth_destination_mac) is at index h.
. the RO fields are filled in by the logic, when the packet header is transmitted, however
the read value does not still represents the MM write value, not the transmitted value.
- . dp_bsn with radix_width = 64 is stored as:
+ . dp_bsn with user_width = 64 is stored as:
word byte
addr addr bits
0 0x0 [31:0] = dp_bsn[31:0]
1 0x4 [31:0] = dp_bsn[63:32]
- . eth_dst_mac with radix_width = 48 is stored as:
+ . eth_dst_mac with user_width = 48 is stored as:
word byte
addr addr bits
21 0x84 [31:0] = eth_dst_mac[31:0]
22 0x88 [15:0] = eth_dst_mac[47:32]
"
- mm_port_type: REG
fields:
# eth field group
- - - { field_name: eth_destination_mac, width: 32, access_mode: RW, address_offset: 0x84, radix_width: 48 }
- - - { field_name: eth_source_mac, width: 32, access_mode: RO, address_offset: 0x7C, radix_width: 48 }
- - - { field_name: eth_type, width: 16, access_mode: RO, address_offset: 0x78 }
+ - - { field_name: eth_destination_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RW, address_offset: 0x84 }
+ - - { field_name: eth_source_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RO, address_offset: 0x7C }
+ - - { field_name: eth_type, mm_width: 16, access_mode: RO, address_offset: 0x78 }
# ip field group
- - - { field_name: ip_version, width: 4, access_mode: RW, address_offset: 0x74 }
- - - { field_name: ip_header_length, width: 4, access_mode: RW, address_offset: 0x70 }
- - - { field_name: ip_services, width: 8, access_mode: RW, address_offset: 0x6C }
- - - { field_name: ip_total_length, width: 16, access_mode: RW, address_offset: 0x68 }
- - - { field_name: ip_identification, width: 16, access_mode: RW, address_offset: 0x64 }
- - - { field_name: ip_flags, width: 3, access_mode: RW, address_offset: 0x60 }
- - - { field_name: ip_fragment_offset, width: 13, access_mode: RW, address_offset: 0x5C }
- - - { field_name: ip_time_to_live, width: 8, access_mode: RW, address_offset: 0x58 }
- - - { field_name: ip_protocol, width: 8, access_mode: RW, address_offset: 0x54 }
- - - { field_name: ip_header_checksum, width: 16, access_mode: RW, address_offset: 0x50 }
- - - { field_name: ip_source_address, width: 32, access_mode: RW, address_offset: 0x4C }
- - - { field_name: ip_destination_address, width: 32, access_mode: RW, address_offset: 0x48 }
+ - - { field_name: ip_version, mm_width: 4, access_mode: RW, address_offset: 0x74 }
+ - - { field_name: ip_header_length, mm_width: 4, access_mode: RW, address_offset: 0x70 }
+ - - { field_name: ip_services, mm_width: 8, access_mode: RW, address_offset: 0x6C }
+ - - { field_name: ip_total_length, mm_width: 16, access_mode: RW, address_offset: 0x68 }
+ - - { field_name: ip_identification, mm_width: 16, access_mode: RW, address_offset: 0x64 }
+ - - { field_name: ip_flags, mm_width: 3, access_mode: RW, address_offset: 0x60 }
+ - - { field_name: ip_fragment_offset, mm_width: 13, access_mode: RW, address_offset: 0x5C }
+ - - { field_name: ip_time_to_live, mm_width: 8, access_mode: RW, address_offset: 0x58 }
+ - - { field_name: ip_protocol, mm_width: 8, access_mode: RW, address_offset: 0x54 }
+ - - { field_name: ip_header_checksum, mm_width: 16, access_mode: RW, address_offset: 0x50 }
+ - - { field_name: ip_source_address, mm_width: 32, access_mode: RW, address_offset: 0x4C }
+ - - { field_name: ip_destination_address, mm_width: 32, access_mode: RW, address_offset: 0x48 }
# udp field group
- - - { field_name: udp_source_port, width: 16, access_mode: RW, address_offset: 0x44 }
- - - { field_name: udp_destination_port, width: 16, access_mode: RW, address_offset: 0x40 }
- - - { field_name: udp_length, width: 16, access_mode: RW, address_offset: 0x3C }
- - - { field_name: udp_checksum, width: 16, access_mode: RW, address_offset: 0x38 }
+ - - { field_name: udp_source_port, mm_width: 16, access_mode: RW, address_offset: 0x44 }
+ - - { field_name: udp_destination_port, mm_width: 16, access_mode: RW, address_offset: 0x40 }
+ - - { field_name: udp_length, mm_width: 16, access_mode: RW, address_offset: 0x3C }
+ - - { field_name: udp_checksum, mm_width: 16, access_mode: RW, address_offset: 0x38 }
# application field group
- - - { field_name: marker, width: 8, access_mode: RO, address_offset: 0x34 }
- - - { field_name: version_id, width: 8, access_mode: RO, address_offset: 0x30 }
- - - { field_name: observation_id, width: 32, access_mode: RW, address_offset: 0x2C }
- - - { field_name: station_id, width: 16, access_mode: RW, address_offset: 0x28 }
- - - { field_name: source_info, width: 16, access_mode: RW, address_offset: 0x24 }
+ - - { field_name: marker, mm_width: 8, access_mode: RO, address_offset: 0x34 }
+ - - { field_name: version_id, mm_width: 8, access_mode: RO, address_offset: 0x30 }
+ - - { field_name: observation_id, mm_width: 32, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: station_id, mm_width: 16, access_mode: RW, address_offset: 0x28 }
+ - - { field_name: source_info, mm_width: 16, access_mode: RW, address_offset: 0x24 }
- "source_info":
- - { field_name: antenna_band_index, width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
- - { field_name: nyquist_zone_index, width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
- - { field_name: f_adc, width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
- - { field_name: fsub_type, width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
- - { field_name: payload_error, width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
- - { field_name: repositioning_flag, width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
- - { field_name: beamlet_width, width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
- - { field_name: gn_index, width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
-
- - - { field_name: reserved, width: 32, access_mode: RW, address_offset: 0x1C, radix_width: 40 }
- - - { field_name: beamlet_scale, width: 16, access_mode: RW, address_offset: 0x18 }
- - - { field_name: beamlet_index, width: 16, access_mode: RW, address_offset: 0x14 }
- - - { field_name: nof_blocks_per_packet, width: 8, access_mode: RW, address_offset: 0x10 }
- - - { field_name: nof_beamlets_per_block, width: 16, access_mode: RW, address_offset: 0xC }
- - - { field_name: block_period, width: 16, access_mode: RW, address_offset: 0x8 }
- - - { field_name: BSN, width: 32, access_mode: RW, address_offset: 0x0, radix_width: 64 }
+ - { field_name: antenna_band_index, mm_width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
+ - { field_name: nyquist_zone_index, mm_width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
+ - { field_name: f_adc, mm_width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
+ - { field_name: fsub_type, mm_width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
+ - { field_name: payload_error, mm_width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
+ - { field_name: repositioning_flag, mm_width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
+ - { field_name: beamlet_width, mm_width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
+ - { field_name: gn_index, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
+
+ - - { field_name: reserved, mm_width: 32, user_width: 40, radix: uint64, access_mode: RW, address_offset: 0x1C }
+ - - { field_name: beamlet_scale, mm_width: 16, access_mode: RW, address_offset: 0x18 }
+ - - { field_name: beamlet_index, mm_width: 16, access_mode: RW, address_offset: 0x14 }
+ - - { field_name: nof_blocks_per_packet, mm_width: 8, access_mode: RW, address_offset: 0x10 }
+ - - { field_name: nof_beamlets_per_block, mm_width: 16, access_mode: RW, address_offset: 0xC }
+ - - { field_name: block_period, mm_width: 16, access_mode: RW, address_offset: 0x8 }
+ - - { field_name: BSN, mm_width: 32, user_width: 64, radix: uint64, access_mode: RW, address_offset: 0x0 }
- peripheral_name: sdp_statistics_offload_hdr_dat_sst # pi_dp_offload_tx_hdr_dat_lofar2_sdp_statistics_offload.py
@@ -226,6 +226,7 @@ peripherals:
mm_ports:
# MM port for sdp_statistics_offload.vhd / dp_offload_tx_v3.vhd
- mm_port_name: REG_DP_OFFLOAD_TX_HDR_DAT
+ mm_port_type: REG
mm_port_description: |
"The ETH/IP/UDP/application header fields for the SST offload UDP packets.
@@ -236,59 +237,59 @@ peripherals:
[1] https://plm.astron.nl/polarion/#/project/LOFAR2System/wiki/L2%20Interface%20Control%20Documents/SC%20to%20SDP%20ICD
"
- mm_port_type: REG
fields:
# eth field group
- - - { field_name: eth_destination_mac, width: 32, access_mode: RW, address_offset: 0x84, radix_width: 48 }
- - - { field_name: eth_source_mac, width: 32, access_mode: RO, address_offset: 0x7C, radix_width: 48 }
- - - { field_name: eth_type, width: 16, access_mode: RO, address_offset: 0x78 }
+ - - { field_name: word_align, mm_width: 16, access_mode: RW, address_offset: 0x8C }
+ - - { field_name: eth_destination_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RW, address_offset: 0x84 }
+ - - { field_name: eth_source_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RO, address_offset: 0x7C }
+ - - { field_name: eth_type, mm_width: 16, access_mode: RO, address_offset: 0x78 }
# ip field group
- - - { field_name: ip_version, width: 4, access_mode: RW, address_offset: 0x74 }
- - - { field_name: ip_header_length, width: 4, access_mode: RW, address_offset: 0x70 }
- - - { field_name: ip_services, width: 8, access_mode: RW, address_offset: 0x6C }
- - - { field_name: ip_total_length, width: 16, access_mode: RW, address_offset: 0x68 }
- - - { field_name: ip_identification, width: 16, access_mode: RW, address_offset: 0x64 }
- - - { field_name: ip_flags, width: 3, access_mode: RW, address_offset: 0x60 }
- - - { field_name: ip_fragment_offset, width: 13, access_mode: RW, address_offset: 0x5C }
- - - { field_name: ip_time_to_live, width: 8, access_mode: RW, address_offset: 0x58 }
- - - { field_name: ip_protocol, width: 8, access_mode: RW, address_offset: 0x54 }
- - - { field_name: ip_header_checksum, width: 16, access_mode: RW, address_offset: 0x50 }
- - - { field_name: ip_source_address, width: 32, access_mode: RW, address_offset: 0x4C }
- - - { field_name: ip_destination_address, width: 32, access_mode: RW, address_offset: 0x48 }
+ - - { field_name: ip_version, mm_width: 4, access_mode: RW, address_offset: 0x74 }
+ - - { field_name: ip_header_length, mm_width: 4, access_mode: RW, address_offset: 0x70 }
+ - - { field_name: ip_services, mm_width: 8, access_mode: RW, address_offset: 0x6C }
+ - - { field_name: ip_total_length, mm_width: 16, access_mode: RW, address_offset: 0x68 }
+ - - { field_name: ip_identification, mm_width: 16, access_mode: RW, address_offset: 0x64 }
+ - - { field_name: ip_flags, mm_width: 3, access_mode: RW, address_offset: 0x60 }
+ - - { field_name: ip_fragment_offset, mm_width: 13, access_mode: RW, address_offset: 0x5C }
+ - - { field_name: ip_time_to_live, mm_width: 8, access_mode: RW, address_offset: 0x58 }
+ - - { field_name: ip_protocol, mm_width: 8, access_mode: RW, address_offset: 0x54 }
+ - - { field_name: ip_header_checksum, mm_width: 16, access_mode: RW, address_offset: 0x50 }
+ - - { field_name: ip_source_address, mm_width: 32, access_mode: RW, address_offset: 0x4C }
+ - - { field_name: ip_destination_address, mm_width: 32, access_mode: RW, address_offset: 0x48 }
# udp field group
- - - { field_name: udp_source_port, width: 16, access_mode: RW, address_offset: 0x44 }
- - - { field_name: udp_destination_port, width: 16, access_mode: RW, address_offset: 0x40 }
- - - { field_name: udp_length, width: 16, access_mode: RW, address_offset: 0x3C }
- - - { field_name: udp_checksum, width: 16, access_mode: RW, address_offset: 0x38 }
+ - - { field_name: udp_source_port, mm_width: 16, access_mode: RW, address_offset: 0x44 }
+ - - { field_name: udp_destination_port, mm_width: 16, access_mode: RW, address_offset: 0x40 }
+ - - { field_name: udp_length, mm_width: 16, access_mode: RW, address_offset: 0x3C }
+ - - { field_name: udp_checksum, mm_width: 16, access_mode: RW, address_offset: 0x38 }
# application field group
- - - { field_name: marker, width: 8, access_mode: RO, address_offset: 0x34 }
- - - { field_name: version_id, width: 8, access_mode: RO, address_offset: 0x30 }
- - - { field_name: observation_id, width: 32, access_mode: RW, address_offset: 0x2C }
- - - { field_name: station_id, width: 16, access_mode: RW, address_offset: 0x28 }
- - - { field_name: source_info, width: 16, access_mode: RW, address_offset: 0x24 }
+ - - { field_name: marker, mm_width: 8, access_mode: RO, address_offset: 0x34 }
+ - - { field_name: version_id, mm_width: 8, access_mode: RO, address_offset: 0x30 }
+ - - { field_name: observation_id, mm_width: 32, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: station_id, mm_width: 16, access_mode: RW, address_offset: 0x28 }
+ - - { field_name: source_info, mm_width: 16, access_mode: RW, address_offset: 0x24 }
- "source_info":
- - { field_name: antenna_band_index, width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
- - { field_name: nyquist_zone_index, width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
- - { field_name: f_adc, width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
- - { field_name: fsub_type, width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
- - { field_name: payload_error, width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
- - { field_name: beam_repositioning_flag, width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
- - { field_name: subband_calibrated_flag, width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x24 }
- - { field_name: reserved, width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
- - { field_name: gn_index, width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
-
- - - { field_name: reserved, width: 8, access_mode: RW, address_offset: 0x20 }
- - - { field_name: integration_interval, width: 24, access_mode: RW, address_offset: 0x1C }
- - - { field_name: data_id, width: 32, access_mode: RW, address_offset: 0x18 }
+ - { field_name: antenna_band_index, mm_width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
+ - { field_name: nyquist_zone_index, mm_width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
+ - { field_name: f_adc, mm_width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
+ - { field_name: fsub_type, mm_width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
+ - { field_name: payload_error, mm_width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
+ - { field_name: beam_repositioning_flag, mm_width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
+ - { field_name: subband_calibrated_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x24 }
+ - { field_name: reserved, mm_width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
+ - { field_name: gn_index, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
+
+ - - { field_name: reserved, mm_width: 8, access_mode: RW, address_offset: 0x20 }
+ - - { field_name: integration_interval, mm_width: 24, access_mode: RW, address_offset: 0x1C }
+ - - { field_name: data_id, mm_width: 32, access_mode: RW, address_offset: 0x18 }
- "data_id_sst":
- - { field_name: reserved, width: 24, bit_offset: 8, access_mode: RW, address_offset: 0x18 }
- - { field_name: signal_input_index, width: 8, bit_offset: 0, access_mode: RW, address_offset: 0x18 }
+ - { field_name: reserved, mm_width: 24, bit_offset: 8, access_mode: RW, address_offset: 0x18 }
+ - { field_name: signal_input_index, mm_width: 8, bit_offset: 0, access_mode: RW, address_offset: 0x18 }
- - - { field_name: nof_signal_inputs, width: 8, access_mode: RW, address_offset: 0x14 }
- - - { field_name: nof_bytes_per_statistic, width: 8, access_mode: RW, address_offset: 0x10 }
- - - { field_name: nof_statistics_per_packet, width: 16, access_mode: RW, address_offset: 0xC }
- - - { field_name: block_period, width: 16, access_mode: RW, address_offset: 0x8 }
- - - { field_name: BSN, width: 32, access_mode: RW, address_offset: 0x0, radix_width: 64 }
+ - - { field_name: nof_signal_inputs, mm_width: 8, access_mode: RW, address_offset: 0x14 }
+ - - { field_name: nof_bytes_per_statistic, mm_width: 8, access_mode: RW, address_offset: 0x10 }
+ - - { field_name: nof_statistics_per_packet, mm_width: 16, access_mode: RW, address_offset: 0xC }
+ - - { field_name: block_period, mm_width: 16, access_mode: RW, address_offset: 0x8 }
+ - - { field_name: BSN, mm_width: 32, user_width: 64, radix: uint64, access_mode: RW, address_offset: 0x0 }
- peripheral_name: sdp_statistics_offload_hdr_dat_bst # pi_dp_offload_tx_hdr_dat_lofar2_sdp_statistics_offload.py
@@ -296,6 +297,7 @@ peripherals:
mm_ports:
# MM port for sdp_statistics_offload.vhd / dp_offload_tx_v3.vhd
- mm_port_name: REG_DP_OFFLOAD_TX_HDR_DAT
+ mm_port_type: REG
mm_port_description: |
"The ETH/IP/UDP/application header fields for the BST offload UDP packets.
@@ -306,59 +308,59 @@ peripherals:
[1] https://plm.astron.nl/polarion/#/project/LOFAR2System/wiki/L2%20Interface%20Control%20Documents/SC%20to%20SDP%20ICD
"
- mm_port_type: REG
fields:
# eth field group
- - - { field_name: eth_destination_mac, width: 32, access_mode: RW, address_offset: 0x84, radix_width: 48 }
- - - { field_name: eth_source_mac, width: 32, access_mode: RO, address_offset: 0x7C, radix_width: 48 }
- - - { field_name: eth_type, width: 16, access_mode: RO, address_offset: 0x78 }
+ - - { field_name: word_align, mm_width: 16, access_mode: RW, address_offset: 0x8C }
+ - - { field_name: eth_destination_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RW, address_offset: 0x84 }
+ - - { field_name: eth_source_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RO, address_offset: 0x7C }
+ - - { field_name: eth_type, mm_width: 16, access_mode: RO, address_offset: 0x78 }
# ip field group
- - - { field_name: ip_version, width: 4, access_mode: RW, address_offset: 0x74 }
- - - { field_name: ip_header_length, width: 4, access_mode: RW, address_offset: 0x70 }
- - - { field_name: ip_services, width: 8, access_mode: RW, address_offset: 0x6C }
- - - { field_name: ip_total_length, width: 16, access_mode: RW, address_offset: 0x68 }
- - - { field_name: ip_identification, width: 16, access_mode: RW, address_offset: 0x64 }
- - - { field_name: ip_flags, width: 3, access_mode: RW, address_offset: 0x60 }
- - - { field_name: ip_fragment_offset, width: 13, access_mode: RW, address_offset: 0x5C }
- - - { field_name: ip_time_to_live, width: 8, access_mode: RW, address_offset: 0x58 }
- - - { field_name: ip_protocol, width: 8, access_mode: RW, address_offset: 0x54 }
- - - { field_name: ip_header_checksum, width: 16, access_mode: RW, address_offset: 0x50 }
- - - { field_name: ip_source_address, width: 32, access_mode: RW, address_offset: 0x4C }
- - - { field_name: ip_destination_address, width: 32, access_mode: RW, address_offset: 0x48 }
+ - - { field_name: ip_version, mm_width: 4, access_mode: RW, address_offset: 0x74 }
+ - - { field_name: ip_header_length, mm_width: 4, access_mode: RW, address_offset: 0x70 }
+ - - { field_name: ip_services, mm_width: 8, access_mode: RW, address_offset: 0x6C }
+ - - { field_name: ip_total_length, mm_width: 16, access_mode: RW, address_offset: 0x68 }
+ - - { field_name: ip_identification, mm_width: 16, access_mode: RW, address_offset: 0x64 }
+ - - { field_name: ip_flags, mm_width: 3, access_mode: RW, address_offset: 0x60 }
+ - - { field_name: ip_fragment_offset, mm_width: 13, access_mode: RW, address_offset: 0x5C }
+ - - { field_name: ip_time_to_live, mm_width: 8, access_mode: RW, address_offset: 0x58 }
+ - - { field_name: ip_protocol, mm_width: 8, access_mode: RW, address_offset: 0x54 }
+ - - { field_name: ip_header_checksum, mm_width: 16, access_mode: RW, address_offset: 0x50 }
+ - - { field_name: ip_source_address, mm_width: 32, access_mode: RW, address_offset: 0x4C }
+ - - { field_name: ip_destination_address, mm_width: 32, access_mode: RW, address_offset: 0x48 }
# udp field group
- - - { field_name: udp_source_port, width: 16, access_mode: RW, address_offset: 0x44 }
- - - { field_name: udp_destination_port, width: 16, access_mode: RW, address_offset: 0x40 }
- - - { field_name: udp_length, width: 16, access_mode: RW, address_offset: 0x3C }
- - - { field_name: udp_checksum, width: 16, access_mode: RW, address_offset: 0x38 }
+ - - { field_name: udp_source_port, mm_width: 16, access_mode: RW, address_offset: 0x44 }
+ - - { field_name: udp_destination_port, mm_width: 16, access_mode: RW, address_offset: 0x40 }
+ - - { field_name: udp_length, mm_width: 16, access_mode: RW, address_offset: 0x3C }
+ - - { field_name: udp_checksum, mm_width: 16, access_mode: RW, address_offset: 0x38 }
# application field group
- - - { field_name: marker, width: 8, access_mode: RO, address_offset: 0x34 }
- - - { field_name: version_id, width: 8, access_mode: RO, address_offset: 0x30 }
- - - { field_name: observation_id, width: 32, access_mode: RW, address_offset: 0x2C }
- - - { field_name: station_id, width: 16, access_mode: RW, address_offset: 0x28 }
- - - { field_name: source_info, width: 16, access_mode: RW, address_offset: 0x24 }
+ - - { field_name: marker, mm_width: 8, access_mode: RO, address_offset: 0x34 }
+ - - { field_name: version_id, mm_width: 8, access_mode: RO, address_offset: 0x30 }
+ - - { field_name: observation_id, mm_width: 32, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: station_id, mm_width: 16, access_mode: RW, address_offset: 0x28 }
+ - - { field_name: source_info, mm_width: 16, access_mode: RW, address_offset: 0x24 }
- "source_info":
- - { field_name: antenna_band_index, width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
- - { field_name: nyquist_zone_index, width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
- - { field_name: f_adc, width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
- - { field_name: fsub_type, width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
- - { field_name: payload_error, width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
- - { field_name: beam_repositioning_flag, width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
- - { field_name: subband_calibrated_flag, width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x24 }
- - { field_name: reserved, width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
- - { field_name: gn_index, width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
-
- - - { field_name: reserved, width: 8, access_mode: RW, address_offset: 0x20 }
- - - { field_name: integration_interval, width: 24, access_mode: RW, address_offset: 0x1C }
- - - { field_name: data_id, width: 32, access_mode: RW, address_offset: 0x18 }
+ - { field_name: antenna_band_index, mm_width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
+ - { field_name: nyquist_zone_index, mm_width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
+ - { field_name: f_adc, mm_width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
+ - { field_name: fsub_type, mm_width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
+ - { field_name: payload_error, mm_width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
+ - { field_name: beam_repositioning_flag, mm_width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
+ - { field_name: subband_calibrated_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x24 }
+ - { field_name: reserved, mm_width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
+ - { field_name: gn_index, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
+
+ - - { field_name: reserved, mm_width: 8, access_mode: RW, address_offset: 0x20 }
+ - - { field_name: integration_interval, mm_width: 24, access_mode: RW, address_offset: 0x1C }
+ - - { field_name: data_id, mm_width: 32, access_mode: RW, address_offset: 0x18 }
- "data_id_bst":
- - { field_name: reserved, width: 16, bit_offset: 16, access_mode: RW, address_offset: 0x18 }
- - { field_name: beamlet_index, width: 16, bit_offset: 0, access_mode: RW, address_offset: 0x18 }
+ - { field_name: reserved, mm_width: 16, bit_offset: 16, access_mode: RW, address_offset: 0x18 }
+ - { field_name: beamlet_index, mm_width: 16, bit_offset: 0, access_mode: RW, address_offset: 0x18 }
- - - { field_name: nof_signal_inputs, width: 8, access_mode: RW, address_offset: 0x14 }
- - - { field_name: nof_bytes_per_statistic, width: 8, access_mode: RW, address_offset: 0x10 }
- - - { field_name: nof_statistics_per_packet, width: 16, access_mode: RW, address_offset: 0xC }
- - - { field_name: block_period, width: 16, access_mode: RW, address_offset: 0x8 }
- - - { field_name: BSN, width: 32, access_mode: RW, address_offset: 0x0, radix_width: 64 }
+ - - { field_name: nof_signal_inputs, mm_width: 8, access_mode: RW, address_offset: 0x14 }
+ - - { field_name: nof_bytes_per_statistic, mm_width: 8, access_mode: RW, address_offset: 0x10 }
+ - - { field_name: nof_statistics_per_packet, mm_width: 16, access_mode: RW, address_offset: 0xC }
+ - - { field_name: block_period, mm_width: 16, access_mode: RW, address_offset: 0x8 }
+ - - { field_name: BSN, mm_width: 32, user_width: 64, radix: uint64, access_mode: RW, address_offset: 0x0 }
- peripheral_name: sdp_statistics_offload_hdr_dat_xst # pi_dp_offload_tx_hdr_dat_lofar2_sdp_statistics_offload.py
@@ -366,6 +368,7 @@ peripherals:
mm_ports:
# MM port for sdp_statistics_offload.vhd / dp_offload_tx_v3.vhd
- mm_port_name: REG_DP_OFFLOAD_TX_HDR_DAT
+ mm_port_type: REG
mm_port_description: |
"The ETH/IP/UDP/application header fields for the XST offload UDP packets.
@@ -377,59 +380,59 @@ peripherals:
[1] https://plm.astron.nl/polarion/#/project/LOFAR2System/wiki/L2%20Interface%20Control%20Documents/SC%20to%20SDP%20ICD
"
- mm_port_type: REG
fields:
# eth field group
- - - { field_name: eth_destination_mac, width: 32, access_mode: RW, address_offset: 0x84, radix_width: 48 }
- - - { field_name: eth_source_mac, width: 32, access_mode: RO, address_offset: 0x7C, radix_width: 48 }
- - - { field_name: eth_type, width: 16, access_mode: RO, address_offset: 0x78 }
+ - - { field_name: word_align, mm_width: 16, access_mode: RW, address_offset: 0x8C }
+ - - { field_name: eth_destination_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RW, address_offset: 0x84 }
+ - - { field_name: eth_source_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RO, address_offset: 0x7C }
+ - - { field_name: eth_type, mm_width: 16, access_mode: RO, address_offset: 0x78 }
# ip field group
- - - { field_name: ip_version, width: 4, access_mode: RW, address_offset: 0x74 }
- - - { field_name: ip_header_length, width: 4, access_mode: RW, address_offset: 0x70 }
- - - { field_name: ip_services, width: 8, access_mode: RW, address_offset: 0x6C }
- - - { field_name: ip_total_length, width: 16, access_mode: RW, address_offset: 0x68 }
- - - { field_name: ip_identification, width: 16, access_mode: RW, address_offset: 0x64 }
- - - { field_name: ip_flags, width: 3, access_mode: RW, address_offset: 0x60 }
- - - { field_name: ip_fragment_offset, width: 13, access_mode: RW, address_offset: 0x5C }
- - - { field_name: ip_time_to_live, width: 8, access_mode: RW, address_offset: 0x58 }
- - - { field_name: ip_protocol, width: 8, access_mode: RW, address_offset: 0x54 }
- - - { field_name: ip_header_checksum, width: 16, access_mode: RW, address_offset: 0x50 }
- - - { field_name: ip_source_address, width: 32, access_mode: RW, address_offset: 0x4C }
- - - { field_name: ip_destination_address, width: 32, access_mode: RW, address_offset: 0x48 }
+ - - { field_name: ip_version, mm_width: 4, access_mode: RW, address_offset: 0x74 }
+ - - { field_name: ip_header_length, mm_width: 4, access_mode: RW, address_offset: 0x70 }
+ - - { field_name: ip_services, mm_width: 8, access_mode: RW, address_offset: 0x6C }
+ - - { field_name: ip_total_length, mm_width: 16, access_mode: RW, address_offset: 0x68 }
+ - - { field_name: ip_identification, mm_width: 16, access_mode: RW, address_offset: 0x64 }
+ - - { field_name: ip_flags, mm_width: 3, access_mode: RW, address_offset: 0x60 }
+ - - { field_name: ip_fragment_offset, mm_width: 13, access_mode: RW, address_offset: 0x5C }
+ - - { field_name: ip_time_to_live, mm_width: 8, access_mode: RW, address_offset: 0x58 }
+ - - { field_name: ip_protocol, mm_width: 8, access_mode: RW, address_offset: 0x54 }
+ - - { field_name: ip_header_checksum, mm_width: 16, access_mode: RW, address_offset: 0x50 }
+ - - { field_name: ip_source_address, mm_width: 32, access_mode: RW, address_offset: 0x4C }
+ - - { field_name: ip_destination_address, mm_width: 32, access_mode: RW, address_offset: 0x48 }
# udp field group
- - - { field_name: udp_source_port, width: 16, access_mode: RW, address_offset: 0x44 }
- - - { field_name: udp_destination_port, width: 16, access_mode: RW, address_offset: 0x40 }
- - - { field_name: udp_length, width: 16, access_mode: RW, address_offset: 0x3C }
- - - { field_name: udp_checksum, width: 16, access_mode: RW, address_offset: 0x38 }
+ - - { field_name: udp_source_port, mm_width: 16, access_mode: RW, address_offset: 0x44 }
+ - - { field_name: udp_destination_port, mm_width: 16, access_mode: RW, address_offset: 0x40 }
+ - - { field_name: udp_length, mm_width: 16, access_mode: RW, address_offset: 0x3C }
+ - - { field_name: udp_checksum, mm_width: 16, access_mode: RW, address_offset: 0x38 }
# application field group
- - - { field_name: marker, width: 8, access_mode: RO, address_offset: 0x34 }
- - - { field_name: version_id, width: 8, access_mode: RO, address_offset: 0x30 }
- - - { field_name: observation_id, width: 32, access_mode: RW, address_offset: 0x2C }
- - - { field_name: station_id, width: 16, access_mode: RW, address_offset: 0x28 }
- - - { field_name: source_info, width: 16, access_mode: RW, address_offset: 0x24 }
+ - - { field_name: marker, mm_width: 8, access_mode: RO, address_offset: 0x34 }
+ - - { field_name: version_id, mm_width: 8, access_mode: RO, address_offset: 0x30 }
+ - - { field_name: observation_id, mm_width: 32, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: station_id, mm_width: 16, access_mode: RW, address_offset: 0x28 }
+ - - { field_name: source_info, mm_width: 16, access_mode: RW, address_offset: 0x24 }
- "source_info":
- - { field_name: antenna_band_index, width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
- - { field_name: nyquist_zone_index, width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
- - { field_name: f_adc, width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
- - { field_name: fsub_type, width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
- - { field_name: payload_error, width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
- - { field_name: beam_repositioning_flag, width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
- - { field_name: subband_calibrated_flag, width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x24 }
- - { field_name: reserved, width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
- - { field_name: gn_index, width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
-
- - - { field_name: reserved, width: 8, access_mode: RW, address_offset: 0x20 }
- - - { field_name: integration_interval, width: 24, access_mode: RW, address_offset: 0x1C }
- - - { field_name: data_id, width: 32, access_mode: RW, address_offset: 0x18 }
+ - { field_name: antenna_band_index, mm_width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
+ - { field_name: nyquist_zone_index, mm_width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
+ - { field_name: f_adc, mm_width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
+ - { field_name: fsub_type, mm_width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
+ - { field_name: payload_error, mm_width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
+ - { field_name: beam_repositioning_flag, mm_width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
+ - { field_name: subband_calibrated_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x24 }
+ - { field_name: reserved, mm_width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
+ - { field_name: gn_index, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
+
+ - - { field_name: reserved, mm_width: 8, access_mode: RW, address_offset: 0x20 }
+ - - { field_name: integration_interval, mm_width: 24, access_mode: RW, address_offset: 0x1C }
+ - - { field_name: data_id, mm_width: 32, access_mode: RW, address_offset: 0x18 }
- "data_id_xst":
- - { field_name: reserved, width: 7, bit_offset: 25, access_mode: RW, address_offset: 0x18 }
- - { field_name: subband_index, width: 9, bit_offset: 16, access_mode: RW, address_offset: 0x18 }
- - { field_name: signal_input_A_index, width: 8, bit_offset: 8, access_mode: RW, address_offset: 0x18 }
- - { field_name: signal_input_B_index, width: 8, bit_offset: 0, access_mode: RW, address_offset: 0x18 }
-
- - - { field_name: nof_signal_inputs, width: 8, access_mode: RW, address_offset: 0x14 }
- - - { field_name: nof_bytes_per_statistic, width: 8, access_mode: RW, address_offset: 0x10 }
- - - { field_name: nof_statistics_per_packet, width: 16, access_mode: RW, address_offset: 0xC }
- - - { field_name: block_period, width: 16, access_mode: RW, address_offset: 0x8 }
- - - { field_name: BSN, width: 32, access_mode: RW, address_offset: 0x0, radix_width: 64 }
+ - { field_name: reserved, mm_width: 7, bit_offset: 25, access_mode: RW, address_offset: 0x18 }
+ - { field_name: subband_index, mm_width: 9, bit_offset: 16, access_mode: RW, address_offset: 0x18 }
+ - { field_name: signal_input_A_index, mm_width: 8, bit_offset: 8, access_mode: RW, address_offset: 0x18 }
+ - { field_name: signal_input_B_index, mm_width: 8, bit_offset: 0, access_mode: RW, address_offset: 0x18 }
+
+ - - { field_name: nof_signal_inputs, mm_width: 8, access_mode: RW, address_offset: 0x14 }
+ - - { field_name: nof_bytes_per_statistic, mm_width: 8, access_mode: RW, address_offset: 0x10 }
+ - - { field_name: nof_statistics_per_packet, mm_width: 16, access_mode: RW, address_offset: 0xC }
+ - - { field_name: block_period, mm_width: 16, access_mode: RW, address_offset: 0x8 }
+ - - { field_name: BSN, mm_width: 32, user_width: 64, radix: uint64, access_mode: RW, address_offset: 0x0 }
diff --git a/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml b/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml
index e85ac86d90071a13a312f2a805e5a9ac0be32bba..faf0c65fd9c6df00dbf7e479840f80d65697ac8d 100644
--- a/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml
+++ b/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml
@@ -44,81 +44,38 @@ peripherals:
# peripheral, unb1_board_wdi_reg
- peripheral_name: ctrl
-
+ peripheral_description: " "
mm_ports:
# actual hdl name: unb1_board_wdi_reg
- mm_port_name : pio_wdi
mm_port_type : REG
+ mm_port_description: "Reset register, for nios "
fields:
- - field_name : nios_reset
- width : 32
- access_mode : WO
- address_offset : 0x0
- number_of_fields: 1
field_description: " Reset done by nios "
+ number_of_fields: 1
+ address_offset : 0x0
+ mm_width : 32
+ access_mode : WO
- mm_port_description: "Reset register, for nios "
- peripheral_description: " "
-
# peripheral, unb1_board_wdi_reg
- peripheral_name: wdi
-
+ peripheral_description: " "
mm_ports:
# actual hdl name: unb1_board_wdi_reg
- mm_port_name : wdi
mm_port_type : REG
+ mm_port_description: "Reset register, if the right value is provided the factory image will be reloaded "
fields:
- - field_name : reset_word
+ field_description: " Only the value 0xB007FAC7 'Boot factory' will result in a reset "
access_mode : WO
address_offset: 0x0
- field_description: " Only the value 0xB007FAC7 'Boot factory' will result in a reset "
-
- mm_port_description: "Reset register, if the right value is provided the factory image will be reloaded "
- peripheral_description: " "
# periheral, unb1_board_sens
- peripheral_name: sens
-
- parameters:
- - { name: g_sim, value: FALSE }
- - { name: g_clk_freq, value: c_unb1_board_mm_clk_freq_125M }
- - { name: g_temp_high, value: 85 }
-
- mm_ports:
- # actual hdl name: reg_unb1_sens
- - mm_port_name : sens
- mm_port_type : REG
- fields:
- - - field_name : sens_data
- width : 8
- access_mode : RO
- address_offset: 0x0
- number_of_fields: 4
- field_description: |
- " data array with sens data
- 0x0 = fpga temperature in degrees (two's complement)
- 0x1 = eth_temp temperature in degrees (two's complement)
- 0x2 = hot_swap_v_sens
- 0x3 = hot_swap_v_source"
-
- - - field_name : sens_err
- width : 1
- access_mode : RO
- address_offset: 0x10
- radix : unsigned
- field_description: ""
-
- - - field_name : temp_high
- width : 7
- address_offset: 0x14
- reset_value : g_temp_high
- software_value: g_temp_high
- field_description: ""
-
- mm_port_description: " "
-
peripheral_description: |
"
+-----------------------------------------------------------------------------+
@@ -142,13 +99,13 @@ peripherals:
LTC4260_V_UNIT_SENSE = 0.0003 -- 0.3 mV over Rs for current sense
LTC4260_V_UNIT_SOURCE = 0.4 -- 400 mV supply voltage (e.g +48 V)
LTC4260_V_UNIT_ADIN = 0.01 -- 10 mV ADC
-
+
. From UniBoard unb_sensors.h:
SENS_HOT_SWAP_R_SENSE = 0.005 -- R sense on UniBoard is 5 mOhm (~= 10 mOhm // 10 mOhm)
SENS_HOT_SWAP_I_UNIT_SENSE = LTC4260_V_UNIT_SENSE / SENS_HOT_SWAP_R_SENSE
SENS_HOT_SWAP_V_UNIT_SOURCE = LTC4260_V_UNIT_SOURCE
-
- ==>
+
+ ==>
Via all FN and BN:
0 = FPGA temperature = TInt8(fpga_temp)
Only via BN3:
@@ -156,4 +113,39 @@ peripherals:
2 = UniBoard hot swap supply current = hot_swap_v_sense * SENS_HOT_SWAP_I_UNIT_SENSE
3 = UniBoard hot swap supply voltage = hot_swap_v_source * SENS_HOT_SWAP_V_UNIT_SOURCE
4 = I2C error status for BN3 sensors access only, 0 = ok"
+ parameters:
+ - { name: g_sim, value: FALSE }
+ - { name: g_clk_freq, value: c_unb1_board_mm_clk_freq_125M }
+ - { name: g_temp_high, value: 85 }
+ mm_ports:
+ # actual hdl name: reg_unb1_sens
+ - mm_port_name : sens
+ mm_port_type : REG
+ mm_port_description: " "
+ fields:
+ - - field_name : sens_data
+ field_description: |
+ " data array with sens data
+ 0x0 = fpga temperature in degrees (two's complement)
+ 0x1 = eth_temp temperature in degrees (two's complement)
+ 0x2 = hot_swap_v_sens
+ 0x3 = hot_swap_v_source"
+ number_of_fields: 4
+ address_offset: 0x0
+ mm_width : 8
+ access_mode : RO
+
+ - - field_name : sens_err
+ field_description: ""
+ address_offset: 0x10
+ mm_width : 1
+ access_mode : RO
+ radix : uint32
+
+ - - field_name : temp_high
+ field_description: ""
+ address_offset: 0x14
+ mm_width : 7
+ reset_value : g_temp_high
+
diff --git a/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml b/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml
index 01243fd42502200dbbc1ec823b7c66f6cb3da100..40f9191902718876c4770eddae1437b8cc66f0fe 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml
+++ b/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml
@@ -11,10 +11,10 @@ peripherals:
# Factory / minimal (from ctrl_unb2b_board.vhd)
#############################################################################
- peripheral_name: unb2b_board/system_info
+ lock_base_address: 0x10000
mm_port_names:
- ROM_SYSTEM_INFO
- PIO_SYSTEM_INFO
- lock_base_address: 0x10000
- peripheral_name: unb2b_board/wdi
mm_port_names:
@@ -24,11 +24,11 @@ peripherals:
mm_port_names:
- REG_FPGA_TEMP_SENS
- REG_FPGA_VOLTAGE_SENS
-
+
- peripheral_name: unb2b_board/ram_scrap
mm_port_names:
- RAM_SCRAP
-
+
- peripheral_name: eth/eth
mm_port_names:
- AVS_ETH_0_TSE
@@ -42,17 +42,17 @@ peripherals:
- peripheral_name: epcs/epcs
mm_port_names:
- REG_EPCS
-
+
- peripheral_name: dp/dpmm
mm_port_names:
- REG_DPMM_CTRL
- REG_DPMM_DATA
-
+
- peripheral_name: dp/mmdp
mm_port_names:
- REG_MMDP_CTRL
- REG_MMDP_DATA
-
+
- peripheral_name: remu/remu
mm_port_names:
- REG_REMU
diff --git a/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml b/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
index 254ac5e1c7e182c50a91e78df03f08789fb39790..fc5f4ccbf3e156fe51d24ed3009ccc25029f53c2 100644
--- a/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
+++ b/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
@@ -1,4 +1,3 @@
----
schema_name: args
schema_version: 1.0
schema_type: peripheral
@@ -17,9 +16,9 @@ peripherals:
fields:
- - field_name: rw_data
field_description: "Void data"
- access_mode: RW
- address_offset: 0x0
number_of_fields: 512
+ address_offset: 0x0
+ access_mode: RW
- peripheral_name: system_info # pi_system_info.py
peripheral_description: ""
@@ -32,10 +31,12 @@ peripherals:
fields:
- - field_name: ro_data
field_description: "FPGA info memory map data"
- access_mode: RO
+ number_of_fields: 32768 # c_rom_addr_w in mms_unb2b_board_system_info
address_offset: 0x0
- number_of_fields: 8192 # c_rom_addr_w in mms_unb2b_board_system_info
- radix: char
+ mm_width: 32
+ user_width: 8
+ radix: char8
+ access_mode: RO
# MM port for mms_unb2b_board_system_info.vhd / unb2b_board_system_info_reg.vhd
- mm_port_name: PIO_SYSTEM_INFO
@@ -52,65 +53,66 @@ peripherals:
# Each field specified
- - field_name: info
field_description: "Info"
- width: 32
+ address_offset: 0x0
bit_offset: 0
+ mm_width: 32
access_mode: RO
- address_offset: 0x0
- "info": # field_group
- field_name: gn_index
field_description: "Global node index, unb2 FPGA id = gn_index % 4, unb2 backplane id = gn_index // 4"
- width: 8
+ address_offset: 0x0
bit_offset: 0
+ mm_width: 8
access_mode: RO
- address_offset: 0x0
- field_name: hw_version
field_description: "UniBoard2 hardware (HW) version."
- width: 2
+ address_offset: 0x0
bit_offset: 8
+ mm_width: 2
access_mode: RO
- address_offset: 0x0
- field_name: cs_sim
field_description: "0 when running on HW, 1 when running in simulation."
- width: 1
+ address_offset: 0x0
bit_offset: 10
+ mm_width: 1
access_mode: RO
- address_offset: 0x0
- field_name: fw_version_major
field_description: "FPGA Firmware (FW) version major number, not used use version stamp instead."
- width: 4
+ address_offset: 0x0
bit_offset: 16
+ mm_width: 4
access_mode: RO
- address_offset: 0x0
- field_name: fw_version_minor
field_description: "FPGA Firmware (FW) version minor number, not used use version stamp instead."
- width: 4
+ address_offset: 0x0
bit_offset: 20
+ mm_width: 4
access_mode: RO
- address_offset: 0x0
- field_name: rom_version
field_description: "Version of the mmap schema in ROM_SYSTEM_INFO."
- width: 3
+ address_offset: 0x0
bit_offset: 24
+ mm_width: 3
access_mode: RO
- address_offset: 0x0
- field_name: technology
field_description: "FPGA technology"
- width: 5
+ address_offset: 0x0
bit_offset: 27
+ mm_width: 5
access_mode: RO
- address_offset: 0x0
- - field_name: use_phy
field_description: "PHY interfaces that are active in the FPGA, not used."
- width: 8
- access_mode: RO
address_offset: 0x4
+ mm_width: 8
+ access_mode: RO
- - field_name: design_name
field_description: "FPGA FW design name string."
- access_mode: RO
+ number_of_fields: 52
address_offset: 0x8
- number_of_fields: 13
- radix: char
- radix_width: 8
+ mm_width: 32
+ user_width: 8
+ radix: char8
+ access_mode: RO
- - field_name: stamp_date
field_description: "FPGA FW compile date string."
access_mode: RO
@@ -118,22 +120,22 @@ peripherals:
number_of_fields: 1
- - field_name: stamp_time
field_description: "FPGA FW compile time string."
- access_mode: RO
- address_offset: 0x40
number_of_fields: 1
+ address_offset: 0x40
+ access_mode: RO
- - field_name: stamp_commit
field_description: "FPGA FW commit hash string."
- access_mode: RO
- address_offset: 0x44
number_of_fields: 3
- radix: hexadecimal
+ address_offset: 0x44
+ access_mode: RO
- - field_name: design_note
field_description: "FPGA FW design note string."
- access_mode: RO
+ number_of_fields: 52
address_offset: 0x50
- number_of_fields: 13
- radix: char
- radix_width: 8
+ mm_width: 32
+ user_width: 8
+ radix: char8
+ access_mode: RO
- peripheral_name: wdi # pi_wdi.py
peripheral_description: ""
@@ -145,8 +147,8 @@ peripherals:
fields:
- - field_name: wdi_override
field_description: "Write value 0xB007FAC7 = 'Boot factory' to disable the watchdog interrupt (WDI), to cause an FPGA image reload."
- access_mode: WO
address_offset: 0x0
+ access_mode: WO
- peripheral_name: unb2_fpga_sens
peripheral_description: ""
@@ -160,9 +162,9 @@ peripherals:
fields:
- - field_name: temp
field_description: "Raw data"
- access_mode: RO
- address_offset: 0x0
number_of_fields: 1
+ address_offset: 0x0
+ access_mode: RO
- mm_port_name: REG_FPGA_VOLTAGE_SENS # pi_unb_fpga_voltagesens.py
mm_port_type: REG
@@ -170,7 +172,7 @@ peripherals:
fields:
- - field_name: voltages
field_description: "Not used"
- access_mode: RO
- address_offset: 0x0
number_of_fields: 6
-
+ address_offset: 0x0
+ access_mode: RO
+
diff --git a/libraries/base/common/common.peripheral.yaml b/libraries/base/common/common.peripheral.yaml
index b9ad15bbbc80f89fafefa2a7b4e206061810d813..5d06bbdbda5d1d9331af904518ebbc63f6a51c9d 100644
--- a/libraries/base/common/common.peripheral.yaml
+++ b/libraries/base/common/common.peripheral.yaml
@@ -21,6 +21,6 @@ peripherals:
fields:
- - field_name: enable
field_description: "When 1 pass on delayed pulse to the output, else disable the output pulse."
- width: 1
- access_mode: RW
address_offset: 0x0
+ mm_width: 1
+ access_mode: RW
diff --git a/libraries/base/diag/diag.peripheral.yaml b/libraries/base/diag/diag.peripheral.yaml
index c92c4a5823e36e62d9b5d26da9d022fb043b7b96..ac86812ef1440c831599e5e484f71145a97cec63 100644
--- a/libraries/base/diag/diag.peripheral.yaml
+++ b/libraries/base/diag/diag.peripheral.yaml
@@ -14,15 +14,15 @@ peripherals:
mm_ports:
# MM port for diag_wg_wideband_reg.vhd
- mm_port_name: REG_DIAG_WG
- mm_port_description: "Waveform control."
mm_port_type: REG
+ mm_port_description: "Waveform control."
number_of_mm_ports: g_nof_streams
fields:
- - field_name: nof_samples
field_description: "Number of samples in WG period."
- width: 16
- bit_offset: 16
address_offset: 0x0
+ bit_offset: 16
+ mm_width: 16
- - field_name: mode
field_description: |
"WG mode:
@@ -30,35 +30,35 @@ peripherals:
1 = calc, uses WG buffer waveform to output sinus with ampl * sin(freq * t + phase
2 = repeat, outputs WG buffer waveform repeatedly
3 = single, outputs WG buffer waveform once"
- width: 8
- bit_offset: 0
address_offset: 0x0
+ bit_offset: 0
+ mm_width: 8
- - field_name: phase
field_description: "Phase of WG sinus, phase = int('phase in degrees' * 2**width / 360)."
- width: 16
- bit_offset: 0
address_offset: 0x4
+ bit_offset: 0
+ mm_width: 16
- - field_name: freq
field_description: "Frequency of WG sinus, freq = int('frequency in range 0 to 1' * f_adc * 2**width), where f_adc is sample frequency in Hz."
- width: 31
- bit_offset: 0
address_offset: 0x8
+ bit_offset: 0
+ mm_width: 31
- - field_name: ampl
field_description: "Amplitude of WG sinus, ampl = int('amplitude in range 0 to 2' * 2**(width-1), where amplitude > 1 causes clipping."
- width: 17
- bit_offset: 0
address_offset: 0xC
+ bit_offset: 0
+ mm_width: 17
# MM port for mms_diag_wg_wideband.vhd
- mm_port_name: RAM_DIAG_WG
- mm_port_description: "Waveform buffer."
mm_port_type: RAM
+ mm_port_description: "Waveform buffer."
number_of_mm_ports: g_nof_streams
fields:
- - field_name: data
field_description: "Waveform default is one sinus period (diag_sin_1024x18.hex)."
- width: 18 # = c_wg_buf_dat_w in node_adc_input_and_timing.vhd
- address_offset: 0x0
number_of_fields: 1024 # = 2**c_wg_buf_addr_w in node_adc_input_and_timing.vhd
+ address_offset: 0x0
+ mm_width: 18 # = c_wg_buf_dat_w in node_adc_input_and_timing.vhd
- peripheral_name: diag_data_buffer # pi_diag_data_buffer.py
peripheral_description: "Data buffer (DB)"
@@ -71,27 +71,27 @@ peripherals:
mm_ports:
# MM port for mms_diag_data_buffer.vhd
- mm_port_name: REG_DIAG_DB
- mm_port_description: "Data buffer status."
mm_port_type: REG
+ mm_port_description: "Data buffer status."
number_of_mm_ports: g_nof_streams
fields:
- - field_name: sync_cnt
field_description: "Number of times the DB has been written."
- access_mode: RO
address_offset: 0x0
+ access_mode: RO
- - field_name: word_cnt
field_description: "Number data words in the DB."
- access_mode: RO
address_offset: 0x4
+ access_mode: RO
# MM port for mms_diag_data_buffer.vhd
- mm_port_name: RAM_DIAG_DB
- mm_port_description: "Data buffer memory, gets filled after the sync when g_use_in_sync = True, else after the last word was read."
mm_port_type: RAM
+ mm_port_description: "Data buffer memory, gets filled after the sync when g_use_in_sync = True, else after the last word was read."
number_of_mm_ports: g_nof_streams
fields:
- - field_name: data
field_description: ""
- width: g_data_w
- address_offset: 0x0
number_of_fields: g_nof_data
+ address_offset: 0x0
+ mm_width: g_data_w
diff --git a/libraries/base/dp/dp.peripheral.yaml b/libraries/base/dp/dp.peripheral.yaml
index 2d2b0570c3c965e81927fb4b479bb79817c3d709..7a8008c0e8addecda2dee9e1579f39f0fd09c9d6 100644
--- a/libraries/base/dp/dp.peripheral.yaml
+++ b/libraries/base/dp/dp.peripheral.yaml
@@ -16,8 +16,8 @@ peripherals:
fields:
- - field_name: rd_usedw
field_description: "Number of words that can be read from the FIFO."
- access_mode: RO
address_offset: 0x0
+ access_mode: RO
# MM port for mms_dp_fifo_to_mm.vhd / dp_fifo_to_mm.vhd
- mm_port_name: REG_DPMM_DATA # Use REG_, instead of preferred FIFO_, to match mm_port_name in pi_dpmm.py
mm_port_type: FIFO
@@ -25,8 +25,8 @@ peripherals:
fields:
- - field_name: rd_data
field_description: "Read data from the FIFO."
- access_mode: RO
address_offset: 0x0
+ access_mode: RO
- peripheral_name: mmdp # pi_mmdp.py
@@ -39,13 +39,13 @@ peripherals:
fields:
- - field_name: wr_usedw
field_description: "Number of words that are in the write FIFO."
- access_mode: RO
address_offset: 0x0
+ access_mode: RO
- - field_name: wr_availw
field_description: "Number of words that can be written to the write FIFO."
- access_mode: RO
address_offset: 0x4
+ access_mode: RO
# MM port for mms_dp_fifo_from_mm.vhd / dp_fifo_from_mm.vhd
- mm_port_name: REG_MMDP_DATA # Use REG_, instead of preferred FIFO_, to match mm_port_name in pi_mmdp.py
mm_port_type: FIFO
@@ -53,8 +53,8 @@ peripherals:
fields:
- - field_name: data
field_description: "Write data to the FIFO."
- access_mode: WO
address_offset: 0x0
+ access_mode: WO
- peripheral_name: dp_xonoff # pi_dp_xonoff.py
@@ -73,10 +73,10 @@ peripherals:
field_description: |
"When enable_stream = 0 the data stream is stopped, else when 1 then the data stream is passed on.
Toggling the data stream on or off happens at block or packet boundaries."
- width: 1
- access_mode: RW
- address_offset: 0x0
number_of_fields: 1 #g_nof_streams #sel_a_b(g_combine_streams, 1, g_nof_streams)
+ address_offset: 0x0
+ mm_width: 1
+ access_mode: RW
- peripheral_name: dp_shiftram # pi_dp_shiftram.py
@@ -95,9 +95,9 @@ peripherals:
fields:
- - field_name: shift
field_description: "Fill level of the sample delay buffer in number of data samples."
- width: ceil_log2(g_nof_words)
- access_mode: RW
address_offset: 0x0
+ mm_width: ceil_log2(g_nof_words)
+ access_mode: RW
- peripheral_name: dp_bsn_source # pi_dp_bsn_source.py
@@ -116,32 +116,25 @@ peripherals:
"When 1 then enable BSN source, else when 0 disable BSN source. If dp_on_pps is 0,
then dp_on = 1 enables the BSN source immediately. To enable the BSN source at
the next PPS, then first set dp_on_pps = 1. Clearing dp_on stops the BSN source."
- width: 1
- access_mode: RW
address_offset: 0x0
+ mm_width: 1
+ access_mode: RW
- - field_name: dp_on_pps
field_description: "When 1 and dp_on = 1 then enable BSN source at next PPS."
- width: 1
+ address_offset: 0x0
bit_offset: 1
+ mm_width: 1
access_mode: RW
- address_offset: 0x0
- - field_name: nof_block_per_sync
field_description: "Number of blocks per sync interval."
- access_mode: RW
address_offset: 0x4
- #- - field_name: bsn_lo
- # field_description: "Initial BSN[31:0]"
- # access_mode: RW
- # address_offset: 0x8
- #- - field_name: bsn_hi
- # field_description: "Initial BSN[63:32]"
- # access_mode: RW
- # address_offset: 0xC
+ access_mode: RW
- - field_name: bsn
field_description: "Initial BSN"
- access_mode: RW
address_offset: 0x8
- radix_width: 64
+ user_width: 64
+ radix: uint64
+ access_mode: RW
- peripheral_name: dp_bsn_source_v2 # pi_dp_bsn_source_v2.py
@@ -162,37 +155,30 @@ peripherals:
"When 1 then enable BSN source, else when 0 disable BSN source. If dp_on_pps is 0,
then dp_on = 1 enables the BSN source immediately. To enable the BSN source at
the next PPS, then first set dp_on_pps = 1. Clearing dp_on stops the BSN source."
- width: 1
- access_mode: RW
address_offset: 0x0
+ mm_width: 1
+ access_mode: RW
- - field_name: dp_on_pps
field_description: "When 1 and dp_on = 1, then enable BSN source at next PPS."
- width: 1
+ address_offset: 0x0
bit_offset: 1
+ mm_width: 1
access_mode: RW
- address_offset: 0x0
- - field_name: nof_block_per_sync
field_description: "Number of clock cycles per sync interval."
- access_mode: RW
address_offset: 0x4
- #- - field_name: bsn_init_lo
- # field_description: "Initial BSN[31:0]"
- # access_mode: RW
- # address_offset: 0x8
- #- - field_name: bsn_init_hi
- # field_description: "Initial BSN[63:32]"
- # access_mode: RW
- # address_offset: 0xC
+ access_mode: RW
- - field_name: bsn_init
field_description: "Initial BSN"
- access_mode: RW
address_offset: 0x8
- radix_width: 64
+ user_width: 64
+ radix: uint64
+ access_mode: RW
- - field_name: bsn_time_offset
field_description: "The BSN block time offset in number of clock cycles, with respect to the PPS."
- width: g_bsn_time_offset_w
- access_mode: RW
address_offset: 0x10
+ mm_width: g_bsn_time_offset_w
+ access_mode: RW
- peripheral_name: dp_bsn_scheduler # pi_dp_bsn_scheduler.py
@@ -203,19 +189,12 @@ peripherals:
mm_port_type: REG
mm_port_description: ""
fields:
- #- - field_name: scheduled_bsn_lo
- # field_description: "Write scheduled BSN lo, read current BSN lo. First access lo, then hi."
- # access_mode: RW
- # address_offset: 0x0
- #- - field_name: scheduled_bsn_hi
- # field_description: "Write scheduled BSN hi, read current BSN hi. First access lo, then hi."
- # access_mode: RW
- # address_offset: 0x4
- - field_name: scheduled_bsn
field_description: "Write scheduled BSN. First access lo, then hi."
- access_mode: RW
address_offset: 0x0
- radix_width: 64
+ user_width: 64
+ radix: uint64
+ access_mode: RW
- peripheral_name: dp_bsn_monitor # pi_dp_bsn_monitor.py
@@ -232,64 +211,50 @@ peripherals:
fields:
- - field_name: xon_stable
field_description: "Data block flow control xon signal was active and stable during last sync interval."
- width: 1
+ address_offset: 0x0
bit_offset: 0
+ mm_width: 1
access_mode: RO
- address_offset: 0x0
- - field_name: ready_stable
field_description: "Clock cycle flow control ready signal was active and stable during last sync interval."
- width: 1
+ address_offset: 0x0
bit_offset: 1
+ mm_width: 1
access_mode: RO
- address_offset: 0x0
- - field_name: sync_timeout
field_description: "Data stream sync did not occur during last sync interval."
- width: 1
+ address_offset: 0x0
bit_offset: 2 # EK TODO: 2 is correct, but using 1 cause gen_doc.py to fail without clear error, because fields then overlap
+ mm_width: 1
access_mode: RO
- address_offset: 0x0
- #- - field_name: bsn_at_sync_lo
- # field_description: "Data stream BSN lo at sync."
- # access_mode: RO
- # address_offset: 0x4
- #- - field_name: bsn_at_sync_hi
- # field_description: "Data stream BSN hi at sync."
- # access_mode: RO
- # address_offset: 0x8
- - field_name: bsn_at_sync
field_description: "Data stream BSN at sync."
- access_mode: RO
address_offset: 0x4
- radix_width: 64
+ user_width: 64
+ radix: uint64
+ access_mode: RO
- - field_name: nof_sop
field_description: "Number data blocks (sop = start of packet) during last sync interval."
- access_mode: RO
address_offset: 0xC
+ access_mode: RO
- - field_name: nof_valid
field_description: "Number valid samples of the data blocks during last sync interval (= nof_sop * block size)."
- access_mode: RO
address_offset: 0x10
+ access_mode: RO
- - field_name: nof_err
field_description: "Number data blocks with error indication during last sync interval."
- access_mode: RO
address_offset: 0x14
- #- - field_name: bsn_first_lo
- # field_description: "First data stream BSN lo ever."
- # access_mode: RO
- # address_offset: 0x18
- #- - field_name: bsn_first_hi
- # field_description: "First data stream BSN hi ever."
- # access_mode: RO
- # address_offset: 0x1C
+ access_mode: RO
- - field_name: bsn_first
field_description: "First data stream BSN ever."
- access_mode: RO
address_offset: 0x18
- radix_width: 64
+ user_width: 64
+ radix: uint64
+ access_mode: RO
- - field_name: bsn_first_cycle_cnt
field_description: "Arrival latency of first data stream BSN ever, relative to local sync."
- access_mode: RO
address_offset: 0x20
+ access_mode: RO
- peripheral_name: dp_bsn_monitor_v2 # pi_dp_bsn_monitor_v2.py
@@ -306,51 +271,44 @@ peripherals:
fields:
- - field_name: xon_stable
field_description: "Data block flow control xon signal was active and stable during last sync interval."
- width: 1
+ address_offset: 0x0
bit_offset: 0
+ mm_width: 1
access_mode: RO
- address_offset: 0x0
- - field_name: ready_stable
field_description: "Clock cycle flow control ready signal was active and stable during last sync interval."
- width: 1
+ address_offset: 0x0
bit_offset: 1
+ mm_width: 1
access_mode: RO
- address_offset: 0x0
- - field_name: sync_timeout
field_description: "Data stream sync did not occur during last sync interval."
- width: 1
+ address_offset: 0x0
bit_offset: 1
+ mm_width: 1
access_mode: RO
- address_offset: 0x0
- #- - field_name: bsn_at_sync_lo
- # field_description: "Data stream BSN lo at sync."
- # access_mode: RO
- # address_offset: 0x4
- #- - field_name: bsn_at_sync_hi
- # field_description: "Data stream BSN hi at sync."
- # access_mode: RO
- # address_offset: 0x8
- - field_name: bsn_at_sync
field_description: "Data stream BSN at sync."
- access_mode: RO
address_offset: 0x4
- radix_width: 64
+ user_width: 64
+ radix: uint64
+ access_mode: RO
- - field_name: nof_sop
field_description: "Number data blocks (sop = start of packet) during last sync interval."
- access_mode: RO
address_offset: 0xC
+ access_mode: RO
- - field_name: nof_valid
field_description: "Number valid samples of the data blocks during last sync interval (= nof_sop * block size)."
- access_mode: RO
address_offset: 0x10
+ access_mode: RO
- - field_name: nof_err
field_description: "Number data blocks with error indication during last sync interval."
- access_mode: RO
address_offset: 0x14
+ access_mode: RO
- - field_name: latency
field_description: "Arrival latency of data stream BSN at sync, relative to local sync."
- access_mode: RO
address_offset: 0x20
+ access_mode: RO
- peripheral_name: dp_selector # pi_dp_selector.py
@@ -365,6 +323,6 @@ peripherals:
field_description: |
"When input_select = 0 select the reference data stream(s), else when 1 select the other data stream(s).
The input_select is synchronsized to the start of a sync interval."
- width: 1
- access_mode: RW
address_offset: 0x0
+ mm_width: 1
+ access_mode: RW
diff --git a/libraries/base/reorder/reorder.peripheral.yaml b/libraries/base/reorder/reorder.peripheral.yaml
index d74d0333fecd7b8a8243da6ffa36e6847b71716a..fa238d51081386f0d1330737dc6f921421944d0a 100644
--- a/libraries/base/reorder/reorder.peripheral.yaml
+++ b/libraries/base/reorder/reorder.peripheral.yaml
@@ -22,13 +22,13 @@ peripherals:
mm_ports:
# MM port for reorder_col_wide.vhd / reorder_col.vhd
- mm_port_name: RAM_SS_SS_WIDE
- mm_port_description: ""
mm_port_type: RAM
+ mm_port_description: ""
number_of_mm_ports: g_wb_factor
fields:
- - field_name: index
field_description: ""
- width: ceil_log2(g_nof_ch_in)
- address_offset: 0x0
number_of_fields: g_nof_ch_sel
+ address_offset: 0x0
+ mm_width: ceil_log2(g_nof_ch_in)
diff --git a/libraries/dsp/bf/bf.peripheral.yaml b/libraries/dsp/bf/bf.peripheral.yaml
index 12c36e3e1a9c95371dbcca9f63b5a2f2d83604fb..0a2824614a9051f0822a1bc9153e0c4827711381 100644
--- a/libraries/dsp/bf/bf.peripheral.yaml
+++ b/libraries/dsp/bf/bf.peripheral.yaml
@@ -7,7 +7,9 @@ hdl_library_description: " This is the description for the bf package "
peripherals:
- peripheral_name: bf
-
+ peripheral_description: |
+ "This is the beamformer unit"
+
parameters:
- { name: g_bf.in_weights_w , value: 16 }
- { name: g_bf.nof_weights , value: 256 }
@@ -18,62 +20,59 @@ peripherals:
mm_ports:
# ram_bf_weights
- - mm_port_name : WEIGHTS
- number_of_mm_ports: g_bf.nof_weights
+ - mm_port_name: WEIGHTS
mm_port_type: RAM
+ mm_port_description: >
+ " "
+ number_of_mm_ports: g_bf.nof_weights
fields:
- - - field_name : bf_weights
- width : g_bf.in_weights_w * c_nof_complex
-
- number_of_fields: g_bf.nof_signal_paths
+ - - field_name: bf_weights
field_description: |
- "Contains the weights.
+ "Contains the weights.
The real and the imaginary parts are concatenated: W_real in Lower part. W_imag in Higher part."
- mm_port_description: >
- " "
+ number_of_fields: g_bf.nof_signal_paths
+ mm_width: g_bf.in_weights_w * c_nof_complex
+
# ram_ss_ss_wide
- - mm_port_name : SS_SS_WIDE
- number_of_mm_ports: g_bf.nof_weights
+ - mm_port_name: SS_SS_WIDE
mm_port_type: RAM
+ mm_port_description: >
+ " "
+ number_of_mm_ports: g_bf.nof_weights
fields:
- - - field_name : ss_ss_wide
- width : 32
- number_of_fields: g_bf.nof_subbands * g_bf.nof_input_streams * c_nof_signal_paths_per_stream # 16*4=64, nof_input_streams*nof_signal_paths_per_stream
+ - - field_name: ss_ss_wide
field_description: |
"Contains the addresses to select from the stored subbands."
- mm_port_description: >
- " "
+ number_of_fields: g_bf.nof_subbands * g_bf.nof_input_streams * c_nof_signal_paths_per_stream # 16*4=64, nof_input_streams*nof_signal_paths_per_stream
+ mm_width: 32
# ram_st_sst_bf
- - mm_port_name : ST_SST
- number_of_mm_ports: g_bf.nof_weights
+ - mm_port_name: ST_SST
mm_port_type: RAM
+ mm_port_description: >
+ " "
+ number_of_mm_ports: g_bf.nof_weights
fields:
- - - field_name : st_sst_bf
- width : 56
- number_of_fields: 512
- access_mode : RO
+ - - field_name: st_sst_bf
field_description: |
"Contains the weights.
The real and the imaginary parts are concatenated: W_real in Lower part. W_imag in Higher part."
- mm_port_description: >
- " "
+ number_of_fields: 512
+ mm_width: 56
+ access_mode : RO
# reg_st_sst_bf
- mm_port_name : treshold
- number_of_mm_ports: 1
mm_port_type: REG
+ mm_port_description: >
+ " "
+ number_of_mm_ports: 1
fields:
- - - field_name : treshold
- address_offset: 0x0
- field_description : |
+ - - field_name: treshold
+ field_description: |
"When the treshold register is set to 0 the statistics will be auto-correlations.
In case the treshold register is set to a non-zero value, it allows to create a sample & hold function
for the a-input of the multiplier.
The a-input of the multiplier is updated every treshold clockcycle. Thereby cross statistics can be created."
- mm_port_description: >
- " "
-
- peripheral_description: |
- "This is the beamformer unit"
+ address_offset: 0x0
diff --git a/libraries/dsp/filter/filter.peripheral.yaml b/libraries/dsp/filter/filter.peripheral.yaml
index af75840c8d526380dcf05aeb4acab04678f8e6de..0e13878acb86d6fbb3315e8cc5692b88869b4225 100644
--- a/libraries/dsp/filter/filter.peripheral.yaml
+++ b/libraries/dsp/filter/filter.peripheral.yaml
@@ -8,37 +8,46 @@ hdl_library_description: "Poly-phase filter (PPF) for a Wideband Poly-phase filt
peripherals:
- peripheral_name: fil_ppf_w # pi_fil_ppf_w.py
peripheral_description: |
- "PPF FIR filter for wideband data streams, all data streams use the same FIR coefficients.
- The PPF has g_nof_bands phases, where g_nof_bands is equal to the size of the FFT in the
- PFB. The PPF has g_nof_taps FIR taps per phase. Hence the total number of FIR coefficients
- is g_nof_taps * g_nof_bands.
- The PPF can process a data stream that is clocked at a wideband factor g_wb_factor higher
- data rate, by running g_wb_factor parts in parallel.
+ "PPF FIR filter for wideband data streams, all g_fil_ppf.nof_streams use the same FIR
+ coefficients. The PPF has g_fil_ppf.nof_bands poly phases, where g_fil_ppf.nof_bands is
+ equal to the size (number of points) of the FFT in the PFB. The PPF has
+ g_fil_ppf.nof_taps FIR taps per poly phase. Hence the total number of FIR coefficients
+ is g_fil_ppf.nof_taps * g_fil_ppf.nof_bands.
+ The PPF can process a data stream that is clocked at a wideband factor g_fil_ppf.wb_factor
+ higher data rate, by running g_fil_ppf.wb_factor parts in parallel. The
+ g_fil_ppf.wb_factor >= 1 and a power of 2.
+ The PPF can process 2**g_fil_ppf.nof_chan channels that are multiplexed in time in
+ a data stream when g_fil_ppf.nof_chan > 0. Therefore typically when g_fil_ppf.nof_chan > 0
+ then g_fil_ppf.wb_factor = 1, and when g_fil_ppf.wb_factor > 1 then g_fil_ppf.nof_chan = 0,
+ because time multiplexing is only useful when the processing clock rate is faster then the
+ data stream rate.
The FIR coefficients are real values."
parameters:
# Parameters of fil_ppf_wide.vhd
- - { name: g_wb_factor, value: 1 }
- - { name: g_nof_taps, value: 8 }
- - { name: g_nof_bands, value: 256 }
- - { name: g_coef_dat_w, value: 16 }
+ - { name: g_fil_ppf.wb_factor, value: 1 }
+ - { name: g_fil_ppf.nof_chan, value: 0 }
+ - { name: g_fil_ppf.nof_bands, value: 256 }
+ - { name: g_fil_ppf.nof_taps, value: 8 }
+ - { name: g_fil_ppf.nof_streams, value: 1 }
+ - { name: g_fil_ppf.coef_dat_w, value: 16 }
mm_ports:
# MM port for fil_ppf_wide.vhd / fil_ppf_single.vhd
- mm_port_name: RAM_FIL_COEFS
+ mm_port_type: RAM
mm_port_description: |
- "The FIR filter coefficients are stored in blocks of g_nof_bands/g_wb_factor real
- coefficients:
+ "The FIR filter coefficients are stored in blocks of g_fil_ppf.nof_bands/g_fil_ppf.wb_factor
+ real coefficients:
- (int16)coefs[g_wb_factor][g_nof_taps][g_nof_bands/g_wb_factor]
+ (int16)coefs[g_fil_ppf.wb_factor][g_fil_ppf.nof_taps][g_fil_ppf.nof_bands/g_fil_ppf.wb_factor]
- For g_wb_factor = 1 this reduces to g_nof_taps blocks of g_nof_bands/g_wb_factor
- coefficients:
+ For g_fil_ppf.wb_factor = 1 this reduces to g_fil_ppf.nof_taps blocks of
+ g_fil_ppf.nof_bands/g_fil_ppf.wb_factor coefficients:
- (int16)coefs[g_nof_taps][g_nof_bands]"
- mm_port_type: RAM
- number_of_mm_ports: g_wb_factor * g_nof_taps
+ (int16)coefs[g_fil_ppf.nof_taps][g_fil_ppf.nof_bands]"
+ number_of_mm_ports: g_fil_ppf.wb_factor * g_fil_ppf.nof_taps
fields:
- - field_name: coef
field_description: "Real FIR filter coefficient"
- width: g_coef_dat_w
+ number_of_fields: g_fil_ppf.nof_bands / g_fil_ppf.wb_factor
address_offset: 0x0
- number_of_fields: g_nof_bands / g_wb_factor
+ mm_width: g_fil_ppf.coef_dat_w
diff --git a/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml b/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml
index 2872466d08baf491453e722ba3bd0403fb03ed53..514869711c507f52a70603d41165b33dfb609efa 100644
--- a/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml
+++ b/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml
@@ -7,85 +7,56 @@ hdl_library_description: " This is the description for the finge_stop library "
peripherals:
- peripheral_name: fringe_stop
-
- parameters:
- - { name: g_nof_channels, value: 256 }
- - { name: g_fs_offset_w , value: 10 }
- - { name: g_fs_step_w , value: 17 }
-
- mm_ports:
- # actual hdl name: ram_fringe_stop_step
- - mm_port_name : STEP
- mm_port_type : RAM
- fields:
- - - field_name : fringe_stop_step
- width: g_fs_step_w
- number_of_fields: g_nof_channels
- field_description: |
- "Contains the step size for all nof_channels channels."
- mm_port_description: " "
-
- # actual hdl name: fringe_stop_offset
- - mm_port_name : STOP_OFFSET
- mm_port_type : RAM
- fields:
- - - field_name: fringe_stop_offset
- width: g_fs_offset_w
- number_of_fields: g_nof_channels
- field_description: |
- "Contains the offset for all nof_channels channels."
- mm_port_description: " "
-
peripheral_description: |
"The fringe stopping peripheral is based on piecewise linear coefficients. The coefficients are indicated as offset and step.
The offset and step are used to calculate an index that is used to select a certain phase from a look-up table. The look-up
table contains a series of complex values that are based on a sinewave. The length of the look-up table is determined by the
width of the offset RAM (offset_w). If offset_w = 10 then the length of the look-up table is 2^offset_w=1024. In that case
the look-up table contains 1024 complex values that make one sine-wave period.
-
+
The index is determined as follows:
-
+
index(t) = (offset + step*t) MOD 2^offset_w
-
+
Where t ranges from 0 to Tmax-1. Tmax is the number of samples that fit in the control interval (the sync interval).
The fringe stop peripheral is capable to process 1 or more channels in series (nof_channels).
-
+
Accumulation Register
The accumulation register that maintains the accumulated step value is flushed by the sync pulse in the system.
The accumulation register in the Apertif case is 31 bit wide. For the additon of the offset and the accumulated step the
10 (offset_w) highest bit of the accumulated value are used --> offset(9:0) + step_accumulated(30:21).
-
+
RAMs
The fringe stop interface is facilitated by two RAMs:
-
+
-RAM_FRINGE_STOP_OFFSET
-RAM_FRINGE_STOP_STEP
-
+
Both RAMs are implemented as dual-page RAMs.The page swap is triggered by the sync-pulse. The VHDL is always accessing
the page that is NOT accessible for the software and vice-versa. This means that the values that are written to the RAMs
will only be actually used in the following sync-interval:
-
-
- A| _ T0 _ T1 _ T2
+
+
+ A| _ T0 _ T1 _ T2
A| sync __| |___________________________| |___________________________| |________________________
- A| | VHDL uses data T0 | VHDL uses data T1 | VHDL uses data T2
+ A| | VHDL uses data T0 | VHDL uses data T1 | VHDL uses data T2
A| | Software writes data T1 | Software writes data T2 | Software writes data T3
- A| | | |
- A| page_swap page_swap page_swap
-
-
+ A| | | |
+ A| page_swap page_swap page_swap
+
+
The software should be sure to write the next set of data before the sync_interval expires. Keeping track of the
synchronization with the sync-pulse can be done, using one of the BSN Monitors in the system. In the Apertif system
the BSN Monitor at the input of the beamformer can be used.
-
+
The number_of_fields of both RAMs is determined by the number of unique channels that ought to be processed.
-
+
RAM_FRINGE_STOP_OFFSET
This RAM contains the offset values for all channels, ranging from Channel 0 to Channel Max-1. The width of the RAM is
defined by the offset_w.
-
+
+-----------------------------------------+
- | RAM_address | RAM_content |
+ | RAM_address | RAM_content |
|-----------------------------------------|
| 0x0 | Offset_Channel_0 |
| 0x1 | Offset_Channel_1 |
@@ -94,13 +65,13 @@ peripherals:
| .. | .. |
| .. | Offset_Channel_Max-1 |
+-----------------------------------------+
-
+
RAM_FRINGE_STOP_STEP
This RAM contains the step size values for all channels, ranging from Channel 0 to Channel Max-1. The width of the RAM is
specified by the step_w.
-
+
+-----------------------------------------+
- | RAM_address | RAM_content |
+ | RAM_address | RAM_content |
|-----------------------------------------|
| 0x0 | Step_Channel_0 |
| 0x1 | Step_Channel_1 |
@@ -109,4 +80,30 @@ peripherals:
| .. | .. |
| .. | Step_Channel_Max-1 |
+-----------------------------------------+"
-
+ parameters:
+ - { name: g_nof_channels, value: 256 }
+ - { name: g_fs_offset_w , value: 10 }
+ - { name: g_fs_step_w , value: 17 }
+ mm_ports:
+ # actual hdl name: ram_fringe_stop_step
+ - mm_port_name : STEP
+ mm_port_type : RAM
+ mm_port_description: " "
+ fields:
+ - - field_name : fringe_stop_step
+ field_description: |
+ "Contains the step size for all nof_channels channels."
+ mm_width: g_fs_step_w
+ number_of_fields: g_nof_channels
+
+ # actual hdl name: fringe_stop_offset
+ - mm_port_name : STOP_OFFSET
+ mm_port_type : RAM
+ mm_port_description: " "
+ fields:
+ - - field_name: fringe_stop_offset
+ field_description: |
+ "Contains the offset for all nof_channels channels."
+ number_of_fields: g_nof_channels
+ mm_width: g_fs_offset_w
+
diff --git a/libraries/dsp/si/si.peripheral.yaml b/libraries/dsp/si/si.peripheral.yaml
index 470bac8cdd0d81af50ff66cb9e581e19edb23db2..206534545d065f54e4b155f8ba1086225391e6c0 100644
--- a/libraries/dsp/si/si.peripheral.yaml
+++ b/libraries/dsp/si/si.peripheral.yaml
@@ -11,10 +11,10 @@ peripherals:
mm_ports:
# MM port for si_arr.vhd
- mm_port_name: REG_SI
- mm_port_description: "In the even Nyquist zones the sampled spectrum gets flipped in frequency. This flip can be compensated for by enabling spectral inversion (SI)."
mm_port_type: REG
+ mm_port_description: "In the even Nyquist zones the sampled spectrum gets flipped in frequency. This flip can be compensated for by enabling spectral inversion (SI)."
fields:
- - field_name: enable
field_description: "When 0 then pass on the array of input signals, when 1 then enable spectral inversion for all the input signals."
- width: 1
address_offset: 0x0
+ mm_width: 1
diff --git a/libraries/dsp/st/st.peripheral.yaml b/libraries/dsp/st/st.peripheral.yaml
index c7c9f0c1f8718215ec467035485555bc0c4dac51..13bbf592e2000dc1d0336ff519d3f8050e8cdef1 100644
--- a/libraries/dsp/st/st.peripheral.yaml
+++ b/libraries/dsp/st/st.peripheral.yaml
@@ -17,25 +17,27 @@ peripherals:
# Parameters of st_sst.vhd
- { name: g_nof_stat, value: 512 } # nof accumulators
- { name: g_xst_enable, value: False } # False for auto powers, True for cross powers
- - { name: g_stat_data_w, value: 64 } # statistics accumulator width in bits
- - { name: g_stat_data_sz, value: 2 } # statistics accumulator width in 32b MM words
+ - { name: g_stat_data_w, value: 64 } # statistics accumulator user_width in bits
+ - { name: g_stat_data_sz, value: 2 } # statistics accumulator user_width in 32b MM words
mm_ports:
# MM port for st_sst.vhd
- mm_port_name: RAM_ST_SST
+ mm_port_type: RAM
mm_port_description: |
"The statistics are calculated for blocks of g_nof_stat time multiplexed data streams.
There are g_nof_instances parallel time multiplexed data streams.
The statistic power values have g_stat_data_w bits. The memory format is:
. g_xst_enable = False, for real powers : (uint32 * g_stat_data_sz)st[g_nof_instances]_[g_nof_stat]
. g_xst_enable = True, for complex powers : (cuint32 * g_stat_data_sz)st[g_nof_instances]_[g_nof_stat]"
- mm_port_type: RAM
number_of_mm_ports: g_nof_instances
fields:
- - field_name: power
field_description: ""
- width: g_stat_data_w
- address_offset: 0x0
number_of_fields: g_nof_stat * g_stat_data_sz
+ address_offset: 0x0
+ mm_width: 32
+ user_width: g_stat_data_w
+ radix: uint64
- peripheral_name: st_sst_for_sdp # pi_st_sst.py
@@ -46,11 +48,12 @@ peripherals:
- { name: g_nof_instances, value: 6 }
# Parameters of st_sst.vhd, fixed in node_sdp_filterbank.vhd / sdp_pkg.vhd
- { name: g_nof_stat, value: 1024 } # nof accumulators: N_sub * Q_fft = 512 * 2 = 1024
- - { name: g_stat_data_w, value: 54 } # statistics accumulator width in bits: W_statistic = 64
- - { name: g_stat_data_sz, value: 2 } # statistics accumulator width in 32b MM words: W_statistic_sz = 2
+ - { name: g_stat_data_w, value: 54 } # statistics accumulator user_width in bits: W_statistic = 64
+ - { name: g_stat_data_sz, value: 2 } # statistics accumulator user_width in 32b MM words: W_statistic_sz = 2
mm_ports:
# MM port for st_sst.vhd
- mm_port_name: RAM_ST_SST
+ mm_port_type: RAM
mm_port_description: |
"The subband statistics per PN are stored in g_nof_instances = P_pfb = S_pn / Q_fft = 6 blocks of
N_sub * Q_fft = 512 * 2 = 1024 real values as:
@@ -58,15 +61,15 @@ peripherals:
(uint64)SST[g_nof_instances]_[g_nof_stat] = (uint64)SST[S_pn/Q_fft]_[N_sub][Q_fft]
where S_pn = 12, Q_fft = 2 and N_sub = 512 are defined in sdp_pkg.vhd."
- mm_port_type: RAM
number_of_mm_ports: g_nof_instances
fields:
- - field_name: power
field_description: ""
- width: 32
- address_offset: 0x0
number_of_fields: g_nof_stat * g_stat_data_sz
- radix_width: g_stat_data_w
+ address_offset: 0x0
+ mm_width: 32
+ user_width: g_stat_data_w
+ radix: uint64
- peripheral_name: st_bst_for_sdp # pi_st_bst.py
@@ -77,23 +80,24 @@ peripherals:
- { name: g_nof_instances, value: 6 }
# Parameters of st_sst.vhd, fixed in node_sdp_filterbank.vhd / sdp_pkg.vhd
- { name: g_nof_stat, value: 976 } # nof accumulators: S_sub_bf * N_pol_bf = 488 * 2 = 976
- - { name: g_stat_data_w, value: 54 } # statistics accumulator width in bits: W_statistic = 64
- - { name: g_stat_data_sz, value: 2 } # statistics accumulator width in 32b MM words: W_statistic_sz = 2
+ - { name: g_stat_data_w, value: 54 } # statistics accumulator user_width in bits: W_statistic = 64
+ - { name: g_stat_data_sz, value: 2 } # statistics accumulator user_width in 32b MM words: W_statistic_sz = 2
mm_ports:
# MM port for st_sst.vhd
- mm_port_name: RAM_ST_SST
+ mm_port_type: RAM
mm_port_description: |
"The beamlet statistics per PN are stored in 1 block of S_sub_bf * N_pol_bf = 488 * 2 = 976 real values as:
(uint64)BST[g_nof_stat] = (uint64)BST[S_sub_bf][N_pol_bf]
where N_pol_bf = 2 and S_sub_bf = 488 are defined in sdp_pkg.vhd."
- mm_port_type: RAM
number_of_mm_ports: 1
fields:
- - field_name: power
field_description: ""
- width: 32
- address_offset: 0x0
number_of_fields: g_nof_stat * g_stat_data_sz
- radix_width: g_stat_data_w
+ address_offset: 0x0
+ mm_width: 32
+ user_width: g_stat_data_w
+ radix: uint64
diff --git a/libraries/io/aduh/aduh.peripheral.yaml b/libraries/io/aduh/aduh.peripheral.yaml
index c364451f0f3de254af4406b59b016b9535923307..5f19809c1d61f2637f413ce97ce5adae7f62935b 100644
--- a/libraries/io/aduh/aduh.peripheral.yaml
+++ b/libraries/io/aduh/aduh.peripheral.yaml
@@ -20,20 +20,20 @@ peripherals:
fields:
- - field_name: mean_sum_lo
field_description: "Mean sum[31:0] of samples during a sync interval."
- access_mode: RO
address_offset: 0x0
+ access_mode: RO
- - field_name: mean_sum_hi
field_description: "Mean sum[63:32] of samples during a sync interval."
- access_mode: RO
address_offset: 0x4
+ access_mode: RO
- - field_name: power_sum_lo
field_description: "Power sum[31:0] of sample powers during a sync interval."
- access_mode: RO
address_offset: 0x8
+ access_mode: RO
- - field_name: power_sum_hi
field_description: "Power sum[63:32] of sample powers during a sync interval."
- access_mode: RO
address_offset: 0xC
+ access_mode: RO
- peripheral_name: aduh_mon_data_buffer # pi_aduh_monitor.py
peripheral_description: "Data buffer to capture samples (= diag_data_buffer)"
@@ -53,7 +53,7 @@ peripherals:
fields:
- - field_name: data
field_description: ""
- width: g_symbol_w * g_nof_symbols_per_data
- address_offset: 0x0
number_of_fields: g_buffer_nof_symbols / g_nof_symbols_per_data
+ address_offset: 0x0
+ mm_width: g_symbol_w * g_nof_symbols_per_data
diff --git a/libraries/io/epcs/epcs.peripheral.yaml b/libraries/io/epcs/epcs.peripheral.yaml
index 2026d2bdf28c1bf9ae67ec48f00edf13fb94b0f5..8a0d28ba86093e3888bb6eb6a4b30921ea844c32 100644
--- a/libraries/io/epcs/epcs.peripheral.yaml
+++ b/libraries/io/epcs/epcs.peripheral.yaml
@@ -27,45 +27,45 @@ peripherals:
fields:
- - field_name: addr
field_description: "Address to write to or read from."
- width: 24
- access_mode: WO
address_offset: 0x0
+ mm_width: 24
+ access_mode: WO
- - field_name: rden
field_description: "Read enable bit."
- width: 1
- access_mode: WO
address_offset: 0x4
+ mm_width: 1
+ access_mode: WO
- - field_name: read_bit
field_description: "Read bit."
- width: 1
+ address_offset: 0x8
+ mm_width: 1
access_mode: WO
side_effect: PW
- address_offset: 0x8
- - field_name: write_bit
field_description: "Write bit."
- width: 1
+ address_offset: 0xc
+ mm_width: 1
access_mode: WO
side_effect: PW
- address_offset: 0xc
- - field_name: sector_erase
field_description: "Sector erase bit."
- width: 1
- access_mode: WO
address_offset: 0x10
+ mm_width: 1
+ access_mode: WO
- - field_name: busy
field_description: "Busy bit."
- width: 1
- access_mode: RO
address_offset: 0x14
+ mm_width: 1
+ access_mode: RO
- - field_name: unprotect
field_description: "Use 0xBEDA221E (= Bedazzle) as password to unprotect address range."
- width: 32
- access_mode: WO
address_offset: 0x18
+ mm_width: 32
+ access_mode: WO
diff --git a/libraries/io/eth/eth.peripheral.yaml b/libraries/io/eth/eth.peripheral.yaml
index 5593e60c884be463d06bf6bce75c1443c9f71e7c..e98da05be1818690181856cb6e972b9b8c50b64d 100644
--- a/libraries/io/eth/eth.peripheral.yaml
+++ b/libraries/io/eth/eth.peripheral.yaml
@@ -22,9 +22,9 @@ peripherals:
fields:
- - field_name: status
field_description: ""
- access_mode: RO
- address_offset: 0x0
number_of_fields: 1024 # = c_tech_tse_byte_addr_w in tech_tse_pkg.vhd
+ address_offset: 0x0
+ access_mode: RO
# MM port for registers in eth_mm_registers.vhd in the ETH module [2]
- mm_port_name: AVS_ETH_0_REG
@@ -33,9 +33,9 @@ peripherals:
fields:
- - field_name: status
field_description: ""
- access_mode: RO
- address_offset: 0x0
number_of_fields: 12 # = c_eth_reg_nof_words in eth_pkg.vhd
+ address_offset: 0x0
+ access_mode: RO
# MM port for ETH packet packet buffers in eth.vhd
- mm_port_name: AVS_ETH_0_RAM
diff --git a/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml b/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml
index c70b59c3b9abca3930868c04f33f630373978632..05a3c22d5427bee0324743a72f9ea6294afe1dfa 100644
--- a/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml
+++ b/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml
@@ -31,120 +31,120 @@ peripherals:
mm_port_description: "MAC registers"
number_of_mm_ports: g_nof_macs
fields:
- - - {field_name: rx_transfer_control, width: 1, access_mode: RW, address_offset: 0x0000 } # = 0x0000
- - - {field_name: rx_transfer_status, width: 1, access_mode: RO, address_offset: 0x0004 } # = 0x0001
- - - {field_name: rx_padcrc_control, width: 2, access_mode: RW, address_offset: 0x0100 } # = 0x0040
- - - {field_name: rx_crccheck_control, width: 2, access_mode: RW, address_offset: 0x0200 } # = 0x0080
- - - {field_name: rx_pktovrflow_error, width: 32, access_mode: RO, address_offset: 0x0300, radix_width: 36 } # = 0x00C0
- - - {field_name: rx_pktovrflow_etherStatsDropEvents, width: 32, access_mode: RO, address_offset: 0x0308, radix_width: 36 } # = 0x00C2
- - - {field_name: rx_lane_decoder_preamble_control, width: 1, access_mode: RW, address_offset: 0x0400 } # = 0x0100
- - - {field_name: rx_preamble_inserter_control, width: 1, access_mode: RW, address_offset: 0x0500 } # = 0x0140
- - - {field_name: rx_frame_control, width: 20, access_mode: RW, address_offset: 0x2000 } # = 0x0800
- - - {field_name: rx_frame_maxlength, width: 16, access_mode: RW, address_offset: 0x2004 } # = 0x0801
- - - {field_name: rx_frame_addr0, width: 16, access_mode: RW, address_offset: 0x2008 } # = 0x0802
- - - {field_name: rx_frame_addr1, width: 16, access_mode: RW, address_offset: 0x200c } # = 0x0803
- - - {field_name: rx_frame_spaddr0_0, width: 16, access_mode: RW, address_offset: 0x2010 } # = 0x0804
- - - {field_name: rx_frame_spaddr0_1, width: 16, access_mode: RW, address_offset: 0x2014 } # = 0x0805
- - - {field_name: rx_frame_spaddr1_0, width: 16, access_mode: RW, address_offset: 0x2018 } # = 0x0806
- - - {field_name: rx_frame_spaddr1_1, width: 16, access_mode: RW, address_offset: 0x201c } # = 0x0807
- - - {field_name: rx_frame_spaddr2_0, width: 16, access_mode: RW, address_offset: 0x2020 } # = 0x0808
- - - {field_name: rx_frame_spaddr2_1, width: 16, access_mode: RW, address_offset: 0x2024 } # = 0x0809
- - - {field_name: rx_frame_spaddr3_0, width: 16, access_mode: RW, address_offset: 0x2028 } # = 0x080A
- - - {field_name: rx_frame_spaddr3_1, width: 16, access_mode: RW, address_offset: 0x202c } # = 0x080B
- - - {field_name: rx_pfc_control, width: 17, access_mode: RW, address_offset: 0x2060 } # = 0x0818
- - - {field_name: tx_transfer_control, width: 1, access_mode: RW, address_offset: 0x4000 } # = 0x1000
- - - {field_name: tx_transfer_status, width: 1, access_mode: RO, address_offset: 0x4004 } # = 0x1001
- - - {field_name: tx_padins_control, width: 1, access_mode: RW, address_offset: 0x4100 } # = 0x1040
- - - {field_name: tx_crcins_control, width: 2, access_mode: RW, address_offset: 0x4200 } # = 0x1080
- - - {field_name: tx_pktunderflow_error, width: 32, access_mode: RO, address_offset: 0x4300, radix_width: 36 } # = 0x10C0
- - - {field_name: tx_preamble_control, width: 1, access_mode: RW, address_offset: 0x4400 } # = 0x1100
- - - {field_name: tx_pauseframe_control, width: 2, access_mode: RW, address_offset: 0x4500 } # = 0x1140
- - - {field_name: tx_pauseframe_quanta, width: 16, access_mode: RW, address_offset: 0x4504 } # = 0x1141
- - - {field_name: tx_pauseframe_enable, width: 1, access_mode: RW, address_offset: 0x4508 } # = 0x1142
+ - - {field_name: rx_transfer_control, mm_width: 1, access_mode: RW, address_offset: 0x0000 } # = 0x0000
+ - - {field_name: rx_transfer_status, mm_width: 1, access_mode: RO, address_offset: 0x0004 } # = 0x0001
+ - - {field_name: rx_padcrc_control, mm_width: 2, access_mode: RW, address_offset: 0x0100 } # = 0x0040
+ - - {field_name: rx_crccheck_control, mm_width: 2, access_mode: RW, address_offset: 0x0200 } # = 0x0080
+ - - {field_name: rx_pktovrflow_error, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x0300 } # = 0x00C0
+ - - {field_name: rx_pktovrflow_etherStatsDropEvents, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x0308 } # = 0x00C2
+ - - {field_name: rx_lane_decoder_preamble_control, mm_width: 1, access_mode: RW, address_offset: 0x0400 } # = 0x0100
+ - - {field_name: rx_preamble_inserter_control, mm_width: 1, access_mode: RW, address_offset: 0x0500 } # = 0x0140
+ - - {field_name: rx_frame_control, mm_width: 20, access_mode: RW, address_offset: 0x2000 } # = 0x0800
+ - - {field_name: rx_frame_maxlength, mm_width: 16, access_mode: RW, address_offset: 0x2004 } # = 0x0801
+ - - {field_name: rx_frame_addr0, mm_width: 16, access_mode: RW, address_offset: 0x2008 } # = 0x0802
+ - - {field_name: rx_frame_addr1, mm_width: 16, access_mode: RW, address_offset: 0x200c } # = 0x0803
+ - - {field_name: rx_frame_spaddr0_0, mm_width: 16, access_mode: RW, address_offset: 0x2010 } # = 0x0804
+ - - {field_name: rx_frame_spaddr0_1, mm_width: 16, access_mode: RW, address_offset: 0x2014 } # = 0x0805
+ - - {field_name: rx_frame_spaddr1_0, mm_width: 16, access_mode: RW, address_offset: 0x2018 } # = 0x0806
+ - - {field_name: rx_frame_spaddr1_1, mm_width: 16, access_mode: RW, address_offset: 0x201c } # = 0x0807
+ - - {field_name: rx_frame_spaddr2_0, mm_width: 16, access_mode: RW, address_offset: 0x2020 } # = 0x0808
+ - - {field_name: rx_frame_spaddr2_1, mm_width: 16, access_mode: RW, address_offset: 0x2024 } # = 0x0809
+ - - {field_name: rx_frame_spaddr3_0, mm_width: 16, access_mode: RW, address_offset: 0x2028 } # = 0x080A
+ - - {field_name: rx_frame_spaddr3_1, mm_width: 16, access_mode: RW, address_offset: 0x202c } # = 0x080B
+ - - {field_name: rx_pfc_control, mm_width: 17, access_mode: RW, address_offset: 0x2060 } # = 0x0818
+ - - {field_name: tx_transfer_control, mm_width: 1, access_mode: RW, address_offset: 0x4000 } # = 0x1000
+ - - {field_name: tx_transfer_status, mm_width: 1, access_mode: RO, address_offset: 0x4004 } # = 0x1001
+ - - {field_name: tx_padins_control, mm_width: 1, access_mode: RW, address_offset: 0x4100 } # = 0x1040
+ - - {field_name: tx_crcins_control, mm_width: 2, access_mode: RW, address_offset: 0x4200 } # = 0x1080
+ - - {field_name: tx_pktunderflow_error, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x4300 } # = 0x10C0
+ - - {field_name: tx_preamble_control, mm_width: 1, access_mode: RW, address_offset: 0x4400 } # = 0x1100
+ - - {field_name: tx_pauseframe_control, mm_width: 2, access_mode: RW, address_offset: 0x4500 } # = 0x1140
+ - - {field_name: tx_pauseframe_quanta, mm_width: 16, access_mode: RW, address_offset: 0x4504 } # = 0x1141
+ - - {field_name: tx_pauseframe_enable, mm_width: 1, access_mode: RW, address_offset: 0x4508 } # = 0x1142
# Altera is unclear about the width of the quanta registers. Assuming 32 bits, where bits 16:31 are reserved:
- - - {field_name: pfc_pause_quanta_0, width: 32, access_mode: RW, address_offset: 0x4600 } # = 0x1180
- - - {field_name: pfc_pause_quanta_1, width: 32, access_mode: RW, address_offset: 0x4604 } # = 0x1181
- - - {field_name: pfc_pause_quanta_2, width: 32, access_mode: RW, address_offset: 0x4608 } # = 0x1182
- - - {field_name: pfc_pause_quanta_3, width: 32, access_mode: RW, address_offset: 0x460c } # = 0x1183
- - - {field_name: pfc_pause_quanta_4, width: 32, access_mode: RW, address_offset: 0x4610 } # = 0x1184
- - - {field_name: pfc_pause_quanta_5, width: 32, access_mode: RW, address_offset: 0x4614 } # = 0x1185
- - - {field_name: pfc_pause_quanta_6, width: 32, access_mode: RW, address_offset: 0x4618 } # = 0x1186
- - - {field_name: pfc_pause_quanta_7, width: 32, access_mode: RW, address_offset: 0x461c } # = 0x1187
- - - {field_name: pfc_holdoff_quanta_0, width: 32, access_mode: RW, address_offset: 0x4640 } # = 0x1190
- - - {field_name: pfc_holdoff_quanta_1, width: 32, access_mode: RW, address_offset: 0x4644 } # = 0x1191
- - - {field_name: pfc_holdoff_quanta_2, width: 32, access_mode: RW, address_offset: 0x4648 } # = 0x1192
- - - {field_name: pfc_holdoff_quanta_3, width: 32, access_mode: RW, address_offset: 0x464c } # = 0x1193
- - - {field_name: pfc_holdoff_quanta_4, width: 32, access_mode: RW, address_offset: 0x4650 } # = 0x1194
- - - {field_name: pfc_holdoff_quanta_5, width: 32, access_mode: RW, address_offset: 0x4654 } # = 0x1195
- - - {field_name: pfc_holdoff_quanta_6, width: 32, access_mode: RW, address_offset: 0x4658 } # = 0x1196
- - - {field_name: pfc_holdoff_quanta_7, width: 32, access_mode: RW, address_offset: 0x465c } # = 0x1197
- - - {field_name: tx_pfc_priority_enable, width: 8, access_mode: RW, address_offset: 0x4680 } # = 0x11A0
- - - {field_name: tx_addrins_control, width: 1, access_mode: RW, address_offset: 0x4800 } # = 0x1200
- - - {field_name: tx_addrins_macaddr0, width: 32, access_mode: RW, address_offset: 0x4804 } # = 0x1201
- - - {field_name: tx_addrins_macaddr1, width: 16, access_mode: RW, address_offset: 0x4808 } # = 0x1202
- - - {field_name: tx_frame_maxlength, width: 16, access_mode: RW, address_offset: 0x6004 } # = 0x1801
- - - {field_name: rx_stats_clr, width: 1, access_mode: RW, address_offset: 0x3000 } # = 0x0C00
- - - {field_name: tx_stats_clr, width: 1, access_mode: RW, address_offset: 0x7000 } # = 0x1C00
- - - {field_name: rx_stats_framesOK, width: 32, access_mode: RO, address_offset: 0x3008, radix_width: 36 } # = 0x0C02
- - - {field_name: tx_stats_framesOK, width: 32, access_mode: RO, address_offset: 0x7008, radix_width: 36 } # = 0x1C02
- - - {field_name: rx_stats_framesErr, width: 32, access_mode: RO, address_offset: 0x3010, radix_width: 36 } # = 0x0C04
- - - {field_name: tx_stats_framesErr, width: 32, access_mode: RO, address_offset: 0x7010, radix_width: 36 } # = 0x1C04
- - - {field_name: rx_stats_framesCRCErr, width: 32, access_mode: RO, address_offset: 0x3018, radix_width: 36 } # = 0x0C06
- - - {field_name: tx_stats_framesCRCErr, width: 32, access_mode: RO, address_offset: 0x7018, radix_width: 36 } # = 0x1C06
- - - {field_name: rx_stats_octetsOK, width: 32, access_mode: RO, address_offset: 0x3020, radix_width: 36 } # = 0x0C08
- - - {field_name: tx_stats_octetsOK, width: 32, access_mode: RO, address_offset: 0x7020, radix_width: 36 } # = 0x1C08
- - - {field_name: rx_stats_pauseMACCtrl_Frames, width: 32, access_mode: RO, address_offset: 0x3028, radix_width: 36 } # = 0x0C0A
- - - {field_name: tx_stats_pauseMACCtrl_Frames, width: 32, access_mode: RO, address_offset: 0x7028, radix_width: 36 } # = 0x1C0A
- - - {field_name: rx_stats_ifErrors, width: 32, access_mode: RO, address_offset: 0x3030, radix_width: 36 } # = 0x0C0C
- - - {field_name: tx_stats_ifErrors, width: 32, access_mode: RO, address_offset: 0x7030, radix_width: 36 } # = 0x1C0C
- - - {field_name: rx_stats_unicast_FramesOK, width: 32, access_mode: RO, address_offset: 0x3038, radix_width: 36 } # = 0x0C0E
- - - {field_name: tx_stats_unicast_FramesOK, width: 32, access_mode: RO, address_offset: 0x7038, radix_width: 36 } # = 0x1C0E
- - - {field_name: rx_stats_unicast_FramesErr, width: 32, access_mode: RO, address_offset: 0x3040, radix_width: 36 } # = 0x0C10
- - - {field_name: tx_stats_unicast_FramesErr, width: 32, access_mode: RO, address_offset: 0x7040, radix_width: 36 } # = 0x1C10
- - - {field_name: rx_stats_multicastFramesOK, width: 32, access_mode: RO, address_offset: 0x3048, radix_width: 36 } # = 0x0C12
- - - {field_name: tx_stats_multicastFramesOK, width: 32, access_mode: RO, address_offset: 0x7048, radix_width: 36 } # = 0x1C12
- - - {field_name: rx_stats_multicast_FramesErr, width: 32, access_mode: RO, address_offset: 0x3050, radix_width: 36 } # = 0x0C14
- - - {field_name: tx_stats_multicast_FramesErr, width: 32, access_mode: RO, address_offset: 0x7050, radix_width: 36 } # = 0x1C14
- - - {field_name: rx_stats_broadcastFramesOK, width: 32, access_mode: RO, address_offset: 0x3058, radix_width: 36 } # = 0x0C16
- - - {field_name: tx_stats_broadcastFramesOK, width: 32, access_mode: RO, address_offset: 0x7058, radix_width: 36 } # = 0x1C16
- - - {field_name: rx_stats_broadcast_FramesErr, width: 32, access_mode: RO, address_offset: 0x3060, radix_width: 36 } # = 0x0C18
- - - {field_name: tx_stats_broadcast_FramesErr, width: 32, access_mode: RO, address_offset: 0x7060, radix_width: 36 } # = 0x1C18
- - - {field_name: rx_stats_etherStatsOctets, width: 32, access_mode: RO, address_offset: 0x3068, radix_width: 36 } # = 0x0C1A
- - - {field_name: tx_stats_etherStatsOctets, width: 32, access_mode: RO, address_offset: 0x7068, radix_width: 36 } # = 0x1C1A
- - - {field_name: rx_stats_etherStatsPkts, width: 32, access_mode: RO, address_offset: 0x3070, radix_width: 36 } # = 0x0C1C
- - - {field_name: tx_stats_etherStatsPkts, width: 32, access_mode: RO, address_offset: 0x7070, radix_width: 36 } # = 0x1C1C
- - - {field_name: rx_stats_etherStats_UndersizePkts, width: 32, access_mode: RO, address_offset: 0x3078, radix_width: 36 } # = 0x0C1E
- - - {field_name: tx_stats_etherStats_UndersizePkts, width: 32, access_mode: RO, address_offset: 0x7078, radix_width: 36 } # = 0x1C1E
- - - {field_name: rx_stats_etherStats_OversizePkts, width: 32, access_mode: RO, address_offset: 0x3080, radix_width: 36 } # = 0x0C20
- - - {field_name: tx_stats_etherStats_OversizePkts, width: 32, access_mode: RO, address_offset: 0x7080, radix_width: 36 } # = 0x1C20
- - - {field_name: rx_stats_etherStats_Pkts64Octets, width: 32, access_mode: RO, address_offset: 0x3088, radix_width: 36 } # = 0x0C22
- - - {field_name: tx_stats_etherStats_Pkts64Octets, width: 32, access_mode: RO, address_offset: 0x7088, radix_width: 36 } # = 0x1C22
- - - {field_name: rx_stats_etherStats_Pkts65to127Octets, width: 32, access_mode: RO, address_offset: 0x3090, radix_width: 36 } # = 0x0C24
- - - {field_name: tx_stats_etherStats_Pkts65to127Octets, width: 32, access_mode: RO, address_offset: 0x7090, radix_width: 36 } # = 0x1C24
- - - {field_name: rx_stats_etherStats_Pkts128to255Octets, width: 32, access_mode: RO, address_offset: 0x3098, radix_width: 36 } # = 0x0C26
- - - {field_name: tx_stats_etherStats_Pkts128to255Octets, width: 32, access_mode: RO, address_offset: 0x7098, radix_width: 36 } # = 0x1C26
- - - {field_name: rx_stats_etherStats_Pkts256to511Octets, width: 32, access_mode: RO, address_offset: 0x30a0, radix_width: 36 } # = 0x0C28
- - - {field_name: tx_stats_etherStats_Pkts256to511Octets, width: 32, access_mode: RO, address_offset: 0x70a0, radix_width: 36 } # = 0x1C28
- - - {field_name: rx_stats_etherStats_Pkts512to1023Octets, width: 32, access_mode: RO, address_offset: 0x30a8, radix_width: 36 } # = 0x0C2A
- - - {field_name: tx_stats_etherStats_Pkts512to1023Octets, width: 32, access_mode: RO, address_offset: 0x70a8, radix_width: 36 } # = 0x1C2A
- - - {field_name: rx_stats_etherStat_Pkts1024to1518Octets, width: 32, access_mode: RO, address_offset: 0x30b0, radix_width: 36 } # = 0x0C2C
- - - {field_name: tx_stats_etherStat_Pkts1024to1518Octets, width: 32, access_mode: RO, address_offset: 0x70b0, radix_width: 36 } # = 0x1C2C
- - - {field_name: rx_stats_etherStats_Pkts1519toXOctets, width: 32, access_mode: RO, address_offset: 0x30b8, radix_width: 36 } # = 0x0C2E
- - - {field_name: tx_stats_etherStats_Pkts1519toXOctets, width: 32, access_mode: RO, address_offset: 0x70b8, radix_width: 36 } # = 0x1C2E
- - - {field_name: rx_stats_etherStats_Fragments, width: 32, access_mode: RO, address_offset: 0x30c0, radix_width: 36 } # = 0x0C30
- - - {field_name: tx_stats_etherStats_Fragments, width: 32, access_mode: RO, address_offset: 0x70c0, radix_width: 36 } # = 0x1C30
- - - {field_name: rx_stats_etherStats_Jabbers, width: 32, access_mode: RO, address_offset: 0x30c8, radix_width: 36 } # = 0x0C32
- - - {field_name: tx_stats_etherStats_Jabbers, width: 32, access_mode: RO, address_offset: 0x70c8, radix_width: 36 } # = 0x1C32
- - - {field_name: rx_stats_etherStatsCRCErr, width: 32, access_mode: RO, address_offset: 0x30d0, radix_width: 36 } # = 0x0C34
- - - {field_name: tx_stats_etherStatsCRCErr, width: 32, access_mode: RO, address_offset: 0x70d0, radix_width: 36 } # = 0x1C34
- - - {field_name: rx_stats_unicastMACCtrlFrames, width: 32, access_mode: RO, address_offset: 0x30d8, radix_width: 36 } # = 0x0C36
- - - {field_name: tx_stats_unicastMACCtrlFrames, width: 32, access_mode: RO, address_offset: 0x70d8, radix_width: 36 } # = 0x1C36
- - - {field_name: rx_stats_multicastMAC_CtrlFrames, width: 32, access_mode: RO, address_offset: 0x30e0, radix_width: 36 } # = 0x0C38
- - - {field_name: tx_stats_multicastMAC_CtrlFrames, width: 32, access_mode: RO, address_offset: 0x70e0, radix_width: 36 } # = 0x1C38
- - - {field_name: rx_stats_broadcastMAC_CtrlFrames, width: 32, access_mode: RO, address_offset: 0x30e8, radix_width: 36 } # = 0x0C3A
- - - {field_name: tx_stats_broadcastMAC_CtrlFrames, width: 32, access_mode: RO, address_offset: 0x70e8, radix_width: 36 } # = 0x1C3A
- - - {field_name: rx_stats_PFCMACCtrlFrames, width: 32, access_mode: RO, address_offset: 0x30f0, radix_width: 36 } # = 0x0C3C
- - - {field_name: tx_stats_PFCMACCtrlFrames, width: 32, access_mode: RO, address_offset: 0x70f0, radix_width: 36 } # = 0x1C3C
+ - - {field_name: pfc_pause_quanta_0, mm_width: 32, access_mode: RW, address_offset: 0x4600 } # = 0x1180
+ - - {field_name: pfc_pause_quanta_1, mm_width: 32, access_mode: RW, address_offset: 0x4604 } # = 0x1181
+ - - {field_name: pfc_pause_quanta_2, mm_width: 32, access_mode: RW, address_offset: 0x4608 } # = 0x1182
+ - - {field_name: pfc_pause_quanta_3, mm_width: 32, access_mode: RW, address_offset: 0x460c } # = 0x1183
+ - - {field_name: pfc_pause_quanta_4, mm_width: 32, access_mode: RW, address_offset: 0x4610 } # = 0x1184
+ - - {field_name: pfc_pause_quanta_5, mm_width: 32, access_mode: RW, address_offset: 0x4614 } # = 0x1185
+ - - {field_name: pfc_pause_quanta_6, mm_width: 32, access_mode: RW, address_offset: 0x4618 } # = 0x1186
+ - - {field_name: pfc_pause_quanta_7, mm_width: 32, access_mode: RW, address_offset: 0x461c } # = 0x1187
+ - - {field_name: pfc_holdoff_quanta_0, mm_width: 32, access_mode: RW, address_offset: 0x4640 } # = 0x1190
+ - - {field_name: pfc_holdoff_quanta_1, mm_width: 32, access_mode: RW, address_offset: 0x4644 } # = 0x1191
+ - - {field_name: pfc_holdoff_quanta_2, mm_width: 32, access_mode: RW, address_offset: 0x4648 } # = 0x1192
+ - - {field_name: pfc_holdoff_quanta_3, mm_width: 32, access_mode: RW, address_offset: 0x464c } # = 0x1193
+ - - {field_name: pfc_holdoff_quanta_4, mm_width: 32, access_mode: RW, address_offset: 0x4650 } # = 0x1194
+ - - {field_name: pfc_holdoff_quanta_5, mm_width: 32, access_mode: RW, address_offset: 0x4654 } # = 0x1195
+ - - {field_name: pfc_holdoff_quanta_6, mm_width: 32, access_mode: RW, address_offset: 0x4658 } # = 0x1196
+ - - {field_name: pfc_holdoff_quanta_7, mm_width: 32, access_mode: RW, address_offset: 0x465c } # = 0x1197
+ - - {field_name: tx_pfc_priority_enable, mm_width: 8, access_mode: RW, address_offset: 0x4680 } # = 0x11A0
+ - - {field_name: tx_addrins_control, mm_width: 1, access_mode: RW, address_offset: 0x4800 } # = 0x1200
+ - - {field_name: tx_addrins_macaddr0, mm_width: 32, access_mode: RW, address_offset: 0x4804 } # = 0x1201
+ - - {field_name: tx_addrins_macaddr1, mm_width: 16, access_mode: RW, address_offset: 0x4808 } # = 0x1202
+ - - {field_name: tx_frame_maxlength, mm_width: 16, access_mode: RW, address_offset: 0x6004 } # = 0x1801
+ - - {field_name: rx_stats_clr, mm_width: 1, access_mode: RW, address_offset: 0x3000 } # = 0x0C00
+ - - {field_name: tx_stats_clr, mm_width: 1, access_mode: RW, address_offset: 0x7000 } # = 0x1C00
+ - - {field_name: rx_stats_framesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3008 } # = 0x0C02
+ - - {field_name: tx_stats_framesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7008 } # = 0x1C02
+ - - {field_name: rx_stats_framesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3010 } # = 0x0C04
+ - - {field_name: tx_stats_framesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7010 } # = 0x1C04
+ - - {field_name: rx_stats_framesCRCErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3018 } # = 0x0C06
+ - - {field_name: tx_stats_framesCRCErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7018 } # = 0x1C06
+ - - {field_name: rx_stats_octetsOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3020 } # = 0x0C08
+ - - {field_name: tx_stats_octetsOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7020 } # = 0x1C08
+ - - {field_name: rx_stats_pauseMACCtrl_Frames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3028 } # = 0x0C0A
+ - - {field_name: tx_stats_pauseMACCtrl_Frames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7028 } # = 0x1C0A
+ - - {field_name: rx_stats_ifErrors, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3030 } # = 0x0C0C
+ - - {field_name: tx_stats_ifErrors, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7030 } # = 0x1C0C
+ - - {field_name: rx_stats_unicast_FramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3038 } # = 0x0C0E
+ - - {field_name: tx_stats_unicast_FramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7038 } # = 0x1C0E
+ - - {field_name: rx_stats_unicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3040 } # = 0x0C10
+ - - {field_name: tx_stats_unicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7040 } # = 0x1C10
+ - - {field_name: rx_stats_multicastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3048 } # = 0x0C12
+ - - {field_name: tx_stats_multicastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7048 } # = 0x1C12
+ - - {field_name: rx_stats_multicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3050 } # = 0x0C14
+ - - {field_name: tx_stats_multicast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7050 } # = 0x1C14
+ - - {field_name: rx_stats_broadcastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3058 } # = 0x0C16
+ - - {field_name: tx_stats_broadcastFramesOK, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7058 } # = 0x1C16
+ - - {field_name: rx_stats_broadcast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3060 } # = 0x0C18
+ - - {field_name: tx_stats_broadcast_FramesErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7060 } # = 0x1C18
+ - - {field_name: rx_stats_etherStatsOctets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3068 } # = 0x0C1A
+ - - {field_name: tx_stats_etherStatsOctets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7068 } # = 0x1C1A
+ - - {field_name: rx_stats_etherStatsPkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3070 } # = 0x0C1C
+ - - {field_name: tx_stats_etherStatsPkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7070 } # = 0x1C1C
+ - - {field_name: rx_stats_etherStats_UndersizePkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3078 } # = 0x0C1E
+ - - {field_name: tx_stats_etherStats_UndersizePkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7078 } # = 0x1C1E
+ - - {field_name: rx_stats_etherStats_OversizePkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3080 } # = 0x0C20
+ - - {field_name: tx_stats_etherStats_OversizePkts, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7080 } # = 0x1C20
+ - - {field_name: rx_stats_etherStats_Pkts64Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3088 } # = 0x0C22
+ - - {field_name: tx_stats_etherStats_Pkts64Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7088 } # = 0x1C22
+ - - {field_name: rx_stats_etherStats_Pkts65to127Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3090 } # = 0x0C24
+ - - {field_name: tx_stats_etherStats_Pkts65to127Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7090 } # = 0x1C24
+ - - {field_name: rx_stats_etherStats_Pkts128to255Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x3098 } # = 0x0C26
+ - - {field_name: tx_stats_etherStats_Pkts128to255Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x7098 } # = 0x1C26
+ - - {field_name: rx_stats_etherStats_Pkts256to511Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30a0 } # = 0x0C28
+ - - {field_name: tx_stats_etherStats_Pkts256to511Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70a0 } # = 0x1C28
+ - - {field_name: rx_stats_etherStats_Pkts512to1023Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30a8 } # = 0x0C2A
+ - - {field_name: tx_stats_etherStats_Pkts512to1023Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70a8 } # = 0x1C2A
+ - - {field_name: rx_stats_etherStat_Pkts1024to1518Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30b0 } # = 0x0C2C
+ - - {field_name: tx_stats_etherStat_Pkts1024to1518Octets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70b0 } # = 0x1C2C
+ - - {field_name: rx_stats_etherStats_Pkts1519toXOctets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30b8 } # = 0x0C2E
+ - - {field_name: tx_stats_etherStats_Pkts1519toXOctets, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70b8 } # = 0x1C2E
+ - - {field_name: rx_stats_etherStats_Fragments, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30c0 } # = 0x0C30
+ - - {field_name: tx_stats_etherStats_Fragments, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70c0 } # = 0x1C30
+ - - {field_name: rx_stats_etherStats_Jabbers, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30c8 } # = 0x0C32
+ - - {field_name: tx_stats_etherStats_Jabbers, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70c8 } # = 0x1C32
+ - - {field_name: rx_stats_etherStatsCRCErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30d0 } # = 0x0C34
+ - - {field_name: tx_stats_etherStatsCRCErr, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70d0 } # = 0x1C34
+ - - {field_name: rx_stats_unicastMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30d8 } # = 0x0C36
+ - - {field_name: tx_stats_unicastMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70d8 } # = 0x1C36
+ - - {field_name: rx_stats_multicastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30e0 } # = 0x0C38
+ - - {field_name: tx_stats_multicastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70e0 } # = 0x1C38
+ - - {field_name: rx_stats_broadcastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30e8 } # = 0x0C3A
+ - - {field_name: tx_stats_broadcastMAC_CtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70e8 } # = 0x1C3A
+ - - {field_name: rx_stats_PFCMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x30f0 } # = 0x0C3C
+ - - {field_name: tx_stats_PFCMACCtrlFrames, mm_width: 32, user_width: 36, user_word_order: be, radix: uint64, access_mode: RO, address_offset: 0x70f0 } # = 0x1C3C
- peripheral_name: nw_10GbE_eth10g # pi_nw_10GbE_eth10g.py / pi_10GbE.py
@@ -161,19 +161,19 @@ peripherals:
fields:
- - field_name: tx_snk_out_xon
field_description: ""
- width: 1
+ address_offset: 0x0
+ mm_width: 1
bit_offset: 0
access_mode: RO
- address_offset: 0x0
- - field_name: xgmii_tx_ready
field_description: ""
- width: 1
+ address_offset: 0x0
+ mm_width: 1
bit_offset: 1
access_mode: RO
- address_offset: 0x0
- - field_name: xgmii_link_status
field_description: ""
- width: 2
+ address_offset: 0x0
+ mm_width: 2
bit_offset: 2
access_mode: RO
- address_offset: 0x0
diff --git a/libraries/io/ppsh/ppsh.peripheral.yaml b/libraries/io/ppsh/ppsh.peripheral.yaml
index e732647b7504398f8be33e9bb3c96763b2d1396b..4de7dd4254b41f1aa02e2f00609864b434c7277b 100644
--- a/libraries/io/ppsh/ppsh.peripheral.yaml
+++ b/libraries/io/ppsh/ppsh.peripheral.yaml
@@ -27,42 +27,41 @@ peripherals:
fields:
- - field_name: capture_cnt
field_description: "Measured number of clock cycles between captured PPS pulses."
- width: 30
+ address_offset: 0x0
+ mm_width: 30
bit_offset: 0
access_mode: RO
- address_offset: 0x0
- - field_name: stable
field_description: "PPS is stable (1) when capture_cnt = expected_cnt for all PPS periods since last time status was read, else PPS is not stable (0)."
- width: 1
+ address_offset: 0x0
+ mm_width: 1
bit_offset: 30
access_mode: RO
- address_offset: 0x0
- - field_name: toggle
field_description: "Level bit that toggles after every PPS."
- width: 1
+ address_offset: 0x0
+ mm_width: 1
bit_offset: 31
access_mode: RO
- address_offset: 0x0
- - field_name: expected_cnt
field_description: "Expected number of clock cycles between captured PPS pulses."
- width: ceil_log2(g_st_clk_freq)
+ address_offset: 0x4
+ mm_width: ceil_log2(g_st_clk_freq)
bit_offset: 0
access_mode: RW
- address_offset: 0x4
- - field_name: edge
field_description: "When 0 then clock PPS in on rising edge of clock, else when 1 use falling edge of clock."
- width: 1
+ address_offset: 0x4
+ mm_width: 1
bit_offset: 31
access_mode: RW
- address_offset: 0x4
- - field_name: offset_cnt
field_description: "Number of clock cycles at read access, that has passed since last PPS."
address_offset: 0x8
- width: ceil_log2(g_st_clk_freq)
+ mm_width: ceil_log2(g_st_clk_freq)
access_mode: RO
-
diff --git a/libraries/io/remu/remu.peripheral.yaml b/libraries/io/remu/remu.peripheral.yaml
index eb13be5b392fb259f245e132111fe583b06b5837..48608f72751dc1405b74e25861cfdb9b5659b78f 100644
--- a/libraries/io/remu/remu.peripheral.yaml
+++ b/libraries/io/remu/remu.peripheral.yaml
@@ -24,45 +24,44 @@ peripherals:
fields:
- - field_name: reconfigure
field_description: "Use 0xB007FAC7 (= boot factory) as password to reconfigure."
- width: c_word_w
- access_mode: WO
address_offset: 0x0
+ mm_width: c_word_w
+ access_mode: WO
- - field_name: param
field_description: "param"
- width: 3
- access_mode: WO
address_offset: 0x4
+ mm_width: 3
+ access_mode: WO
- - field_name: read_param
field_description: "read_param"
- width: 1
+ address_offset: 0x8
+ mm_width: 1
access_mode: WO
side_effect: PW
- address_offset: 0x8
- - field_name: write_param
field_description: "write_param"
- width: 1
+ address_offset: 0xc
+ mm_width: 1
access_mode: WO
side_effect: PW
- address_offset: 0xc
- - field_name: data_out
field_description: "data_out"
- width: g_data_w
- access_mode: RO
address_offset: 0x10
+ mm_width: g_data_w
+ access_mode: RO
- - field_name: data_in
field_description: "data_in"
- width: g_data_w
- access_mode: WO
address_offset: 0x14
+ mm_width: g_data_w
+ access_mode: WO
- - field_name: busy
field_description: "busy"
- width: 1
- access_mode: RO
address_offset: 0x18
-
+ mm_width: 1
+ access_mode: RO
diff --git a/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml b/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml
index 4c748e535c27266b3077edf9f05275364aedd2d1..7fe5b2d604102e508778a46ad52f5545bb7ffa41 100644
--- a/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml
+++ b/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml
@@ -16,16 +16,16 @@ peripherals:
fields:
- - field_name: reset
field_description: "Write 1 to reset the full JESD interface for all JESD signal inputs."
- width: 1
+ address_offset: 0x0
bit_offset: 31
+ mm_width: 1
access_mode: RW
- address_offset: 0x0
- - field_name: enable
field_description: "Enable JESD signal input i by setting bit i = 1, disable by clearing bit i = 0."
- width: 31
+ address_offset: 0x0
bit_offset: 0
+ mm_width: 31
access_mode: RW
- address_offset: 0x0
- peripheral_name: jesd204b_arria10 # pi_jesd204b_unb2.py
peripheral_description: |
@@ -36,31 +36,31 @@ peripherals:
mm_port_type: REG
mm_port_description: ""
fields:
- - - {field_name: rx_dll_ctrl, width: 17, bit_offset: 0, access_mode: RW, address_offset: 0x50}
- - - {field_name: rx_syncn_sysref_ctrl, width: 25, bit_offset: 0, access_mode: RW, address_offset: 0x54}
- - - {field_name: rx_csr_lmfc_offset, width: 8, bit_offset: 12, access_mode: RW, address_offset: 0x54}
- - - {field_name: rx_csr_rbd_offset, width: 8, bit_offset: 3, access_mode: RW, address_offset: 0x54}
- - - {field_name: rx_csr_sysref_always_on, width: 1, bit_offset: 1, access_mode: RW, address_offset: 0x54}
- - - {field_name: rx_err0, width: 9, bit_offset: 0, access_mode: RW, address_offset: 0x60}
- - - {field_name: rx_err1, width: 10, bit_offset: 0, access_mode: RW, address_offset: 0x64}
- - - {field_name: csr_rbd_count, width: 8, bit_offset: 3, access_mode: RO, address_offset: 0x80}
- - - {field_name: csr_dev_syncn, width: 1, bit_offset: 0, access_mode: RO, address_offset: 0x80}
- - - {field_name: rx_status1, width: 24, bit_offset: 0, access_mode: RW, address_offset: 0x84}
- - - {field_name: rx_status2, width: 24, bit_offset: 0, access_mode: RW, address_offset: 0x88}
- - - {field_name: rx_status3, width: 8, bit_offset: 0, access_mode: RW, address_offset: 0x8C}
- - - {field_name: rx_ilas_csr_m, width: 8, bit_offset: 24, access_mode: RW, address_offset: 0x94}
- - - {field_name: rx_ilas_csr_k, width: 5, bit_offset: 16, access_mode: RW, address_offset: 0x94}
- - - {field_name: rx_ilas_csr_f, width: 8, bit_offset: 8, access_mode: RW, address_offset: 0x94}
- - - {field_name: rx_ilas_csr_l, width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x94}
- - - {field_name: rx_ilas_csr_hd, width: 1, bit_offset: 31, access_mode: RW, address_offset: 0x98}
- - - {field_name: rx_ilas_csr_cf, width: 5, bit_offset: 24, access_mode: RW, address_offset: 0x98}
- - - {field_name: rx_ilas_csr_jesdv, width: 3, bit_offset: 21, access_mode: RW, address_offset: 0x98}
- - - {field_name: rx_ilas_csr_s, width: 5, bit_offset: 16, access_mode: RW, address_offset: 0x98}
- - - {field_name: rx_ilas_csr_subclassv, width: 3, bit_offset: 13, access_mode: RW, address_offset: 0x98}
- - - {field_name: rx_ilas_csr_np, width: 5, bit_offset: 8, access_mode: RW, address_offset: 0x98}
- - - {field_name: rx_ilas_csr_cs, width: 2, bit_offset: 6, access_mode: RW, address_offset: 0x98}
- - - {field_name: rx_ilas_csr_n, width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x98}
- - - {field_name: rx_status4, width: 16, bit_offset: 0, access_mode: RW, address_offset: 0xF0}
- - - {field_name: rx_status5, width: 16, bit_offset: 0, access_mode: RW, address_offset: 0xF4}
- - - {field_name: rx_status6, width: 24, bit_offset: 0, access_mode: RW, address_offset: 0xF8}
- - - {field_name: rx_status7, width: 32, bit_offset: 0, access_mode: RO, address_offset: 0xFC}
+ - - {field_name: rx_dll_ctrl, mm_width: 17, bit_offset: 0, access_mode: RW, address_offset: 0x50}
+ - - {field_name: rx_syncn_sysref_ctrl, mm_width: 25, bit_offset: 0, access_mode: RW, address_offset: 0x54}
+ - - {field_name: rx_csr_lmfc_offset, mm_width: 8, bit_offset: 12, access_mode: RW, address_offset: 0x54}
+ - - {field_name: rx_csr_rbd_offset, mm_width: 8, bit_offset: 3, access_mode: RW, address_offset: 0x54}
+ - - {field_name: rx_csr_sysref_always_on, mm_width: 1, bit_offset: 1, access_mode: RW, address_offset: 0x54}
+ - - {field_name: rx_err0, mm_width: 9, bit_offset: 0, access_mode: RW, address_offset: 0x60}
+ - - {field_name: rx_err1, mm_width: 10, bit_offset: 0, access_mode: RW, address_offset: 0x64}
+ - - {field_name: csr_rbd_count, mm_width: 8, bit_offset: 3, access_mode: RO, address_offset: 0x80}
+ - - {field_name: csr_dev_syncn, mm_width: 1, bit_offset: 0, access_mode: RO, address_offset: 0x80}
+ - - {field_name: rx_status1, mm_width: 24, bit_offset: 0, access_mode: RW, address_offset: 0x84}
+ - - {field_name: rx_status2, mm_width: 24, bit_offset: 0, access_mode: RW, address_offset: 0x88}
+ - - {field_name: rx_status3, mm_width: 8, bit_offset: 0, access_mode: RW, address_offset: 0x8C}
+ - - {field_name: rx_ilas_csr_m, mm_width: 8, bit_offset: 24, access_mode: RW, address_offset: 0x94}
+ - - {field_name: rx_ilas_csr_k, mm_width: 5, bit_offset: 16, access_mode: RW, address_offset: 0x94}
+ - - {field_name: rx_ilas_csr_f, mm_width: 8, bit_offset: 8, access_mode: RW, address_offset: 0x94}
+ - - {field_name: rx_ilas_csr_l, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x94}
+ - - {field_name: rx_ilas_csr_hd, mm_width: 1, bit_offset: 31, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_cf, mm_width: 5, bit_offset: 24, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_jesdv, mm_width: 3, bit_offset: 21, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_s, mm_width: 5, bit_offset: 16, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_subclassv, mm_width: 3, bit_offset: 13, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_np, mm_width: 5, bit_offset: 8, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_cs, mm_width: 2, bit_offset: 6, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_ilas_csr_n, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x98}
+ - - {field_name: rx_status4, mm_width: 16, bit_offset: 0, access_mode: RW, address_offset: 0xF0}
+ - - {field_name: rx_status5, mm_width: 16, bit_offset: 0, access_mode: RW, address_offset: 0xF4}
+ - - {field_name: rx_status6, mm_width: 24, bit_offset: 0, access_mode: RW, address_offset: 0xF8}
+ - - {field_name: rx_status7, mm_width: 32, bit_offset: 0, access_mode: RO, address_offset: 0xFC}