diff --git a/doc/erko_hdl_design_article.txt b/doc/erko_hdl_design_article.txt
index bd1a76b1206da56a341a15b54e638a32f13c7fd7..f33018fb8cf93b0123681154e039cd08b261fa8f 100644
--- a/doc/erko_hdl_design_article.txt
+++ b/doc/erko_hdl_design_article.txt
@@ -1,3 +1,15 @@
+
+
+Synchronous logic RTL
+Asynchronous logic to cross clock domains, typically from IO to internal logic.
+ . single signal --> FF in series strobes
+ . parallel word --> FF in series for strobes that transfer the data
+ . streaming data --> FIFO using gray encoding for wr and rd address comparision, use one
+                      wide FIFO for all data inputs in parallel to preserve their relative
+                      timing.
+
+Reset : asynchronous or synchronous ?
+
 Digital logic: Ik noem logic zonder klok vaak "combinatorial logic". Deze term is op zich correct, maar de meer gangbare term is "combinational logic", zie
 https://en.wikipedia.org/wiki/Combinational_logic . Ik zal dat aanpassen in de documentatie. De logic met klok wordt "sequential logic" genoemd. Tesamen heet het "digital logic".
 
@@ -36,7 +48,7 @@ Idea / rule: Distinguish beteen state registers and pipeline registers.
 . Components that do need input flow control can OR their input flow control with the external flow control
   and wire that to the input_siso.
 
-  
+
 
 $RADIOHDL_WORK/applications/lofar2/doc/prestudy/
 
@@ -72,6 +84,8 @@ Ik zie twee niveaus:
    dat de packets die binnenkomen van buiten de FPGA correct zijn (bijv. mbv CRC ok) dan is de
    block processing foutloos (dwz what you want is what you get). Dan kunnen we er intern steeds
    van uitgaan dat de blokken data correct zijn en hoeven we dus intern geen checks meer te doen.
+   De processing moet wel bestand zijn tegen missende blocken, bijv. tgv data loss aan een input
+   of uit en aan zetten van een input.
 
 
 Design steps:
@@ -97,6 +111,11 @@ Implementation steps:
     SIGNAL r             : t_reg;
     SIGNAL nxt_r         : t_reg;
 
+  . -- Memoryless signals in p_comb (wires used as local auxiliary variables)
+    SIGNAL s             : t_comb;
+
+  . -- Structural signals (wires used to connect components and IO)
+
   . -- Pipeline registers
     SIGNAL in_data_p     : ...
 
@@ -131,11 +150,24 @@ Implementation steps:
 
       -- next state
       nxt_r <= v;
+
+      -- memory less signals, only for view in wave window
+      s <= d;
     END PROCESS;
 
   . -- Pipelining
 
 - TB: Test the functionality of the DUT:
+  . Every component should have a tb (= unit test)
+  . The tb should be self checking and self stopping, so that it can be part of a
+    regression test.
+  . Only test the added functionality of the DUT, do not test lower level component
+    instances, because these have been tested already in detail at their level. E.g
+    for an MMP interface component, only check that the MM access is wired correctly.
+  . if possible also create the dual component, e.g. tx --> rx, encoder --> decoder
+    multiplexer --> demultiplexer (see dp, diag examples). This makes tb verification
+    easier, because expected results are in the same format as the stimuli and
+    because it yields the dual component, which can be useful for future applications.
   . start with easiest, default use case,
   . then verify the additional functions and features,
   . then verify the corner cases (e.g. 0, 1, some prime value, smallest, largest),