diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl new file mode 100644 index 0000000000000000000000000000000000000000..78cfca72bd307a5d516047cf40a897c494e8fc9a --- /dev/null +++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl @@ -0,0 +1,530 @@ +# TCL File Generated by Component Editor 17.0.1 +# Thu Jul 13 11:06:59 CEST 2017 +# DO NOT MODIFY + + +# +# avs2_eth_coe "avs2_eth_coe" v1.0 +# ASTRON 2017.07.13.11:06:59 +# MM slave port to conduit for the ETH module +# + +# +# request TCL package from ACDS 18.0 +# +package require -exact qsys 18.0 + + +# +# module avs2_eth_coe +# +set_module_property DESCRIPTION "MM slave port to conduit for the ETH module" +set_module_property NAME avs2_eth_coe +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP Uniboard +set_module_property AUTHOR ASTRON +set_module_property DISPLAY_NAME avs2_eth_coe +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" +set_fileset_property quartus_synth TOP_LEVEL avs2_eth_coe +set_fileset_property quartus_synth ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property quartus_synth ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file avs2_eth_coe.vhd VHDL PATH avs2_eth_coe.vhd TOP_LEVEL_FILE +add_fileset_file common_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_pkg.vhd +add_fileset_file dp_stream_pkg.vhd VHDL PATH ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd +add_fileset_file tech_tse_pkg.vhd VHDL PATH ../../../../technology/tse/tech_tse_pkg.vhd +add_fileset_file eth_pkg.vhd VHDL PATH eth_pkg.vhd +add_fileset_file common_network_layers_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_network_layers_pkg.vhd + +add_fileset sim_vhdl SIM_VHDL "" "VHDL Simulation" +set_fileset_property sim_vhdl ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property sim_vhdl ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file avs2_eth_coe.vhd VHDL PATH avs2_eth_coe.vhd +add_fileset_file common_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_pkg.vhd +add_fileset_file dp_stream_pkg.vhd VHDL PATH ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd +add_fileset_file tech_tse_pkg.vhd VHDL PATH ../../../../technology/tse/tech_tse_pkg.vhd +add_fileset_file eth_pkg.vhd VHDL PATH eth_pkg.vhd +add_fileset_file common_network_layers_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_network_layers_pkg.vhd + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point mm +# +add_interface mm clock end +set_interface_property mm clockRate 0 +set_interface_property mm ENABLED true +set_interface_property mm EXPORT_OF "" +set_interface_property mm PORT_NAME_MAP "" +set_interface_property mm CMSIS_SVD_VARIABLES "" +set_interface_property mm SVD_ADDRESS_GROUP "" + +add_interface_port mm csi_mm_clk clk Input 1 + + +# +# connection point mm_reset +# +add_interface mm_reset reset end +set_interface_property mm_reset associatedClock mm +set_interface_property mm_reset synchronousEdges DEASSERT +set_interface_property mm_reset ENABLED true +set_interface_property mm_reset EXPORT_OF "" +set_interface_property mm_reset PORT_NAME_MAP "" +set_interface_property mm_reset CMSIS_SVD_VARIABLES "" +set_interface_property mm_reset SVD_ADDRESS_GROUP "" + +add_interface_port mm_reset csi_mm_reset reset Input 1 + + +# +# connection point mms_tse +# +add_interface mms_tse avalon end +set_interface_property mms_tse addressUnits WORDS +set_interface_property mms_tse associatedClock mm +set_interface_property mms_tse associatedReset mm_reset +set_interface_property mms_tse bitsPerSymbol 8 +set_interface_property mms_tse bridgedAddressOffset "" +set_interface_property mms_tse bridgesToMaster "" +set_interface_property mms_tse burstOnBurstBoundariesOnly false +set_interface_property mms_tse burstcountUnits WORDS +set_interface_property mms_tse explicitAddressSpan 0 +set_interface_property mms_tse holdTime 0 +set_interface_property mms_tse linewrapBursts false +set_interface_property mms_tse maximumPendingReadTransactions 0 +set_interface_property mms_tse maximumPendingWriteTransactions 0 +set_interface_property mms_tse minimumResponseLatency 1 +set_interface_property mms_tse readLatency 0 +set_interface_property mms_tse readWaitTime 1 +set_interface_property mms_tse setupTime 0 +set_interface_property mms_tse timingUnits Cycles +set_interface_property mms_tse transparentBridge false +set_interface_property mms_tse waitrequestAllowance 0 +set_interface_property mms_tse writeWaitTime 0 +set_interface_property mms_tse ENABLED true +set_interface_property mms_tse EXPORT_OF "" +set_interface_property mms_tse PORT_NAME_MAP "" +set_interface_property mms_tse CMSIS_SVD_VARIABLES "" +set_interface_property mms_tse SVD_ADDRESS_GROUP "" + +add_interface_port mms_tse mms_tse_address address Input 10 +add_interface_port mms_tse mms_tse_write write Input 1 +add_interface_port mms_tse mms_tse_read read Input 1 +add_interface_port mms_tse mms_tse_writedata writedata Input 32 +add_interface_port mms_tse mms_tse_readdata readdata Output 32 +add_interface_port mms_tse mms_tse_waitrequest waitrequest Output 1 +set_interface_assignment mms_tse embeddedsw.configuration.isFlash 0 +set_interface_assignment mms_tse embeddedsw.configuration.isMemoryDevice false +set_interface_assignment mms_tse embeddedsw.configuration.isNonVolatileStorage false +set_interface_assignment mms_tse embeddedsw.configuration.isPrintableDevice false + + +# +# connection point mms_reg +# +add_interface mms_reg avalon end +set_interface_property mms_reg addressUnits WORDS +set_interface_property mms_reg associatedClock mm +set_interface_property mms_reg associatedReset mm_reset +set_interface_property mms_reg bitsPerSymbol 8 +set_interface_property mms_reg bridgedAddressOffset "" +set_interface_property mms_reg bridgesToMaster "" +set_interface_property mms_reg burstOnBurstBoundariesOnly false +set_interface_property mms_reg burstcountUnits WORDS +set_interface_property mms_reg explicitAddressSpan 0 +set_interface_property mms_reg holdTime 0 +set_interface_property mms_reg linewrapBursts false +set_interface_property mms_reg maximumPendingReadTransactions 0 +set_interface_property mms_reg maximumPendingWriteTransactions 0 +set_interface_property mms_reg minimumResponseLatency 1 +set_interface_property mms_reg readLatency 1 +set_interface_property mms_reg readWaitStates 0 +set_interface_property mms_reg readWaitTime 0 +set_interface_property mms_reg setupTime 0 +set_interface_property mms_reg timingUnits Cycles +set_interface_property mms_reg transparentBridge false +set_interface_property mms_reg waitrequestAllowance 0 +set_interface_property mms_reg writeWaitTime 0 +set_interface_property mms_reg ENABLED true +set_interface_property mms_reg EXPORT_OF "" +set_interface_property mms_reg PORT_NAME_MAP "" +set_interface_property mms_reg CMSIS_SVD_VARIABLES "" +set_interface_property mms_reg SVD_ADDRESS_GROUP "" + +add_interface_port mms_reg mms_reg_address address Input 4 +add_interface_port mms_reg mms_reg_write write Input 1 +add_interface_port mms_reg mms_reg_read read Input 1 +add_interface_port mms_reg mms_reg_writedata writedata Input 32 +add_interface_port mms_reg mms_reg_readdata readdata Output 32 +set_interface_assignment mms_reg embeddedsw.configuration.isFlash 0 +set_interface_assignment mms_reg embeddedsw.configuration.isMemoryDevice false +set_interface_assignment mms_reg embeddedsw.configuration.isNonVolatileStorage false +set_interface_assignment mms_reg embeddedsw.configuration.isPrintableDevice false + + +# +# connection point mms_ram +# +add_interface mms_ram avalon end +set_interface_property mms_ram addressUnits WORDS +set_interface_property mms_ram associatedClock mm +set_interface_property mms_ram associatedReset mm_reset +set_interface_property mms_ram bitsPerSymbol 8 +set_interface_property mms_ram bridgedAddressOffset "" +set_interface_property mms_ram bridgesToMaster "" +set_interface_property mms_ram burstOnBurstBoundariesOnly false +set_interface_property mms_ram burstcountUnits WORDS +set_interface_property mms_ram explicitAddressSpan 0 +set_interface_property mms_ram holdTime 0 +set_interface_property mms_ram linewrapBursts false +set_interface_property mms_ram maximumPendingReadTransactions 0 +set_interface_property mms_ram maximumPendingWriteTransactions 0 +set_interface_property mms_ram minimumResponseLatency 1 +set_interface_property mms_ram readLatency 2 +set_interface_property mms_ram readWaitStates 0 +set_interface_property mms_ram readWaitTime 0 +set_interface_property mms_ram setupTime 0 +set_interface_property mms_ram timingUnits Cycles +set_interface_property mms_ram transparentBridge false +set_interface_property mms_ram waitrequestAllowance 0 +set_interface_property mms_ram writeWaitTime 0 +set_interface_property mms_ram ENABLED true +set_interface_property mms_ram EXPORT_OF "" +set_interface_property mms_ram PORT_NAME_MAP "" +set_interface_property mms_ram CMSIS_SVD_VARIABLES "" +set_interface_property mms_ram SVD_ADDRESS_GROUP "" + +add_interface_port mms_ram mms_ram_address address Input 10 +add_interface_port mms_ram mms_ram_write write Input 1 +add_interface_port mms_ram mms_ram_read read Input 1 +add_interface_port mms_ram mms_ram_writedata writedata Input 32 +add_interface_port mms_ram mms_ram_readdata readdata Output 32 +set_interface_assignment mms_ram embeddedsw.configuration.isFlash 0 +set_interface_assignment mms_ram embeddedsw.configuration.isMemoryDevice false +set_interface_assignment mms_ram embeddedsw.configuration.isNonVolatileStorage false +set_interface_assignment mms_ram embeddedsw.configuration.isPrintableDevice false + + +# +# connection point interrupt +# +add_interface interrupt interrupt end +set_interface_property interrupt associatedAddressablePoint mms_reg +set_interface_property interrupt associatedClock mm +set_interface_property interrupt associatedReset mm_reset +set_interface_property interrupt bridgedReceiverOffset "" +set_interface_property interrupt bridgesToReceiver "" +set_interface_property interrupt ENABLED true +set_interface_property interrupt EXPORT_OF "" +set_interface_property interrupt PORT_NAME_MAP "" +set_interface_property interrupt CMSIS_SVD_VARIABLES "" +set_interface_property interrupt SVD_ADDRESS_GROUP "" + +add_interface_port interrupt ins_interrupt_irq irq Output 1 + + +# +# connection point reset +# +add_interface reset conduit end +set_interface_property reset associatedClock "" +set_interface_property reset associatedReset "" +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset coe_reset_export export Output 1 + + +# +# connection point clk +# +add_interface clk conduit end +set_interface_property clk associatedClock "" +set_interface_property clk associatedReset "" +set_interface_property clk ENABLED true +set_interface_property clk EXPORT_OF "" +set_interface_property clk PORT_NAME_MAP "" +set_interface_property clk CMSIS_SVD_VARIABLES "" +set_interface_property clk SVD_ADDRESS_GROUP "" + +add_interface_port clk coe_clk_export export Output 1 + + +# +# connection point tse_address +# +add_interface tse_address conduit end +set_interface_property tse_address associatedClock "" +set_interface_property tse_address associatedReset "" +set_interface_property tse_address ENABLED true +set_interface_property tse_address EXPORT_OF "" +set_interface_property tse_address PORT_NAME_MAP "" +set_interface_property tse_address CMSIS_SVD_VARIABLES "" +set_interface_property tse_address SVD_ADDRESS_GROUP "" + +add_interface_port tse_address coe_tse_address_export export Output 10 + + +# +# connection point tse_write +# +add_interface tse_write conduit end +set_interface_property tse_write associatedClock "" +set_interface_property tse_write associatedReset "" +set_interface_property tse_write ENABLED true +set_interface_property tse_write EXPORT_OF "" +set_interface_property tse_write PORT_NAME_MAP "" +set_interface_property tse_write CMSIS_SVD_VARIABLES "" +set_interface_property tse_write SVD_ADDRESS_GROUP "" + +add_interface_port tse_write coe_tse_write_export export Output 1 + + +# +# connection point tse_read +# +add_interface tse_read conduit end +set_interface_property tse_read associatedClock "" +set_interface_property tse_read associatedReset "" +set_interface_property tse_read ENABLED true +set_interface_property tse_read EXPORT_OF "" +set_interface_property tse_read PORT_NAME_MAP "" +set_interface_property tse_read CMSIS_SVD_VARIABLES "" +set_interface_property tse_read SVD_ADDRESS_GROUP "" + +add_interface_port tse_read coe_tse_read_export export Output 1 + + +# +# connection point tse_writedata +# +add_interface tse_writedata conduit end +set_interface_property tse_writedata associatedClock "" +set_interface_property tse_writedata associatedReset "" +set_interface_property tse_writedata ENABLED true +set_interface_property tse_writedata EXPORT_OF "" +set_interface_property tse_writedata PORT_NAME_MAP "" +set_interface_property tse_writedata CMSIS_SVD_VARIABLES "" +set_interface_property tse_writedata SVD_ADDRESS_GROUP "" + +add_interface_port tse_writedata coe_tse_writedata_export export Output 32 + + +# +# connection point tse_readdata +# +add_interface tse_readdata conduit end +set_interface_property tse_readdata associatedClock "" +set_interface_property tse_readdata associatedReset "" +set_interface_property tse_readdata ENABLED true +set_interface_property tse_readdata EXPORT_OF "" +set_interface_property tse_readdata PORT_NAME_MAP "" +set_interface_property tse_readdata CMSIS_SVD_VARIABLES "" +set_interface_property tse_readdata SVD_ADDRESS_GROUP "" + +add_interface_port tse_readdata coe_tse_readdata_export export Input 32 + + +# +# connection point tse_waitrequest +# +add_interface tse_waitrequest conduit end +set_interface_property tse_waitrequest associatedClock "" +set_interface_property tse_waitrequest associatedReset "" +set_interface_property tse_waitrequest ENABLED true +set_interface_property tse_waitrequest EXPORT_OF "" +set_interface_property tse_waitrequest PORT_NAME_MAP "" +set_interface_property tse_waitrequest CMSIS_SVD_VARIABLES "" +set_interface_property tse_waitrequest SVD_ADDRESS_GROUP "" + +add_interface_port tse_waitrequest coe_tse_waitrequest_export export Input 1 + + +# +# connection point reg_address +# +add_interface reg_address conduit end +set_interface_property reg_address associatedClock "" +set_interface_property reg_address associatedReset "" +set_interface_property reg_address ENABLED true +set_interface_property reg_address EXPORT_OF "" +set_interface_property reg_address PORT_NAME_MAP "" +set_interface_property reg_address CMSIS_SVD_VARIABLES "" +set_interface_property reg_address SVD_ADDRESS_GROUP "" + +add_interface_port reg_address coe_reg_address_export export Output 4 + + +# +# connection point reg_write +# +add_interface reg_write conduit end +set_interface_property reg_write associatedClock "" +set_interface_property reg_write associatedReset "" +set_interface_property reg_write ENABLED true +set_interface_property reg_write EXPORT_OF "" +set_interface_property reg_write PORT_NAME_MAP "" +set_interface_property reg_write CMSIS_SVD_VARIABLES "" +set_interface_property reg_write SVD_ADDRESS_GROUP "" + +add_interface_port reg_write coe_reg_write_export export Output 1 + + +# +# connection point reg_read +# +add_interface reg_read conduit end +set_interface_property reg_read associatedClock "" +set_interface_property reg_read associatedReset "" +set_interface_property reg_read ENABLED true +set_interface_property reg_read EXPORT_OF "" +set_interface_property reg_read PORT_NAME_MAP "" +set_interface_property reg_read CMSIS_SVD_VARIABLES "" +set_interface_property reg_read SVD_ADDRESS_GROUP "" + +add_interface_port reg_read coe_reg_read_export export Output 1 + + +# +# connection point reg_writedata +# +add_interface reg_writedata conduit end +set_interface_property reg_writedata associatedClock "" +set_interface_property reg_writedata associatedReset "" +set_interface_property reg_writedata ENABLED true +set_interface_property reg_writedata EXPORT_OF "" +set_interface_property reg_writedata PORT_NAME_MAP "" +set_interface_property reg_writedata CMSIS_SVD_VARIABLES "" +set_interface_property reg_writedata SVD_ADDRESS_GROUP "" + +add_interface_port reg_writedata coe_reg_writedata_export export Output 32 + + +# +# connection point reg_readdata +# +add_interface reg_readdata conduit end +set_interface_property reg_readdata associatedClock "" +set_interface_property reg_readdata associatedReset "" +set_interface_property reg_readdata ENABLED true +set_interface_property reg_readdata EXPORT_OF "" +set_interface_property reg_readdata PORT_NAME_MAP "" +set_interface_property reg_readdata CMSIS_SVD_VARIABLES "" +set_interface_property reg_readdata SVD_ADDRESS_GROUP "" + +add_interface_port reg_readdata coe_reg_readdata_export export Input 32 + + +# +# connection point ram_address +# +add_interface ram_address conduit end +set_interface_property ram_address associatedClock "" +set_interface_property ram_address associatedReset "" +set_interface_property ram_address ENABLED true +set_interface_property ram_address EXPORT_OF "" +set_interface_property ram_address PORT_NAME_MAP "" +set_interface_property ram_address CMSIS_SVD_VARIABLES "" +set_interface_property ram_address SVD_ADDRESS_GROUP "" + +add_interface_port ram_address coe_ram_address_export export Output 10 + + +# +# connection point ram_write +# +add_interface ram_write conduit end +set_interface_property ram_write associatedClock "" +set_interface_property ram_write associatedReset "" +set_interface_property ram_write ENABLED true +set_interface_property ram_write EXPORT_OF "" +set_interface_property ram_write PORT_NAME_MAP "" +set_interface_property ram_write CMSIS_SVD_VARIABLES "" +set_interface_property ram_write SVD_ADDRESS_GROUP "" + +add_interface_port ram_write coe_ram_write_export export Output 1 + + +# +# connection point ram_read +# +add_interface ram_read conduit end +set_interface_property ram_read associatedClock "" +set_interface_property ram_read associatedReset "" +set_interface_property ram_read ENABLED true +set_interface_property ram_read EXPORT_OF "" +set_interface_property ram_read PORT_NAME_MAP "" +set_interface_property ram_read CMSIS_SVD_VARIABLES "" +set_interface_property ram_read SVD_ADDRESS_GROUP "" + +add_interface_port ram_read coe_ram_read_export export Output 1 + + +# +# connection point ram_writedata +# +add_interface ram_writedata conduit end +set_interface_property ram_writedata associatedClock "" +set_interface_property ram_writedata associatedReset "" +set_interface_property ram_writedata ENABLED true +set_interface_property ram_writedata EXPORT_OF "" +set_interface_property ram_writedata PORT_NAME_MAP "" +set_interface_property ram_writedata CMSIS_SVD_VARIABLES "" +set_interface_property ram_writedata SVD_ADDRESS_GROUP "" + +add_interface_port ram_writedata coe_ram_writedata_export export Output 32 + + +# +# connection point ram_readdata +# +add_interface ram_readdata conduit end +set_interface_property ram_readdata associatedClock "" +set_interface_property ram_readdata associatedReset "" +set_interface_property ram_readdata ENABLED true +set_interface_property ram_readdata EXPORT_OF "" +set_interface_property ram_readdata PORT_NAME_MAP "" +set_interface_property ram_readdata CMSIS_SVD_VARIABLES "" +set_interface_property ram_readdata SVD_ADDRESS_GROUP "" + +add_interface_port ram_readdata coe_ram_readdata_export export Input 32 + + +# +# connection point irq +# +add_interface irq conduit end +set_interface_property irq associatedClock "" +set_interface_property irq associatedReset "" +set_interface_property irq ENABLED true +set_interface_property irq EXPORT_OF "" +set_interface_property irq PORT_NAME_MAP "" +set_interface_property irq CMSIS_SVD_VARIABLES "" +set_interface_property irq SVD_ADDRESS_GROUP "" + +add_interface_port irq coe_irq_export export Input 1 + diff --git a/libraries/technology/technology_select_pkg_unb2c.vhd b/libraries/technology/technology_select_pkg_unb2c.vhd new file mode 100644 index 0000000000000000000000000000000000000000..c917c75addffbec503cff882baed27ca9a3c529b --- /dev/null +++ b/libraries/technology/technology_select_pkg_unb2c.vhd @@ -0,0 +1,38 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2014 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +-- Purpose: Define default technology selection value for g_technology. +-- Description: +-- In case g_technology is not overruled by the application design then the +-- g_technology defaults to c_tech_select_default. + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE work.technology_pkg.ALL; + +PACKAGE technology_select_pkg IS + + --CONSTANT c_tech_select_default : INTEGER := c_tech_stratixiv; + --CONSTANT c_tech_select_default : INTEGER := c_tech_arria10; + --CONSTANT c_tech_select_default : INTEGER := c_tech_arria10_e3sge3; + CONSTANT c_tech_select_default : INTEGER := c_tech_arria10_e1sg; + +END technology_select_pkg;