diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
index d712c37ea97368476c54d55bfe2a21a23b3517ce..38a56d5a4b4bec6ef5bcac7ee64e9545c60807f6 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
@@ -234,7 +234,14 @@ peripherals:
peripheral_group: sst
mm_port_names:
- REG_STAT_HDR_DAT_SST
-
+
+ - peripheral_name: dp/dp_bsn_monitor_v2
+ peripheral_group: sst_udp
+ parameter_overrides:
+ - { name: g_nof_streams, value: 1 }
+ mm_port_names:
+ - REG_BSN_MONITOR_V2_SST_OFFLOAD
+
#############################################################################
# Xsub = Subband Correlator (from node_sdp_correlator.vhd)
#############################################################################
@@ -416,5 +423,11 @@ peripherals:
mm_port_names:
- REG_NW_10GBE_ETH10G
-
+ - peripheral_name: dp/dp_bsn_monitor_v2
+ peripheral_group: bst_udp
+ number_of_peripherals: c_N_beamsets
+ parameter_overrides:
+ - { name: g_nof_streams, value: 1 }
+ mm_port_names:
+ - REG_BSN_MONITOR_V2_BST_OFFLOAD
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index 9d8f88314e6a10f0605469342c88327c05d6e671..905e382dc5f93808a9527a1597698cb91c915750 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -148,269 +148,275 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL pout_wdi : STD_LOGIC;
-- WDI override
- SIGNAL reg_wdi_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_wdi_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_wdi_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_wdi_cipo : t_mem_cipo := c_mem_cipo_rst;
-- PPSH
- SIGNAL reg_ppsh_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_ppsh_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_ppsh_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_ppsh_cipo : t_mem_cipo := c_mem_cipo_rst;
-- UniBoard system info
- SIGNAL reg_unb_system_info_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_unb_system_info_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL rom_unb_system_info_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL rom_unb_system_info_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_unb_system_info_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_unb_system_info_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL rom_unb_system_info_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL rom_unb_system_info_cipo : t_mem_cipo := c_mem_cipo_rst;
-- UniBoard I2C sens
- SIGNAL reg_unb_sens_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_unb_sens_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_unb_sens_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_unb_sens_cipo : t_mem_cipo := c_mem_cipo_rst;
-- pm bus
- SIGNAL reg_unb_pmbus_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_unb_pmbus_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_unb_pmbus_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_unb_pmbus_cipo : t_mem_cipo := c_mem_cipo_rst;
-- FPGA sensors
- SIGNAL reg_fpga_temp_sens_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_fpga_temp_sens_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_fpga_voltage_sens_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_fpga_voltage_sens_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_fpga_temp_sens_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_fpga_temp_sens_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_fpga_voltage_sens_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_fpga_voltage_sens_cipo : t_mem_cipo := c_mem_cipo_rst;
-- eth1g
SIGNAL eth1g_mm_rst : STD_LOGIC;
- SIGNAL eth1g_tse_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH TSE MAC registers
- SIGNAL eth1g_tse_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL eth1g_reg_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH control and status registers
- SIGNAL eth1g_reg_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL eth1g_tse_copi : t_mem_copi := c_mem_copi_rst; -- ETH TSE MAC registers
+ SIGNAL eth1g_tse_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL eth1g_reg_copi : t_mem_copi := c_mem_copi_rst; -- ETH control and status registers
+ SIGNAL eth1g_reg_cipo : t_mem_cipo := c_mem_cipo_rst;
SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
- SIGNAL eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH rx frame and tx frame memory
- SIGNAL eth1g_ram_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL eth1g_ram_copi : t_mem_copi := c_mem_copi_rst; -- ETH rx frame and tx frame memory
+ SIGNAL eth1g_ram_cipo : t_mem_cipo := c_mem_cipo_rst;
-- EPCS read
- SIGNAL reg_dpmm_data_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dpmm_data_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dpmm_ctrl_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_dpmm_data_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dpmm_data_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_dpmm_ctrl_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dpmm_ctrl_cipo : t_mem_cipo := c_mem_cipo_rst;
-- EPCS write
- SIGNAL reg_mmdp_data_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_mmdp_data_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_mmdp_ctrl_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_mmdp_data_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_mmdp_data_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_mmdp_ctrl_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_mmdp_ctrl_cipo : t_mem_cipo := c_mem_cipo_rst;
-- EPCS status/control
- SIGNAL reg_epcs_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_epcs_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_epcs_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_epcs_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Remote Update
- SIGNAL reg_remu_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_remu_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_remu_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_remu_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Scrap ram
- SIGNAL ram_scrap_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_scrap_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_scrap_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_scrap_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- AIT
----------------------------------------------
-- JESD
- SIGNAL jesd204b_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL jesd204b_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL jesd204b_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL jesd204b_cipo : t_mem_cipo := c_mem_cipo_rst;
-- JESD control
- SIGNAL jesd_ctrl_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL jesd_ctrl_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL jesd_ctrl_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL jesd_ctrl_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Shiftram (applies per-antenna delay)
- SIGNAL reg_dp_shiftram_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dp_shiftram_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_dp_shiftram_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dp_shiftram_cipo : t_mem_cipo := c_mem_cipo_rst;
-- bsn source
- SIGNAL reg_bsn_source_v2_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bsn_source_v2_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bsn_source_v2_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_source_v2_cipo : t_mem_cipo := c_mem_cipo_rst;
-- bsn scheduler
- SIGNAL reg_bsn_scheduler_wg_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bsn_scheduler_wg_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bsn_scheduler_wg_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_scheduler_wg_cipo : t_mem_cipo := c_mem_cipo_rst;
-- WG
- SIGNAL reg_wg_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_wg_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL ram_wg_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_wg_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_wg_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_wg_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL ram_wg_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_wg_cipo : t_mem_cipo := c_mem_cipo_rst;
-- BSN MONITOR
- SIGNAL reg_bsn_monitor_input_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bsn_monitor_input_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bsn_monitor_input_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_input_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Data buffer bsn
- SIGNAL ram_diag_data_buf_bsn_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_diag_data_buf_bsn_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_diag_data_buf_bsn_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_diag_data_buf_bsn_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_diag_data_buf_bsn_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_diag_data_buf_bsn_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_diag_data_buf_bsn_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_diag_data_buf_bsn_cipo : t_mem_cipo := c_mem_cipo_rst;
-- ST Histogram
- SIGNAL ram_st_histogram_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_st_histogram_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_st_histogram_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_st_histogram_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Aduh statistics monitor
- SIGNAL reg_aduh_monitor_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_aduh_monitor_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_aduh_monitor_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_aduh_monitor_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- FSUB
----------------------------------------------
-- Subband statistics
- SIGNAL ram_st_sst_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_st_sst_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_st_sst_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_st_sst_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Spectral Inversion
- SIGNAL reg_si_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_si_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_si_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_si_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Filter coefficients
- SIGNAL ram_fil_coefs_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_fil_coefs_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_fil_coefs_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_fil_coefs_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Equalizer gains
- SIGNAL ram_equalizer_gains_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_equalizer_gains_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_equalizer_gains_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_equalizer_gains_cipo : t_mem_cipo := c_mem_cipo_rst;
-- DP Selector
- SIGNAL reg_dp_selector_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dp_selector_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_dp_selector_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dp_selector_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- SDP Info
----------------------------------------------
- SIGNAL reg_sdp_info_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_sdp_info_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_sdp_info_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_sdp_info_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- RING Info
----------------------------------------------
- SIGNAL reg_ring_info_copi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_ring_info_cipo : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_ring_info_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_ring_info_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- XSUB
----------------------------------------------
-- crosslets_info
- SIGNAL reg_crosslets_info_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_crosslets_info_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_crosslets_info_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_crosslets_info_cipo : t_mem_cipo := c_mem_cipo_rst;
-- crosslets_info
- SIGNAL reg_nof_crosslets_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_nof_crosslets_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_nof_crosslets_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_nof_crosslets_cipo : t_mem_cipo := c_mem_cipo_rst;
-- bsn_scheduler_xsub
- SIGNAL reg_bsn_sync_scheduler_xsub_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bsn_sync_scheduler_xsub_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bsn_sync_scheduler_xsub_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_sync_scheduler_xsub_cipo : t_mem_cipo := c_mem_cipo_rst;
-- st_xsq
- SIGNAL ram_st_xsq_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_st_xsq_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_st_xsq_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_st_xsq_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- BF
----------------------------------------------
-- Beamlet Subband Select
- SIGNAL ram_ss_ss_wide_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_ss_ss_wide_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_ss_ss_wide_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_ss_ss_wide_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Local BF bf weights
- SIGNAL ram_bf_weights_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_bf_weights_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_bf_weights_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_bf_weights_cipo : t_mem_cipo := c_mem_cipo_rst;
-- mms_dp_scale Scale Beamlets
- SIGNAL reg_bf_scale_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bf_scale_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bf_scale_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bf_scale_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Beamlet Data Output header fields
- SIGNAL reg_hdr_dat_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_hdr_dat_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_hdr_dat_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_hdr_dat_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Beamlet Data Output xonoff
- SIGNAL reg_dp_xonoff_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dp_xonoff_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_dp_xonoff_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dp_xonoff_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Beamlet Statistics (BST)
- SIGNAL ram_st_bst_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_st_bst_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_st_bst_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_st_bst_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- SST
----------------------------------------------
-- Statistics Enable
- SIGNAL reg_stat_enable_sst_mosi : t_mem_mosi;
- SIGNAL reg_stat_enable_sst_miso : t_mem_miso;
+ SIGNAL reg_stat_enable_sst_copi : t_mem_copi;
+ SIGNAL reg_stat_enable_sst_cipo : t_mem_cipo;
-- Statistics header info
- SIGNAL reg_stat_hdr_dat_sst_mosi : t_mem_mosi;
- SIGNAL reg_stat_hdr_dat_sst_miso : t_mem_miso;
+ SIGNAL reg_stat_hdr_dat_sst_copi : t_mem_copi;
+ SIGNAL reg_stat_hdr_dat_sst_cipo : t_mem_cipo;
+ -- SST UDP offload bsn monitor
+ SIGNAL reg_bsn_monitor_v2_sst_offload_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_sst_offload_cipo : t_mem_cipo;
----------------------------------------------
-- XST
----------------------------------------------
-- Statistics Enable
- SIGNAL reg_stat_enable_xst_mosi : t_mem_mosi;
- SIGNAL reg_stat_enable_xst_miso : t_mem_miso;
+ SIGNAL reg_stat_enable_xst_copi : t_mem_copi;
+ SIGNAL reg_stat_enable_xst_cipo : t_mem_cipo;
-- Statistics header info
- SIGNAL reg_stat_hdr_dat_xst_mosi : t_mem_mosi;
- SIGNAL reg_stat_hdr_dat_xst_miso : t_mem_miso;
+ SIGNAL reg_stat_hdr_dat_xst_copi : t_mem_copi;
+ SIGNAL reg_stat_hdr_dat_xst_cipo : t_mem_cipo;
-- XST bsn aligner_v2
- SIGNAL reg_bsn_align_v2_copi : t_mem_mosi;
- SIGNAL reg_bsn_align_v2_cipo : t_mem_miso;
+ SIGNAL reg_bsn_align_v2_copi : t_mem_copi;
+ SIGNAL reg_bsn_align_v2_cipo : t_mem_cipo;
-- XST bsn aligner_v2 bsn monitors
- SIGNAL reg_bsn_monitor_v2_bsn_align_v2_input_copi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_v2_bsn_align_v2_input_cipo : t_mem_miso;
- SIGNAL reg_bsn_monitor_v2_bsn_align_v2_output_copi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_v2_bsn_align_v2_output_cipo : t_mem_miso;
+ SIGNAL reg_bsn_monitor_v2_bsn_align_v2_input_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_bsn_align_v2_input_cipo : t_mem_cipo;
+ SIGNAL reg_bsn_monitor_v2_bsn_align_v2_output_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_bsn_align_v2_output_cipo : t_mem_cipo;
-- XST UDP offload bsn monitor
- SIGNAL reg_bsn_monitor_v2_xst_offload_copi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_v2_xst_offload_cipo : t_mem_miso;
+ SIGNAL reg_bsn_monitor_v2_xst_offload_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_xst_offload_cipo : t_mem_cipo;
-- XST ring lane info
- SIGNAL reg_ring_lane_info_xst_copi : t_mem_mosi;
- SIGNAL reg_ring_lane_info_xst_cipo : t_mem_miso;
+ SIGNAL reg_ring_lane_info_xst_copi : t_mem_copi;
+ SIGNAL reg_ring_lane_info_xst_cipo : t_mem_cipo;
-- XST ring bsn monitor rx
- SIGNAL reg_bsn_monitor_v2_ring_rx_xst_copi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_v2_ring_rx_xst_cipo : t_mem_miso;
+ SIGNAL reg_bsn_monitor_v2_ring_rx_xst_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_ring_rx_xst_cipo : t_mem_cipo;
-- XST ring bsn monitor tx
- SIGNAL reg_bsn_monitor_v2_ring_tx_xst_copi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_v2_ring_tx_xst_cipo : t_mem_miso;
+ SIGNAL reg_bsn_monitor_v2_ring_tx_xst_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_ring_tx_xst_cipo : t_mem_cipo;
-- XST ring validate err
- SIGNAL reg_dp_block_validate_err_xst_copi : t_mem_mosi;
- SIGNAL reg_dp_block_validate_err_xst_cipo : t_mem_miso;
+ SIGNAL reg_dp_block_validate_err_xst_copi : t_mem_copi;
+ SIGNAL reg_dp_block_validate_err_xst_cipo : t_mem_cipo;
-- XST ring bsn at sync
- SIGNAL reg_dp_block_validate_bsn_at_sync_xst_copi : t_mem_mosi;
- SIGNAL reg_dp_block_validate_bsn_at_sync_xst_cipo : t_mem_miso;
+ SIGNAL reg_dp_block_validate_bsn_at_sync_xst_copi : t_mem_copi;
+ SIGNAL reg_dp_block_validate_bsn_at_sync_xst_cipo : t_mem_cipo;
-- XST ring MAC10G
- SIGNAL reg_tr_10GbE_mac_copi : t_mem_mosi;
- SIGNAL reg_tr_10GbE_mac_cipo : t_mem_miso;
+ SIGNAL reg_tr_10GbE_mac_copi : t_mem_copi;
+ SIGNAL reg_tr_10GbE_mac_cipo : t_mem_cipo;
-- XST ring ETH10G
- SIGNAL reg_tr_10GbE_eth10g_copi : t_mem_mosi;
- SIGNAL reg_tr_10GbE_eth10g_cipo : t_mem_miso;
+ SIGNAL reg_tr_10GbE_eth10g_copi : t_mem_copi;
+ SIGNAL reg_tr_10GbE_eth10g_cipo : t_mem_cipo;
----------------------------------------------
-- BST
----------------------------------------------
-- Statistics Enable
- SIGNAL reg_stat_enable_bst_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_stat_enable_bst_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_stat_enable_bst_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_stat_enable_bst_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Statistics header info
- SIGNAL reg_stat_hdr_dat_bst_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_stat_hdr_dat_bst_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_stat_hdr_dat_bst_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_stat_hdr_dat_bst_cipo : t_mem_cipo := c_mem_cipo_rst;
+ -- BST UDP offload bsn monitor
+ SIGNAL reg_bsn_monitor_v2_bst_offload_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_bst_offload_cipo : t_mem_cipo;
----------------------------------------------
-- UDP Offload
----------------------------------------------
@@ -420,11 +426,11 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
----------------------------------------------
-- 10 GbE
----------------------------------------------
- SIGNAL reg_nw_10GbE_mac_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_nw_10GbE_mac_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_nw_10GbE_mac_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_nw_10GbE_mac_cipo : t_mem_cipo := c_mem_cipo_rst;
- SIGNAL reg_nw_10GbE_eth10g_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_nw_10GbE_eth10g_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_nw_10GbE_eth10g_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_nw_10GbE_eth10g_cipo : t_mem_cipo := c_mem_cipo_rst;
-- 10GbE
SIGNAL i_QSFP_TX : t_unb2b_board_qsfp_bus_2arr(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
@@ -493,68 +499,68 @@ BEGIN
-- MM buses
-- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
+ reg_remu_mosi => reg_remu_copi,
+ reg_remu_miso => reg_remu_cipo,
-- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ reg_dpmm_data_mosi => reg_dpmm_data_copi,
+ reg_dpmm_data_miso => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
-- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ reg_mmdp_data_mosi => reg_mmdp_data_copi,
+ reg_mmdp_data_miso => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
-- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
+ reg_epcs_mosi => reg_epcs_copi,
+ reg_epcs_miso => reg_epcs_cipo,
-- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
+ reg_wdi_mosi => reg_wdi_copi,
+ reg_wdi_miso => reg_wdi_cipo,
-- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_copi,
+ reg_unb_system_info_miso => reg_unb_system_info_cipo,
+ rom_unb_system_info_mosi => rom_unb_system_info_copi,
+ rom_unb_system_info_miso => rom_unb_system_info_cipo,
-- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_unb_sens_mosi => reg_unb_sens_copi,
+ reg_unb_sens_miso => reg_unb_sens_cipo,
-- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+ reg_unb_pmbus_mosi => reg_unb_pmbus_copi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_cipo,
-- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
+ reg_ppsh_mosi => reg_ppsh_copi,
+ reg_ppsh_miso => reg_ppsh_cipo,
-- eth1g
eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_tse_mosi => eth1g_tse_copi,
+ eth1g_tse_miso => eth1g_tse_cipo,
+ eth1g_reg_mosi => eth1g_reg_copi,
+ eth1g_reg_miso => eth1g_reg_cipo,
eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
+ eth1g_ram_mosi => eth1g_ram_copi,
+ eth1g_ram_miso => eth1g_ram_cipo,
-- eth1g UDP streaming
udp_tx_sosi_arr => udp_tx_sosi_arr,
udp_tx_siso_arr => udp_tx_siso_arr,
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
+ ram_scrap_mosi => ram_scrap_copi,
+ ram_scrap_miso => ram_scrap_cipo,
-- FPGA pins
-- . General
@@ -598,119 +604,119 @@ BEGIN
pout_wdi => pout_wdi,
-- mm interfaces for control
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
+ reg_wdi_copi => reg_wdi_copi,
+ reg_wdi_cipo => reg_wdi_cipo,
+ reg_unb_system_info_copi => reg_unb_system_info_copi,
+ reg_unb_system_info_cipo => reg_unb_system_info_cipo,
+ rom_unb_system_info_copi => rom_unb_system_info_copi,
+ rom_unb_system_info_cipo => rom_unb_system_info_cipo,
+ reg_unb_sens_copi => reg_unb_sens_copi,
+ reg_unb_sens_cipo => reg_unb_sens_cipo,
+ reg_unb_pmbus_copi => reg_unb_pmbus_copi,
+ reg_unb_pmbus_cipo => reg_unb_pmbus_cipo,
+ reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
+ reg_ppsh_copi => reg_ppsh_copi,
+ reg_ppsh_cipo => reg_ppsh_cipo,
eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_tse_copi => eth1g_tse_copi,
+ eth1g_tse_cipo => eth1g_tse_cipo,
+ eth1g_reg_copi => eth1g_reg_copi,
+ eth1g_reg_cipo => eth1g_reg_cipo,
eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
+ eth1g_ram_copi => eth1g_ram_copi,
+ eth1g_ram_cipo => eth1g_ram_cipo,
+ reg_dpmm_data_copi => reg_dpmm_data_copi,
+ reg_dpmm_data_cipo => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
+ reg_mmdp_data_copi => reg_mmdp_data_copi,
+ reg_mmdp_data_cipo => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
+ reg_epcs_copi => reg_epcs_copi,
+ reg_epcs_cipo => reg_epcs_cipo,
+ reg_remu_copi => reg_remu_copi,
+ reg_remu_cipo => reg_remu_cipo,
-- mm buses for signal flow blocks
-- Jesd ip status/control
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_v2_mosi => reg_bsn_source_v2_mosi,
- reg_bsn_source_v2_miso => reg_bsn_source_v2_miso,
- reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_st_histogram_mosi => ram_st_histogram_mosi,
- ram_st_histogram_miso => ram_st_histogram_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
- ram_equalizer_gains_miso => ram_equalizer_gains_miso,
- reg_dp_selector_mosi => reg_dp_selector_mosi,
- reg_dp_selector_miso => reg_dp_selector_miso,
- reg_sdp_info_mosi => reg_sdp_info_mosi,
- reg_sdp_info_miso => reg_sdp_info_miso,
+ jesd204b_copi => jesd204b_copi,
+ jesd204b_cipo => jesd204b_cipo,
+ jesd_ctrl_copi => jesd_ctrl_copi,
+ jesd_ctrl_cipo => jesd_ctrl_cipo,
+ reg_dp_shiftram_copi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_copi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_cipo => reg_bsn_scheduler_wg_cipo,
+ reg_wg_copi => reg_wg_copi,
+ reg_wg_cipo => reg_wg_cipo,
+ ram_wg_copi => ram_wg_copi,
+ ram_wg_cipo => ram_wg_cipo,
+ reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_copi => ram_st_histogram_copi,
+ ram_st_histogram_cipo => ram_st_histogram_cipo,
+ reg_aduh_monitor_copi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
+ ram_st_sst_copi => ram_st_sst_copi,
+ ram_st_sst_cipo => ram_st_sst_cipo,
+ ram_fil_coefs_copi => ram_fil_coefs_copi,
+ ram_fil_coefs_cipo => ram_fil_coefs_cipo,
+ reg_si_copi => reg_si_copi,
+ reg_si_cipo => reg_si_cipo,
+ ram_equalizer_gains_copi => ram_equalizer_gains_copi,
+ ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
+ reg_dp_selector_copi => reg_dp_selector_copi,
+ reg_dp_selector_cipo => reg_dp_selector_cipo,
+ reg_sdp_info_copi => reg_sdp_info_copi,
+ reg_sdp_info_cipo => reg_sdp_info_cipo,
reg_ring_info_copi => reg_ring_info_copi,
reg_ring_info_cipo => reg_ring_info_cipo,
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
- ram_bf_weights_mosi => ram_bf_weights_mosi,
- ram_bf_weights_miso => ram_bf_weights_miso,
- reg_bf_scale_mosi => reg_bf_scale_mosi,
- reg_bf_scale_miso => reg_bf_scale_miso,
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
- reg_dp_xonoff_miso => reg_dp_xonoff_miso,
- ram_st_bst_mosi => ram_st_bst_mosi,
- ram_st_bst_miso => ram_st_bst_miso,
- reg_nw_10GbE_mac_mosi => reg_nw_10GbE_mac_mosi,
- reg_nw_10GbE_mac_miso => reg_nw_10GbE_mac_miso,
- reg_nw_10GbE_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
- reg_nw_10GbE_eth10g_miso => reg_nw_10GbE_eth10g_miso,
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
- reg_stat_enable_sst_mosi => reg_stat_enable_sst_mosi,
- reg_stat_enable_sst_miso => reg_stat_enable_sst_miso,
- reg_stat_hdr_dat_sst_mosi => reg_stat_hdr_dat_sst_mosi,
- reg_stat_hdr_dat_sst_miso => reg_stat_hdr_dat_sst_miso,
- reg_stat_enable_xst_mosi => reg_stat_enable_xst_mosi,
- reg_stat_enable_xst_miso => reg_stat_enable_xst_miso,
- reg_stat_hdr_dat_xst_mosi => reg_stat_hdr_dat_xst_mosi,
- reg_stat_hdr_dat_xst_miso => reg_stat_hdr_dat_xst_miso,
- reg_stat_enable_bst_mosi => reg_stat_enable_bst_mosi,
- reg_stat_enable_bst_miso => reg_stat_enable_bst_miso,
- reg_stat_hdr_dat_bst_mosi => reg_stat_hdr_dat_bst_mosi,
- reg_stat_hdr_dat_bst_miso => reg_stat_hdr_dat_bst_miso,
- reg_crosslets_info_mosi => reg_crosslets_info_mosi,
- reg_crosslets_info_miso => reg_crosslets_info_miso,
- reg_nof_crosslets_mosi => reg_nof_crosslets_mosi,
- reg_nof_crosslets_miso => reg_nof_crosslets_miso,
- reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
- reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
+ ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
+ ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
+ ram_bf_weights_copi => ram_bf_weights_copi,
+ ram_bf_weights_cipo => ram_bf_weights_cipo,
+ reg_bf_scale_copi => reg_bf_scale_copi,
+ reg_bf_scale_cipo => reg_bf_scale_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_dp_xonoff_copi => reg_dp_xonoff_copi,
+ reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
+ ram_st_bst_copi => ram_st_bst_copi,
+ ram_st_bst_cipo => ram_st_bst_cipo,
+ reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
+ reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
+ reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
+ reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
+ ram_scrap_copi => ram_scrap_copi,
+ ram_scrap_cipo => ram_scrap_cipo,
+ reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
+ reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
+ reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
+ reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
+ reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
+ reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
+ reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
+ reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
+ reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
reg_bsn_align_v2_copi => reg_bsn_align_v2_copi,
reg_bsn_align_v2_cipo => reg_bsn_align_v2_cipo,
reg_bsn_monitor_v2_bsn_align_v2_input_copi => reg_bsn_monitor_v2_bsn_align_v2_input_copi,
@@ -718,7 +724,11 @@ BEGIN
reg_bsn_monitor_v2_bsn_align_v2_output_copi => reg_bsn_monitor_v2_bsn_align_v2_output_copi,
reg_bsn_monitor_v2_bsn_align_v2_output_cipo => reg_bsn_monitor_v2_bsn_align_v2_output_cipo,
reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
@@ -733,8 +743,8 @@ BEGIN
reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
- ram_st_xsq_mosi => ram_st_xsq_mosi,
- ram_st_xsq_miso => ram_st_xsq_miso
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo
);
@@ -781,92 +791,94 @@ BEGIN
udp_tx_siso_arr => udp_tx_siso_arr,
-- 10 GbE
- reg_nw_10GbE_mac_mosi => reg_nw_10GbE_mac_mosi,
- reg_nw_10GbE_mac_miso => reg_nw_10GbE_mac_miso,
- reg_nw_10GbE_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
- reg_nw_10GbE_eth10g_miso => reg_nw_10GbE_eth10g_miso,
+ reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
+ reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
+ reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
+ reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
-- AIT
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_v2_mosi => reg_bsn_source_v2_mosi,
- reg_bsn_source_v2_miso => reg_bsn_source_v2_miso,
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_st_histogram_mosi => ram_st_histogram_mosi,
- ram_st_histogram_miso => ram_st_histogram_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+ jesd204b_copi => jesd204b_copi,
+ jesd204b_cipo => jesd204b_cipo,
+ jesd_ctrl_copi => jesd_ctrl_copi,
+ jesd_ctrl_cipo => jesd_ctrl_cipo,
+ reg_dp_shiftram_copi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_wg_copi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_wg_cipo => reg_bsn_scheduler_wg_cipo,
+ reg_wg_copi => reg_wg_copi,
+ reg_wg_cipo => reg_wg_cipo,
+ ram_wg_copi => ram_wg_copi,
+ ram_wg_cipo => ram_wg_cipo,
+ reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_copi => ram_st_histogram_copi,
+ ram_st_histogram_cipo => ram_st_histogram_cipo,
+ reg_aduh_monitor_copi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
-- FSUB
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
- ram_equalizer_gains_miso => ram_equalizer_gains_miso,
- reg_dp_selector_mosi => reg_dp_selector_mosi,
- reg_dp_selector_miso => reg_dp_selector_miso,
+ ram_st_sst_copi => ram_st_sst_copi,
+ ram_st_sst_cipo => ram_st_sst_cipo,
+ reg_si_copi => reg_si_copi,
+ reg_si_cipo => reg_si_cipo,
+ ram_fil_coefs_copi => ram_fil_coefs_copi,
+ ram_fil_coefs_cipo => ram_fil_coefs_cipo,
+ ram_equalizer_gains_copi => ram_equalizer_gains_copi,
+ ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
+ reg_dp_selector_copi => reg_dp_selector_copi,
+ reg_dp_selector_cipo => reg_dp_selector_cipo,
-- SDP Info
- reg_sdp_info_mosi => reg_sdp_info_mosi,
- reg_sdp_info_miso => reg_sdp_info_miso,
+ reg_sdp_info_copi => reg_sdp_info_copi,
+ reg_sdp_info_cipo => reg_sdp_info_cipo,
-- RING Info
reg_ring_info_copi => reg_ring_info_copi,
reg_ring_info_cipo => reg_ring_info_cipo,
-- XSUB
- reg_crosslets_info_mosi => reg_crosslets_info_mosi,
- reg_crosslets_info_miso => reg_crosslets_info_miso,
- reg_nof_crosslets_mosi => reg_nof_crosslets_mosi,
- reg_nof_crosslets_miso => reg_nof_crosslets_miso,
- reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
- reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
- ram_st_xsq_mosi => ram_st_xsq_mosi,
- ram_st_xsq_miso => ram_st_xsq_miso,
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo,
-- BF
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
- ram_bf_weights_mosi => ram_bf_weights_mosi,
- ram_bf_weights_miso => ram_bf_weights_miso,
- reg_bf_scale_mosi => reg_bf_scale_mosi,
- reg_bf_scale_miso => reg_bf_scale_miso,
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
- reg_dp_xonoff_miso => reg_dp_xonoff_miso,
- ram_st_bst_mosi => ram_st_bst_mosi,
- ram_st_bst_miso => ram_st_bst_miso,
+ ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
+ ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
+ ram_bf_weights_copi => ram_bf_weights_copi,
+ ram_bf_weights_cipo => ram_bf_weights_cipo,
+ reg_bf_scale_copi => reg_bf_scale_copi,
+ reg_bf_scale_cipo => reg_bf_scale_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_dp_xonoff_copi => reg_dp_xonoff_copi,
+ reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
+ ram_st_bst_copi => ram_st_bst_copi,
+ ram_st_bst_cipo => ram_st_bst_cipo,
-- SST
- reg_stat_enable_sst_mosi => reg_stat_enable_sst_mosi,
- reg_stat_enable_sst_miso => reg_stat_enable_sst_miso,
- reg_stat_hdr_dat_sst_mosi => reg_stat_hdr_dat_sst_mosi,
- reg_stat_hdr_dat_sst_miso => reg_stat_hdr_dat_sst_miso,
+ reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
+ reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
+ reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
+ reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
-- XST
- reg_stat_enable_xst_mosi => reg_stat_enable_xst_mosi,
- reg_stat_enable_xst_miso => reg_stat_enable_xst_miso,
- reg_stat_hdr_dat_xst_mosi => reg_stat_hdr_dat_xst_mosi,
- reg_stat_hdr_dat_xst_miso => reg_stat_hdr_dat_xst_miso,
+ reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
reg_bsn_align_copi => reg_bsn_align_v2_copi,
reg_bsn_align_cipo => reg_bsn_align_v2_cipo,
@@ -874,8 +886,8 @@ BEGIN
reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_bsn_align_v2_input_cipo,
reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_bsn_align_v2_output_copi,
reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_bsn_align_v2_output_cipo,
- reg_xst_udp_monitor_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_xst_udp_monitor_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
@@ -892,10 +904,12 @@ BEGIN
reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
-- BST
- reg_stat_enable_bst_mosi => reg_stat_enable_bst_mosi,
- reg_stat_enable_bst_miso => reg_stat_enable_bst_miso,
- reg_stat_hdr_dat_bst_mosi => reg_stat_hdr_dat_bst_mosi,
- reg_stat_hdr_dat_bst_miso => reg_stat_hdr_dat_bst_miso,
+ reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
+ reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
+ reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
+ reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
RING_0_TX => RING_0_TX,
RING_0_RX => RING_0_RX,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
index 49693f03c1dec83cde6d603d98d65978307fb140..bff0dd292ada1ef6612dc850cd8a33918bafbbb4 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
@@ -43,250 +43,258 @@ ENTITY mmm_lofar2_unb2b_sdp_station IS
pout_wdi : OUT STD_LOGIC;
-- Manual WDI override
- reg_wdi_mosi : OUT t_mem_mosi;
- reg_wdi_miso : IN t_mem_miso;
+ reg_wdi_copi : OUT t_mem_copi;
+ reg_wdi_cipo : IN t_mem_cipo;
-- system_info
- reg_unb_system_info_mosi : OUT t_mem_mosi;
- reg_unb_system_info_miso : IN t_mem_miso;
- rom_unb_system_info_mosi : OUT t_mem_mosi;
- rom_unb_system_info_miso : IN t_mem_miso;
+ reg_unb_system_info_copi : OUT t_mem_copi;
+ reg_unb_system_info_cipo : IN t_mem_cipo;
+ rom_unb_system_info_copi : OUT t_mem_copi;
+ rom_unb_system_info_cipo : IN t_mem_cipo;
-- UniBoard I2C sensors
- reg_unb_sens_mosi : OUT t_mem_mosi;
- reg_unb_sens_miso : IN t_mem_miso;
+ reg_unb_sens_copi : OUT t_mem_copi;
+ reg_unb_sens_cipo : IN t_mem_cipo;
- reg_fpga_temp_sens_mosi : OUT t_mem_mosi;
- reg_fpga_temp_sens_miso : IN t_mem_miso;
- reg_fpga_voltage_sens_mosi: OUT t_mem_mosi;
- reg_fpga_voltage_sens_miso: IN t_mem_miso;
+ reg_fpga_temp_sens_copi : OUT t_mem_copi;
+ reg_fpga_temp_sens_cipo : IN t_mem_cipo;
+ reg_fpga_voltage_sens_copi: OUT t_mem_copi;
+ reg_fpga_voltage_sens_cipo: IN t_mem_cipo;
- reg_unb_pmbus_mosi : OUT t_mem_mosi;
- reg_unb_pmbus_miso : IN t_mem_miso;
+ reg_unb_pmbus_copi : OUT t_mem_copi;
+ reg_unb_pmbus_cipo : IN t_mem_cipo;
-- PPSH
- reg_ppsh_mosi : OUT t_mem_mosi;
- reg_ppsh_miso : IN t_mem_miso;
+ reg_ppsh_copi : OUT t_mem_copi;
+ reg_ppsh_cipo : IN t_mem_cipo;
-- eth1g
eth1g_mm_rst : OUT STD_LOGIC;
- eth1g_tse_mosi : OUT t_mem_mosi;
- eth1g_tse_miso : IN t_mem_miso;
- eth1g_reg_mosi : OUT t_mem_mosi;
- eth1g_reg_miso : IN t_mem_miso;
+ eth1g_tse_copi : OUT t_mem_copi;
+ eth1g_tse_cipo : IN t_mem_cipo;
+ eth1g_reg_copi : OUT t_mem_copi;
+ eth1g_reg_cipo : IN t_mem_cipo;
eth1g_reg_interrupt : IN STD_LOGIC;
- eth1g_ram_mosi : OUT t_mem_mosi;
- eth1g_ram_miso : IN t_mem_miso;
+ eth1g_ram_copi : OUT t_mem_copi;
+ eth1g_ram_cipo : IN t_mem_cipo;
-- EPCS read
- reg_dpmm_data_mosi : OUT t_mem_mosi;
- reg_dpmm_data_miso : IN t_mem_miso;
- reg_dpmm_ctrl_mosi : OUT t_mem_mosi;
- reg_dpmm_ctrl_miso : IN t_mem_miso;
+ reg_dpmm_data_copi : OUT t_mem_copi;
+ reg_dpmm_data_cipo : IN t_mem_cipo;
+ reg_dpmm_ctrl_copi : OUT t_mem_copi;
+ reg_dpmm_ctrl_cipo : IN t_mem_cipo;
-- EPCS write
- reg_mmdp_data_mosi : OUT t_mem_mosi;
- reg_mmdp_data_miso : IN t_mem_miso;
- reg_mmdp_ctrl_mosi : OUT t_mem_mosi;
- reg_mmdp_ctrl_miso : IN t_mem_miso;
+ reg_mmdp_data_copi : OUT t_mem_copi;
+ reg_mmdp_data_cipo : IN t_mem_cipo;
+ reg_mmdp_ctrl_copi : OUT t_mem_copi;
+ reg_mmdp_ctrl_cipo : IN t_mem_cipo;
-- EPCS status/control
- reg_epcs_mosi : OUT t_mem_mosi;
- reg_epcs_miso : IN t_mem_miso;
+ reg_epcs_copi : OUT t_mem_copi;
+ reg_epcs_cipo : IN t_mem_cipo;
-- Remote Update
- reg_remu_mosi : OUT t_mem_mosi;
- reg_remu_miso : IN t_mem_miso;
+ reg_remu_copi : OUT t_mem_copi;
+ reg_remu_cipo : IN t_mem_cipo;
-- Jesd control
- jesd204b_mosi : OUT t_mem_mosi;
- jesd204b_miso : IN t_mem_miso;
+ jesd204b_copi : OUT t_mem_copi;
+ jesd204b_cipo : IN t_mem_cipo;
-- Dp shiftram
- reg_dp_shiftram_mosi : OUT t_mem_mosi;
- reg_dp_shiftram_miso : IN t_mem_miso;
+ reg_dp_shiftram_copi : OUT t_mem_copi;
+ reg_dp_shiftram_cipo : IN t_mem_cipo;
-- Bsn source
- reg_bsn_source_v2_mosi : OUT t_mem_mosi;
- reg_bsn_source_v2_miso : IN t_mem_miso;
+ reg_bsn_source_v2_copi : OUT t_mem_copi;
+ reg_bsn_source_v2_cipo : IN t_mem_cipo;
-- bsn schduler for wg trigger
- reg_bsn_scheduler_mosi : OUT t_mem_mosi;
- reg_bsn_scheduler_miso : IN t_mem_miso;
+ reg_bsn_scheduler_copi : OUT t_mem_copi;
+ reg_bsn_scheduler_cipo : IN t_mem_cipo;
-- BSN Monitor
- reg_bsn_monitor_input_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_monitor_input_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_bsn_monitor_input_copi : OUT t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_input_cipo : IN t_mem_cipo := c_mem_cipo_rst;
-- MM wideband waveform generator registers [0,1,2,3] for signal paths [A,B,C,D]
- reg_wg_mosi : OUT t_mem_mosi;
- reg_wg_miso : IN t_mem_miso;
- ram_wg_mosi : OUT t_mem_mosi;
- ram_wg_miso : IN t_mem_miso;
+ reg_wg_copi : OUT t_mem_copi;
+ reg_wg_cipo : IN t_mem_cipo;
+ ram_wg_copi : OUT t_mem_copi;
+ ram_wg_cipo : IN t_mem_cipo;
-- Bsn databuffer
- ram_diag_data_buf_bsn_mosi : OUT t_mem_mosi;
- ram_diag_data_buf_bsn_miso : IN t_mem_miso;
- reg_diag_data_buf_bsn_mosi : OUT t_mem_mosi;
- reg_diag_data_buf_bsn_miso : IN t_mem_miso;
+ ram_diag_data_buf_bsn_copi : OUT t_mem_copi;
+ ram_diag_data_buf_bsn_cipo : IN t_mem_cipo;
+ reg_diag_data_buf_bsn_copi : OUT t_mem_copi;
+ reg_diag_data_buf_bsn_cipo : IN t_mem_cipo;
-- ST Histogram
- ram_st_histogram_mosi : OUT t_mem_mosi;
- ram_st_histogram_miso : IN t_mem_miso;
+ ram_st_histogram_copi : OUT t_mem_copi;
+ ram_st_histogram_cipo : IN t_mem_cipo;
-- Aduh
- reg_aduh_monitor_mosi : OUT t_mem_mosi;
- reg_aduh_monitor_miso : IN t_mem_miso;
+ reg_aduh_monitor_copi : OUT t_mem_copi;
+ reg_aduh_monitor_cipo : IN t_mem_cipo;
-- Subband statistics
- ram_st_sst_mosi : OUT t_mem_mosi;
- ram_st_sst_miso : IN t_mem_miso;
+ ram_st_sst_copi : OUT t_mem_copi;
+ ram_st_sst_cipo : IN t_mem_cipo;
-- Filter coefficients
- ram_fil_coefs_mosi : OUT t_mem_mosi;
- ram_fil_coefs_miso : IN t_mem_miso;
+ ram_fil_coefs_copi : OUT t_mem_copi;
+ ram_fil_coefs_cipo : IN t_mem_cipo;
-- Spectral Inversion
- reg_si_mosi : OUT t_mem_mosi;
- reg_si_miso : IN t_mem_miso;
+ reg_si_copi : OUT t_mem_copi;
+ reg_si_cipo : IN t_mem_cipo;
-- Equalizer gains
- ram_equalizer_gains_mosi : OUT t_mem_mosi;
- ram_equalizer_gains_miso : IN t_mem_miso;
+ ram_equalizer_gains_copi : OUT t_mem_copi;
+ ram_equalizer_gains_cipo : IN t_mem_cipo;
-- DP Selector
- reg_dp_selector_mosi : OUT t_mem_mosi;
- reg_dp_selector_miso : IN t_mem_miso;
+ reg_dp_selector_copi : OUT t_mem_copi;
+ reg_dp_selector_cipo : IN t_mem_cipo;
-- SDP Info
- reg_sdp_info_mosi : OUT t_mem_mosi;
- reg_sdp_info_miso : IN t_mem_miso;
+ reg_sdp_info_copi : OUT t_mem_copi;
+ reg_sdp_info_cipo : IN t_mem_cipo;
-- RING Info
- reg_ring_info_copi : OUT t_mem_mosi;
- reg_ring_info_cipo : IN t_mem_miso;
+ reg_ring_info_copi : OUT t_mem_copi;
+ reg_ring_info_cipo : IN t_mem_cipo;
-- Beamlet Subband Select
- ram_ss_ss_wide_mosi : OUT t_mem_mosi;
- ram_ss_ss_wide_miso : IN t_mem_miso;
+ ram_ss_ss_wide_copi : OUT t_mem_copi;
+ ram_ss_ss_wide_cipo : IN t_mem_cipo;
-- Local BF bf weights
- ram_bf_weights_mosi : OUT t_mem_mosi;
- ram_bf_weights_miso : IN t_mem_miso;
+ ram_bf_weights_copi : OUT t_mem_copi;
+ ram_bf_weights_cipo : IN t_mem_cipo;
-- mms_dp_scale Scale Beamlets
- reg_bf_scale_mosi : OUT t_mem_mosi;
- reg_bf_scale_miso : IN t_mem_miso;
+ reg_bf_scale_copi : OUT t_mem_copi;
+ reg_bf_scale_cipo : IN t_mem_cipo;
-- Beamlet Data Output header fields
- reg_hdr_dat_mosi : OUT t_mem_mosi;
- reg_hdr_dat_miso : IN t_mem_miso;
+ reg_hdr_dat_copi : OUT t_mem_copi;
+ reg_hdr_dat_cipo : IN t_mem_cipo;
-- Beamlet Data Output xonoff
- reg_dp_xonoff_mosi : OUT t_mem_mosi;
- reg_dp_xonoff_miso : IN t_mem_miso;
+ reg_dp_xonoff_copi : OUT t_mem_copi;
+ reg_dp_xonoff_cipo : IN t_mem_cipo;
-- Beamlet Statistics (BST)
- ram_st_bst_mosi : OUT t_mem_mosi;
- ram_st_bst_miso : IN t_mem_miso;
+ ram_st_bst_copi : OUT t_mem_copi;
+ ram_st_bst_cipo : IN t_mem_cipo;
-- Subband Statistics offload
- reg_stat_enable_sst_mosi : OUT t_mem_mosi;
- reg_stat_enable_sst_miso : IN t_mem_miso;
+ reg_stat_enable_sst_copi : OUT t_mem_copi;
+ reg_stat_enable_sst_cipo : IN t_mem_cipo;
-- Statistics header info
- reg_stat_hdr_dat_sst_mosi : OUT t_mem_mosi;
- reg_stat_hdr_dat_sst_miso : IN t_mem_miso;
+ reg_stat_hdr_dat_sst_copi : OUT t_mem_copi;
+ reg_stat_hdr_dat_sst_cipo : IN t_mem_cipo;
-- Crosslet Statistics offload
- reg_stat_enable_xst_mosi : OUT t_mem_mosi;
- reg_stat_enable_xst_miso : IN t_mem_miso;
+ reg_stat_enable_xst_copi : OUT t_mem_copi;
+ reg_stat_enable_xst_cipo : IN t_mem_cipo;
-- Crosslet Statistics header info
- reg_stat_hdr_dat_xst_mosi : OUT t_mem_mosi;
- reg_stat_hdr_dat_xst_miso : IN t_mem_miso;
+ reg_stat_hdr_dat_xst_copi : OUT t_mem_copi;
+ reg_stat_hdr_dat_xst_cipo : IN t_mem_cipo;
-- Beamlet Statistics offload
- reg_stat_enable_bst_mosi : OUT t_mem_mosi;
- reg_stat_enable_bst_miso : IN t_mem_miso;
+ reg_stat_enable_bst_copi : OUT t_mem_copi;
+ reg_stat_enable_bst_cipo : IN t_mem_cipo;
-- Beamlet Statistics header info
- reg_stat_hdr_dat_bst_mosi : OUT t_mem_mosi;
- reg_stat_hdr_dat_bst_miso : IN t_mem_miso;
+ reg_stat_hdr_dat_bst_copi : OUT t_mem_copi;
+ reg_stat_hdr_dat_bst_cipo : IN t_mem_cipo;
-- crosslets_info
- reg_crosslets_info_mosi : OUT t_mem_mosi;
- reg_crosslets_info_miso : IN t_mem_miso;
+ reg_crosslets_info_copi : OUT t_mem_copi;
+ reg_crosslets_info_cipo : IN t_mem_cipo;
-- crosslets_info
- reg_nof_crosslets_mosi : OUT t_mem_mosi;
- reg_nof_crosslets_miso : IN t_mem_miso;
+ reg_nof_crosslets_copi : OUT t_mem_copi;
+ reg_nof_crosslets_cipo : IN t_mem_cipo;
-- bsn_sync_scheduler_xsub
- reg_bsn_sync_scheduler_xsub_mosi : OUT t_mem_mosi;
- reg_bsn_sync_scheduler_xsub_miso : IN t_mem_miso;
+ reg_bsn_sync_scheduler_xsub_copi : OUT t_mem_copi;
+ reg_bsn_sync_scheduler_xsub_cipo : IN t_mem_cipo;
-- st_xsq (XST)
- ram_st_xsq_mosi : OUT t_mem_mosi;
- ram_st_xsq_miso : IN t_mem_miso;
+ ram_st_xsq_copi : OUT t_mem_copi;
+ ram_st_xsq_cipo : IN t_mem_cipo;
-- 10 GbE mac
- reg_nw_10GbE_mac_mosi : OUT t_mem_mosi;
- reg_nw_10GbE_mac_miso : IN t_mem_miso;
+ reg_nw_10GbE_mac_copi : OUT t_mem_copi;
+ reg_nw_10GbE_mac_cipo : IN t_mem_cipo;
-- 10 GbE eth
- reg_nw_10GbE_eth10g_mosi : OUT t_mem_mosi;
- reg_nw_10GbE_eth10g_miso : IN t_mem_miso;
+ reg_nw_10GbE_eth10g_copi : OUT t_mem_copi;
+ reg_nw_10GbE_eth10g_cipo : IN t_mem_cipo;
-- XST bsn aligner_v2
- reg_bsn_align_v2_copi : OUT t_mem_mosi;
- reg_bsn_align_v2_cipo : IN t_mem_miso;
+ reg_bsn_align_v2_copi : OUT t_mem_copi;
+ reg_bsn_align_v2_cipo : IN t_mem_cipo;
-- XST bsn aligner_v2 bsn monitors
- reg_bsn_monitor_v2_bsn_align_v2_input_copi : OUT t_mem_mosi;
- reg_bsn_monitor_v2_bsn_align_v2_input_cipo : IN t_mem_miso;
- reg_bsn_monitor_v2_bsn_align_v2_output_copi : OUT t_mem_mosi;
- reg_bsn_monitor_v2_bsn_align_v2_output_cipo : IN t_mem_miso;
+ reg_bsn_monitor_v2_bsn_align_v2_input_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_bsn_align_v2_input_cipo : IN t_mem_cipo;
+ reg_bsn_monitor_v2_bsn_align_v2_output_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_bsn_align_v2_output_cipo : IN t_mem_cipo;
-- XST UDP offload bsn monitor
- reg_bsn_monitor_v2_xst_offload_copi : OUT t_mem_mosi;
- reg_bsn_monitor_v2_xst_offload_cipo : IN t_mem_miso;
+ reg_bsn_monitor_v2_xst_offload_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_xst_offload_cipo : IN t_mem_cipo;
+
+ -- BST UDP offload bsn monitor
+ reg_bsn_monitor_v2_bst_offload_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_bst_offload_cipo : IN t_mem_cipo;
+
+ -- SST UDP offload bsn monitor
+ reg_bsn_monitor_v2_sst_offload_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_sst_offload_cipo : IN t_mem_cipo;
-- XST ring lane info
- reg_ring_lane_info_xst_copi : OUT t_mem_mosi;
- reg_ring_lane_info_xst_cipo : IN t_mem_miso;
+ reg_ring_lane_info_xst_copi : OUT t_mem_copi;
+ reg_ring_lane_info_xst_cipo : IN t_mem_cipo;
-- XST ring bsn monitor rx
- reg_bsn_monitor_v2_ring_rx_xst_copi: OUT t_mem_mosi;
- reg_bsn_monitor_v2_ring_rx_xst_cipo: IN t_mem_miso;
+ reg_bsn_monitor_v2_ring_rx_xst_copi: OUT t_mem_copi;
+ reg_bsn_monitor_v2_ring_rx_xst_cipo: IN t_mem_cipo;
-- XST ring bsn monitor tx
- reg_bsn_monitor_v2_ring_tx_xst_copi : OUT t_mem_mosi;
- reg_bsn_monitor_v2_ring_tx_xst_cipo : IN t_mem_miso;
+ reg_bsn_monitor_v2_ring_tx_xst_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_ring_tx_xst_cipo : IN t_mem_cipo;
-- XST ring validate err
- reg_dp_block_validate_err_xst_copi : OUT t_mem_mosi;
- reg_dp_block_validate_err_xst_cipo : IN t_mem_miso;
+ reg_dp_block_validate_err_xst_copi : OUT t_mem_copi;
+ reg_dp_block_validate_err_xst_cipo : IN t_mem_cipo;
-- XST ring bsn at sync
- reg_dp_block_validate_bsn_at_sync_xst_copi : OUT t_mem_mosi;
- reg_dp_block_validate_bsn_at_sync_xst_cipo : IN t_mem_miso;
+ reg_dp_block_validate_bsn_at_sync_xst_copi : OUT t_mem_copi;
+ reg_dp_block_validate_bsn_at_sync_xst_cipo : IN t_mem_cipo;
-- XST ring MAC
- reg_tr_10GbE_mac_copi : OUT t_mem_mosi;
- reg_tr_10GbE_mac_cipo : IN t_mem_miso;
+ reg_tr_10GbE_mac_copi : OUT t_mem_copi;
+ reg_tr_10GbE_mac_cipo : IN t_mem_cipo;
-- XST ring ETH
- reg_tr_10GbE_eth10g_copi : OUT t_mem_mosi;
- reg_tr_10GbE_eth10g_cipo : IN t_mem_miso;
+ reg_tr_10GbE_eth10g_copi : OUT t_mem_copi;
+ reg_tr_10GbE_eth10g_cipo : IN t_mem_cipo;
-- Scrap ram
- ram_scrap_mosi : OUT t_mem_mosi;
- ram_scrap_miso : IN t_mem_miso;
+ ram_scrap_copi : OUT t_mem_copi;
+ ram_scrap_cipo : IN t_mem_cipo;
-- Jesd reset control
- jesd_ctrl_mosi : OUT t_mem_mosi;
- jesd_ctrl_miso : IN t_mem_miso
+ jesd_ctrl_copi : OUT t_mem_copi;
+ jesd_ctrl_cipo : IN t_mem_cipo
);
END mmm_lofar2_unb2b_sdp_station;
@@ -306,138 +314,138 @@ BEGIN
gen_mm_file_io : IF g_sim = TRUE GENERATE
u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ PORT MAP(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ PORT MAP(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ PORT MAP(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ PORT MAP(mm_rst, mm_clk, reg_unb_sens_copi, reg_unb_sens_cipo );
u_mm_file_reg_unb_pmbus : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- PORT MAP(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ PORT MAP(mm_rst, mm_clk, reg_unb_pmbus_copi, reg_unb_pmbus_cipo );
u_mm_file_reg_fpga_temp_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- PORT MAP(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ PORT MAP(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
u_mm_file_reg_fpga_voltage_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- PORT MAP(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ PORT MAP(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ PORT MAP(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ PORT MAP(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
u_mm_file_jesd204b : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
- PORT MAP(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
+ PORT MAP(mm_rst, mm_clk, jesd204b_copi, jesd204b_cipo );
u_mm_file_reg_dp_shiftram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
- PORT MAP(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
+ PORT MAP(mm_rst, mm_clk, reg_dp_shiftram_copi, reg_dp_shiftram_cipo );
u_mm_file_reg_bsn_source_v2 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE_V2")
- PORT MAP(mm_rst, mm_clk, reg_bsn_source_v2_mosi, reg_bsn_source_v2_miso );
+ PORT MAP(mm_rst, mm_clk, reg_bsn_source_v2_copi, reg_bsn_source_v2_cipo );
u_mm_file_reg_bsn_scheduler : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- PORT MAP(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
+ PORT MAP(mm_rst, mm_clk, reg_bsn_scheduler_copi, reg_bsn_scheduler_cipo );
u_mm_file_reg_bsn_monitor_input : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_input_copi, reg_bsn_monitor_input_cipo );
u_mm_file_reg_wg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
- PORT MAP(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
+ PORT MAP(mm_rst, mm_clk, reg_wg_copi, reg_wg_cipo );
u_mm_file_ram_wg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
- PORT MAP(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
+ PORT MAP(mm_rst, mm_clk, ram_wg_copi, ram_wg_cipo );
u_mm_file_ram_diag_data_buf_bsn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_BSN")
- PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
+ PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_bsn_copi, ram_diag_data_buf_bsn_cipo );
u_mm_file_reg_diag_data_buf_bsn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_BSN")
- PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
+ PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_bsn_copi, reg_diag_data_buf_bsn_cipo );
u_mm_file_ram_st_histogram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_HISTOGRAM")
- PORT MAP(mm_rst, mm_clk, ram_st_histogram_mosi, ram_st_histogram_miso );
+ PORT MAP(mm_rst, mm_clk, ram_st_histogram_copi, ram_st_histogram_cipo );
u_mm_file_reg_aduh_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
- PORT MAP(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
+ PORT MAP(mm_rst, mm_clk, reg_aduh_monitor_copi, reg_aduh_monitor_cipo );
u_mm_file_ram_st_sst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
- PORT MAP(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
+ PORT MAP(mm_rst, mm_clk, ram_st_sst_copi, ram_st_sst_cipo );
u_mm_file_ram_fil_coefs : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
- PORT MAP(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
+ PORT MAP(mm_rst, mm_clk, ram_fil_coefs_copi, ram_fil_coefs_cipo );
u_mm_file_reg_si : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
- PORT MAP(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
+ PORT MAP(mm_rst, mm_clk, reg_si_copi, reg_si_cipo );
u_mm_file_ram_equalizer_gains : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
- PORT MAP(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
+ PORT MAP(mm_rst, mm_clk, ram_equalizer_gains_copi, ram_equalizer_gains_cipo );
u_mm_file_reg_dp_selector : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
- PORT MAP(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
+ PORT MAP(mm_rst, mm_clk, reg_dp_selector_copi, reg_dp_selector_cipo );
u_mm_file_reg_sdp_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
- PORT MAP(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
+ PORT MAP(mm_rst, mm_clk, reg_sdp_info_copi, reg_sdp_info_cipo );
u_mm_file_reg_ring_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
PORT MAP(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo );
u_mm_file_ram_ss_ss_wide : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- PORT MAP(mm_rst, mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso );
+ PORT MAP(mm_rst, mm_clk, ram_ss_ss_wide_copi, ram_ss_ss_wide_cipo );
u_mm_file_ram_bf_weights : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
- PORT MAP(mm_rst, mm_clk, ram_bf_weights_mosi, ram_bf_weights_miso );
+ PORT MAP(mm_rst, mm_clk, ram_bf_weights_copi, ram_bf_weights_cipo );
u_mm_file_reg_bf_scale : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BF_SCALE")
- PORT MAP(mm_rst, mm_clk, reg_bf_scale_mosi, reg_bf_scale_miso );
+ PORT MAP(mm_rst, mm_clk, reg_bf_scale_copi, reg_bf_scale_cipo );
u_mm_file_reg_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT")
- PORT MAP(mm_rst, mm_clk, reg_hdr_dat_mosi, reg_hdr_dat_miso );
+ PORT MAP(mm_rst, mm_clk, reg_hdr_dat_copi, reg_hdr_dat_cipo );
u_mm_file_reg_dp_xonoff : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF")
- PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_mosi, reg_dp_xonoff_miso );
+ PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_copi, reg_dp_xonoff_cipo );
u_mm_file_ram_st_bst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_BST")
- PORT MAP(mm_rst, mm_clk, ram_st_bst_mosi, ram_st_bst_miso );
+ PORT MAP(mm_rst, mm_clk, ram_st_bst_copi, ram_st_bst_cipo );
u_mm_file_reg_stat_enable_sst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_SST")
- PORT MAP(mm_rst, mm_clk, reg_stat_enable_sst_mosi, reg_stat_enable_sst_miso );
+ PORT MAP(mm_rst, mm_clk, reg_stat_enable_sst_copi, reg_stat_enable_sst_cipo );
u_mm_file_reg_stat_hdr_info_sst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_SST")
- PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_sst_mosi, reg_stat_hdr_dat_sst_miso);
+ PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_sst_copi, reg_stat_hdr_dat_sst_cipo);
u_mm_file_reg_stat_enable_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_XST")
- PORT MAP(mm_rst, mm_clk, reg_stat_enable_xst_mosi, reg_stat_enable_xst_miso );
+ PORT MAP(mm_rst, mm_clk, reg_stat_enable_xst_copi, reg_stat_enable_xst_cipo );
u_mm_file_reg_stat_hdr_info_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_XST")
- PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_xst_mosi, reg_stat_hdr_dat_xst_miso);
+ PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_xst_copi, reg_stat_hdr_dat_xst_cipo);
u_mm_file_reg_stat_enable_bst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_BST")
- PORT MAP(mm_rst, mm_clk, reg_stat_enable_bst_mosi, reg_stat_enable_bst_miso );
+ PORT MAP(mm_rst, mm_clk, reg_stat_enable_bst_copi, reg_stat_enable_bst_cipo );
u_mm_file_reg_stat_hdr_info_bst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST")
- PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_bst_mosi, reg_stat_hdr_dat_bst_miso);
+ PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_bst_copi, reg_stat_hdr_dat_bst_cipo);
u_mm_file_reg_crosslets_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_CROSSLETS_INFO")
- PORT MAP(mm_rst, mm_clk, reg_crosslets_info_mosi, reg_crosslets_info_miso);
+ PORT MAP(mm_rst, mm_clk, reg_crosslets_info_copi, reg_crosslets_info_cipo);
u_mm_file_reg_nof_crosslets : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NOF_CROSSLETS")
- PORT MAP(mm_rst, mm_clk, reg_nof_crosslets_mosi, reg_nof_crosslets_miso);
+ PORT MAP(mm_rst, mm_clk, reg_nof_crosslets_copi, reg_nof_crosslets_cipo);
u_mm_file_reg_bsn_sync_scheduler_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SYNC_SCHEDULER_XSUB")
- PORT MAP(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_mosi, reg_bsn_sync_scheduler_xsub_miso);
+ PORT MAP(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_copi, reg_bsn_sync_scheduler_xsub_cipo);
u_mm_file_ram_st_xsq : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_XSQ")
- PORT MAP(mm_rst, mm_clk, ram_st_xsq_mosi, ram_st_xsq_miso);
+ PORT MAP(mm_rst, mm_clk, ram_st_xsq_copi, ram_st_xsq_cipo);
u_mm_file_reg_nw_10GbE_mac : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
- PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_mac_mosi, reg_nw_10GbE_mac_miso );
+ PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_mac_copi, reg_nw_10GbE_mac_cipo );
u_mm_file_reg_nw_10GbE_eth10g : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
- PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_eth10g_mosi, reg_nw_10GbE_eth10g_miso );
+ PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_eth10g_copi, reg_nw_10GbE_eth10g_cipo );
u_mm_file_reg_bsn_align_v2 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2")
PORT MAP(mm_rst, mm_clk, reg_bsn_align_v2_copi, reg_bsn_align_v2_cipo );
@@ -448,6 +456,12 @@ BEGIN
u_mm_file_reg_bsn_monitor_v2_bsn_align_v2_output: mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT")
PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_bsn_align_v2_output_copi, reg_bsn_monitor_v2_bsn_align_v2_output_cipo );
+ u_mm_file_reg_bsn_monitor_v2_sst_offload : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_SST_OFFLOAD")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_sst_offload_copi, reg_bsn_monitor_v2_sst_offload_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_bst_offload : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BST_OFFLOAD")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_bst_offload_copi, reg_bsn_monitor_v2_bst_offload_cipo );
+
u_mm_file_reg_bsn_monitor_v2_xst_offload : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_XST_OFFLOAD")
PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_xst_offload_copi, reg_bsn_monitor_v2_xst_offload_cipo );
@@ -473,7 +487,7 @@ BEGIN
PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
u_mm_file_ram_scrap : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- PORT MAP(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+ PORT MAP(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
@@ -498,282 +512,282 @@ BEGIN
avs_eth_0_reset_export => eth1g_mm_rst,
avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
- avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
- avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
- avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_tse_address_export => eth1g_tse_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ avs_eth_0_tse_write_export => eth1g_tse_copi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_copi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_copi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_cipo.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_cipo.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_reg_write_export => eth1g_reg_copi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_copi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_copi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_cipo.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_ram_address_export => eth1g_ram_copi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_ram_write_export => eth1g_ram_copi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_copi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_copi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_cipo.rddata(c_word_w-1 DOWNTO 0),
avs_eth_0_irq_export => eth1g_reg_interrupt,
reg_unb_sens_reset_export => OPEN,
reg_unb_sens_clk_export => OPEN,
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
- reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
- reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
- reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_unb_sens_address_export => reg_unb_sens_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
+ reg_unb_sens_write_export => reg_unb_sens_copi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_unb_sens_read_export => reg_unb_sens_copi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_unb_pmbus_reset_export => OPEN,
reg_unb_pmbus_clk_export => OPEN,
- reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w-1 DOWNTO 0),
- reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
- reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
- reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_unb_pmbus_address_export => reg_unb_pmbus_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w-1 DOWNTO 0),
+ reg_unb_pmbus_write_export => reg_unb_pmbus_copi.wr,
+ reg_unb_pmbus_writedata_export => reg_unb_pmbus_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_unb_pmbus_read_export => reg_unb_pmbus_copi.rd,
+ reg_unb_pmbus_readdata_export => reg_unb_pmbus_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_fpga_temp_sens_reset_export => OPEN,
reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w-1 DOWNTO 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w-1 DOWNTO 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_copi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_copi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_fpga_voltage_sens_reset_export => OPEN,
reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w-1 DOWNTO 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w-1 DOWNTO 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_copi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_copi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_cipo.rddata(c_word_w-1 DOWNTO 0),
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
-- ToDo: This has changed in the peripherals package
--- rom_system_info_address_export => rom_unb_system_info_mosi.address(9 DOWNTO 0),
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+-- rom_system_info_address_export => rom_unb_system_info_copi.address(9 DOWNTO 0),
+ rom_system_info_address_export => rom_unb_system_info_copi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ rom_system_info_write_export => rom_unb_system_info_copi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_copi.wrdata(c_word_w-1 DOWNTO 0),
+ rom_system_info_read_export => rom_unb_system_info_copi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_cipo.rddata(c_word_w-1 DOWNTO 0),
pio_system_info_reset_export => OPEN,
pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ pio_system_info_address_export => reg_unb_system_info_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
+ pio_system_info_write_export => reg_unb_system_info_copi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_copi.wrdata(c_word_w-1 DOWNTO 0),
+ pio_system_info_read_export => reg_unb_system_info_copi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_cipo.rddata(c_word_w-1 DOWNTO 0),
pio_pps_reset_export => OPEN,
pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
+ pio_pps_address_export => reg_ppsh_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ pio_pps_write_export => reg_ppsh_copi.wr,
+ pio_pps_writedata_export => reg_ppsh_copi.wrdata(c_word_w-1 DOWNTO 0),
+ pio_pps_read_export => reg_ppsh_copi.rd,
+ pio_pps_readdata_export => reg_ppsh_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_wdi_reset_export => OPEN,
reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_mosi.address(0 DOWNTO 0),
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_wdi_address_export => reg_wdi_copi.address(0 DOWNTO 0),
+ reg_wdi_write_export => reg_wdi_copi.wr,
+ reg_wdi_writedata_export => reg_wdi_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_wdi_read_export => reg_wdi_copi.rd,
+ reg_wdi_readdata_export => reg_wdi_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_remu_reset_export => OPEN,
reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
- reg_remu_write_export => reg_remu_mosi.wr,
- reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_remu_read_export => reg_remu_mosi.rd,
- reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_remu_address_export => reg_remu_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
+ reg_remu_write_export => reg_remu_copi.wr,
+ reg_remu_writedata_export => reg_remu_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_remu_read_export => reg_remu_copi.rd,
+ reg_remu_readdata_export => reg_remu_cipo.rddata(c_word_w-1 DOWNTO 0),
jesd204b_reset_export => OPEN,
jesd204b_clk_export => OPEN,
- jesd204b_address_export => jesd204b_mosi.address(c_sdp_jesd204b_addr_w-1 DOWNTO 0),
- jesd204b_write_export => jesd204b_mosi.wr,
- jesd204b_writedata_export => jesd204b_mosi.wrdata(c_word_w-1 DOWNTO 0),
- jesd204b_read_export => jesd204b_mosi.rd,
- jesd204b_readdata_export => jesd204b_miso.rddata(c_word_w-1 DOWNTO 0),
+ jesd204b_address_export => jesd204b_copi.address(c_sdp_jesd204b_addr_w-1 DOWNTO 0),
+ jesd204b_write_export => jesd204b_copi.wr,
+ jesd204b_writedata_export => jesd204b_copi.wrdata(c_word_w-1 DOWNTO 0),
+ jesd204b_read_export => jesd204b_copi.rd,
+ jesd204b_readdata_export => jesd204b_cipo.rddata(c_word_w-1 DOWNTO 0),
pio_jesd_ctrl_reset_export => OPEN,
pio_jesd_ctrl_clk_export => OPEN,
- pio_jesd_ctrl_address_export => jesd_ctrl_mosi.address(c_sdp_jesd_ctrl_addr_w-1 DOWNTO 0),
- pio_jesd_ctrl_write_export => jesd_ctrl_mosi.wr,
- pio_jesd_ctrl_writedata_export => jesd_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
- pio_jesd_ctrl_read_export => jesd_ctrl_mosi.rd,
- pio_jesd_ctrl_readdata_export => jesd_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
+ pio_jesd_ctrl_address_export => jesd_ctrl_copi.address(c_sdp_jesd_ctrl_addr_w-1 DOWNTO 0),
+ pio_jesd_ctrl_write_export => jesd_ctrl_copi.wr,
+ pio_jesd_ctrl_writedata_export => jesd_ctrl_copi.wrdata(c_word_w-1 DOWNTO 0),
+ pio_jesd_ctrl_read_export => jesd_ctrl_copi.rd,
+ pio_jesd_ctrl_readdata_export => jesd_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0),
- reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_mosi.address(c_sdp_reg_bsn_monitor_input_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_copi.address(c_sdp_reg_bsn_monitor_input_addr_w-1 DOWNTO 0),
reg_bsn_monitor_input_clk_export => OPEN,
- reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_mosi.rd,
- reg_bsn_monitor_input_readdata_export => reg_bsn_monitor_input_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_copi.rd,
+ reg_bsn_monitor_input_readdata_export => reg_bsn_monitor_input_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_bsn_monitor_input_reset_export => OPEN,
- reg_bsn_monitor_input_write_export => reg_bsn_monitor_input_mosi.wr,
- reg_bsn_monitor_input_writedata_export => reg_bsn_monitor_input_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_input_write_export => reg_bsn_monitor_input_copi.wr,
+ reg_bsn_monitor_input_writedata_export => reg_bsn_monitor_input_copi.wrdata(c_word_w-1 DOWNTO 0),
-- waveform generators (multiplexed)
reg_wg_clk_export => OPEN,
reg_wg_reset_export => OPEN,
- reg_wg_address_export => reg_wg_mosi.address(c_sdp_reg_wg_addr_w-1 DOWNTO 0),
- reg_wg_read_export => reg_wg_mosi.rd,
- reg_wg_readdata_export => reg_wg_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_wg_write_export => reg_wg_mosi.wr,
- reg_wg_writedata_export => reg_wg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_wg_address_export => reg_wg_copi.address(c_sdp_reg_wg_addr_w-1 DOWNTO 0),
+ reg_wg_read_export => reg_wg_copi.rd,
+ reg_wg_readdata_export => reg_wg_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_wg_write_export => reg_wg_copi.wr,
+ reg_wg_writedata_export => reg_wg_copi.wrdata(c_word_w-1 DOWNTO 0),
ram_wg_clk_export => OPEN,
ram_wg_reset_export => OPEN,
- ram_wg_address_export => ram_wg_mosi.address(c_sdp_ram_wg_addr_w-1 DOWNTO 0),
- ram_wg_read_export => ram_wg_mosi.rd,
- ram_wg_readdata_export => ram_wg_miso.rddata(c_word_w-1 DOWNTO 0),
- ram_wg_write_export => ram_wg_mosi.wr,
- ram_wg_writedata_export => ram_wg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_wg_address_export => ram_wg_copi.address(c_sdp_ram_wg_addr_w-1 DOWNTO 0),
+ ram_wg_read_export => ram_wg_copi.rd,
+ ram_wg_readdata_export => ram_wg_cipo.rddata(c_word_w-1 DOWNTO 0),
+ ram_wg_write_export => ram_wg_copi.wr,
+ ram_wg_writedata_export => ram_wg_copi.wrdata(c_word_w-1 DOWNTO 0),
reg_dp_shiftram_clk_export => OPEN,
reg_dp_shiftram_reset_export => OPEN,
- reg_dp_shiftram_address_export => reg_dp_shiftram_mosi.address(c_sdp_reg_dp_shiftram_addr_w-1 DOWNTO 0),
- reg_dp_shiftram_read_export => reg_dp_shiftram_mosi.rd,
- reg_dp_shiftram_readdata_export => reg_dp_shiftram_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_dp_shiftram_write_export => reg_dp_shiftram_mosi.wr,
- reg_dp_shiftram_writedata_export => reg_dp_shiftram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_shiftram_address_export => reg_dp_shiftram_copi.address(c_sdp_reg_dp_shiftram_addr_w-1 DOWNTO 0),
+ reg_dp_shiftram_read_export => reg_dp_shiftram_copi.rd,
+ reg_dp_shiftram_readdata_export => reg_dp_shiftram_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_shiftram_write_export => reg_dp_shiftram_copi.wr,
+ reg_dp_shiftram_writedata_export => reg_dp_shiftram_copi.wrdata(c_word_w-1 DOWNTO 0),
reg_bsn_source_v2_clk_export => OPEN,
reg_bsn_source_v2_reset_export => OPEN,
- reg_bsn_source_v2_address_export => reg_bsn_source_v2_mosi.address(c_sdp_reg_bsn_source_v2_addr_w-1 DOWNTO 0),
- reg_bsn_source_v2_read_export => reg_bsn_source_v2_mosi.rd,
- reg_bsn_source_v2_readdata_export => reg_bsn_source_v2_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_bsn_source_v2_write_export => reg_bsn_source_v2_mosi.wr,
- reg_bsn_source_v2_writedata_export => reg_bsn_source_v2_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_source_v2_address_export => reg_bsn_source_v2_copi.address(c_sdp_reg_bsn_source_v2_addr_w-1 DOWNTO 0),
+ reg_bsn_source_v2_read_export => reg_bsn_source_v2_copi.rd,
+ reg_bsn_source_v2_readdata_export => reg_bsn_source_v2_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_source_v2_write_export => reg_bsn_source_v2_copi.wr,
+ reg_bsn_source_v2_writedata_export => reg_bsn_source_v2_copi.wrdata(c_word_w-1 DOWNTO 0),
reg_bsn_scheduler_clk_export => OPEN,
reg_bsn_scheduler_reset_export => OPEN,
- reg_bsn_scheduler_address_export => reg_bsn_scheduler_mosi.address(c_sdp_reg_bsn_scheduler_addr_w-1 DOWNTO 0),
- reg_bsn_scheduler_read_export => reg_bsn_scheduler_mosi.rd,
- reg_bsn_scheduler_readdata_export => reg_bsn_scheduler_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_bsn_scheduler_write_export => reg_bsn_scheduler_mosi.wr,
- reg_bsn_scheduler_writedata_export => reg_bsn_scheduler_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_scheduler_address_export => reg_bsn_scheduler_copi.address(c_sdp_reg_bsn_scheduler_addr_w-1 DOWNTO 0),
+ reg_bsn_scheduler_read_export => reg_bsn_scheduler_copi.rd,
+ reg_bsn_scheduler_readdata_export => reg_bsn_scheduler_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_scheduler_write_export => reg_bsn_scheduler_copi.wr,
+ reg_bsn_scheduler_writedata_export => reg_bsn_scheduler_copi.wrdata(c_word_w-1 DOWNTO 0),
reg_epcs_reset_export => OPEN,
reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
- reg_epcs_write_export => reg_epcs_mosi.wr,
- reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_epcs_read_export => reg_epcs_mosi.rd,
- reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_epcs_address_export => reg_epcs_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
+ reg_epcs_write_export => reg_epcs_copi.wr,
+ reg_epcs_writedata_export => reg_epcs_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_epcs_read_export => reg_epcs_copi.rd,
+ reg_epcs_readdata_export => reg_epcs_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_dpmm_ctrl_reset_export => OPEN,
reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 DOWNTO 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_copi.address(0 DOWNTO 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_copi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_copi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_mmdp_data_reset_export => OPEN,
reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 DOWNTO 0),
- reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_mmdp_data_address_export => reg_mmdp_data_copi.address(0 DOWNTO 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_copi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_copi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_dpmm_data_reset_export => OPEN,
reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 DOWNTO 0),
- reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dpmm_data_address_export => reg_dpmm_data_copi.address(0 DOWNTO 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_copi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_copi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_copi.wrdata(c_word_w-1 DOWNTO 0),
reg_mmdp_ctrl_reset_export => OPEN,
reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 DOWNTO 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_copi.address(0 DOWNTO 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_copi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_copi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_copi.wrdata(c_word_w-1 DOWNTO 0),
ram_diag_data_buffer_bsn_clk_export => OPEN,
ram_diag_data_buffer_bsn_reset_export => OPEN,
- ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(c_sdp_ram_diag_data_buf_bsn_addr_w-1 DOWNTO 0),
- ram_diag_data_buffer_bsn_write_export => ram_diag_data_buf_bsn_mosi.wr,
- ram_diag_data_buffer_bsn_writedata_export => ram_diag_data_buf_bsn_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_diag_data_buffer_bsn_read_export => ram_diag_data_buf_bsn_mosi.rd,
- ram_diag_data_buffer_bsn_readdata_export => ram_diag_data_buf_bsn_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_copi.address(c_sdp_ram_diag_data_buf_bsn_addr_w-1 DOWNTO 0),
+ ram_diag_data_buffer_bsn_write_export => ram_diag_data_buf_bsn_copi.wr,
+ ram_diag_data_buffer_bsn_writedata_export => ram_diag_data_buf_bsn_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_diag_data_buffer_bsn_read_export => ram_diag_data_buf_bsn_copi.rd,
+ ram_diag_data_buffer_bsn_readdata_export => ram_diag_data_buf_bsn_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_diag_data_buffer_bsn_reset_export => OPEN,
reg_diag_data_buffer_bsn_clk_export => OPEN,
- reg_diag_data_buffer_bsn_address_export => reg_diag_data_buf_bsn_mosi.address(c_sdp_reg_diag_data_buf_bsn_addr_w-1 DOWNTO 0),
- reg_diag_data_buffer_bsn_write_export => reg_diag_data_buf_bsn_mosi.wr,
- reg_diag_data_buffer_bsn_writedata_export => reg_diag_data_buf_bsn_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_diag_data_buffer_bsn_read_export => reg_diag_data_buf_bsn_mosi.rd,
- reg_diag_data_buffer_bsn_readdata_export => reg_diag_data_buf_bsn_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_data_buffer_bsn_address_export => reg_diag_data_buf_bsn_copi.address(c_sdp_reg_diag_data_buf_bsn_addr_w-1 DOWNTO 0),
+ reg_diag_data_buffer_bsn_write_export => reg_diag_data_buf_bsn_copi.wr,
+ reg_diag_data_buffer_bsn_writedata_export => reg_diag_data_buf_bsn_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_data_buffer_bsn_read_export => reg_diag_data_buf_bsn_copi.rd,
+ reg_diag_data_buffer_bsn_readdata_export => reg_diag_data_buf_bsn_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_st_histogram_clk_export => OPEN,
ram_st_histogram_reset_export => OPEN,
- ram_st_histogram_address_export => ram_st_histogram_mosi.address(c_sdp_ram_st_histogram_addr_w-1 DOWNTO 0),
- ram_st_histogram_write_export => ram_st_histogram_mosi.wr,
- ram_st_histogram_writedata_export => ram_st_histogram_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_st_histogram_read_export => ram_st_histogram_mosi.rd,
- ram_st_histogram_readdata_export => ram_st_histogram_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_st_histogram_address_export => ram_st_histogram_copi.address(c_sdp_ram_st_histogram_addr_w-1 DOWNTO 0),
+ ram_st_histogram_write_export => ram_st_histogram_copi.wr,
+ ram_st_histogram_writedata_export => ram_st_histogram_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_st_histogram_read_export => ram_st_histogram_copi.rd,
+ ram_st_histogram_readdata_export => ram_st_histogram_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_aduh_monitor_reset_export => OPEN,
reg_aduh_monitor_clk_export => OPEN,
- reg_aduh_monitor_address_export => reg_aduh_monitor_mosi.address(c_sdp_reg_aduh_monitor_addr_w-1 DOWNTO 0),
- reg_aduh_monitor_write_export => reg_aduh_monitor_mosi.wr,
- reg_aduh_monitor_writedata_export => reg_aduh_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_aduh_monitor_read_export => reg_aduh_monitor_mosi.rd,
- reg_aduh_monitor_readdata_export => reg_aduh_monitor_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_aduh_monitor_address_export => reg_aduh_monitor_copi.address(c_sdp_reg_aduh_monitor_addr_w-1 DOWNTO 0),
+ reg_aduh_monitor_write_export => reg_aduh_monitor_copi.wr,
+ reg_aduh_monitor_writedata_export => reg_aduh_monitor_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_aduh_monitor_read_export => reg_aduh_monitor_copi.rd,
+ reg_aduh_monitor_readdata_export => reg_aduh_monitor_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_fil_coefs_clk_export => OPEN,
ram_fil_coefs_reset_export => OPEN,
- ram_fil_coefs_address_export => ram_fil_coefs_mosi.address(c_sdp_ram_fil_coefs_addr_w-1 DOWNTO 0),
- ram_fil_coefs_write_export => ram_fil_coefs_mosi.wr,
- ram_fil_coefs_writedata_export => ram_fil_coefs_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_fil_coefs_read_export => ram_fil_coefs_mosi.rd,
- ram_fil_coefs_readdata_export => ram_fil_coefs_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_fil_coefs_address_export => ram_fil_coefs_copi.address(c_sdp_ram_fil_coefs_addr_w-1 DOWNTO 0),
+ ram_fil_coefs_write_export => ram_fil_coefs_copi.wr,
+ ram_fil_coefs_writedata_export => ram_fil_coefs_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_fil_coefs_read_export => ram_fil_coefs_copi.rd,
+ ram_fil_coefs_readdata_export => ram_fil_coefs_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_st_sst_clk_export => OPEN,
ram_st_sst_reset_export => OPEN,
- ram_st_sst_address_export => ram_st_sst_mosi.address(c_sdp_ram_st_sst_addr_w-1 DOWNTO 0),
- ram_st_sst_write_export => ram_st_sst_mosi.wr,
- ram_st_sst_writedata_export => ram_st_sst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_st_sst_read_export => ram_st_sst_mosi.rd,
- ram_st_sst_readdata_export => ram_st_sst_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_st_sst_address_export => ram_st_sst_copi.address(c_sdp_ram_st_sst_addr_w-1 DOWNTO 0),
+ ram_st_sst_write_export => ram_st_sst_copi.wr,
+ ram_st_sst_writedata_export => ram_st_sst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_st_sst_read_export => ram_st_sst_copi.rd,
+ ram_st_sst_readdata_export => ram_st_sst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_si_clk_export => OPEN,
reg_si_reset_export => OPEN,
- reg_si_address_export => reg_si_mosi.address(c_sdp_reg_si_addr_w-1 DOWNTO 0),
- reg_si_write_export => reg_si_mosi.wr,
- reg_si_writedata_export => reg_si_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_si_read_export => reg_si_mosi.rd,
- reg_si_readdata_export => reg_si_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_si_address_export => reg_si_copi.address(c_sdp_reg_si_addr_w-1 DOWNTO 0),
+ reg_si_write_export => reg_si_copi.wr,
+ reg_si_writedata_export => reg_si_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_si_read_export => reg_si_copi.rd,
+ reg_si_readdata_export => reg_si_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_equalizer_gains_clk_export => OPEN,
ram_equalizer_gains_reset_export => OPEN,
- ram_equalizer_gains_address_export => ram_equalizer_gains_mosi.address(c_sdp_ram_equalizer_gains_addr_w-1 DOWNTO 0),
- ram_equalizer_gains_write_export => ram_equalizer_gains_mosi.wr,
- ram_equalizer_gains_writedata_export => ram_equalizer_gains_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_equalizer_gains_read_export => ram_equalizer_gains_mosi.rd,
- ram_equalizer_gains_readdata_export => ram_equalizer_gains_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_equalizer_gains_address_export => ram_equalizer_gains_copi.address(c_sdp_ram_equalizer_gains_addr_w-1 DOWNTO 0),
+ ram_equalizer_gains_write_export => ram_equalizer_gains_copi.wr,
+ ram_equalizer_gains_writedata_export => ram_equalizer_gains_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_equalizer_gains_read_export => ram_equalizer_gains_copi.rd,
+ ram_equalizer_gains_readdata_export => ram_equalizer_gains_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_dp_selector_clk_export => OPEN,
reg_dp_selector_reset_export => OPEN,
- reg_dp_selector_address_export => reg_dp_selector_mosi.address(c_sdp_reg_dp_selector_addr_w-1 DOWNTO 0),
- reg_dp_selector_write_export => reg_dp_selector_mosi.wr,
- reg_dp_selector_writedata_export => reg_dp_selector_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_dp_selector_read_export => reg_dp_selector_mosi.rd,
- reg_dp_selector_readdata_export => reg_dp_selector_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_selector_address_export => reg_dp_selector_copi.address(c_sdp_reg_dp_selector_addr_w-1 DOWNTO 0),
+ reg_dp_selector_write_export => reg_dp_selector_copi.wr,
+ reg_dp_selector_writedata_export => reg_dp_selector_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_selector_read_export => reg_dp_selector_copi.rd,
+ reg_dp_selector_readdata_export => reg_dp_selector_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_sdp_info_clk_export => OPEN,
reg_sdp_info_reset_export => OPEN,
- reg_sdp_info_address_export => reg_sdp_info_mosi.address(c_sdp_reg_sdp_info_addr_w-1 DOWNTO 0),
- reg_sdp_info_write_export => reg_sdp_info_mosi.wr,
- reg_sdp_info_writedata_export => reg_sdp_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_sdp_info_read_export => reg_sdp_info_mosi.rd,
- reg_sdp_info_readdata_export => reg_sdp_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_sdp_info_address_export => reg_sdp_info_copi.address(c_sdp_reg_sdp_info_addr_w-1 DOWNTO 0),
+ reg_sdp_info_write_export => reg_sdp_info_copi.wr,
+ reg_sdp_info_writedata_export => reg_sdp_info_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_sdp_info_read_export => reg_sdp_info_copi.rd,
+ reg_sdp_info_readdata_export => reg_sdp_info_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_ring_info_clk_export => OPEN,
reg_ring_info_reset_export => OPEN,
@@ -785,147 +799,147 @@ BEGIN
ram_ss_ss_wide_clk_export => OPEN,
ram_ss_ss_wide_reset_export => OPEN,
- ram_ss_ss_wide_address_export => ram_ss_ss_wide_mosi.address(c_sdp_ram_ss_ss_wide_addr_w-1 DOWNTO 0),
- ram_ss_ss_wide_write_export => ram_ss_ss_wide_mosi.wr,
- ram_ss_ss_wide_writedata_export => ram_ss_ss_wide_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_ss_ss_wide_read_export => ram_ss_ss_wide_mosi.rd,
- ram_ss_ss_wide_readdata_export => ram_ss_ss_wide_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_ss_ss_wide_address_export => ram_ss_ss_wide_copi.address(c_sdp_ram_ss_ss_wide_addr_w-1 DOWNTO 0),
+ ram_ss_ss_wide_write_export => ram_ss_ss_wide_copi.wr,
+ ram_ss_ss_wide_writedata_export => ram_ss_ss_wide_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_ss_ss_wide_read_export => ram_ss_ss_wide_copi.rd,
+ ram_ss_ss_wide_readdata_export => ram_ss_ss_wide_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_bf_weights_clk_export => OPEN,
ram_bf_weights_reset_export => OPEN,
- ram_bf_weights_address_export => ram_bf_weights_mosi.address(c_sdp_ram_bf_weights_addr_w-1 DOWNTO 0),
- ram_bf_weights_write_export => ram_bf_weights_mosi.wr,
- ram_bf_weights_writedata_export => ram_bf_weights_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_bf_weights_read_export => ram_bf_weights_mosi.rd,
- ram_bf_weights_readdata_export => ram_bf_weights_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_bf_weights_address_export => ram_bf_weights_copi.address(c_sdp_ram_bf_weights_addr_w-1 DOWNTO 0),
+ ram_bf_weights_write_export => ram_bf_weights_copi.wr,
+ ram_bf_weights_writedata_export => ram_bf_weights_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_bf_weights_read_export => ram_bf_weights_copi.rd,
+ ram_bf_weights_readdata_export => ram_bf_weights_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_bf_scale_clk_export => OPEN,
reg_bf_scale_reset_export => OPEN,
- reg_bf_scale_address_export => reg_bf_scale_mosi.address(c_sdp_reg_bf_scale_addr_w-1 DOWNTO 0),
- reg_bf_scale_write_export => reg_bf_scale_mosi.wr,
- reg_bf_scale_writedata_export => reg_bf_scale_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_bf_scale_read_export => reg_bf_scale_mosi.rd,
- reg_bf_scale_readdata_export => reg_bf_scale_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_bf_scale_address_export => reg_bf_scale_copi.address(c_sdp_reg_bf_scale_addr_w-1 DOWNTO 0),
+ reg_bf_scale_write_export => reg_bf_scale_copi.wr,
+ reg_bf_scale_writedata_export => reg_bf_scale_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bf_scale_read_export => reg_bf_scale_copi.rd,
+ reg_bf_scale_readdata_export => reg_bf_scale_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_hdr_dat_clk_export => OPEN,
reg_hdr_dat_reset_export => OPEN,
- reg_hdr_dat_address_export => reg_hdr_dat_mosi.address(c_sdp_reg_bf_hdr_dat_addr_w-1 DOWNTO 0),
- reg_hdr_dat_write_export => reg_hdr_dat_mosi.wr,
- reg_hdr_dat_writedata_export => reg_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_hdr_dat_read_export => reg_hdr_dat_mosi.rd,
- reg_hdr_dat_readdata_export => reg_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_hdr_dat_address_export => reg_hdr_dat_copi.address(c_sdp_reg_bf_hdr_dat_addr_w-1 DOWNTO 0),
+ reg_hdr_dat_write_export => reg_hdr_dat_copi.wr,
+ reg_hdr_dat_writedata_export => reg_hdr_dat_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_hdr_dat_read_export => reg_hdr_dat_copi.rd,
+ reg_hdr_dat_readdata_export => reg_hdr_dat_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_dp_xonoff_clk_export => OPEN,
reg_dp_xonoff_reset_export => OPEN,
- reg_dp_xonoff_address_export => reg_dp_xonoff_mosi.address(c_sdp_reg_dp_xonoff_addr_w-1 DOWNTO 0),
- reg_dp_xonoff_write_export => reg_dp_xonoff_mosi.wr,
- reg_dp_xonoff_writedata_export => reg_dp_xonoff_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_dp_xonoff_read_export => reg_dp_xonoff_mosi.rd,
- reg_dp_xonoff_readdata_export => reg_dp_xonoff_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_xonoff_address_export => reg_dp_xonoff_copi.address(c_sdp_reg_dp_xonoff_addr_w-1 DOWNTO 0),
+ reg_dp_xonoff_write_export => reg_dp_xonoff_copi.wr,
+ reg_dp_xonoff_writedata_export => reg_dp_xonoff_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_xonoff_read_export => reg_dp_xonoff_copi.rd,
+ reg_dp_xonoff_readdata_export => reg_dp_xonoff_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_st_bst_clk_export => OPEN,
ram_st_bst_reset_export => OPEN,
- ram_st_bst_address_export => ram_st_bst_mosi.address(c_sdp_ram_st_bst_addr_w-1 DOWNTO 0),
- ram_st_bst_write_export => ram_st_bst_mosi.wr,
- ram_st_bst_writedata_export => ram_st_bst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_st_bst_read_export => ram_st_bst_mosi.rd,
- ram_st_bst_readdata_export => ram_st_bst_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_st_bst_address_export => ram_st_bst_copi.address(c_sdp_ram_st_bst_addr_w-1 DOWNTO 0),
+ ram_st_bst_write_export => ram_st_bst_copi.wr,
+ ram_st_bst_writedata_export => ram_st_bst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_st_bst_read_export => ram_st_bst_copi.rd,
+ ram_st_bst_readdata_export => ram_st_bst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_enable_sst_clk_export => OPEN,
reg_stat_enable_sst_reset_export => OPEN,
- reg_stat_enable_sst_address_export => reg_stat_enable_sst_mosi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
- reg_stat_enable_sst_write_export => reg_stat_enable_sst_mosi.wr,
- reg_stat_enable_sst_writedata_export => reg_stat_enable_sst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_enable_sst_read_export => reg_stat_enable_sst_mosi.rd,
- reg_stat_enable_sst_readdata_export => reg_stat_enable_sst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_sst_address_export => reg_stat_enable_sst_copi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
+ reg_stat_enable_sst_write_export => reg_stat_enable_sst_copi.wr,
+ reg_stat_enable_sst_writedata_export => reg_stat_enable_sst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_sst_read_export => reg_stat_enable_sst_copi.rd,
+ reg_stat_enable_sst_readdata_export => reg_stat_enable_sst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_hdr_dat_sst_clk_export => OPEN,
reg_stat_hdr_dat_sst_reset_export => OPEN,
- reg_stat_hdr_dat_sst_address_export => reg_stat_hdr_dat_sst_mosi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
- reg_stat_hdr_dat_sst_write_export => reg_stat_hdr_dat_sst_mosi.wr,
- reg_stat_hdr_dat_sst_writedata_export => reg_stat_hdr_dat_sst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_hdr_dat_sst_read_export => reg_stat_hdr_dat_sst_mosi.rd,
- reg_stat_hdr_dat_sst_readdata_export => reg_stat_hdr_dat_sst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_sst_address_export => reg_stat_hdr_dat_sst_copi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_sst_write_export => reg_stat_hdr_dat_sst_copi.wr,
+ reg_stat_hdr_dat_sst_writedata_export => reg_stat_hdr_dat_sst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_sst_read_export => reg_stat_hdr_dat_sst_copi.rd,
+ reg_stat_hdr_dat_sst_readdata_export => reg_stat_hdr_dat_sst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_enable_xst_clk_export => OPEN,
reg_stat_enable_xst_reset_export => OPEN,
- reg_stat_enable_xst_address_export => reg_stat_enable_xst_mosi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
- reg_stat_enable_xst_write_export => reg_stat_enable_xst_mosi.wr,
- reg_stat_enable_xst_writedata_export => reg_stat_enable_xst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_enable_xst_read_export => reg_stat_enable_xst_mosi.rd,
- reg_stat_enable_xst_readdata_export => reg_stat_enable_xst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_xst_address_export => reg_stat_enable_xst_copi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
+ reg_stat_enable_xst_write_export => reg_stat_enable_xst_copi.wr,
+ reg_stat_enable_xst_writedata_export => reg_stat_enable_xst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_xst_read_export => reg_stat_enable_xst_copi.rd,
+ reg_stat_enable_xst_readdata_export => reg_stat_enable_xst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_hdr_dat_xst_clk_export => OPEN,
reg_stat_hdr_dat_xst_reset_export => OPEN,
- reg_stat_hdr_dat_xst_address_export => reg_stat_hdr_dat_xst_mosi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
- reg_stat_hdr_dat_xst_write_export => reg_stat_hdr_dat_xst_mosi.wr,
- reg_stat_hdr_dat_xst_writedata_export => reg_stat_hdr_dat_xst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_hdr_dat_xst_read_export => reg_stat_hdr_dat_xst_mosi.rd,
- reg_stat_hdr_dat_xst_readdata_export => reg_stat_hdr_dat_xst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_xst_address_export => reg_stat_hdr_dat_xst_copi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_xst_write_export => reg_stat_hdr_dat_xst_copi.wr,
+ reg_stat_hdr_dat_xst_writedata_export => reg_stat_hdr_dat_xst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_xst_read_export => reg_stat_hdr_dat_xst_copi.rd,
+ reg_stat_hdr_dat_xst_readdata_export => reg_stat_hdr_dat_xst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_enable_bst_clk_export => OPEN,
reg_stat_enable_bst_reset_export => OPEN,
- reg_stat_enable_bst_address_export => reg_stat_enable_bst_mosi.address(c_sdp_reg_stat_enable_bst_addr_w-1 DOWNTO 0),
- reg_stat_enable_bst_write_export => reg_stat_enable_bst_mosi.wr,
- reg_stat_enable_bst_writedata_export => reg_stat_enable_bst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_enable_bst_read_export => reg_stat_enable_bst_mosi.rd,
- reg_stat_enable_bst_readdata_export => reg_stat_enable_bst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_bst_address_export => reg_stat_enable_bst_copi.address(c_sdp_reg_stat_enable_bst_addr_w-1 DOWNTO 0),
+ reg_stat_enable_bst_write_export => reg_stat_enable_bst_copi.wr,
+ reg_stat_enable_bst_writedata_export => reg_stat_enable_bst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_bst_read_export => reg_stat_enable_bst_copi.rd,
+ reg_stat_enable_bst_readdata_export => reg_stat_enable_bst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_hdr_dat_bst_clk_export => OPEN,
reg_stat_hdr_dat_bst_reset_export => OPEN,
- reg_stat_hdr_dat_bst_address_export => reg_stat_hdr_dat_bst_mosi.address(c_sdp_reg_stat_hdr_dat_bst_addr_w-1 DOWNTO 0),
- reg_stat_hdr_dat_bst_write_export => reg_stat_hdr_dat_bst_mosi.wr,
- reg_stat_hdr_dat_bst_writedata_export => reg_stat_hdr_dat_bst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_hdr_dat_bst_read_export => reg_stat_hdr_dat_bst_mosi.rd,
- reg_stat_hdr_dat_bst_readdata_export => reg_stat_hdr_dat_bst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_bst_address_export => reg_stat_hdr_dat_bst_copi.address(c_sdp_reg_stat_hdr_dat_bst_addr_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_bst_write_export => reg_stat_hdr_dat_bst_copi.wr,
+ reg_stat_hdr_dat_bst_writedata_export => reg_stat_hdr_dat_bst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_bst_read_export => reg_stat_hdr_dat_bst_copi.rd,
+ reg_stat_hdr_dat_bst_readdata_export => reg_stat_hdr_dat_bst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_crosslets_info_clk_export => OPEN,
reg_crosslets_info_reset_export => OPEN,
- reg_crosslets_info_address_export => reg_crosslets_info_mosi.address(c_sdp_reg_crosslets_info_addr_w-1 DOWNTO 0),
- reg_crosslets_info_write_export => reg_crosslets_info_mosi.wr,
- reg_crosslets_info_writedata_export => reg_crosslets_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_crosslets_info_read_export => reg_crosslets_info_mosi.rd,
- reg_crosslets_info_readdata_export => reg_crosslets_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_crosslets_info_address_export => reg_crosslets_info_copi.address(c_sdp_reg_crosslets_info_addr_w-1 DOWNTO 0),
+ reg_crosslets_info_write_export => reg_crosslets_info_copi.wr,
+ reg_crosslets_info_writedata_export => reg_crosslets_info_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_crosslets_info_read_export => reg_crosslets_info_copi.rd,
+ reg_crosslets_info_readdata_export => reg_crosslets_info_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_nof_crosslets_clk_export => OPEN,
reg_nof_crosslets_reset_export => OPEN,
- reg_nof_crosslets_address_export => reg_nof_crosslets_mosi.address(c_sdp_reg_nof_crosslets_addr_w-1 DOWNTO 0),
- reg_nof_crosslets_write_export => reg_nof_crosslets_mosi.wr,
- reg_nof_crosslets_writedata_export => reg_nof_crosslets_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_nof_crosslets_read_export => reg_nof_crosslets_mosi.rd,
- reg_nof_crosslets_readdata_export => reg_nof_crosslets_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_nof_crosslets_address_export => reg_nof_crosslets_copi.address(c_sdp_reg_nof_crosslets_addr_w-1 DOWNTO 0),
+ reg_nof_crosslets_write_export => reg_nof_crosslets_copi.wr,
+ reg_nof_crosslets_writedata_export => reg_nof_crosslets_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_nof_crosslets_read_export => reg_nof_crosslets_copi.rd,
+ reg_nof_crosslets_readdata_export => reg_nof_crosslets_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_bsn_sync_scheduler_xsub_clk_export => OPEN,
reg_bsn_sync_scheduler_xsub_reset_export => OPEN,
- reg_bsn_sync_scheduler_xsub_address_export => reg_bsn_sync_scheduler_xsub_mosi.address(c_sdp_reg_bsn_sync_scheduler_xsub_addr_w-1 DOWNTO 0),
- reg_bsn_sync_scheduler_xsub_write_export => reg_bsn_sync_scheduler_xsub_mosi.wr,
- reg_bsn_sync_scheduler_xsub_writedata_export => reg_bsn_sync_scheduler_xsub_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_bsn_sync_scheduler_xsub_read_export => reg_bsn_sync_scheduler_xsub_mosi.rd,
- reg_bsn_sync_scheduler_xsub_readdata_export => reg_bsn_sync_scheduler_xsub_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_sync_scheduler_xsub_address_export => reg_bsn_sync_scheduler_xsub_copi.address(c_sdp_reg_bsn_sync_scheduler_xsub_addr_w-1 DOWNTO 0),
+ reg_bsn_sync_scheduler_xsub_write_export => reg_bsn_sync_scheduler_xsub_copi.wr,
+ reg_bsn_sync_scheduler_xsub_writedata_export => reg_bsn_sync_scheduler_xsub_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_sync_scheduler_xsub_read_export => reg_bsn_sync_scheduler_xsub_copi.rd,
+ reg_bsn_sync_scheduler_xsub_readdata_export => reg_bsn_sync_scheduler_xsub_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_st_xsq_clk_export => OPEN,
ram_st_xsq_reset_export => OPEN,
- ram_st_xsq_address_export => ram_st_xsq_mosi.address(c_sdp_ram_st_xsq_arr_addr_w-1 DOWNTO 0),
- ram_st_xsq_write_export => ram_st_xsq_mosi.wr,
- ram_st_xsq_writedata_export => ram_st_xsq_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_st_xsq_read_export => ram_st_xsq_mosi.rd,
- ram_st_xsq_readdata_export => ram_st_xsq_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_st_xsq_address_export => ram_st_xsq_copi.address(c_sdp_ram_st_xsq_arr_addr_w-1 DOWNTO 0),
+ ram_st_xsq_write_export => ram_st_xsq_copi.wr,
+ ram_st_xsq_writedata_export => ram_st_xsq_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_st_xsq_read_export => ram_st_xsq_copi.rd,
+ ram_st_xsq_readdata_export => ram_st_xsq_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_nw_10GbE_mac_clk_export => OPEN,
reg_nw_10GbE_mac_reset_export => OPEN,
- reg_nw_10GbE_mac_address_export => reg_nw_10GbE_mac_mosi.address(c_sdp_reg_nw_10GbE_mac_addr_w-1 DOWNTO 0),
- reg_nw_10GbE_mac_write_export => reg_nw_10GbE_mac_mosi.wr,
- reg_nw_10GbE_mac_writedata_export => reg_nw_10GbE_mac_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_nw_10GbE_mac_read_export => reg_nw_10GbE_mac_mosi.rd,
- reg_nw_10GbE_mac_readdata_export => reg_nw_10GbE_mac_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_nw_10GbE_mac_address_export => reg_nw_10GbE_mac_copi.address(c_sdp_reg_nw_10GbE_mac_addr_w-1 DOWNTO 0),
+ reg_nw_10GbE_mac_write_export => reg_nw_10GbE_mac_copi.wr,
+ reg_nw_10GbE_mac_writedata_export => reg_nw_10GbE_mac_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_nw_10GbE_mac_read_export => reg_nw_10GbE_mac_copi.rd,
+ reg_nw_10GbE_mac_readdata_export => reg_nw_10GbE_mac_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_nw_10GbE_eth10g_clk_export => OPEN,
reg_nw_10GbE_eth10g_reset_export => OPEN,
- reg_nw_10GbE_eth10g_address_export => reg_nw_10GbE_eth10g_mosi.address(c_sdp_reg_nw_10GbE_eth10g_addr_w-1 DOWNTO 0),
- reg_nw_10GbE_eth10g_write_export => reg_nw_10GbE_eth10g_mosi.wr,
- reg_nw_10GbE_eth10g_writedata_export => reg_nw_10GbE_eth10g_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_nw_10GbE_eth10g_read_export => reg_nw_10GbE_eth10g_mosi.rd,
- reg_nw_10GbE_eth10g_readdata_export => reg_nw_10GbE_eth10g_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_nw_10GbE_eth10g_address_export => reg_nw_10GbE_eth10g_copi.address(c_sdp_reg_nw_10GbE_eth10g_addr_w-1 DOWNTO 0),
+ reg_nw_10GbE_eth10g_write_export => reg_nw_10GbE_eth10g_copi.wr,
+ reg_nw_10GbE_eth10g_writedata_export => reg_nw_10GbE_eth10g_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_nw_10GbE_eth10g_read_export => reg_nw_10GbE_eth10g_copi.rd,
+ reg_nw_10GbE_eth10g_readdata_export => reg_nw_10GbE_eth10g_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_bsn_align_v2_clk_export => OPEN,
reg_bsn_align_v2_reset_export => OPEN,
@@ -951,6 +965,22 @@ BEGIN
reg_bsn_monitor_v2_bsn_align_v2_output_read_export => reg_bsn_monitor_v2_bsn_align_v2_output_copi.rd,
reg_bsn_monitor_v2_bsn_align_v2_output_readdata_export => reg_bsn_monitor_v2_bsn_align_v2_output_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_sst_offload_clk_export => OPEN,
+ reg_bsn_monitor_v2_sst_offload_reset_export => OPEN,
+ reg_bsn_monitor_v2_sst_offload_address_export => reg_bsn_monitor_v2_sst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_sst_offload_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_sst_offload_write_export => reg_bsn_monitor_v2_sst_offload_copi.wr,
+ reg_bsn_monitor_v2_sst_offload_writedata_export => reg_bsn_monitor_v2_sst_offload_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_sst_offload_read_export => reg_bsn_monitor_v2_sst_offload_copi.rd,
+ reg_bsn_monitor_v2_sst_offload_readdata_export => reg_bsn_monitor_v2_sst_offload_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_bst_offload_clk_export => OPEN,
+ reg_bsn_monitor_v2_bst_offload_reset_export => OPEN,
+ reg_bsn_monitor_v2_bst_offload_address_export => reg_bsn_monitor_v2_bst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_bst_offload_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_bst_offload_write_export => reg_bsn_monitor_v2_bst_offload_copi.wr,
+ reg_bsn_monitor_v2_bst_offload_writedata_export => reg_bsn_monitor_v2_bst_offload_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_bst_offload_read_export => reg_bsn_monitor_v2_bst_offload_copi.rd,
+ reg_bsn_monitor_v2_bst_offload_readdata_export => reg_bsn_monitor_v2_bst_offload_cipo.rddata(c_word_w-1 DOWNTO 0),
+
reg_bsn_monitor_v2_xst_offload_clk_export => OPEN,
reg_bsn_monitor_v2_xst_offload_reset_export => OPEN,
reg_bsn_monitor_v2_xst_offload_address_export => reg_bsn_monitor_v2_xst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_xst_offload_addr_w-1 DOWNTO 0),
@@ -1017,11 +1047,11 @@ BEGIN
ram_scrap_clk_export => OPEN,
ram_scrap_reset_export => OPEN,
- ram_scrap_address_export => ram_scrap_mosi.address(9-1 DOWNTO 0),
- ram_scrap_write_export => ram_scrap_mosi.wr,
- ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_scrap_read_export => ram_scrap_mosi.rd,
- ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w-1 DOWNTO 0)
+ ram_scrap_address_export => ram_scrap_copi.address(9-1 DOWNTO 0),
+ ram_scrap_write_export => ram_scrap_copi.wr,
+ ram_scrap_writedata_export => ram_scrap_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_scrap_read_export => ram_scrap_copi.rd,
+ ram_scrap_readdata_export => ram_scrap_cipo.rddata(c_word_w-1 DOWNTO 0)
);
END GENERATE;
END str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
index f6a22135a9c37dd3b307b6d11191e56656552c8d..abd9fb9b616577f2224fd1531dd99b32e01ddf08 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
@@ -234,7 +234,14 @@ peripherals:
peripheral_group: sst
mm_port_names:
- REG_STAT_HDR_DAT_SST
-
+
+ - peripheral_name: dp/dp_bsn_monitor_v2
+ peripheral_group: sst_udp
+ parameter_overrides:
+ - { name: g_nof_streams, value: 1 }
+ mm_port_names:
+ - REG_BSN_MONITOR_V2_SST_OFFLOAD
+
#############################################################################
# Xsub = Subband Correlator (from node_sdp_correlator.vhd)
#############################################################################
@@ -416,5 +423,11 @@ peripherals:
mm_port_names:
- REG_NW_10GBE_ETH10G
-
+ - peripheral_name: dp/dp_bsn_monitor_v2
+ peripheral_group: bst_udp
+ number_of_peripherals: c_N_beamsets
+ parameter_overrides:
+ - { name: g_nof_streams, value: 1 }
+ mm_port_names:
+ - REG_BSN_MONITOR_V2_BST_OFFLOAD
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
index 45baadee029688b91db26f4e13b0c6a81ead2a91..97b4b2b1927ba29db70beb27db43bf9b55ed29d7 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
@@ -141,262 +141,268 @@ ARCHITECTURE str OF lofar2_unb2c_sdp_station IS
SIGNAL pout_wdi : STD_LOGIC;
-- WDI override
- SIGNAL reg_wdi_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_wdi_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_wdi_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_wdi_cipo : t_mem_cipo := c_mem_cipo_rst;
-- PPSH
- SIGNAL reg_ppsh_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_ppsh_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_ppsh_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_ppsh_cipo : t_mem_cipo := c_mem_cipo_rst;
-- UniBoard system info
- SIGNAL reg_unb_system_info_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_unb_system_info_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL rom_unb_system_info_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL rom_unb_system_info_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_unb_system_info_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_unb_system_info_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL rom_unb_system_info_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL rom_unb_system_info_cipo : t_mem_cipo := c_mem_cipo_rst;
-- FPGA sensors
- SIGNAL reg_fpga_temp_sens_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_fpga_temp_sens_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_fpga_voltage_sens_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_fpga_voltage_sens_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_fpga_temp_sens_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_fpga_temp_sens_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_fpga_voltage_sens_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_fpga_voltage_sens_cipo : t_mem_cipo := c_mem_cipo_rst;
-- eth1g
SIGNAL eth1g_mm_rst : STD_LOGIC;
- SIGNAL eth1g_tse_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH TSE MAC registers
- SIGNAL eth1g_tse_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL eth1g_reg_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH control and status registers
- SIGNAL eth1g_reg_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL eth1g_tse_copi : t_mem_copi := c_mem_copi_rst; -- ETH TSE MAC registers
+ SIGNAL eth1g_tse_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL eth1g_reg_copi : t_mem_copi := c_mem_copi_rst; -- ETH control and status registers
+ SIGNAL eth1g_reg_cipo : t_mem_cipo := c_mem_cipo_rst;
SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
- SIGNAL eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH rx frame and tx frame memory
- SIGNAL eth1g_ram_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL eth1g_ram_copi : t_mem_copi := c_mem_copi_rst; -- ETH rx frame and tx frame memory
+ SIGNAL eth1g_ram_cipo : t_mem_cipo := c_mem_cipo_rst;
-- EPCS read
- SIGNAL reg_dpmm_data_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dpmm_data_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dpmm_ctrl_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_dpmm_data_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dpmm_data_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_dpmm_ctrl_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dpmm_ctrl_cipo : t_mem_cipo := c_mem_cipo_rst;
-- EPCS write
- SIGNAL reg_mmdp_data_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_mmdp_data_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_mmdp_ctrl_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_mmdp_data_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_mmdp_data_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_mmdp_ctrl_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_mmdp_ctrl_cipo : t_mem_cipo := c_mem_cipo_rst;
-- EPCS status/control
- SIGNAL reg_epcs_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_epcs_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_epcs_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_epcs_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Remote Update
- SIGNAL reg_remu_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_remu_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_remu_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_remu_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Scrap ram
- SIGNAL ram_scrap_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_scrap_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_scrap_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_scrap_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- AIT
----------------------------------------------
-- JESD
- SIGNAL jesd204b_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL jesd204b_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL jesd204b_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL jesd204b_cipo : t_mem_cipo := c_mem_cipo_rst;
-- JESD control
- SIGNAL jesd_ctrl_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL jesd_ctrl_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL jesd_ctrl_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL jesd_ctrl_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Shiftram (applies per-antenna delay)
- SIGNAL reg_dp_shiftram_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dp_shiftram_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_dp_shiftram_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dp_shiftram_cipo : t_mem_cipo := c_mem_cipo_rst;
-- bsn source
- SIGNAL reg_bsn_source_v2_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bsn_source_v2_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bsn_source_v2_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_source_v2_cipo : t_mem_cipo := c_mem_cipo_rst;
-- bsn scheduler
- SIGNAL reg_bsn_scheduler_wg_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bsn_scheduler_wg_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bsn_scheduler_wg_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_scheduler_wg_cipo : t_mem_cipo := c_mem_cipo_rst;
-- WG
- SIGNAL reg_wg_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_wg_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL ram_wg_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_wg_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_wg_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_wg_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL ram_wg_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_wg_cipo : t_mem_cipo := c_mem_cipo_rst;
-- BSN MONITOR
- SIGNAL reg_bsn_monitor_input_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bsn_monitor_input_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bsn_monitor_input_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_input_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Data buffer bsn
- SIGNAL ram_diag_data_buf_bsn_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_diag_data_buf_bsn_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_diag_data_buf_bsn_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_diag_data_buf_bsn_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_diag_data_buf_bsn_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_diag_data_buf_bsn_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_diag_data_buf_bsn_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_diag_data_buf_bsn_cipo : t_mem_cipo := c_mem_cipo_rst;
-- ST Histogram
- SIGNAL ram_st_histogram_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_st_histogram_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_st_histogram_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_st_histogram_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Aduh statistics monitor
- SIGNAL reg_aduh_monitor_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_aduh_monitor_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_aduh_monitor_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_aduh_monitor_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- FSUB
----------------------------------------------
-- Subband statistics
- SIGNAL ram_st_sst_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_st_sst_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_st_sst_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_st_sst_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Spectral Inversion
- SIGNAL reg_si_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_si_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_si_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_si_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Filter coefficients
- SIGNAL ram_fil_coefs_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_fil_coefs_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_fil_coefs_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_fil_coefs_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Equalizer gains
- SIGNAL ram_equalizer_gains_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_equalizer_gains_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_equalizer_gains_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_equalizer_gains_cipo : t_mem_cipo := c_mem_cipo_rst;
-- DP Selector
- SIGNAL reg_dp_selector_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dp_selector_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_dp_selector_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dp_selector_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- SDP Info
----------------------------------------------
- SIGNAL reg_sdp_info_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_sdp_info_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_sdp_info_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_sdp_info_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- RING Info
----------------------------------------------
- SIGNAL reg_ring_info_copi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_ring_info_cipo : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_ring_info_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_ring_info_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- XSUB
----------------------------------------------
-- crosslets_info
- SIGNAL reg_crosslets_info_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_crosslets_info_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_crosslets_info_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_crosslets_info_cipo : t_mem_cipo := c_mem_cipo_rst;
-- crosslets_info
- SIGNAL reg_nof_crosslets_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_nof_crosslets_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_nof_crosslets_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_nof_crosslets_cipo : t_mem_cipo := c_mem_cipo_rst;
-- bsn_scheduler_xsub
- SIGNAL reg_bsn_sync_scheduler_xsub_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bsn_sync_scheduler_xsub_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bsn_sync_scheduler_xsub_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_sync_scheduler_xsub_cipo : t_mem_cipo := c_mem_cipo_rst;
-- st_xsq
- SIGNAL ram_st_xsq_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_st_xsq_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_st_xsq_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_st_xsq_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- BF
----------------------------------------------
-- Beamlet Subband Select
- SIGNAL ram_ss_ss_wide_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_ss_ss_wide_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_ss_ss_wide_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_ss_ss_wide_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Local BF bf weights
- SIGNAL ram_bf_weights_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_bf_weights_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_bf_weights_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_bf_weights_cipo : t_mem_cipo := c_mem_cipo_rst;
-- mms_dp_scale Scale Beamlets
- SIGNAL reg_bf_scale_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bf_scale_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bf_scale_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bf_scale_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Beamlet Data Output header fields
- SIGNAL reg_hdr_dat_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_hdr_dat_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_hdr_dat_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_hdr_dat_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Beamlet Data Output xonoff
- SIGNAL reg_dp_xonoff_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dp_xonoff_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_dp_xonoff_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dp_xonoff_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Beamlet Statistics (BST)
- SIGNAL ram_st_bst_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_st_bst_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_st_bst_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_st_bst_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- SST
----------------------------------------------
-- Statistics Enable
- SIGNAL reg_stat_enable_sst_mosi : t_mem_mosi;
- SIGNAL reg_stat_enable_sst_miso : t_mem_miso;
+ SIGNAL reg_stat_enable_sst_copi : t_mem_copi;
+ SIGNAL reg_stat_enable_sst_cipo : t_mem_cipo;
-- Statistics header info
- SIGNAL reg_stat_hdr_dat_sst_mosi : t_mem_mosi;
- SIGNAL reg_stat_hdr_dat_sst_miso : t_mem_miso;
+ SIGNAL reg_stat_hdr_dat_sst_copi : t_mem_copi;
+ SIGNAL reg_stat_hdr_dat_sst_cipo : t_mem_cipo;
+ -- SST UDP offload bsn monitor
+ SIGNAL reg_bsn_monitor_v2_sst_offload_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_sst_offload_cipo : t_mem_cipo;
----------------------------------------------
-- XST
----------------------------------------------
-- Statistics Enable
- SIGNAL reg_stat_enable_xst_mosi : t_mem_mosi;
- SIGNAL reg_stat_enable_xst_miso : t_mem_miso;
+ SIGNAL reg_stat_enable_xst_copi : t_mem_copi;
+ SIGNAL reg_stat_enable_xst_cipo : t_mem_cipo;
-- Statistics header info
- SIGNAL reg_stat_hdr_dat_xst_mosi : t_mem_mosi;
- SIGNAL reg_stat_hdr_dat_xst_miso : t_mem_miso;
+ SIGNAL reg_stat_hdr_dat_xst_copi : t_mem_copi;
+ SIGNAL reg_stat_hdr_dat_xst_cipo : t_mem_cipo;
-- XST bsn aligner_v2
- SIGNAL reg_bsn_align_v2_copi : t_mem_mosi;
- SIGNAL reg_bsn_align_v2_cipo : t_mem_miso;
+ SIGNAL reg_bsn_align_v2_copi : t_mem_copi;
+ SIGNAL reg_bsn_align_v2_cipo : t_mem_cipo;
-- XST bsn aligner_v2 bsn monitors
- SIGNAL reg_bsn_monitor_v2_bsn_align_v2_input_copi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_v2_bsn_align_v2_input_cipo : t_mem_miso;
- SIGNAL reg_bsn_monitor_v2_bsn_align_v2_output_copi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_v2_bsn_align_v2_output_cipo : t_mem_miso;
+ SIGNAL reg_bsn_monitor_v2_bsn_align_v2_input_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_bsn_align_v2_input_cipo : t_mem_cipo;
+ SIGNAL reg_bsn_monitor_v2_bsn_align_v2_output_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_bsn_align_v2_output_cipo : t_mem_cipo;
-- XST UDP offload bsn monitor
- SIGNAL reg_bsn_monitor_v2_xst_offload_copi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_v2_xst_offload_cipo : t_mem_miso;
+ SIGNAL reg_bsn_monitor_v2_xst_offload_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_xst_offload_cipo : t_mem_cipo;
-- XST ring lane info
- SIGNAL reg_ring_lane_info_xst_copi : t_mem_mosi;
- SIGNAL reg_ring_lane_info_xst_cipo : t_mem_miso;
+ SIGNAL reg_ring_lane_info_xst_copi : t_mem_copi;
+ SIGNAL reg_ring_lane_info_xst_cipo : t_mem_cipo;
-- XST ring bsn monitor rx
- SIGNAL reg_bsn_monitor_v2_ring_rx_xst_copi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_v2_ring_rx_xst_cipo : t_mem_miso;
+ SIGNAL reg_bsn_monitor_v2_ring_rx_xst_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_ring_rx_xst_cipo : t_mem_cipo;
-- XST ring bsn monitor tx
- SIGNAL reg_bsn_monitor_v2_ring_tx_xst_copi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_v2_ring_tx_xst_cipo : t_mem_miso;
+ SIGNAL reg_bsn_monitor_v2_ring_tx_xst_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_ring_tx_xst_cipo : t_mem_cipo;
-- XST ring validate err
- SIGNAL reg_dp_block_validate_err_xst_copi : t_mem_mosi;
- SIGNAL reg_dp_block_validate_err_xst_cipo : t_mem_miso;
+ SIGNAL reg_dp_block_validate_err_xst_copi : t_mem_copi;
+ SIGNAL reg_dp_block_validate_err_xst_cipo : t_mem_cipo;
-- XST ring bsn at sync
- SIGNAL reg_dp_block_validate_bsn_at_sync_xst_copi : t_mem_mosi;
- SIGNAL reg_dp_block_validate_bsn_at_sync_xst_cipo : t_mem_miso;
+ SIGNAL reg_dp_block_validate_bsn_at_sync_xst_copi : t_mem_copi;
+ SIGNAL reg_dp_block_validate_bsn_at_sync_xst_cipo : t_mem_cipo;
-- XST ring MAC10G
- SIGNAL reg_tr_10GbE_mac_copi : t_mem_mosi;
- SIGNAL reg_tr_10GbE_mac_cipo : t_mem_miso;
+ SIGNAL reg_tr_10GbE_mac_copi : t_mem_copi;
+ SIGNAL reg_tr_10GbE_mac_cipo : t_mem_cipo;
-- XST ring ETH10G
- SIGNAL reg_tr_10GbE_eth10g_copi : t_mem_mosi;
- SIGNAL reg_tr_10GbE_eth10g_cipo : t_mem_miso;
+ SIGNAL reg_tr_10GbE_eth10g_copi : t_mem_copi;
+ SIGNAL reg_tr_10GbE_eth10g_cipo : t_mem_cipo;
----------------------------------------------
-- BST
----------------------------------------------
-- Statistics Enable
- SIGNAL reg_stat_enable_bst_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_stat_enable_bst_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_stat_enable_bst_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_stat_enable_bst_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Statistics header info
- SIGNAL reg_stat_hdr_dat_bst_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_stat_hdr_dat_bst_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_stat_hdr_dat_bst_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_stat_hdr_dat_bst_cipo : t_mem_cipo := c_mem_cipo_rst;
+ -- BST UDP offload bsn monitor
+ SIGNAL reg_bsn_monitor_v2_bst_offload_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_bst_offload_cipo : t_mem_cipo;
----------------------------------------------
-- UDP Offload
----------------------------------------------
@@ -406,11 +412,11 @@ ARCHITECTURE str OF lofar2_unb2c_sdp_station IS
----------------------------------------------
-- 10 GbE
----------------------------------------------
- SIGNAL reg_nw_10GbE_mac_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_nw_10GbE_mac_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_nw_10GbE_mac_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_nw_10GbE_mac_cipo : t_mem_cipo := c_mem_cipo_rst;
- SIGNAL reg_nw_10GbE_eth10g_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_nw_10GbE_eth10g_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_nw_10GbE_eth10g_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_nw_10GbE_eth10g_cipo : t_mem_cipo := c_mem_cipo_rst;
-- 10GbE
SIGNAL i_QSFP_TX : t_unb2c_board_qsfp_bus_2arr(c_unb2c_board_tr_qsfp.nof_bus-1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
@@ -479,61 +485,61 @@ BEGIN
-- MM buses
-- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
+ reg_remu_mosi => reg_remu_copi,
+ reg_remu_miso => reg_remu_cipo,
-- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ reg_dpmm_data_mosi => reg_dpmm_data_copi,
+ reg_dpmm_data_miso => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
-- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ reg_mmdp_data_mosi => reg_mmdp_data_copi,
+ reg_mmdp_data_miso => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
-- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
+ reg_epcs_mosi => reg_epcs_copi,
+ reg_epcs_miso => reg_epcs_cipo,
-- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
+ reg_wdi_mosi => reg_wdi_copi,
+ reg_wdi_miso => reg_wdi_cipo,
-- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_copi,
+ reg_unb_system_info_miso => reg_unb_system_info_cipo,
+ rom_unb_system_info_mosi => rom_unb_system_info_copi,
+ rom_unb_system_info_miso => rom_unb_system_info_cipo,
-- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
-- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
+ reg_ppsh_mosi => reg_ppsh_copi,
+ reg_ppsh_miso => reg_ppsh_cipo,
-- eth1g
eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_tse_mosi => eth1g_tse_copi,
+ eth1g_tse_miso => eth1g_tse_cipo,
+ eth1g_reg_mosi => eth1g_reg_copi,
+ eth1g_reg_miso => eth1g_reg_cipo,
eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
+ eth1g_ram_mosi => eth1g_ram_copi,
+ eth1g_ram_miso => eth1g_ram_cipo,
-- eth1g UDP streaming
udp_tx_sosi_arr => udp_tx_sosi_arr,
udp_tx_siso_arr => udp_tx_siso_arr,
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
+ ram_scrap_mosi => ram_scrap_copi,
+ ram_scrap_miso => ram_scrap_cipo,
-- FPGA pins
-- . General
@@ -570,115 +576,115 @@ BEGIN
pout_wdi => pout_wdi,
-- mm interfaces for control
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
+ reg_wdi_copi => reg_wdi_copi,
+ reg_wdi_cipo => reg_wdi_cipo,
+ reg_unb_system_info_copi => reg_unb_system_info_copi,
+ reg_unb_system_info_cipo => reg_unb_system_info_cipo,
+ rom_unb_system_info_copi => rom_unb_system_info_copi,
+ rom_unb_system_info_cipo => rom_unb_system_info_cipo,
+ reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
+ reg_ppsh_copi => reg_ppsh_copi,
+ reg_ppsh_cipo => reg_ppsh_cipo,
eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_tse_copi => eth1g_tse_copi,
+ eth1g_tse_cipo => eth1g_tse_cipo,
+ eth1g_reg_copi => eth1g_reg_copi,
+ eth1g_reg_cipo => eth1g_reg_cipo,
eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
+ eth1g_ram_copi => eth1g_ram_copi,
+ eth1g_ram_cipo => eth1g_ram_cipo,
+ reg_dpmm_data_copi => reg_dpmm_data_copi,
+ reg_dpmm_data_cipo => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
+ reg_mmdp_data_copi => reg_mmdp_data_copi,
+ reg_mmdp_data_cipo => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
+ reg_epcs_copi => reg_epcs_copi,
+ reg_epcs_cipo => reg_epcs_cipo,
+ reg_remu_copi => reg_remu_copi,
+ reg_remu_cipo => reg_remu_cipo,
-- mm buses for signal flow blocks
-- Jesd ip status/control
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_v2_mosi => reg_bsn_source_v2_mosi,
- reg_bsn_source_v2_miso => reg_bsn_source_v2_miso,
- reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_st_histogram_mosi => ram_st_histogram_mosi,
- ram_st_histogram_miso => ram_st_histogram_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
- ram_equalizer_gains_miso => ram_equalizer_gains_miso,
- reg_dp_selector_mosi => reg_dp_selector_mosi,
- reg_dp_selector_miso => reg_dp_selector_miso,
- reg_sdp_info_mosi => reg_sdp_info_mosi,
- reg_sdp_info_miso => reg_sdp_info_miso,
+ jesd204b_copi => jesd204b_copi,
+ jesd204b_cipo => jesd204b_cipo,
+ jesd_ctrl_copi => jesd_ctrl_copi,
+ jesd_ctrl_cipo => jesd_ctrl_cipo,
+ reg_dp_shiftram_copi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_copi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_cipo => reg_bsn_scheduler_wg_cipo,
+ reg_wg_copi => reg_wg_copi,
+ reg_wg_cipo => reg_wg_cipo,
+ ram_wg_copi => ram_wg_copi,
+ ram_wg_cipo => ram_wg_cipo,
+ reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_copi => ram_st_histogram_copi,
+ ram_st_histogram_cipo => ram_st_histogram_cipo,
+ reg_aduh_monitor_copi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
+ ram_st_sst_copi => ram_st_sst_copi,
+ ram_st_sst_cipo => ram_st_sst_cipo,
+ ram_fil_coefs_copi => ram_fil_coefs_copi,
+ ram_fil_coefs_cipo => ram_fil_coefs_cipo,
+ reg_si_copi => reg_si_copi,
+ reg_si_cipo => reg_si_cipo,
+ ram_equalizer_gains_copi => ram_equalizer_gains_copi,
+ ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
+ reg_dp_selector_copi => reg_dp_selector_copi,
+ reg_dp_selector_cipo => reg_dp_selector_cipo,
+ reg_sdp_info_copi => reg_sdp_info_copi,
+ reg_sdp_info_cipo => reg_sdp_info_cipo,
reg_ring_info_copi => reg_ring_info_copi,
reg_ring_info_cipo => reg_ring_info_cipo,
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
- ram_bf_weights_mosi => ram_bf_weights_mosi,
- ram_bf_weights_miso => ram_bf_weights_miso,
- reg_bf_scale_mosi => reg_bf_scale_mosi,
- reg_bf_scale_miso => reg_bf_scale_miso,
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
- reg_dp_xonoff_miso => reg_dp_xonoff_miso,
- ram_st_bst_mosi => ram_st_bst_mosi,
- ram_st_bst_miso => ram_st_bst_miso,
- reg_nw_10GbE_mac_mosi => reg_nw_10GbE_mac_mosi,
- reg_nw_10GbE_mac_miso => reg_nw_10GbE_mac_miso,
- reg_nw_10GbE_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
- reg_nw_10GbE_eth10g_miso => reg_nw_10GbE_eth10g_miso,
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
- reg_stat_enable_sst_mosi => reg_stat_enable_sst_mosi,
- reg_stat_enable_sst_miso => reg_stat_enable_sst_miso,
- reg_stat_hdr_dat_sst_mosi => reg_stat_hdr_dat_sst_mosi,
- reg_stat_hdr_dat_sst_miso => reg_stat_hdr_dat_sst_miso,
- reg_stat_enable_xst_mosi => reg_stat_enable_xst_mosi,
- reg_stat_enable_xst_miso => reg_stat_enable_xst_miso,
- reg_stat_hdr_dat_xst_mosi => reg_stat_hdr_dat_xst_mosi,
- reg_stat_hdr_dat_xst_miso => reg_stat_hdr_dat_xst_miso,
- reg_stat_enable_bst_mosi => reg_stat_enable_bst_mosi,
- reg_stat_enable_bst_miso => reg_stat_enable_bst_miso,
- reg_stat_hdr_dat_bst_mosi => reg_stat_hdr_dat_bst_mosi,
- reg_stat_hdr_dat_bst_miso => reg_stat_hdr_dat_bst_miso,
- reg_crosslets_info_mosi => reg_crosslets_info_mosi,
- reg_crosslets_info_miso => reg_crosslets_info_miso,
- reg_nof_crosslets_mosi => reg_nof_crosslets_mosi,
- reg_nof_crosslets_miso => reg_nof_crosslets_miso,
- reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
- reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
+ ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
+ ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
+ ram_bf_weights_copi => ram_bf_weights_copi,
+ ram_bf_weights_cipo => ram_bf_weights_cipo,
+ reg_bf_scale_copi => reg_bf_scale_copi,
+ reg_bf_scale_cipo => reg_bf_scale_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_dp_xonoff_copi => reg_dp_xonoff_copi,
+ reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
+ ram_st_bst_copi => ram_st_bst_copi,
+ ram_st_bst_cipo => ram_st_bst_cipo,
+ reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
+ reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
+ reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
+ reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
+ ram_scrap_copi => ram_scrap_copi,
+ ram_scrap_cipo => ram_scrap_cipo,
+ reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
+ reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
+ reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
+ reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
+ reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
+ reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
+ reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
+ reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
+ reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
reg_bsn_align_v2_copi => reg_bsn_align_v2_copi,
reg_bsn_align_v2_cipo => reg_bsn_align_v2_cipo,
reg_bsn_monitor_v2_bsn_align_v2_input_copi => reg_bsn_monitor_v2_bsn_align_v2_input_copi,
@@ -687,6 +693,10 @@ BEGIN
reg_bsn_monitor_v2_bsn_align_v2_output_cipo => reg_bsn_monitor_v2_bsn_align_v2_output_cipo,
reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
@@ -701,8 +711,8 @@ BEGIN
reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
- ram_st_xsq_mosi => ram_st_xsq_mosi,
- ram_st_xsq_miso => ram_st_xsq_miso
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo
);
@@ -749,92 +759,94 @@ BEGIN
udp_tx_siso_arr => udp_tx_siso_arr,
-- 10 GbE
- reg_nw_10GbE_mac_mosi => reg_nw_10GbE_mac_mosi,
- reg_nw_10GbE_mac_miso => reg_nw_10GbE_mac_miso,
- reg_nw_10GbE_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
- reg_nw_10GbE_eth10g_miso => reg_nw_10GbE_eth10g_miso,
+ reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
+ reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
+ reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
+ reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
-- AIT
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_v2_mosi => reg_bsn_source_v2_mosi,
- reg_bsn_source_v2_miso => reg_bsn_source_v2_miso,
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_st_histogram_mosi => ram_st_histogram_mosi,
- ram_st_histogram_miso => ram_st_histogram_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+ jesd204b_copi => jesd204b_copi,
+ jesd204b_cipo => jesd204b_cipo,
+ jesd_ctrl_copi => jesd_ctrl_copi,
+ jesd_ctrl_cipo => jesd_ctrl_cipo,
+ reg_dp_shiftram_copi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_wg_copi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_wg_cipo => reg_bsn_scheduler_wg_cipo,
+ reg_wg_copi => reg_wg_copi,
+ reg_wg_cipo => reg_wg_cipo,
+ ram_wg_copi => ram_wg_copi,
+ ram_wg_cipo => ram_wg_cipo,
+ reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_copi => ram_st_histogram_copi,
+ ram_st_histogram_cipo => ram_st_histogram_cipo,
+ reg_aduh_monitor_copi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
-- FSUB
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
- ram_equalizer_gains_miso => ram_equalizer_gains_miso,
- reg_dp_selector_mosi => reg_dp_selector_mosi,
- reg_dp_selector_miso => reg_dp_selector_miso,
+ ram_st_sst_copi => ram_st_sst_copi,
+ ram_st_sst_cipo => ram_st_sst_cipo,
+ reg_si_copi => reg_si_copi,
+ reg_si_cipo => reg_si_cipo,
+ ram_fil_coefs_copi => ram_fil_coefs_copi,
+ ram_fil_coefs_cipo => ram_fil_coefs_cipo,
+ ram_equalizer_gains_copi => ram_equalizer_gains_copi,
+ ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
+ reg_dp_selector_copi => reg_dp_selector_copi,
+ reg_dp_selector_cipo => reg_dp_selector_cipo,
-- SDP Info
- reg_sdp_info_mosi => reg_sdp_info_mosi,
- reg_sdp_info_miso => reg_sdp_info_miso,
+ reg_sdp_info_copi => reg_sdp_info_copi,
+ reg_sdp_info_cipo => reg_sdp_info_cipo,
-- RING Info
reg_ring_info_copi => reg_ring_info_copi,
reg_ring_info_cipo => reg_ring_info_cipo,
-- XSUB
- reg_crosslets_info_mosi => reg_crosslets_info_mosi,
- reg_crosslets_info_miso => reg_crosslets_info_miso,
- reg_nof_crosslets_mosi => reg_nof_crosslets_mosi,
- reg_nof_crosslets_miso => reg_nof_crosslets_miso,
- reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
- reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
- ram_st_xsq_mosi => ram_st_xsq_mosi,
- ram_st_xsq_miso => ram_st_xsq_miso,
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo,
-- BF
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
- ram_bf_weights_mosi => ram_bf_weights_mosi,
- ram_bf_weights_miso => ram_bf_weights_miso,
- reg_bf_scale_mosi => reg_bf_scale_mosi,
- reg_bf_scale_miso => reg_bf_scale_miso,
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
- reg_dp_xonoff_miso => reg_dp_xonoff_miso,
- ram_st_bst_mosi => ram_st_bst_mosi,
- ram_st_bst_miso => ram_st_bst_miso,
+ ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
+ ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
+ ram_bf_weights_copi => ram_bf_weights_copi,
+ ram_bf_weights_cipo => ram_bf_weights_cipo,
+ reg_bf_scale_copi => reg_bf_scale_copi,
+ reg_bf_scale_cipo => reg_bf_scale_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_dp_xonoff_copi => reg_dp_xonoff_copi,
+ reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
+ ram_st_bst_copi => ram_st_bst_copi,
+ ram_st_bst_cipo => ram_st_bst_cipo,
-- SST
- reg_stat_enable_sst_mosi => reg_stat_enable_sst_mosi,
- reg_stat_enable_sst_miso => reg_stat_enable_sst_miso,
- reg_stat_hdr_dat_sst_mosi => reg_stat_hdr_dat_sst_mosi,
- reg_stat_hdr_dat_sst_miso => reg_stat_hdr_dat_sst_miso,
+ reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
+ reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
+ reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
+ reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
-- XST
- reg_stat_enable_xst_mosi => reg_stat_enable_xst_mosi,
- reg_stat_enable_xst_miso => reg_stat_enable_xst_miso,
- reg_stat_hdr_dat_xst_mosi => reg_stat_hdr_dat_xst_mosi,
- reg_stat_hdr_dat_xst_miso => reg_stat_hdr_dat_xst_miso,
+ reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
reg_bsn_align_copi => reg_bsn_align_v2_copi,
reg_bsn_align_cipo => reg_bsn_align_v2_cipo,
@@ -842,8 +854,8 @@ BEGIN
reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_bsn_align_v2_input_cipo,
reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_bsn_align_v2_output_copi,
reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_bsn_align_v2_output_cipo,
- reg_xst_udp_monitor_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_xst_udp_monitor_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
@@ -858,12 +870,14 @@ BEGIN
reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
-
+
-- BST
- reg_stat_enable_bst_mosi => reg_stat_enable_bst_mosi,
- reg_stat_enable_bst_miso => reg_stat_enable_bst_miso,
- reg_stat_hdr_dat_bst_mosi => reg_stat_hdr_dat_bst_mosi,
- reg_stat_hdr_dat_bst_miso => reg_stat_hdr_dat_bst_miso,
+ reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
+ reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
+ reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
+ reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
RING_0_TX => RING_0_TX,
RING_0_RX => RING_0_RX,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
index 891f1d9e142edb221b29b545294285327f711465..4ff1520986c397fd31a4b84f42bb1208a4392524 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
@@ -43,244 +43,252 @@ ENTITY mmm_lofar2_unb2c_sdp_station IS
pout_wdi : OUT STD_LOGIC;
-- Manual WDI override
- reg_wdi_mosi : OUT t_mem_mosi;
- reg_wdi_miso : IN t_mem_miso;
+ reg_wdi_copi : OUT t_mem_copi;
+ reg_wdi_cipo : IN t_mem_cipo;
-- system_info
- reg_unb_system_info_mosi : OUT t_mem_mosi;
- reg_unb_system_info_miso : IN t_mem_miso;
- rom_unb_system_info_mosi : OUT t_mem_mosi;
- rom_unb_system_info_miso : IN t_mem_miso;
+ reg_unb_system_info_copi : OUT t_mem_copi;
+ reg_unb_system_info_cipo : IN t_mem_cipo;
+ rom_unb_system_info_copi : OUT t_mem_copi;
+ rom_unb_system_info_cipo : IN t_mem_cipo;
- reg_fpga_temp_sens_mosi : OUT t_mem_mosi;
- reg_fpga_temp_sens_miso : IN t_mem_miso;
- reg_fpga_voltage_sens_mosi: OUT t_mem_mosi;
- reg_fpga_voltage_sens_miso: IN t_mem_miso;
+ reg_fpga_temp_sens_copi : OUT t_mem_copi;
+ reg_fpga_temp_sens_cipo : IN t_mem_cipo;
+ reg_fpga_voltage_sens_copi: OUT t_mem_copi;
+ reg_fpga_voltage_sens_cipo: IN t_mem_cipo;
-- PPSH
- reg_ppsh_mosi : OUT t_mem_mosi;
- reg_ppsh_miso : IN t_mem_miso;
+ reg_ppsh_copi : OUT t_mem_copi;
+ reg_ppsh_cipo : IN t_mem_cipo;
-- eth1g
eth1g_mm_rst : OUT STD_LOGIC;
- eth1g_tse_mosi : OUT t_mem_mosi;
- eth1g_tse_miso : IN t_mem_miso;
- eth1g_reg_mosi : OUT t_mem_mosi;
- eth1g_reg_miso : IN t_mem_miso;
+ eth1g_tse_copi : OUT t_mem_copi;
+ eth1g_tse_cipo : IN t_mem_cipo;
+ eth1g_reg_copi : OUT t_mem_copi;
+ eth1g_reg_cipo : IN t_mem_cipo;
eth1g_reg_interrupt : IN STD_LOGIC;
- eth1g_ram_mosi : OUT t_mem_mosi;
- eth1g_ram_miso : IN t_mem_miso;
+ eth1g_ram_copi : OUT t_mem_copi;
+ eth1g_ram_cipo : IN t_mem_cipo;
-- EPCS read
- reg_dpmm_data_mosi : OUT t_mem_mosi;
- reg_dpmm_data_miso : IN t_mem_miso;
- reg_dpmm_ctrl_mosi : OUT t_mem_mosi;
- reg_dpmm_ctrl_miso : IN t_mem_miso;
+ reg_dpmm_data_copi : OUT t_mem_copi;
+ reg_dpmm_data_cipo : IN t_mem_cipo;
+ reg_dpmm_ctrl_copi : OUT t_mem_copi;
+ reg_dpmm_ctrl_cipo : IN t_mem_cipo;
-- EPCS write
- reg_mmdp_data_mosi : OUT t_mem_mosi;
- reg_mmdp_data_miso : IN t_mem_miso;
- reg_mmdp_ctrl_mosi : OUT t_mem_mosi;
- reg_mmdp_ctrl_miso : IN t_mem_miso;
+ reg_mmdp_data_copi : OUT t_mem_copi;
+ reg_mmdp_data_cipo : IN t_mem_cipo;
+ reg_mmdp_ctrl_copi : OUT t_mem_copi;
+ reg_mmdp_ctrl_cipo : IN t_mem_cipo;
-- EPCS status/control
- reg_epcs_mosi : OUT t_mem_mosi;
- reg_epcs_miso : IN t_mem_miso;
+ reg_epcs_copi : OUT t_mem_copi;
+ reg_epcs_cipo : IN t_mem_cipo;
-- Remote Update
- reg_remu_mosi : OUT t_mem_mosi;
- reg_remu_miso : IN t_mem_miso;
+ reg_remu_copi : OUT t_mem_copi;
+ reg_remu_cipo : IN t_mem_cipo;
-- Jesd control
- jesd204b_mosi : OUT t_mem_mosi;
- jesd204b_miso : IN t_mem_miso;
+ jesd204b_copi : OUT t_mem_copi;
+ jesd204b_cipo : IN t_mem_cipo;
-- Dp shiftram
- reg_dp_shiftram_mosi : OUT t_mem_mosi;
- reg_dp_shiftram_miso : IN t_mem_miso;
+ reg_dp_shiftram_copi : OUT t_mem_copi;
+ reg_dp_shiftram_cipo : IN t_mem_cipo;
-- Bsn source
- reg_bsn_source_v2_mosi : OUT t_mem_mosi;
- reg_bsn_source_v2_miso : IN t_mem_miso;
+ reg_bsn_source_v2_copi : OUT t_mem_copi;
+ reg_bsn_source_v2_cipo : IN t_mem_cipo;
-- bsn schduler for wg trigger
- reg_bsn_scheduler_mosi : OUT t_mem_mosi;
- reg_bsn_scheduler_miso : IN t_mem_miso;
+ reg_bsn_scheduler_copi : OUT t_mem_copi;
+ reg_bsn_scheduler_cipo : IN t_mem_cipo;
-- BSN Monitor
- reg_bsn_monitor_input_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_monitor_input_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_bsn_monitor_input_copi : OUT t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_input_cipo : IN t_mem_cipo := c_mem_cipo_rst;
-- MM wideband waveform generator registers [0,1,2,3] for signal paths [A,B,C,D]
- reg_wg_mosi : OUT t_mem_mosi;
- reg_wg_miso : IN t_mem_miso;
- ram_wg_mosi : OUT t_mem_mosi;
- ram_wg_miso : IN t_mem_miso;
+ reg_wg_copi : OUT t_mem_copi;
+ reg_wg_cipo : IN t_mem_cipo;
+ ram_wg_copi : OUT t_mem_copi;
+ ram_wg_cipo : IN t_mem_cipo;
-- Bsn databuffer
- ram_diag_data_buf_bsn_mosi : OUT t_mem_mosi;
- ram_diag_data_buf_bsn_miso : IN t_mem_miso;
- reg_diag_data_buf_bsn_mosi : OUT t_mem_mosi;
- reg_diag_data_buf_bsn_miso : IN t_mem_miso;
+ ram_diag_data_buf_bsn_copi : OUT t_mem_copi;
+ ram_diag_data_buf_bsn_cipo : IN t_mem_cipo;
+ reg_diag_data_buf_bsn_copi : OUT t_mem_copi;
+ reg_diag_data_buf_bsn_cipo : IN t_mem_cipo;
-- ST Histogram
- ram_st_histogram_mosi : OUT t_mem_mosi;
- ram_st_histogram_miso : IN t_mem_miso;
+ ram_st_histogram_copi : OUT t_mem_copi;
+ ram_st_histogram_cipo : IN t_mem_cipo;
-- Aduh
- reg_aduh_monitor_mosi : OUT t_mem_mosi;
- reg_aduh_monitor_miso : IN t_mem_miso;
+ reg_aduh_monitor_copi : OUT t_mem_copi;
+ reg_aduh_monitor_cipo : IN t_mem_cipo;
-- Subband statistics
- ram_st_sst_mosi : OUT t_mem_mosi;
- ram_st_sst_miso : IN t_mem_miso;
+ ram_st_sst_copi : OUT t_mem_copi;
+ ram_st_sst_cipo : IN t_mem_cipo;
-- Filter coefficients
- ram_fil_coefs_mosi : OUT t_mem_mosi;
- ram_fil_coefs_miso : IN t_mem_miso;
+ ram_fil_coefs_copi : OUT t_mem_copi;
+ ram_fil_coefs_cipo : IN t_mem_cipo;
-- Spectral Inversion
- reg_si_mosi : OUT t_mem_mosi;
- reg_si_miso : IN t_mem_miso;
+ reg_si_copi : OUT t_mem_copi;
+ reg_si_cipo : IN t_mem_cipo;
-- Equalizer gains
- ram_equalizer_gains_mosi : OUT t_mem_mosi;
- ram_equalizer_gains_miso : IN t_mem_miso;
+ ram_equalizer_gains_copi : OUT t_mem_copi;
+ ram_equalizer_gains_cipo : IN t_mem_cipo;
-- DP Selector
- reg_dp_selector_mosi : OUT t_mem_mosi;
- reg_dp_selector_miso : IN t_mem_miso;
+ reg_dp_selector_copi : OUT t_mem_copi;
+ reg_dp_selector_cipo : IN t_mem_cipo;
-- SDP Info
- reg_sdp_info_mosi : OUT t_mem_mosi;
- reg_sdp_info_miso : IN t_mem_miso;
+ reg_sdp_info_copi : OUT t_mem_copi;
+ reg_sdp_info_cipo : IN t_mem_cipo;
-- RING Info
- reg_ring_info_copi : OUT t_mem_mosi;
- reg_ring_info_cipo : IN t_mem_miso;
+ reg_ring_info_copi : OUT t_mem_copi;
+ reg_ring_info_cipo : IN t_mem_cipo;
-- Beamlet Subband Select
- ram_ss_ss_wide_mosi : OUT t_mem_mosi;
- ram_ss_ss_wide_miso : IN t_mem_miso;
+ ram_ss_ss_wide_copi : OUT t_mem_copi;
+ ram_ss_ss_wide_cipo : IN t_mem_cipo;
-- Local BF bf weights
- ram_bf_weights_mosi : OUT t_mem_mosi;
- ram_bf_weights_miso : IN t_mem_miso;
+ ram_bf_weights_copi : OUT t_mem_copi;
+ ram_bf_weights_cipo : IN t_mem_cipo;
-- mms_dp_scale Scale Beamlets
- reg_bf_scale_mosi : OUT t_mem_mosi;
- reg_bf_scale_miso : IN t_mem_miso;
+ reg_bf_scale_copi : OUT t_mem_copi;
+ reg_bf_scale_cipo : IN t_mem_cipo;
-- Beamlet Data Output header fields
- reg_hdr_dat_mosi : OUT t_mem_mosi;
- reg_hdr_dat_miso : IN t_mem_miso;
+ reg_hdr_dat_copi : OUT t_mem_copi;
+ reg_hdr_dat_cipo : IN t_mem_cipo;
-- Beamlet Data Output xonoff
- reg_dp_xonoff_mosi : OUT t_mem_mosi;
- reg_dp_xonoff_miso : IN t_mem_miso;
+ reg_dp_xonoff_copi : OUT t_mem_copi;
+ reg_dp_xonoff_cipo : IN t_mem_cipo;
-- Beamlet Statistics (BST)
- ram_st_bst_mosi : OUT t_mem_mosi;
- ram_st_bst_miso : IN t_mem_miso;
+ ram_st_bst_copi : OUT t_mem_copi;
+ ram_st_bst_cipo : IN t_mem_cipo;
-- Subband Statistics offload
- reg_stat_enable_sst_mosi : OUT t_mem_mosi;
- reg_stat_enable_sst_miso : IN t_mem_miso;
+ reg_stat_enable_sst_copi : OUT t_mem_copi;
+ reg_stat_enable_sst_cipo : IN t_mem_cipo;
-- Statistics header info
- reg_stat_hdr_dat_sst_mosi : OUT t_mem_mosi;
- reg_stat_hdr_dat_sst_miso : IN t_mem_miso;
+ reg_stat_hdr_dat_sst_copi : OUT t_mem_copi;
+ reg_stat_hdr_dat_sst_cipo : IN t_mem_cipo;
-- Crosslet Statistics offload
- reg_stat_enable_xst_mosi : OUT t_mem_mosi;
- reg_stat_enable_xst_miso : IN t_mem_miso;
+ reg_stat_enable_xst_copi : OUT t_mem_copi;
+ reg_stat_enable_xst_cipo : IN t_mem_cipo;
-- Crosslet Statistics header info
- reg_stat_hdr_dat_xst_mosi : OUT t_mem_mosi;
- reg_stat_hdr_dat_xst_miso : IN t_mem_miso;
+ reg_stat_hdr_dat_xst_copi : OUT t_mem_copi;
+ reg_stat_hdr_dat_xst_cipo : IN t_mem_cipo;
-- Beamlet Statistics offload
- reg_stat_enable_bst_mosi : OUT t_mem_mosi;
- reg_stat_enable_bst_miso : IN t_mem_miso;
+ reg_stat_enable_bst_copi : OUT t_mem_copi;
+ reg_stat_enable_bst_cipo : IN t_mem_cipo;
-- Beamlet Statistics header info
- reg_stat_hdr_dat_bst_mosi : OUT t_mem_mosi;
- reg_stat_hdr_dat_bst_miso : IN t_mem_miso;
+ reg_stat_hdr_dat_bst_copi : OUT t_mem_copi;
+ reg_stat_hdr_dat_bst_cipo : IN t_mem_cipo;
-- crosslets_info
- reg_crosslets_info_mosi : OUT t_mem_mosi;
- reg_crosslets_info_miso : IN t_mem_miso;
+ reg_crosslets_info_copi : OUT t_mem_copi;
+ reg_crosslets_info_cipo : IN t_mem_cipo;
-- crosslets_info
- reg_nof_crosslets_mosi : OUT t_mem_mosi;
- reg_nof_crosslets_miso : IN t_mem_miso;
+ reg_nof_crosslets_copi : OUT t_mem_copi;
+ reg_nof_crosslets_cipo : IN t_mem_cipo;
-- bsn_sync_scheduler_xsub
- reg_bsn_sync_scheduler_xsub_mosi : OUT t_mem_mosi;
- reg_bsn_sync_scheduler_xsub_miso : IN t_mem_miso;
+ reg_bsn_sync_scheduler_xsub_copi : OUT t_mem_copi;
+ reg_bsn_sync_scheduler_xsub_cipo : IN t_mem_cipo;
-- st_xsq (XST)
- ram_st_xsq_mosi : OUT t_mem_mosi;
- ram_st_xsq_miso : IN t_mem_miso;
+ ram_st_xsq_copi : OUT t_mem_copi;
+ ram_st_xsq_cipo : IN t_mem_cipo;
-- 10 GbE mac
- reg_nw_10GbE_mac_mosi : OUT t_mem_mosi;
- reg_nw_10GbE_mac_miso : IN t_mem_miso;
+ reg_nw_10GbE_mac_copi : OUT t_mem_copi;
+ reg_nw_10GbE_mac_cipo : IN t_mem_cipo;
-- 10 GbE eth
- reg_nw_10GbE_eth10g_mosi : OUT t_mem_mosi;
- reg_nw_10GbE_eth10g_miso : IN t_mem_miso;
+ reg_nw_10GbE_eth10g_copi : OUT t_mem_copi;
+ reg_nw_10GbE_eth10g_cipo : IN t_mem_cipo;
-- XST bsn aligner_v2
- reg_bsn_align_v2_copi : OUT t_mem_mosi;
- reg_bsn_align_v2_cipo : IN t_mem_miso;
+ reg_bsn_align_v2_copi : OUT t_mem_copi;
+ reg_bsn_align_v2_cipo : IN t_mem_cipo;
-- XST bsn aligner_v2 bsn monitors
- reg_bsn_monitor_v2_bsn_align_v2_input_copi : OUT t_mem_mosi;
- reg_bsn_monitor_v2_bsn_align_v2_input_cipo : IN t_mem_miso;
- reg_bsn_monitor_v2_bsn_align_v2_output_copi : OUT t_mem_mosi;
- reg_bsn_monitor_v2_bsn_align_v2_output_cipo : IN t_mem_miso;
+ reg_bsn_monitor_v2_bsn_align_v2_input_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_bsn_align_v2_input_cipo : IN t_mem_cipo;
+ reg_bsn_monitor_v2_bsn_align_v2_output_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_bsn_align_v2_output_cipo : IN t_mem_cipo;
-- XST UDP offload bsn monitor
- reg_bsn_monitor_v2_xst_offload_copi : OUT t_mem_mosi;
- reg_bsn_monitor_v2_xst_offload_cipo : IN t_mem_miso;
+ reg_bsn_monitor_v2_xst_offload_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_xst_offload_cipo : IN t_mem_cipo;
+
+ -- BST UDP offload bsn monitor
+ reg_bsn_monitor_v2_bst_offload_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_bst_offload_cipo : IN t_mem_cipo;
+
+ -- SST UDP offload bsn monitor
+ reg_bsn_monitor_v2_sst_offload_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_sst_offload_cipo : IN t_mem_cipo;
-- XST ring lane info
- reg_ring_lane_info_xst_copi : OUT t_mem_mosi;
- reg_ring_lane_info_xst_cipo : IN t_mem_miso;
+ reg_ring_lane_info_xst_copi : OUT t_mem_copi;
+ reg_ring_lane_info_xst_cipo : IN t_mem_cipo;
-- XST ring bsn monitor rx
- reg_bsn_monitor_v2_ring_rx_xst_copi: OUT t_mem_mosi;
- reg_bsn_monitor_v2_ring_rx_xst_cipo: IN t_mem_miso;
+ reg_bsn_monitor_v2_ring_rx_xst_copi: OUT t_mem_copi;
+ reg_bsn_monitor_v2_ring_rx_xst_cipo: IN t_mem_cipo;
-- XST ring bsn monitor tx
- reg_bsn_monitor_v2_ring_tx_xst_copi : OUT t_mem_mosi;
- reg_bsn_monitor_v2_ring_tx_xst_cipo : IN t_mem_miso;
+ reg_bsn_monitor_v2_ring_tx_xst_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_ring_tx_xst_cipo : IN t_mem_cipo;
-- XST ring validate err
- reg_dp_block_validate_err_xst_copi : OUT t_mem_mosi;
- reg_dp_block_validate_err_xst_cipo : IN t_mem_miso;
+ reg_dp_block_validate_err_xst_copi : OUT t_mem_copi;
+ reg_dp_block_validate_err_xst_cipo : IN t_mem_cipo;
-- XST ring bsn at sync
- reg_dp_block_validate_bsn_at_sync_xst_copi : OUT t_mem_mosi;
- reg_dp_block_validate_bsn_at_sync_xst_cipo : IN t_mem_miso;
+ reg_dp_block_validate_bsn_at_sync_xst_copi : OUT t_mem_copi;
+ reg_dp_block_validate_bsn_at_sync_xst_cipo : IN t_mem_cipo;
-- XST ring MAC
- reg_tr_10GbE_mac_copi : OUT t_mem_mosi;
- reg_tr_10GbE_mac_cipo : IN t_mem_miso;
+ reg_tr_10GbE_mac_copi : OUT t_mem_copi;
+ reg_tr_10GbE_mac_cipo : IN t_mem_cipo;
-- XST ring ETH
- reg_tr_10GbE_eth10g_copi : OUT t_mem_mosi;
- reg_tr_10GbE_eth10g_cipo : IN t_mem_miso;
+ reg_tr_10GbE_eth10g_copi : OUT t_mem_copi;
+ reg_tr_10GbE_eth10g_cipo : IN t_mem_cipo;
-- Scrap ram
- ram_scrap_mosi : OUT t_mem_mosi;
- ram_scrap_miso : IN t_mem_miso;
+ ram_scrap_copi : OUT t_mem_copi;
+ ram_scrap_cipo : IN t_mem_cipo;
-- Jesd reset control
- jesd_ctrl_mosi : OUT t_mem_mosi;
- jesd_ctrl_miso : IN t_mem_miso
+ jesd_ctrl_copi : OUT t_mem_copi;
+ jesd_ctrl_cipo : IN t_mem_cipo
);
END mmm_lofar2_unb2c_sdp_station;
@@ -300,132 +308,132 @@ BEGIN
gen_mm_file_io : IF g_sim = TRUE GENERATE
u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ PORT MAP(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ PORT MAP(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ PORT MAP(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
u_mm_file_reg_fpga_temp_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- PORT MAP(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ PORT MAP(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
u_mm_file_reg_fpga_voltage_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- PORT MAP(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ PORT MAP(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ PORT MAP(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ PORT MAP(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
u_mm_file_jesd204b : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
- PORT MAP(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
+ PORT MAP(mm_rst, mm_clk, jesd204b_copi, jesd204b_cipo );
u_mm_file_reg_dp_shiftram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
- PORT MAP(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
+ PORT MAP(mm_rst, mm_clk, reg_dp_shiftram_copi, reg_dp_shiftram_cipo );
u_mm_file_reg_bsn_source_v2 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE_V2")
- PORT MAP(mm_rst, mm_clk, reg_bsn_source_v2_mosi, reg_bsn_source_v2_miso );
+ PORT MAP(mm_rst, mm_clk, reg_bsn_source_v2_copi, reg_bsn_source_v2_cipo );
u_mm_file_reg_bsn_scheduler : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- PORT MAP(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
+ PORT MAP(mm_rst, mm_clk, reg_bsn_scheduler_copi, reg_bsn_scheduler_cipo );
u_mm_file_reg_bsn_monitor_input : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_input_copi, reg_bsn_monitor_input_cipo );
u_mm_file_reg_wg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
- PORT MAP(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
+ PORT MAP(mm_rst, mm_clk, reg_wg_copi, reg_wg_cipo );
u_mm_file_ram_wg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
- PORT MAP(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
+ PORT MAP(mm_rst, mm_clk, ram_wg_copi, ram_wg_cipo );
u_mm_file_ram_diag_data_buf_bsn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_BSN")
- PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
+ PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_bsn_copi, ram_diag_data_buf_bsn_cipo );
u_mm_file_reg_diag_data_buf_bsn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_BSN")
- PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
+ PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_bsn_copi, reg_diag_data_buf_bsn_cipo );
u_mm_file_ram_st_histogram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_HISTOGRAM")
- PORT MAP(mm_rst, mm_clk, ram_st_histogram_mosi, ram_st_histogram_miso );
+ PORT MAP(mm_rst, mm_clk, ram_st_histogram_copi, ram_st_histogram_cipo );
u_mm_file_reg_aduh_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
- PORT MAP(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
+ PORT MAP(mm_rst, mm_clk, reg_aduh_monitor_copi, reg_aduh_monitor_cipo );
u_mm_file_ram_st_sst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
- PORT MAP(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
+ PORT MAP(mm_rst, mm_clk, ram_st_sst_copi, ram_st_sst_cipo );
u_mm_file_ram_fil_coefs : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
- PORT MAP(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
+ PORT MAP(mm_rst, mm_clk, ram_fil_coefs_copi, ram_fil_coefs_cipo );
u_mm_file_reg_si : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
- PORT MAP(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
+ PORT MAP(mm_rst, mm_clk, reg_si_copi, reg_si_cipo );
u_mm_file_ram_equalizer_gains : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
- PORT MAP(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
+ PORT MAP(mm_rst, mm_clk, ram_equalizer_gains_copi, ram_equalizer_gains_cipo );
u_mm_file_reg_dp_selector : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
- PORT MAP(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
+ PORT MAP(mm_rst, mm_clk, reg_dp_selector_copi, reg_dp_selector_cipo );
u_mm_file_reg_sdp_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
- PORT MAP(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
+ PORT MAP(mm_rst, mm_clk, reg_sdp_info_copi, reg_sdp_info_cipo );
u_mm_file_reg_ring_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
PORT MAP(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo );
u_mm_file_ram_ss_ss_wide : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- PORT MAP(mm_rst, mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso );
+ PORT MAP(mm_rst, mm_clk, ram_ss_ss_wide_copi, ram_ss_ss_wide_cipo );
u_mm_file_ram_bf_weights : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
- PORT MAP(mm_rst, mm_clk, ram_bf_weights_mosi, ram_bf_weights_miso );
+ PORT MAP(mm_rst, mm_clk, ram_bf_weights_copi, ram_bf_weights_cipo );
u_mm_file_reg_bf_scale : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BF_SCALE")
- PORT MAP(mm_rst, mm_clk, reg_bf_scale_mosi, reg_bf_scale_miso );
+ PORT MAP(mm_rst, mm_clk, reg_bf_scale_copi, reg_bf_scale_cipo );
u_mm_file_reg_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT")
- PORT MAP(mm_rst, mm_clk, reg_hdr_dat_mosi, reg_hdr_dat_miso );
+ PORT MAP(mm_rst, mm_clk, reg_hdr_dat_copi, reg_hdr_dat_cipo );
u_mm_file_reg_dp_xonoff : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF")
- PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_mosi, reg_dp_xonoff_miso );
+ PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_copi, reg_dp_xonoff_cipo );
u_mm_file_ram_st_bst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_BST")
- PORT MAP(mm_rst, mm_clk, ram_st_bst_mosi, ram_st_bst_miso );
+ PORT MAP(mm_rst, mm_clk, ram_st_bst_copi, ram_st_bst_cipo );
u_mm_file_reg_stat_enable_sst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_SST")
- PORT MAP(mm_rst, mm_clk, reg_stat_enable_sst_mosi, reg_stat_enable_sst_miso );
+ PORT MAP(mm_rst, mm_clk, reg_stat_enable_sst_copi, reg_stat_enable_sst_cipo );
u_mm_file_reg_stat_hdr_info_sst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_SST")
- PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_sst_mosi, reg_stat_hdr_dat_sst_miso);
+ PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_sst_copi, reg_stat_hdr_dat_sst_cipo);
u_mm_file_reg_stat_enable_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_XST")
- PORT MAP(mm_rst, mm_clk, reg_stat_enable_xst_mosi, reg_stat_enable_xst_miso );
+ PORT MAP(mm_rst, mm_clk, reg_stat_enable_xst_copi, reg_stat_enable_xst_cipo );
u_mm_file_reg_stat_hdr_info_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_XST")
- PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_xst_mosi, reg_stat_hdr_dat_xst_miso);
+ PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_xst_copi, reg_stat_hdr_dat_xst_cipo);
u_mm_file_reg_stat_enable_bst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_BST")
- PORT MAP(mm_rst, mm_clk, reg_stat_enable_bst_mosi, reg_stat_enable_bst_miso );
+ PORT MAP(mm_rst, mm_clk, reg_stat_enable_bst_copi, reg_stat_enable_bst_cipo );
u_mm_file_reg_stat_hdr_info_bst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST")
- PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_bst_mosi, reg_stat_hdr_dat_bst_miso);
+ PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_bst_copi, reg_stat_hdr_dat_bst_cipo);
u_mm_file_reg_crosslets_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_CROSSLETS_INFO")
- PORT MAP(mm_rst, mm_clk, reg_crosslets_info_mosi, reg_crosslets_info_miso);
+ PORT MAP(mm_rst, mm_clk, reg_crosslets_info_copi, reg_crosslets_info_cipo);
u_mm_file_reg_nof_crosslets : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NOF_CROSSLETS")
- PORT MAP(mm_rst, mm_clk, reg_nof_crosslets_mosi, reg_nof_crosslets_miso);
+ PORT MAP(mm_rst, mm_clk, reg_nof_crosslets_copi, reg_nof_crosslets_cipo);
u_mm_file_reg_bsn_sync_scheduler_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SYNC_SCHEDULER_XSUB")
- PORT MAP(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_mosi, reg_bsn_sync_scheduler_xsub_miso);
+ PORT MAP(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_copi, reg_bsn_sync_scheduler_xsub_cipo);
u_mm_file_ram_st_xsq : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_XSQ")
- PORT MAP(mm_rst, mm_clk, ram_st_xsq_mosi, ram_st_xsq_miso);
+ PORT MAP(mm_rst, mm_clk, ram_st_xsq_copi, ram_st_xsq_cipo);
u_mm_file_reg_nw_10GbE_mac : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
- PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_mac_mosi, reg_nw_10GbE_mac_miso );
+ PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_mac_copi, reg_nw_10GbE_mac_cipo );
u_mm_file_reg_nw_10GbE_eth10g : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
- PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_eth10g_mosi, reg_nw_10GbE_eth10g_miso );
+ PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_eth10g_copi, reg_nw_10GbE_eth10g_cipo );
u_mm_file_reg_bsn_align_v2 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2")
PORT MAP(mm_rst, mm_clk, reg_bsn_align_v2_copi, reg_bsn_align_v2_cipo );
@@ -436,6 +444,12 @@ BEGIN
u_mm_file_reg_bsn_monitor_v2_bsn_align_v2_output: mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT")
PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_bsn_align_v2_output_copi, reg_bsn_monitor_v2_bsn_align_v2_output_cipo );
+ u_mm_file_reg_bsn_monitor_v2_sst_offload : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_SST_OFFLOAD")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_sst_offload_copi, reg_bsn_monitor_v2_sst_offload_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_bst_offload : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BST_OFFLOAD")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_bst_offload_copi, reg_bsn_monitor_v2_bst_offload_cipo );
+
u_mm_file_reg_bsn_monitor_v2_xst_offload : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_XST_OFFLOAD")
PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_xst_offload_copi, reg_bsn_monitor_v2_xst_offload_cipo );
@@ -461,7 +475,7 @@ BEGIN
PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
u_mm_file_ram_scrap : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- PORT MAP(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+ PORT MAP(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
@@ -486,266 +500,266 @@ BEGIN
avs_eth_0_reset_export => eth1g_mm_rst,
avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
- avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
- avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
- avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_tse_address_export => eth1g_tse_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ avs_eth_0_tse_write_export => eth1g_tse_copi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_copi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_copi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_cipo.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_cipo.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_reg_write_export => eth1g_reg_copi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_copi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_copi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_cipo.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_ram_address_export => eth1g_ram_copi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_ram_write_export => eth1g_ram_copi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_copi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_copi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_cipo.rddata(c_word_w-1 DOWNTO 0),
avs_eth_0_irq_export => eth1g_reg_interrupt,
reg_fpga_temp_sens_reset_export => OPEN,
reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w-1 DOWNTO 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w-1 DOWNTO 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_copi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_copi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_fpga_voltage_sens_reset_export => OPEN,
reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w-1 DOWNTO 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w-1 DOWNTO 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_copi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_copi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_cipo.rddata(c_word_w-1 DOWNTO 0),
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
-- ToDo: This has changed in the peripherals package
--- rom_system_info_address_export => rom_unb_system_info_mosi.address(9 DOWNTO 0),
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+-- rom_system_info_address_export => rom_unb_system_info_copi.address(9 DOWNTO 0),
+ rom_system_info_address_export => rom_unb_system_info_copi.address(c_unb2c_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ rom_system_info_write_export => rom_unb_system_info_copi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_copi.wrdata(c_word_w-1 DOWNTO 0),
+ rom_system_info_read_export => rom_unb_system_info_copi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_cipo.rddata(c_word_w-1 DOWNTO 0),
pio_system_info_reset_export => OPEN,
pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ pio_system_info_address_export => reg_unb_system_info_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
+ pio_system_info_write_export => reg_unb_system_info_copi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_copi.wrdata(c_word_w-1 DOWNTO 0),
+ pio_system_info_read_export => reg_unb_system_info_copi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_cipo.rddata(c_word_w-1 DOWNTO 0),
pio_pps_reset_export => OPEN,
pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
+ pio_pps_address_export => reg_ppsh_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ pio_pps_write_export => reg_ppsh_copi.wr,
+ pio_pps_writedata_export => reg_ppsh_copi.wrdata(c_word_w-1 DOWNTO 0),
+ pio_pps_read_export => reg_ppsh_copi.rd,
+ pio_pps_readdata_export => reg_ppsh_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_wdi_reset_export => OPEN,
reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_mosi.address(0 DOWNTO 0),
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_wdi_address_export => reg_wdi_copi.address(0 DOWNTO 0),
+ reg_wdi_write_export => reg_wdi_copi.wr,
+ reg_wdi_writedata_export => reg_wdi_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_wdi_read_export => reg_wdi_copi.rd,
+ reg_wdi_readdata_export => reg_wdi_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_remu_reset_export => OPEN,
reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
- reg_remu_write_export => reg_remu_mosi.wr,
- reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_remu_read_export => reg_remu_mosi.rd,
- reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_remu_address_export => reg_remu_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
+ reg_remu_write_export => reg_remu_copi.wr,
+ reg_remu_writedata_export => reg_remu_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_remu_read_export => reg_remu_copi.rd,
+ reg_remu_readdata_export => reg_remu_cipo.rddata(c_word_w-1 DOWNTO 0),
jesd204b_reset_export => OPEN,
jesd204b_clk_export => OPEN,
- jesd204b_address_export => jesd204b_mosi.address(c_sdp_jesd204b_addr_w-1 DOWNTO 0),
- jesd204b_write_export => jesd204b_mosi.wr,
- jesd204b_writedata_export => jesd204b_mosi.wrdata(c_word_w-1 DOWNTO 0),
- jesd204b_read_export => jesd204b_mosi.rd,
- jesd204b_readdata_export => jesd204b_miso.rddata(c_word_w-1 DOWNTO 0),
+ jesd204b_address_export => jesd204b_copi.address(c_sdp_jesd204b_addr_w-1 DOWNTO 0),
+ jesd204b_write_export => jesd204b_copi.wr,
+ jesd204b_writedata_export => jesd204b_copi.wrdata(c_word_w-1 DOWNTO 0),
+ jesd204b_read_export => jesd204b_copi.rd,
+ jesd204b_readdata_export => jesd204b_cipo.rddata(c_word_w-1 DOWNTO 0),
pio_jesd_ctrl_reset_export => OPEN,
pio_jesd_ctrl_clk_export => OPEN,
- pio_jesd_ctrl_address_export => jesd_ctrl_mosi.address(c_sdp_jesd_ctrl_addr_w-1 DOWNTO 0),
- pio_jesd_ctrl_write_export => jesd_ctrl_mosi.wr,
- pio_jesd_ctrl_writedata_export => jesd_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
- pio_jesd_ctrl_read_export => jesd_ctrl_mosi.rd,
- pio_jesd_ctrl_readdata_export => jesd_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
+ pio_jesd_ctrl_address_export => jesd_ctrl_copi.address(c_sdp_jesd_ctrl_addr_w-1 DOWNTO 0),
+ pio_jesd_ctrl_write_export => jesd_ctrl_copi.wr,
+ pio_jesd_ctrl_writedata_export => jesd_ctrl_copi.wrdata(c_word_w-1 DOWNTO 0),
+ pio_jesd_ctrl_read_export => jesd_ctrl_copi.rd,
+ pio_jesd_ctrl_readdata_export => jesd_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0),
- reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_mosi.address(c_sdp_reg_bsn_monitor_input_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_copi.address(c_sdp_reg_bsn_monitor_input_addr_w-1 DOWNTO 0),
reg_bsn_monitor_input_clk_export => OPEN,
- reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_mosi.rd,
- reg_bsn_monitor_input_readdata_export => reg_bsn_monitor_input_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_copi.rd,
+ reg_bsn_monitor_input_readdata_export => reg_bsn_monitor_input_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_bsn_monitor_input_reset_export => OPEN,
- reg_bsn_monitor_input_write_export => reg_bsn_monitor_input_mosi.wr,
- reg_bsn_monitor_input_writedata_export => reg_bsn_monitor_input_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_input_write_export => reg_bsn_monitor_input_copi.wr,
+ reg_bsn_monitor_input_writedata_export => reg_bsn_monitor_input_copi.wrdata(c_word_w-1 DOWNTO 0),
-- waveform generators (multiplexed)
reg_wg_clk_export => OPEN,
reg_wg_reset_export => OPEN,
- reg_wg_address_export => reg_wg_mosi.address(c_sdp_reg_wg_addr_w-1 DOWNTO 0),
- reg_wg_read_export => reg_wg_mosi.rd,
- reg_wg_readdata_export => reg_wg_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_wg_write_export => reg_wg_mosi.wr,
- reg_wg_writedata_export => reg_wg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_wg_address_export => reg_wg_copi.address(c_sdp_reg_wg_addr_w-1 DOWNTO 0),
+ reg_wg_read_export => reg_wg_copi.rd,
+ reg_wg_readdata_export => reg_wg_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_wg_write_export => reg_wg_copi.wr,
+ reg_wg_writedata_export => reg_wg_copi.wrdata(c_word_w-1 DOWNTO 0),
ram_wg_clk_export => OPEN,
ram_wg_reset_export => OPEN,
- ram_wg_address_export => ram_wg_mosi.address(c_sdp_ram_wg_addr_w-1 DOWNTO 0),
- ram_wg_read_export => ram_wg_mosi.rd,
- ram_wg_readdata_export => ram_wg_miso.rddata(c_word_w-1 DOWNTO 0),
- ram_wg_write_export => ram_wg_mosi.wr,
- ram_wg_writedata_export => ram_wg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_wg_address_export => ram_wg_copi.address(c_sdp_ram_wg_addr_w-1 DOWNTO 0),
+ ram_wg_read_export => ram_wg_copi.rd,
+ ram_wg_readdata_export => ram_wg_cipo.rddata(c_word_w-1 DOWNTO 0),
+ ram_wg_write_export => ram_wg_copi.wr,
+ ram_wg_writedata_export => ram_wg_copi.wrdata(c_word_w-1 DOWNTO 0),
reg_dp_shiftram_clk_export => OPEN,
reg_dp_shiftram_reset_export => OPEN,
- reg_dp_shiftram_address_export => reg_dp_shiftram_mosi.address(c_sdp_reg_dp_shiftram_addr_w-1 DOWNTO 0),
- reg_dp_shiftram_read_export => reg_dp_shiftram_mosi.rd,
- reg_dp_shiftram_readdata_export => reg_dp_shiftram_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_dp_shiftram_write_export => reg_dp_shiftram_mosi.wr,
- reg_dp_shiftram_writedata_export => reg_dp_shiftram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_shiftram_address_export => reg_dp_shiftram_copi.address(c_sdp_reg_dp_shiftram_addr_w-1 DOWNTO 0),
+ reg_dp_shiftram_read_export => reg_dp_shiftram_copi.rd,
+ reg_dp_shiftram_readdata_export => reg_dp_shiftram_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_shiftram_write_export => reg_dp_shiftram_copi.wr,
+ reg_dp_shiftram_writedata_export => reg_dp_shiftram_copi.wrdata(c_word_w-1 DOWNTO 0),
reg_bsn_source_v2_clk_export => OPEN,
reg_bsn_source_v2_reset_export => OPEN,
- reg_bsn_source_v2_address_export => reg_bsn_source_v2_mosi.address(c_sdp_reg_bsn_source_v2_addr_w-1 DOWNTO 0),
- reg_bsn_source_v2_read_export => reg_bsn_source_v2_mosi.rd,
- reg_bsn_source_v2_readdata_export => reg_bsn_source_v2_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_bsn_source_v2_write_export => reg_bsn_source_v2_mosi.wr,
- reg_bsn_source_v2_writedata_export => reg_bsn_source_v2_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_source_v2_address_export => reg_bsn_source_v2_copi.address(c_sdp_reg_bsn_source_v2_addr_w-1 DOWNTO 0),
+ reg_bsn_source_v2_read_export => reg_bsn_source_v2_copi.rd,
+ reg_bsn_source_v2_readdata_export => reg_bsn_source_v2_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_source_v2_write_export => reg_bsn_source_v2_copi.wr,
+ reg_bsn_source_v2_writedata_export => reg_bsn_source_v2_copi.wrdata(c_word_w-1 DOWNTO 0),
reg_bsn_scheduler_clk_export => OPEN,
reg_bsn_scheduler_reset_export => OPEN,
- reg_bsn_scheduler_address_export => reg_bsn_scheduler_mosi.address(c_sdp_reg_bsn_scheduler_addr_w-1 DOWNTO 0),
- reg_bsn_scheduler_read_export => reg_bsn_scheduler_mosi.rd,
- reg_bsn_scheduler_readdata_export => reg_bsn_scheduler_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_bsn_scheduler_write_export => reg_bsn_scheduler_mosi.wr,
- reg_bsn_scheduler_writedata_export => reg_bsn_scheduler_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_scheduler_address_export => reg_bsn_scheduler_copi.address(c_sdp_reg_bsn_scheduler_addr_w-1 DOWNTO 0),
+ reg_bsn_scheduler_read_export => reg_bsn_scheduler_copi.rd,
+ reg_bsn_scheduler_readdata_export => reg_bsn_scheduler_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_scheduler_write_export => reg_bsn_scheduler_copi.wr,
+ reg_bsn_scheduler_writedata_export => reg_bsn_scheduler_copi.wrdata(c_word_w-1 DOWNTO 0),
reg_epcs_reset_export => OPEN,
reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
- reg_epcs_write_export => reg_epcs_mosi.wr,
- reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_epcs_read_export => reg_epcs_mosi.rd,
- reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_epcs_address_export => reg_epcs_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
+ reg_epcs_write_export => reg_epcs_copi.wr,
+ reg_epcs_writedata_export => reg_epcs_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_epcs_read_export => reg_epcs_copi.rd,
+ reg_epcs_readdata_export => reg_epcs_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_dpmm_ctrl_reset_export => OPEN,
reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 DOWNTO 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_copi.address(0 DOWNTO 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_copi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_copi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_mmdp_data_reset_export => OPEN,
reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 DOWNTO 0),
- reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_mmdp_data_address_export => reg_mmdp_data_copi.address(0 DOWNTO 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_copi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_copi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_dpmm_data_reset_export => OPEN,
reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 DOWNTO 0),
- reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dpmm_data_address_export => reg_dpmm_data_copi.address(0 DOWNTO 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_copi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_copi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_copi.wrdata(c_word_w-1 DOWNTO 0),
reg_mmdp_ctrl_reset_export => OPEN,
reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 DOWNTO 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_copi.address(0 DOWNTO 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_copi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_copi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_copi.wrdata(c_word_w-1 DOWNTO 0),
ram_diag_data_buffer_bsn_clk_export => OPEN,
ram_diag_data_buffer_bsn_reset_export => OPEN,
- ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(c_sdp_ram_diag_data_buf_bsn_addr_w-1 DOWNTO 0),
- ram_diag_data_buffer_bsn_write_export => ram_diag_data_buf_bsn_mosi.wr,
- ram_diag_data_buffer_bsn_writedata_export => ram_diag_data_buf_bsn_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_diag_data_buffer_bsn_read_export => ram_diag_data_buf_bsn_mosi.rd,
- ram_diag_data_buffer_bsn_readdata_export => ram_diag_data_buf_bsn_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_copi.address(c_sdp_ram_diag_data_buf_bsn_addr_w-1 DOWNTO 0),
+ ram_diag_data_buffer_bsn_write_export => ram_diag_data_buf_bsn_copi.wr,
+ ram_diag_data_buffer_bsn_writedata_export => ram_diag_data_buf_bsn_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_diag_data_buffer_bsn_read_export => ram_diag_data_buf_bsn_copi.rd,
+ ram_diag_data_buffer_bsn_readdata_export => ram_diag_data_buf_bsn_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_diag_data_buffer_bsn_reset_export => OPEN,
reg_diag_data_buffer_bsn_clk_export => OPEN,
- reg_diag_data_buffer_bsn_address_export => reg_diag_data_buf_bsn_mosi.address(c_sdp_reg_diag_data_buf_bsn_addr_w-1 DOWNTO 0),
- reg_diag_data_buffer_bsn_write_export => reg_diag_data_buf_bsn_mosi.wr,
- reg_diag_data_buffer_bsn_writedata_export => reg_diag_data_buf_bsn_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_diag_data_buffer_bsn_read_export => reg_diag_data_buf_bsn_mosi.rd,
- reg_diag_data_buffer_bsn_readdata_export => reg_diag_data_buf_bsn_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_data_buffer_bsn_address_export => reg_diag_data_buf_bsn_copi.address(c_sdp_reg_diag_data_buf_bsn_addr_w-1 DOWNTO 0),
+ reg_diag_data_buffer_bsn_write_export => reg_diag_data_buf_bsn_copi.wr,
+ reg_diag_data_buffer_bsn_writedata_export => reg_diag_data_buf_bsn_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_data_buffer_bsn_read_export => reg_diag_data_buf_bsn_copi.rd,
+ reg_diag_data_buffer_bsn_readdata_export => reg_diag_data_buf_bsn_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_st_histogram_clk_export => OPEN,
ram_st_histogram_reset_export => OPEN,
- ram_st_histogram_address_export => ram_st_histogram_mosi.address(c_sdp_ram_st_histogram_addr_w-1 DOWNTO 0),
- ram_st_histogram_write_export => ram_st_histogram_mosi.wr,
- ram_st_histogram_writedata_export => ram_st_histogram_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_st_histogram_read_export => ram_st_histogram_mosi.rd,
- ram_st_histogram_readdata_export => ram_st_histogram_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_st_histogram_address_export => ram_st_histogram_copi.address(c_sdp_ram_st_histogram_addr_w-1 DOWNTO 0),
+ ram_st_histogram_write_export => ram_st_histogram_copi.wr,
+ ram_st_histogram_writedata_export => ram_st_histogram_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_st_histogram_read_export => ram_st_histogram_copi.rd,
+ ram_st_histogram_readdata_export => ram_st_histogram_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_aduh_monitor_reset_export => OPEN,
reg_aduh_monitor_clk_export => OPEN,
- reg_aduh_monitor_address_export => reg_aduh_monitor_mosi.address(c_sdp_reg_aduh_monitor_addr_w-1 DOWNTO 0),
- reg_aduh_monitor_write_export => reg_aduh_monitor_mosi.wr,
- reg_aduh_monitor_writedata_export => reg_aduh_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_aduh_monitor_read_export => reg_aduh_monitor_mosi.rd,
- reg_aduh_monitor_readdata_export => reg_aduh_monitor_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_aduh_monitor_address_export => reg_aduh_monitor_copi.address(c_sdp_reg_aduh_monitor_addr_w-1 DOWNTO 0),
+ reg_aduh_monitor_write_export => reg_aduh_monitor_copi.wr,
+ reg_aduh_monitor_writedata_export => reg_aduh_monitor_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_aduh_monitor_read_export => reg_aduh_monitor_copi.rd,
+ reg_aduh_monitor_readdata_export => reg_aduh_monitor_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_fil_coefs_clk_export => OPEN,
ram_fil_coefs_reset_export => OPEN,
- ram_fil_coefs_address_export => ram_fil_coefs_mosi.address(c_sdp_ram_fil_coefs_addr_w-1 DOWNTO 0),
- ram_fil_coefs_write_export => ram_fil_coefs_mosi.wr,
- ram_fil_coefs_writedata_export => ram_fil_coefs_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_fil_coefs_read_export => ram_fil_coefs_mosi.rd,
- ram_fil_coefs_readdata_export => ram_fil_coefs_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_fil_coefs_address_export => ram_fil_coefs_copi.address(c_sdp_ram_fil_coefs_addr_w-1 DOWNTO 0),
+ ram_fil_coefs_write_export => ram_fil_coefs_copi.wr,
+ ram_fil_coefs_writedata_export => ram_fil_coefs_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_fil_coefs_read_export => ram_fil_coefs_copi.rd,
+ ram_fil_coefs_readdata_export => ram_fil_coefs_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_st_sst_clk_export => OPEN,
ram_st_sst_reset_export => OPEN,
- ram_st_sst_address_export => ram_st_sst_mosi.address(c_sdp_ram_st_sst_addr_w-1 DOWNTO 0),
- ram_st_sst_write_export => ram_st_sst_mosi.wr,
- ram_st_sst_writedata_export => ram_st_sst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_st_sst_read_export => ram_st_sst_mosi.rd,
- ram_st_sst_readdata_export => ram_st_sst_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_st_sst_address_export => ram_st_sst_copi.address(c_sdp_ram_st_sst_addr_w-1 DOWNTO 0),
+ ram_st_sst_write_export => ram_st_sst_copi.wr,
+ ram_st_sst_writedata_export => ram_st_sst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_st_sst_read_export => ram_st_sst_copi.rd,
+ ram_st_sst_readdata_export => ram_st_sst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_si_clk_export => OPEN,
reg_si_reset_export => OPEN,
- reg_si_address_export => reg_si_mosi.address(c_sdp_reg_si_addr_w-1 DOWNTO 0),
- reg_si_write_export => reg_si_mosi.wr,
- reg_si_writedata_export => reg_si_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_si_read_export => reg_si_mosi.rd,
- reg_si_readdata_export => reg_si_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_si_address_export => reg_si_copi.address(c_sdp_reg_si_addr_w-1 DOWNTO 0),
+ reg_si_write_export => reg_si_copi.wr,
+ reg_si_writedata_export => reg_si_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_si_read_export => reg_si_copi.rd,
+ reg_si_readdata_export => reg_si_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_equalizer_gains_clk_export => OPEN,
ram_equalizer_gains_reset_export => OPEN,
- ram_equalizer_gains_address_export => ram_equalizer_gains_mosi.address(c_sdp_ram_equalizer_gains_addr_w-1 DOWNTO 0),
- ram_equalizer_gains_write_export => ram_equalizer_gains_mosi.wr,
- ram_equalizer_gains_writedata_export => ram_equalizer_gains_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_equalizer_gains_read_export => ram_equalizer_gains_mosi.rd,
- ram_equalizer_gains_readdata_export => ram_equalizer_gains_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_equalizer_gains_address_export => ram_equalizer_gains_copi.address(c_sdp_ram_equalizer_gains_addr_w-1 DOWNTO 0),
+ ram_equalizer_gains_write_export => ram_equalizer_gains_copi.wr,
+ ram_equalizer_gains_writedata_export => ram_equalizer_gains_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_equalizer_gains_read_export => ram_equalizer_gains_copi.rd,
+ ram_equalizer_gains_readdata_export => ram_equalizer_gains_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_dp_selector_clk_export => OPEN,
reg_dp_selector_reset_export => OPEN,
- reg_dp_selector_address_export => reg_dp_selector_mosi.address(c_sdp_reg_dp_selector_addr_w-1 DOWNTO 0),
- reg_dp_selector_write_export => reg_dp_selector_mosi.wr,
- reg_dp_selector_writedata_export => reg_dp_selector_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_dp_selector_read_export => reg_dp_selector_mosi.rd,
- reg_dp_selector_readdata_export => reg_dp_selector_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_selector_address_export => reg_dp_selector_copi.address(c_sdp_reg_dp_selector_addr_w-1 DOWNTO 0),
+ reg_dp_selector_write_export => reg_dp_selector_copi.wr,
+ reg_dp_selector_writedata_export => reg_dp_selector_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_selector_read_export => reg_dp_selector_copi.rd,
+ reg_dp_selector_readdata_export => reg_dp_selector_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_sdp_info_clk_export => OPEN,
reg_sdp_info_reset_export => OPEN,
- reg_sdp_info_address_export => reg_sdp_info_mosi.address(c_sdp_reg_sdp_info_addr_w-1 DOWNTO 0),
- reg_sdp_info_write_export => reg_sdp_info_mosi.wr,
- reg_sdp_info_writedata_export => reg_sdp_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_sdp_info_read_export => reg_sdp_info_mosi.rd,
- reg_sdp_info_readdata_export => reg_sdp_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_sdp_info_address_export => reg_sdp_info_copi.address(c_sdp_reg_sdp_info_addr_w-1 DOWNTO 0),
+ reg_sdp_info_write_export => reg_sdp_info_copi.wr,
+ reg_sdp_info_writedata_export => reg_sdp_info_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_sdp_info_read_export => reg_sdp_info_copi.rd,
+ reg_sdp_info_readdata_export => reg_sdp_info_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_ring_info_clk_export => OPEN,
reg_ring_info_reset_export => OPEN,
@@ -757,147 +771,147 @@ BEGIN
ram_ss_ss_wide_clk_export => OPEN,
ram_ss_ss_wide_reset_export => OPEN,
- ram_ss_ss_wide_address_export => ram_ss_ss_wide_mosi.address(c_sdp_ram_ss_ss_wide_addr_w-1 DOWNTO 0),
- ram_ss_ss_wide_write_export => ram_ss_ss_wide_mosi.wr,
- ram_ss_ss_wide_writedata_export => ram_ss_ss_wide_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_ss_ss_wide_read_export => ram_ss_ss_wide_mosi.rd,
- ram_ss_ss_wide_readdata_export => ram_ss_ss_wide_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_ss_ss_wide_address_export => ram_ss_ss_wide_copi.address(c_sdp_ram_ss_ss_wide_addr_w-1 DOWNTO 0),
+ ram_ss_ss_wide_write_export => ram_ss_ss_wide_copi.wr,
+ ram_ss_ss_wide_writedata_export => ram_ss_ss_wide_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_ss_ss_wide_read_export => ram_ss_ss_wide_copi.rd,
+ ram_ss_ss_wide_readdata_export => ram_ss_ss_wide_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_bf_weights_clk_export => OPEN,
ram_bf_weights_reset_export => OPEN,
- ram_bf_weights_address_export => ram_bf_weights_mosi.address(c_sdp_ram_bf_weights_addr_w-1 DOWNTO 0),
- ram_bf_weights_write_export => ram_bf_weights_mosi.wr,
- ram_bf_weights_writedata_export => ram_bf_weights_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_bf_weights_read_export => ram_bf_weights_mosi.rd,
- ram_bf_weights_readdata_export => ram_bf_weights_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_bf_weights_address_export => ram_bf_weights_copi.address(c_sdp_ram_bf_weights_addr_w-1 DOWNTO 0),
+ ram_bf_weights_write_export => ram_bf_weights_copi.wr,
+ ram_bf_weights_writedata_export => ram_bf_weights_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_bf_weights_read_export => ram_bf_weights_copi.rd,
+ ram_bf_weights_readdata_export => ram_bf_weights_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_bf_scale_clk_export => OPEN,
reg_bf_scale_reset_export => OPEN,
- reg_bf_scale_address_export => reg_bf_scale_mosi.address(c_sdp_reg_bf_scale_addr_w-1 DOWNTO 0),
- reg_bf_scale_write_export => reg_bf_scale_mosi.wr,
- reg_bf_scale_writedata_export => reg_bf_scale_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_bf_scale_read_export => reg_bf_scale_mosi.rd,
- reg_bf_scale_readdata_export => reg_bf_scale_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_bf_scale_address_export => reg_bf_scale_copi.address(c_sdp_reg_bf_scale_addr_w-1 DOWNTO 0),
+ reg_bf_scale_write_export => reg_bf_scale_copi.wr,
+ reg_bf_scale_writedata_export => reg_bf_scale_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bf_scale_read_export => reg_bf_scale_copi.rd,
+ reg_bf_scale_readdata_export => reg_bf_scale_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_hdr_dat_clk_export => OPEN,
reg_hdr_dat_reset_export => OPEN,
- reg_hdr_dat_address_export => reg_hdr_dat_mosi.address(c_sdp_reg_bf_hdr_dat_addr_w-1 DOWNTO 0),
- reg_hdr_dat_write_export => reg_hdr_dat_mosi.wr,
- reg_hdr_dat_writedata_export => reg_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_hdr_dat_read_export => reg_hdr_dat_mosi.rd,
- reg_hdr_dat_readdata_export => reg_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_hdr_dat_address_export => reg_hdr_dat_copi.address(c_sdp_reg_bf_hdr_dat_addr_w-1 DOWNTO 0),
+ reg_hdr_dat_write_export => reg_hdr_dat_copi.wr,
+ reg_hdr_dat_writedata_export => reg_hdr_dat_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_hdr_dat_read_export => reg_hdr_dat_copi.rd,
+ reg_hdr_dat_readdata_export => reg_hdr_dat_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_dp_xonoff_clk_export => OPEN,
reg_dp_xonoff_reset_export => OPEN,
- reg_dp_xonoff_address_export => reg_dp_xonoff_mosi.address(c_sdp_reg_dp_xonoff_addr_w-1 DOWNTO 0),
- reg_dp_xonoff_write_export => reg_dp_xonoff_mosi.wr,
- reg_dp_xonoff_writedata_export => reg_dp_xonoff_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_dp_xonoff_read_export => reg_dp_xonoff_mosi.rd,
- reg_dp_xonoff_readdata_export => reg_dp_xonoff_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_xonoff_address_export => reg_dp_xonoff_copi.address(c_sdp_reg_dp_xonoff_addr_w-1 DOWNTO 0),
+ reg_dp_xonoff_write_export => reg_dp_xonoff_copi.wr,
+ reg_dp_xonoff_writedata_export => reg_dp_xonoff_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_xonoff_read_export => reg_dp_xonoff_copi.rd,
+ reg_dp_xonoff_readdata_export => reg_dp_xonoff_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_st_bst_clk_export => OPEN,
ram_st_bst_reset_export => OPEN,
- ram_st_bst_address_export => ram_st_bst_mosi.address(c_sdp_ram_st_bst_addr_w-1 DOWNTO 0),
- ram_st_bst_write_export => ram_st_bst_mosi.wr,
- ram_st_bst_writedata_export => ram_st_bst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_st_bst_read_export => ram_st_bst_mosi.rd,
- ram_st_bst_readdata_export => ram_st_bst_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_st_bst_address_export => ram_st_bst_copi.address(c_sdp_ram_st_bst_addr_w-1 DOWNTO 0),
+ ram_st_bst_write_export => ram_st_bst_copi.wr,
+ ram_st_bst_writedata_export => ram_st_bst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_st_bst_read_export => ram_st_bst_copi.rd,
+ ram_st_bst_readdata_export => ram_st_bst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_enable_sst_clk_export => OPEN,
reg_stat_enable_sst_reset_export => OPEN,
- reg_stat_enable_sst_address_export => reg_stat_enable_sst_mosi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
- reg_stat_enable_sst_write_export => reg_stat_enable_sst_mosi.wr,
- reg_stat_enable_sst_writedata_export => reg_stat_enable_sst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_enable_sst_read_export => reg_stat_enable_sst_mosi.rd,
- reg_stat_enable_sst_readdata_export => reg_stat_enable_sst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_sst_address_export => reg_stat_enable_sst_copi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
+ reg_stat_enable_sst_write_export => reg_stat_enable_sst_copi.wr,
+ reg_stat_enable_sst_writedata_export => reg_stat_enable_sst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_sst_read_export => reg_stat_enable_sst_copi.rd,
+ reg_stat_enable_sst_readdata_export => reg_stat_enable_sst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_hdr_dat_sst_clk_export => OPEN,
reg_stat_hdr_dat_sst_reset_export => OPEN,
- reg_stat_hdr_dat_sst_address_export => reg_stat_hdr_dat_sst_mosi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
- reg_stat_hdr_dat_sst_write_export => reg_stat_hdr_dat_sst_mosi.wr,
- reg_stat_hdr_dat_sst_writedata_export => reg_stat_hdr_dat_sst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_hdr_dat_sst_read_export => reg_stat_hdr_dat_sst_mosi.rd,
- reg_stat_hdr_dat_sst_readdata_export => reg_stat_hdr_dat_sst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_sst_address_export => reg_stat_hdr_dat_sst_copi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_sst_write_export => reg_stat_hdr_dat_sst_copi.wr,
+ reg_stat_hdr_dat_sst_writedata_export => reg_stat_hdr_dat_sst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_sst_read_export => reg_stat_hdr_dat_sst_copi.rd,
+ reg_stat_hdr_dat_sst_readdata_export => reg_stat_hdr_dat_sst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_enable_xst_clk_export => OPEN,
reg_stat_enable_xst_reset_export => OPEN,
- reg_stat_enable_xst_address_export => reg_stat_enable_xst_mosi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
- reg_stat_enable_xst_write_export => reg_stat_enable_xst_mosi.wr,
- reg_stat_enable_xst_writedata_export => reg_stat_enable_xst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_enable_xst_read_export => reg_stat_enable_xst_mosi.rd,
- reg_stat_enable_xst_readdata_export => reg_stat_enable_xst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_xst_address_export => reg_stat_enable_xst_copi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
+ reg_stat_enable_xst_write_export => reg_stat_enable_xst_copi.wr,
+ reg_stat_enable_xst_writedata_export => reg_stat_enable_xst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_xst_read_export => reg_stat_enable_xst_copi.rd,
+ reg_stat_enable_xst_readdata_export => reg_stat_enable_xst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_hdr_dat_xst_clk_export => OPEN,
reg_stat_hdr_dat_xst_reset_export => OPEN,
- reg_stat_hdr_dat_xst_address_export => reg_stat_hdr_dat_xst_mosi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
- reg_stat_hdr_dat_xst_write_export => reg_stat_hdr_dat_xst_mosi.wr,
- reg_stat_hdr_dat_xst_writedata_export => reg_stat_hdr_dat_xst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_hdr_dat_xst_read_export => reg_stat_hdr_dat_xst_mosi.rd,
- reg_stat_hdr_dat_xst_readdata_export => reg_stat_hdr_dat_xst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_xst_address_export => reg_stat_hdr_dat_xst_copi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_xst_write_export => reg_stat_hdr_dat_xst_copi.wr,
+ reg_stat_hdr_dat_xst_writedata_export => reg_stat_hdr_dat_xst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_xst_read_export => reg_stat_hdr_dat_xst_copi.rd,
+ reg_stat_hdr_dat_xst_readdata_export => reg_stat_hdr_dat_xst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_enable_bst_clk_export => OPEN,
reg_stat_enable_bst_reset_export => OPEN,
- reg_stat_enable_bst_address_export => reg_stat_enable_bst_mosi.address(c_sdp_reg_stat_enable_bst_addr_w-1 DOWNTO 0),
- reg_stat_enable_bst_write_export => reg_stat_enable_bst_mosi.wr,
- reg_stat_enable_bst_writedata_export => reg_stat_enable_bst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_enable_bst_read_export => reg_stat_enable_bst_mosi.rd,
- reg_stat_enable_bst_readdata_export => reg_stat_enable_bst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_bst_address_export => reg_stat_enable_bst_copi.address(c_sdp_reg_stat_enable_bst_addr_w-1 DOWNTO 0),
+ reg_stat_enable_bst_write_export => reg_stat_enable_bst_copi.wr,
+ reg_stat_enable_bst_writedata_export => reg_stat_enable_bst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_bst_read_export => reg_stat_enable_bst_copi.rd,
+ reg_stat_enable_bst_readdata_export => reg_stat_enable_bst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_hdr_dat_bst_clk_export => OPEN,
reg_stat_hdr_dat_bst_reset_export => OPEN,
- reg_stat_hdr_dat_bst_address_export => reg_stat_hdr_dat_bst_mosi.address(c_sdp_reg_stat_hdr_dat_bst_addr_w-1 DOWNTO 0),
- reg_stat_hdr_dat_bst_write_export => reg_stat_hdr_dat_bst_mosi.wr,
- reg_stat_hdr_dat_bst_writedata_export => reg_stat_hdr_dat_bst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_hdr_dat_bst_read_export => reg_stat_hdr_dat_bst_mosi.rd,
- reg_stat_hdr_dat_bst_readdata_export => reg_stat_hdr_dat_bst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_bst_address_export => reg_stat_hdr_dat_bst_copi.address(c_sdp_reg_stat_hdr_dat_bst_addr_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_bst_write_export => reg_stat_hdr_dat_bst_copi.wr,
+ reg_stat_hdr_dat_bst_writedata_export => reg_stat_hdr_dat_bst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_bst_read_export => reg_stat_hdr_dat_bst_copi.rd,
+ reg_stat_hdr_dat_bst_readdata_export => reg_stat_hdr_dat_bst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_crosslets_info_clk_export => OPEN,
reg_crosslets_info_reset_export => OPEN,
- reg_crosslets_info_address_export => reg_crosslets_info_mosi.address(c_sdp_reg_crosslets_info_addr_w-1 DOWNTO 0),
- reg_crosslets_info_write_export => reg_crosslets_info_mosi.wr,
- reg_crosslets_info_writedata_export => reg_crosslets_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_crosslets_info_read_export => reg_crosslets_info_mosi.rd,
- reg_crosslets_info_readdata_export => reg_crosslets_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_crosslets_info_address_export => reg_crosslets_info_copi.address(c_sdp_reg_crosslets_info_addr_w-1 DOWNTO 0),
+ reg_crosslets_info_write_export => reg_crosslets_info_copi.wr,
+ reg_crosslets_info_writedata_export => reg_crosslets_info_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_crosslets_info_read_export => reg_crosslets_info_copi.rd,
+ reg_crosslets_info_readdata_export => reg_crosslets_info_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_nof_crosslets_clk_export => OPEN,
reg_nof_crosslets_reset_export => OPEN,
- reg_nof_crosslets_address_export => reg_nof_crosslets_mosi.address(c_sdp_reg_nof_crosslets_addr_w-1 DOWNTO 0),
- reg_nof_crosslets_write_export => reg_nof_crosslets_mosi.wr,
- reg_nof_crosslets_writedata_export => reg_nof_crosslets_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_nof_crosslets_read_export => reg_nof_crosslets_mosi.rd,
- reg_nof_crosslets_readdata_export => reg_nof_crosslets_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_nof_crosslets_address_export => reg_nof_crosslets_copi.address(c_sdp_reg_nof_crosslets_addr_w-1 DOWNTO 0),
+ reg_nof_crosslets_write_export => reg_nof_crosslets_copi.wr,
+ reg_nof_crosslets_writedata_export => reg_nof_crosslets_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_nof_crosslets_read_export => reg_nof_crosslets_copi.rd,
+ reg_nof_crosslets_readdata_export => reg_nof_crosslets_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_bsn_sync_scheduler_xsub_clk_export => OPEN,
reg_bsn_sync_scheduler_xsub_reset_export => OPEN,
- reg_bsn_sync_scheduler_xsub_address_export => reg_bsn_sync_scheduler_xsub_mosi.address(c_sdp_reg_bsn_sync_scheduler_xsub_addr_w-1 DOWNTO 0),
- reg_bsn_sync_scheduler_xsub_write_export => reg_bsn_sync_scheduler_xsub_mosi.wr,
- reg_bsn_sync_scheduler_xsub_writedata_export => reg_bsn_sync_scheduler_xsub_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_bsn_sync_scheduler_xsub_read_export => reg_bsn_sync_scheduler_xsub_mosi.rd,
- reg_bsn_sync_scheduler_xsub_readdata_export => reg_bsn_sync_scheduler_xsub_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_sync_scheduler_xsub_address_export => reg_bsn_sync_scheduler_xsub_copi.address(c_sdp_reg_bsn_sync_scheduler_xsub_addr_w-1 DOWNTO 0),
+ reg_bsn_sync_scheduler_xsub_write_export => reg_bsn_sync_scheduler_xsub_copi.wr,
+ reg_bsn_sync_scheduler_xsub_writedata_export => reg_bsn_sync_scheduler_xsub_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_sync_scheduler_xsub_read_export => reg_bsn_sync_scheduler_xsub_copi.rd,
+ reg_bsn_sync_scheduler_xsub_readdata_export => reg_bsn_sync_scheduler_xsub_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_st_xsq_clk_export => OPEN,
ram_st_xsq_reset_export => OPEN,
- ram_st_xsq_address_export => ram_st_xsq_mosi.address(c_sdp_ram_st_xsq_arr_addr_w-1 DOWNTO 0),
- ram_st_xsq_write_export => ram_st_xsq_mosi.wr,
- ram_st_xsq_writedata_export => ram_st_xsq_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_st_xsq_read_export => ram_st_xsq_mosi.rd,
- ram_st_xsq_readdata_export => ram_st_xsq_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_st_xsq_address_export => ram_st_xsq_copi.address(c_sdp_ram_st_xsq_arr_addr_w-1 DOWNTO 0),
+ ram_st_xsq_write_export => ram_st_xsq_copi.wr,
+ ram_st_xsq_writedata_export => ram_st_xsq_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_st_xsq_read_export => ram_st_xsq_copi.rd,
+ ram_st_xsq_readdata_export => ram_st_xsq_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_nw_10GbE_mac_clk_export => OPEN,
reg_nw_10GbE_mac_reset_export => OPEN,
- reg_nw_10GbE_mac_address_export => reg_nw_10GbE_mac_mosi.address(c_sdp_reg_nw_10GbE_mac_addr_w-1 DOWNTO 0),
- reg_nw_10GbE_mac_write_export => reg_nw_10GbE_mac_mosi.wr,
- reg_nw_10GbE_mac_writedata_export => reg_nw_10GbE_mac_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_nw_10GbE_mac_read_export => reg_nw_10GbE_mac_mosi.rd,
- reg_nw_10GbE_mac_readdata_export => reg_nw_10GbE_mac_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_nw_10GbE_mac_address_export => reg_nw_10GbE_mac_copi.address(c_sdp_reg_nw_10GbE_mac_addr_w-1 DOWNTO 0),
+ reg_nw_10GbE_mac_write_export => reg_nw_10GbE_mac_copi.wr,
+ reg_nw_10GbE_mac_writedata_export => reg_nw_10GbE_mac_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_nw_10GbE_mac_read_export => reg_nw_10GbE_mac_copi.rd,
+ reg_nw_10GbE_mac_readdata_export => reg_nw_10GbE_mac_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_nw_10GbE_eth10g_clk_export => OPEN,
reg_nw_10GbE_eth10g_reset_export => OPEN,
- reg_nw_10GbE_eth10g_address_export => reg_nw_10GbE_eth10g_mosi.address(c_sdp_reg_nw_10GbE_eth10g_addr_w-1 DOWNTO 0),
- reg_nw_10GbE_eth10g_write_export => reg_nw_10GbE_eth10g_mosi.wr,
- reg_nw_10GbE_eth10g_writedata_export => reg_nw_10GbE_eth10g_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_nw_10GbE_eth10g_read_export => reg_nw_10GbE_eth10g_mosi.rd,
- reg_nw_10GbE_eth10g_readdata_export => reg_nw_10GbE_eth10g_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_nw_10GbE_eth10g_address_export => reg_nw_10GbE_eth10g_copi.address(c_sdp_reg_nw_10GbE_eth10g_addr_w-1 DOWNTO 0),
+ reg_nw_10GbE_eth10g_write_export => reg_nw_10GbE_eth10g_copi.wr,
+ reg_nw_10GbE_eth10g_writedata_export => reg_nw_10GbE_eth10g_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_nw_10GbE_eth10g_read_export => reg_nw_10GbE_eth10g_copi.rd,
+ reg_nw_10GbE_eth10g_readdata_export => reg_nw_10GbE_eth10g_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_bsn_align_v2_clk_export => OPEN,
reg_bsn_align_v2_reset_export => OPEN,
@@ -923,6 +937,22 @@ BEGIN
reg_bsn_monitor_v2_bsn_align_v2_output_read_export => reg_bsn_monitor_v2_bsn_align_v2_output_copi.rd,
reg_bsn_monitor_v2_bsn_align_v2_output_readdata_export => reg_bsn_monitor_v2_bsn_align_v2_output_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_sst_offload_clk_export => OPEN,
+ reg_bsn_monitor_v2_sst_offload_reset_export => OPEN,
+ reg_bsn_monitor_v2_sst_offload_address_export => reg_bsn_monitor_v2_sst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_sst_offload_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_sst_offload_write_export => reg_bsn_monitor_v2_sst_offload_copi.wr,
+ reg_bsn_monitor_v2_sst_offload_writedata_export => reg_bsn_monitor_v2_sst_offload_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_sst_offload_read_export => reg_bsn_monitor_v2_sst_offload_copi.rd,
+ reg_bsn_monitor_v2_sst_offload_readdata_export => reg_bsn_monitor_v2_sst_offload_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_bst_offload_clk_export => OPEN,
+ reg_bsn_monitor_v2_bst_offload_reset_export => OPEN,
+ reg_bsn_monitor_v2_bst_offload_address_export => reg_bsn_monitor_v2_bst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_bst_offload_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_bst_offload_write_export => reg_bsn_monitor_v2_bst_offload_copi.wr,
+ reg_bsn_monitor_v2_bst_offload_writedata_export => reg_bsn_monitor_v2_bst_offload_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_bst_offload_read_export => reg_bsn_monitor_v2_bst_offload_copi.rd,
+ reg_bsn_monitor_v2_bst_offload_readdata_export => reg_bsn_monitor_v2_bst_offload_cipo.rddata(c_word_w-1 DOWNTO 0),
+
reg_bsn_monitor_v2_xst_offload_clk_export => OPEN,
reg_bsn_monitor_v2_xst_offload_reset_export => OPEN,
reg_bsn_monitor_v2_xst_offload_address_export => reg_bsn_monitor_v2_xst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_xst_offload_addr_w-1 DOWNTO 0),
@@ -989,11 +1019,11 @@ BEGIN
ram_scrap_clk_export => OPEN,
ram_scrap_reset_export => OPEN,
- ram_scrap_address_export => ram_scrap_mosi.address(9-1 DOWNTO 0),
- ram_scrap_write_export => ram_scrap_mosi.wr,
- ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_scrap_read_export => ram_scrap_mosi.rd,
- ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w-1 DOWNTO 0)
+ ram_scrap_address_export => ram_scrap_copi.address(9-1 DOWNTO 0),
+ ram_scrap_write_export => ram_scrap_copi.wr,
+ ram_scrap_writedata_export => ram_scrap_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_scrap_read_export => ram_scrap_copi.rd,
+ ram_scrap_readdata_export => ram_scrap_cipo.rddata(c_word_w-1 DOWNTO 0)
);
END GENERATE;
END str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
index c82f450ad9525890f4a7ba21931f133b48df1123..44cd2f84d367c441163b6a06abb07f44a80849f9 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
@@ -73,6 +73,8 @@ ENTITY node_sdp_beamformer IS
reg_stat_enable_miso : OUT t_mem_miso;
reg_stat_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_stat_hdr_dat_miso : OUT t_mem_miso;
+ reg_bsn_monitor_v2_bst_offload_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_bst_offload_cipo : OUT t_mem_cipo;
sdp_info : IN t_sdp_info;
gn_id : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
@@ -302,6 +304,9 @@ BEGIN
reg_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
reg_hdr_dat_miso => reg_stat_hdr_dat_miso,
+ reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
+
in_sosi => bf_sum_sosi,
out_sosi => bst_udp_sosi,
out_siso => bst_udp_siso,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
index 03f715308242a93f66576406a97ecc7148d20e3d..4a0ad75b512b560e095066e0f5b7cf3df80c230a 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
@@ -75,8 +75,8 @@ ENTITY node_sdp_correlator IS
reg_bsn_monitor_v2_bsn_align_input_cipo : OUT t_mem_cipo;
reg_bsn_monitor_v2_bsn_align_output_copi : IN t_mem_copi := c_mem_copi_rst;
reg_bsn_monitor_v2_bsn_align_output_cipo : OUT t_mem_cipo;
- reg_xst_udp_monitor_copi : IN t_mem_copi := c_mem_copi_rst;
- reg_xst_udp_monitor_cipo : OUT t_mem_cipo;
+ reg_bsn_monitor_v2_xst_offload_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_xst_offload_cipo : OUT t_mem_cipo;
sdp_info : IN t_sdp_info;
ring_info : IN t_ring_info;
@@ -457,6 +457,9 @@ BEGIN
reg_hdr_dat_mosi => reg_stat_hdr_dat_copi,
reg_hdr_dat_miso => reg_stat_hdr_dat_cipo,
+ reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+
in_sosi => crosslets_sosi,
out_sosi => mon_xst_udp_sosi_arr(0),
out_siso => xst_udp_siso,
@@ -472,33 +475,4 @@ BEGIN
crosslets_info => crosslets_info
);
- ---------------------------------------------------------------
- -- BSN Monitor for XST UDP offload
- ---------------------------------------------------------------
- u_bsn_mon_xst_udp : ENTITY dp_lib.mms_dp_bsn_monitor_v2
- GENERIC MAP (
- g_nof_streams => 1,
- g_cross_clock_domain => TRUE,
- g_sync_timeout => c_sdp_N_clk_per_sync,
- g_bsn_w => c_dp_stream_bsn_w,
- g_error_bi => 0,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_cnt_latency_w => c_word_w
- )
- PORT MAP (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_xst_udp_monitor_copi,
- reg_miso => reg_xst_udp_monitor_cipo,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ref_sync => crosslets_sosi.sync, -- using crosslets_sosi sync instead of xst_udp_sosi as it has no sync.
-
- in_sosi_arr => mon_xst_udp_sosi_arr
- );
-
END str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
index aadbfee3b3af8fc6980d565c488d954dad0ec29c..dddef0eb92b56a52d0b045b5c42c685d70d8b172 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
@@ -82,6 +82,8 @@ ENTITY node_sdp_filterbank IS
reg_enable_miso : OUT t_mem_miso;
reg_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_hdr_dat_miso : OUT t_mem_miso;
+ reg_bsn_monitor_v2_sst_offload_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_sst_offload_cipo : OUT t_mem_cipo;
sdp_info : IN t_sdp_info;
gn_id : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
@@ -354,6 +356,9 @@ BEGIN
reg_hdr_dat_mosi => reg_hdr_dat_mosi,
reg_hdr_dat_miso => reg_hdr_dat_miso,
+ reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+
in_sosi => dp_selector_out_sosi_arr(0),
out_sosi => sst_udp_sosi,
out_siso => sst_udp_siso,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 554dc4248add36930664d7f767a9554118eba53c..75776be2c4d5b0fd2f72bf2f333ee4e3074ed64c 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -394,6 +394,8 @@ PACKAGE sdp_pkg is
-----------------------------------------------------------------------------
-- MM
-----------------------------------------------------------------------------
+ -- BSN monitor V2 address width
+ CONSTANT c_sdp_reg_bsn_monitor_v2_addr_w : NATURAL := ceil_Log2(7);
-- 10GbE MM address widths
CONSTANT c_sdp_reg_bf_hdr_dat_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_cep_hdr_dat_addr_w;
@@ -423,24 +425,26 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_reg_aduh_monitor_addr_w : NATURAL := ceil_log2(c_sdp_S_pn) + 2;
-- FSUB MM address widths
- CONSTANT c_sdp_ram_fil_coefs_addr_w : NATURAL := ceil_log2(c_sdp_N_fft * c_sdp_N_taps);
- CONSTANT c_sdp_ram_st_sst_addr_w : NATURAL := ceil_log2(c_sdp_P_pfb * c_sdp_N_sub * c_sdp_Q_fft * c_sdp_W_statistic_sz);
- CONSTANT c_sdp_reg_si_addr_w : NATURAL := 1; --enable/disable
- CONSTANT c_sdp_ram_equalizer_gains_addr_w : NATURAL := ceil_log2(c_sdp_P_pfb*c_sdp_N_sub*c_sdp_Q_fft);
- CONSTANT c_sdp_reg_dp_selector_addr_w : NATURAL := 1; --Select input 0 or 1.
+ CONSTANT c_sdp_ram_fil_coefs_addr_w : NATURAL := ceil_log2(c_sdp_N_fft * c_sdp_N_taps);
+ CONSTANT c_sdp_ram_st_sst_addr_w : NATURAL := ceil_log2(c_sdp_P_pfb * c_sdp_N_sub * c_sdp_Q_fft * c_sdp_W_statistic_sz);
+ CONSTANT c_sdp_reg_si_addr_w : NATURAL := 1; --enable/disable
+ CONSTANT c_sdp_ram_equalizer_gains_addr_w : NATURAL := ceil_log2(c_sdp_P_pfb*c_sdp_N_sub*c_sdp_Q_fft);
+ CONSTANT c_sdp_reg_dp_selector_addr_w : NATURAL := 1; --Select input 0 or 1.
+ CONSTANT c_sdp_reg_bsn_monitor_v2_sst_offload_addr_w : NATURAL := c_sdp_reg_bsn_monitor_v2_addr_w;
-- STAT UDP offload MM address widths
CONSTANT c_sdp_reg_stat_enable_addr_w : NATURAL := 1;
-- BF MM address widths
- CONSTANT c_sdp_reg_sdp_info_addr_w : NATURAL := 4;
- CONSTANT c_sdp_ram_ss_ss_wide_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
- CONSTANT c_sdp_ram_bf_weights_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_N_pol_bf * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
- CONSTANT c_sdp_reg_bf_scale_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 1;
- CONSTANT c_sdp_reg_dp_xonoff_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 1;
- CONSTANT c_sdp_ram_st_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_S_sub_bf * c_sdp_N_pol_bf * c_sdp_W_statistic_sz);
- CONSTANT c_sdp_reg_stat_enable_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_stat_enable_addr_w;
- CONSTANT c_sdp_reg_stat_hdr_dat_bst_addr_w: NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_stat_hdr_dat_addr_w;
+ CONSTANT c_sdp_reg_sdp_info_addr_w : NATURAL := 4;
+ CONSTANT c_sdp_ram_ss_ss_wide_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
+ CONSTANT c_sdp_ram_bf_weights_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_N_pol_bf * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
+ CONSTANT c_sdp_reg_bf_scale_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 1;
+ CONSTANT c_sdp_reg_dp_xonoff_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 1;
+ CONSTANT c_sdp_ram_st_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_S_sub_bf * c_sdp_N_pol_bf * c_sdp_W_statistic_sz);
+ CONSTANT c_sdp_reg_stat_enable_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_stat_enable_addr_w;
+ CONSTANT c_sdp_reg_stat_hdr_dat_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_stat_hdr_dat_addr_w;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_bst_offload_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bsn_monitor_v2_addr_w;
-- XSUB
CONSTANT c_sdp_crosslets_index_w : NATURAL := ceil_log2(c_sdp_N_sub);
@@ -467,25 +471,25 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_xst_nof_clk_per_sync_min : NATURAL := c_sdp_N_clk_per_sync / 10; -- 0.1 second
-- XSUB MM address widths
- CONSTANT c_sdp_reg_crosslets_info_addr_w : NATURAL := c_sdp_mm_reg_crosslets_info.adr_w;
- CONSTANT c_sdp_reg_nof_crosslets_addr_w : NATURAL := c_sdp_mm_reg_nof_crosslets.adr_w;
- CONSTANT c_sdp_reg_bsn_sync_scheduler_xsub_addr_w : NATURAL := 4;
- CONSTANT c_sdp_ram_st_xsq_addr_w : NATURAL := ceil_log2(c_sdp_N_crosslets_max * c_sdp_X_sq * c_nof_complex * c_sdp_W_statistic_sz);
- CONSTANT c_sdp_ram_st_xsq_arr_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + c_sdp_ram_st_xsq_addr_w;
- CONSTANT c_sdp_reg_bsn_align_v2_addr_w : NATURAL := ceil_log2(2*c_sdp_P_sq);
- CONSTANT c_sdp_reg_bsn_monitor_v2_bsn_align_v2_input_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + ceil_Log2(7);
- CONSTANT c_sdp_reg_bsn_monitor_v2_bsn_align_v2_output_addr_w : NATURAL := ceil_Log2(7);
- CONSTANT c_sdp_reg_bsn_monitor_v2_xst_offload_addr_w : NATURAL := ceil_Log2(7);
- CONSTANT c_sdp_reg_ring_lane_info_xst_addr_w : NATURAL := 1;
- CONSTANT c_sdp_reg_bsn_monitor_v2_ring_rx_xst_addr_w : NATURAL := ceil_log2(c_sdp_N_pn_max) + ceil_Log2(7);
- CONSTANT c_sdp_reg_bsn_monitor_v2_ring_tx_xst_addr_w : NATURAL := ceil_log2(c_sdp_N_pn_max) + ceil_Log2(7);
- CONSTANT c_sdp_reg_dp_block_validate_err_xst_addr_w : NATURAL := 4;
- CONSTANT c_sdp_reg_dp_block_validate_bsn_at_sync_xst_addr_w : NATURAL := 2;
+ CONSTANT c_sdp_reg_crosslets_info_addr_w : NATURAL := c_sdp_mm_reg_crosslets_info.adr_w;
+ CONSTANT c_sdp_reg_nof_crosslets_addr_w : NATURAL := c_sdp_mm_reg_nof_crosslets.adr_w;
+ CONSTANT c_sdp_reg_bsn_sync_scheduler_xsub_addr_w : NATURAL := 4;
+ CONSTANT c_sdp_ram_st_xsq_addr_w : NATURAL := ceil_log2(c_sdp_N_crosslets_max * c_sdp_X_sq * c_nof_complex * c_sdp_W_statistic_sz);
+ CONSTANT c_sdp_ram_st_xsq_arr_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + c_sdp_ram_st_xsq_addr_w;
+ CONSTANT c_sdp_reg_bsn_align_v2_addr_w : NATURAL := ceil_log2(2*c_sdp_P_sq);
+ CONSTANT c_sdp_reg_bsn_monitor_v2_bsn_align_v2_input_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_bsn_align_v2_output_addr_w : NATURAL := c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_xst_offload_addr_w : NATURAL := c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_ring_lane_info_xst_addr_w : NATURAL := 1;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_ring_rx_xst_addr_w : NATURAL := ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_ring_tx_xst_addr_w : NATURAL := ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_dp_block_validate_err_xst_addr_w : NATURAL := 4;
+ CONSTANT c_sdp_reg_dp_block_validate_bsn_at_sync_xst_addr_w : NATURAL := 2;
-- RING MM address widths
- CONSTANT c_sdp_reg_bsn_monitor_v2_ring_rx_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + ceil_log2(c_sdp_N_pn_max) + ceil_Log2(7);
- CONSTANT c_sdp_reg_bsn_monitor_v2_ring_tx_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + ceil_log2(c_sdp_N_pn_max) + ceil_Log2(7);
+ CONSTANT c_sdp_reg_bsn_monitor_v2_ring_rx_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_ring_tx_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
CONSTANT c_sdp_reg_ring_lane_info_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 1;
CONSTANT c_sdp_reg_dp_xonoff_lane_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 1;
CONSTANT c_sdp_reg_dp_xonoff_local_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 1;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index 36ab5c31f894559bb67b51e2e29f1c5e8afdc804..8d0c7a7b0f6bb8fa246a6b53c09ef17854fa0b50 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -92,215 +92,223 @@ ENTITY sdp_station IS
----------------------------------------------
-- 10 GbE
----------------------------------------------
- reg_nw_10GbE_mac_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_nw_10GbE_mac_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_nw_10GbE_mac_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_nw_10GbE_mac_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
- reg_nw_10GbE_eth10g_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_nw_10GbE_eth10g_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_nw_10GbE_eth10g_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_nw_10GbE_eth10g_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- AIT
----------------------------------------------
-- JESD
- jesd204b_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- jesd204b_miso : OUT t_mem_miso := c_mem_miso_rst;
+ jesd204b_copi : IN t_mem_copi := c_mem_copi_rst;
+ jesd204b_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- JESD control
- jesd_ctrl_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- jesd_ctrl_miso : OUT t_mem_miso := c_mem_miso_rst;
+ jesd_ctrl_copi : IN t_mem_copi := c_mem_copi_rst;
+ jesd_ctrl_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Shiftram (applies per-antenna delay)
- reg_dp_shiftram_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_dp_shiftram_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_dp_shiftram_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_dp_shiftram_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- bsn source
- reg_bsn_source_v2_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_source_v2_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_bsn_source_v2_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_source_v2_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- bsn scheduler
- reg_bsn_scheduler_wg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_scheduler_wg_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_bsn_scheduler_wg_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_scheduler_wg_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- WG
- reg_wg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_wg_miso : OUT t_mem_miso := c_mem_miso_rst;
- ram_wg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_wg_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_wg_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_wg_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+ ram_wg_copi : IN t_mem_copi := c_mem_copi_rst;
+ ram_wg_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- BSN MONITOR
- reg_bsn_monitor_input_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_monitor_input_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_bsn_monitor_input_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_input_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Data buffer bsn
- ram_diag_data_buf_bsn_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_diag_data_buf_bsn_miso : OUT t_mem_miso := c_mem_miso_rst;
- reg_diag_data_buf_bsn_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_diag_data_buf_bsn_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_diag_data_buf_bsn_copi : IN t_mem_copi := c_mem_copi_rst;
+ ram_diag_data_buf_bsn_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+ reg_diag_data_buf_bsn_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_diag_data_buf_bsn_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- ST Histogram
- ram_st_histogram_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_st_histogram_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_st_histogram_copi : IN t_mem_copi := c_mem_copi_rst;
+ ram_st_histogram_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Aduh statistics monitor
- reg_aduh_monitor_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_aduh_monitor_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_aduh_monitor_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_aduh_monitor_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- FSUB
----------------------------------------------
-- Subband statistics
- ram_st_sst_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_st_sst_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_st_sst_copi : IN t_mem_copi := c_mem_copi_rst;
+ ram_st_sst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Spectral Inversion
- reg_si_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_si_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_si_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_si_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Filter coefficients
- ram_fil_coefs_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_fil_coefs_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_fil_coefs_copi : IN t_mem_copi := c_mem_copi_rst;
+ ram_fil_coefs_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Equalizer gains
- ram_equalizer_gains_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_equalizer_gains_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_equalizer_gains_copi : IN t_mem_copi := c_mem_copi_rst;
+ ram_equalizer_gains_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- DP Selector
- reg_dp_selector_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_dp_selector_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_dp_selector_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_dp_selector_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+ -- SST UDP offload bsn monitor
+ reg_bsn_monitor_v2_sst_offload_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_sst_offload_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- SDP Info
----------------------------------------------
- reg_sdp_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_sdp_info_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_sdp_info_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_sdp_info_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- RING Info
----------------------------------------------
- reg_ring_info_copi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_ring_info_cipo : OUT t_mem_miso := c_mem_miso_rst;
+ reg_ring_info_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_ring_info_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- XSUB
----------------------------------------------
-- crosslets_info
- reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_crosslets_info_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_crosslets_info_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_crosslets_info_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- nof_crosslets
- reg_nof_crosslets_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_nof_crosslets_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_nof_crosslets_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_nof_crosslets_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- bsn_scheduler_xsub
- reg_bsn_sync_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_sync_scheduler_xsub_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_bsn_sync_scheduler_xsub_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_sync_scheduler_xsub_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- st_xsq
- ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_st_xsq_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_st_xsq_copi : IN t_mem_copi := c_mem_copi_rst;
+ ram_st_xsq_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- BF
----------------------------------------------
-- Beamlet Subband Select
- ram_ss_ss_wide_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_ss_ss_wide_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_ss_ss_wide_copi : IN t_mem_copi := c_mem_copi_rst;
+ ram_ss_ss_wide_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Local BF bf weights
- ram_bf_weights_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_bf_weights_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_bf_weights_copi : IN t_mem_copi := c_mem_copi_rst;
+ ram_bf_weights_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- mms_dp_scale Scale Beamlets
- reg_bf_scale_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_bf_scale_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_bf_scale_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bf_scale_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Beamlet Data Output header fields
- reg_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_hdr_dat_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_hdr_dat_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_hdr_dat_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Beamlet Data Output xonoff
- reg_dp_xonoff_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_dp_xonoff_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_dp_xonoff_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_dp_xonoff_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Beamlet Statistics (BST)
- ram_st_bst_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_st_bst_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_st_bst_copi : IN t_mem_copi := c_mem_copi_rst;
+ ram_st_bst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+
+ -- BST UDP offload bsn monitor
+ reg_bsn_monitor_v2_bst_offload_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_bst_offload_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+
----------------------------------------------
-- SST
----------------------------------------------
-- Statistics Enable
- reg_stat_enable_sst_mosi : IN t_mem_mosi;
- reg_stat_enable_sst_miso : OUT t_mem_miso;
+ reg_stat_enable_sst_copi : IN t_mem_copi;
+ reg_stat_enable_sst_cipo : OUT t_mem_cipo;
-- Statistics header info
- reg_stat_hdr_dat_sst_mosi : IN t_mem_mosi;
- reg_stat_hdr_dat_sst_miso : OUT t_mem_miso;
+ reg_stat_hdr_dat_sst_copi : IN t_mem_copi;
+ reg_stat_hdr_dat_sst_cipo : OUT t_mem_cipo;
----------------------------------------------
-- XST
----------------------------------------------
-- Statistics Enable
- reg_stat_enable_xst_mosi : IN t_mem_mosi;
- reg_stat_enable_xst_miso : OUT t_mem_miso;
+ reg_stat_enable_xst_copi : IN t_mem_copi;
+ reg_stat_enable_xst_cipo : OUT t_mem_cipo;
-- Statistics header info
- reg_stat_hdr_dat_xst_mosi : IN t_mem_mosi;
- reg_stat_hdr_dat_xst_miso : OUT t_mem_miso;
+ reg_stat_hdr_dat_xst_copi : IN t_mem_copi;
+ reg_stat_hdr_dat_xst_cipo : OUT t_mem_cipo;
-- XST bsn aligner_v2
- reg_bsn_align_copi : IN t_mem_mosi;
- reg_bsn_align_cipo : OUT t_mem_miso;
+ reg_bsn_align_copi : IN t_mem_copi;
+ reg_bsn_align_cipo : OUT t_mem_cipo;
-- XST bsn aligner_v2 bsn monitors
- reg_bsn_monitor_v2_bsn_align_input_copi : IN t_mem_mosi;
- reg_bsn_monitor_v2_bsn_align_input_cipo : OUT t_mem_miso;
- reg_bsn_monitor_v2_bsn_align_output_copi : IN t_mem_mosi;
- reg_bsn_monitor_v2_bsn_align_output_cipo : OUT t_mem_miso;
+ reg_bsn_monitor_v2_bsn_align_input_copi : IN t_mem_copi;
+ reg_bsn_monitor_v2_bsn_align_input_cipo : OUT t_mem_cipo;
+ reg_bsn_monitor_v2_bsn_align_output_copi : IN t_mem_copi;
+ reg_bsn_monitor_v2_bsn_align_output_cipo : OUT t_mem_cipo;
-- XST UDP offload bsn monitor
- reg_xst_udp_monitor_copi : IN t_mem_mosi;
- reg_xst_udp_monitor_cipo : OUT t_mem_miso;
+ reg_bsn_monitor_v2_xst_offload_copi : IN t_mem_copi;
+ reg_bsn_monitor_v2_xst_offload_cipo : OUT t_mem_cipo;
-- XST ring lane info
- reg_ring_lane_info_xst_copi : IN t_mem_mosi;
- reg_ring_lane_info_xst_cipo : OUT t_mem_miso;
+ reg_ring_lane_info_xst_copi : IN t_mem_copi;
+ reg_ring_lane_info_xst_cipo : OUT t_mem_cipo;
-- XST ring bsn monitor rx
- reg_bsn_monitor_v2_ring_rx_xst_copi : IN t_mem_mosi;
- reg_bsn_monitor_v2_ring_rx_xst_cipo : OUT t_mem_miso;
+ reg_bsn_monitor_v2_ring_rx_xst_copi : IN t_mem_copi;
+ reg_bsn_monitor_v2_ring_rx_xst_cipo : OUT t_mem_cipo;
-- XST ring bsn monitor tx
- reg_bsn_monitor_v2_ring_tx_xst_copi : IN t_mem_mosi;
- reg_bsn_monitor_v2_ring_tx_xst_cipo : OUT t_mem_miso;
+ reg_bsn_monitor_v2_ring_tx_xst_copi : IN t_mem_copi;
+ reg_bsn_monitor_v2_ring_tx_xst_cipo : OUT t_mem_cipo;
-- XST ring validate err
- reg_dp_block_validate_err_xst_copi : IN t_mem_mosi;
- reg_dp_block_validate_err_xst_cipo : OUT t_mem_miso;
+ reg_dp_block_validate_err_xst_copi : IN t_mem_copi;
+ reg_dp_block_validate_err_xst_cipo : OUT t_mem_cipo;
-- XST ring bsn at sync
- reg_dp_block_validate_bsn_at_sync_xst_copi : IN t_mem_mosi;
- reg_dp_block_validate_bsn_at_sync_xst_cipo : OUT t_mem_miso;
+ reg_dp_block_validate_bsn_at_sync_xst_copi : IN t_mem_copi;
+ reg_dp_block_validate_bsn_at_sync_xst_cipo : OUT t_mem_cipo;
-- XST ring MAC
- reg_tr_10GbE_mac_copi : IN t_mem_mosi;
- reg_tr_10GbE_mac_cipo : OUT t_mem_miso;
+ reg_tr_10GbE_mac_copi : IN t_mem_copi;
+ reg_tr_10GbE_mac_cipo : OUT t_mem_cipo;
-- XST ring ETH
- reg_tr_10GbE_eth10g_copi : IN t_mem_mosi;
- reg_tr_10GbE_eth10g_cipo : OUT t_mem_miso;
+ reg_tr_10GbE_eth10g_copi : IN t_mem_copi;
+ reg_tr_10GbE_eth10g_cipo : OUT t_mem_cipo;
----------------------------------------------
-- BST
----------------------------------------------
-- Statistics Enable
- reg_stat_enable_bst_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_stat_enable_bst_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_stat_enable_bst_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_stat_enable_bst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Statistics header info
- reg_stat_hdr_dat_bst_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_stat_hdr_dat_bst_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_stat_hdr_dat_bst_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_stat_hdr_dat_bst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- RING_0 serial
RING_0_TX: OUT STD_LOGIC_VECTOR( c_quad - 1 DOWNTO 0) := (OTHERS => '0');
@@ -367,39 +375,44 @@ ARCHITECTURE str OF sdp_station IS
-- BF
----------------------------------------------
-- Beamlet Subband Select
- SIGNAL ram_ss_ss_wide_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL ram_ss_ss_wide_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ SIGNAL ram_ss_ss_wide_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL ram_ss_ss_wide_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
-- Local BF bf weights
- SIGNAL ram_bf_weights_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL ram_bf_weights_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ SIGNAL ram_bf_weights_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL ram_bf_weights_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
-- mms_dp_scale Scale Beamlets
- SIGNAL reg_bf_scale_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL reg_bf_scale_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ SIGNAL reg_bf_scale_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_bf_scale_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
-- Beamlet Data Output header fields
- SIGNAL reg_hdr_dat_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL reg_hdr_dat_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ SIGNAL reg_hdr_dat_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_hdr_dat_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
-- Beamlet Data Output xonoff
- SIGNAL reg_dp_xonoff_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL reg_dp_xonoff_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ SIGNAL reg_dp_xonoff_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_dp_xonoff_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
-- Beamlet Statistics (BST)
- SIGNAL ram_st_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL ram_st_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ SIGNAL ram_st_bst_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL ram_st_bst_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
----------------------------------------------
-- BST
----------------------------------------------
-- Statistics Enable
- SIGNAL reg_stat_enable_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL reg_stat_enable_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ SIGNAL reg_stat_enable_bst_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_stat_enable_bst_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
-- Statistics header info
- SIGNAL reg_stat_hdr_dat_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL reg_stat_hdr_dat_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ SIGNAL reg_stat_hdr_dat_bst_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_stat_hdr_dat_bst_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
+
+
+ SIGNAL reg_bsn_monitor_v2_bst_offload_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_bsn_monitor_v2_bst_offload_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
+
----------------------------------------------
SIGNAL ait_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
@@ -479,8 +492,8 @@ BEGIN
dp_clk => dp_clk,
dp_rst => dp_rst,
- reg_mosi => reg_sdp_info_mosi,
- reg_miso => reg_sdp_info_miso,
+ reg_mosi => reg_sdp_info_copi,
+ reg_miso => reg_sdp_info_cipo,
-- inputs from other blocks
gn_index => gn_index,
@@ -528,30 +541,30 @@ BEGIN
dp_rst => dp_rst,
-- mm control buses
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_v2_mosi => reg_bsn_source_v2_mosi,
- reg_bsn_source_v2_miso => reg_bsn_source_v2_miso,
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_st_histogram_mosi => ram_st_histogram_mosi,
- ram_st_histogram_miso => ram_st_histogram_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+ jesd_ctrl_mosi => jesd_ctrl_copi,
+ jesd_ctrl_miso => jesd_ctrl_cipo,
+ jesd204b_mosi => jesd204b_copi,
+ jesd204b_miso => jesd204b_cipo,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_mosi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_miso => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_cipo,
+ reg_wg_mosi => reg_wg_copi,
+ reg_wg_miso => reg_wg_cipo,
+ ram_wg_mosi => ram_wg_copi,
+ ram_wg_miso => ram_wg_cipo,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_mosi => ram_st_histogram_copi,
+ ram_st_histogram_miso => ram_st_histogram_cipo,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_cipo,
-- Jesd external IOs
jesd204b_serial_data => JESD204B_SERIAL_DATA,
@@ -576,41 +589,44 @@ BEGIN
g_scope_selected_subband => g_scope_selected_subband
)
PORT MAP(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => ait_sosi_arr,
- pfb_sosi_arr => pfb_sosi_arr,
- fsub_sosi_arr => fsub_sosi_arr,
- dp_bsn_source_restart => dp_bsn_source_restart,
-
- sst_udp_sosi => udp_tx_sosi_arr(0),
- sst_udp_siso => udp_tx_siso_arr(0),
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- ram_gains_mosi => ram_equalizer_gains_mosi,
- ram_gains_miso => ram_equalizer_gains_miso,
- reg_selector_mosi => reg_dp_selector_mosi,
- reg_selector_miso => reg_dp_selector_miso,
-
- reg_enable_mosi => reg_stat_enable_sst_mosi,
- reg_enable_miso => reg_stat_enable_sst_miso,
- reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_mosi,
- reg_hdr_dat_miso => reg_stat_hdr_dat_sst_miso,
-
- sdp_info => sdp_info,
- gn_id => gn_id,
- eth_src_mac => stat_eth_src_mac,
- ip_src_addr => stat_ip_src_addr,
- udp_src_port => sst_udp_src_port
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => ait_sosi_arr,
+ pfb_sosi_arr => pfb_sosi_arr,
+ fsub_sosi_arr => fsub_sosi_arr,
+ dp_bsn_source_restart => dp_bsn_source_restart,
+
+ sst_udp_sosi => udp_tx_sosi_arr(0),
+ sst_udp_siso => udp_tx_siso_arr(0),
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_si_mosi => reg_si_copi,
+ reg_si_miso => reg_si_cipo,
+ ram_st_sst_mosi => ram_st_sst_copi,
+ ram_st_sst_miso => ram_st_sst_cipo,
+ ram_fil_coefs_mosi => ram_fil_coefs_copi,
+ ram_fil_coefs_miso => ram_fil_coefs_cipo,
+ ram_gains_mosi => ram_equalizer_gains_copi,
+ ram_gains_miso => ram_equalizer_gains_cipo,
+ reg_selector_mosi => reg_dp_selector_copi,
+ reg_selector_miso => reg_dp_selector_cipo,
+
+ reg_enable_mosi => reg_stat_enable_sst_copi,
+ reg_enable_miso => reg_stat_enable_sst_cipo,
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_copi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_sst_cipo,
+
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+ eth_src_mac => stat_eth_src_mac,
+ ip_src_addr => stat_ip_src_addr,
+ udp_src_port => sst_udp_src_port
);
END GENERATE;
@@ -642,19 +658,19 @@ BEGIN
mm_rst => mm_rst,
mm_clk => mm_clk,
- reg_crosslets_info_copi => reg_crosslets_info_mosi,
- reg_crosslets_info_cipo => reg_crosslets_info_miso,
- reg_nof_crosslets_copi => reg_nof_crosslets_mosi,
- reg_nof_crosslets_cipo => reg_nof_crosslets_miso,
- reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_mosi,
- reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_miso,
- ram_st_xsq_copi => ram_st_xsq_mosi,
- ram_st_xsq_cipo => ram_st_xsq_miso,
-
- reg_stat_enable_copi => reg_stat_enable_xst_mosi,
- reg_stat_enable_cipo => reg_stat_enable_xst_miso,
- reg_stat_hdr_dat_copi => reg_stat_hdr_dat_xst_mosi,
- reg_stat_hdr_dat_cipo => reg_stat_hdr_dat_xst_miso,
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo,
+
+ reg_stat_enable_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_cipo => reg_stat_hdr_dat_xst_cipo,
reg_bsn_align_copi => reg_bsn_align_copi,
reg_bsn_align_cipo => reg_bsn_align_cipo,
@@ -662,8 +678,8 @@ BEGIN
reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo,
- reg_xst_udp_monitor_copi => reg_xst_udp_monitor_copi,
- reg_xst_udp_monitor_cipo => reg_xst_udp_monitor_cipo,
+ reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
sdp_info => sdp_info,
ring_info => ring_info,
@@ -827,23 +843,25 @@ BEGIN
mm_rst => mm_rst,
mm_clk => mm_clk,
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi_arr(beamset_id),
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso_arr(beamset_id),
- ram_bf_weights_mosi => ram_bf_weights_mosi_arr(beamset_id),
- ram_bf_weights_miso => ram_bf_weights_miso_arr(beamset_id),
- reg_bf_scale_mosi => reg_bf_scale_mosi_arr(beamset_id),
- reg_bf_scale_miso => reg_bf_scale_miso_arr(beamset_id),
- reg_hdr_dat_mosi => reg_hdr_dat_mosi_arr(beamset_id),
- reg_hdr_dat_miso => reg_hdr_dat_miso_arr(beamset_id),
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi_arr(beamset_id),
- reg_dp_xonoff_miso => reg_dp_xonoff_miso_arr(beamset_id),
- ram_st_bst_mosi => ram_st_bst_mosi_arr(beamset_id),
- ram_st_bst_miso => ram_st_bst_miso_arr(beamset_id),
- reg_stat_enable_mosi => reg_stat_enable_bst_mosi_arr(beamset_id),
- reg_stat_enable_miso => reg_stat_enable_bst_miso_arr(beamset_id),
- reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_bst_mosi_arr(beamset_id),
- reg_stat_hdr_dat_miso => reg_stat_hdr_dat_bst_miso_arr(beamset_id),
-
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_copi_arr(beamset_id),
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_cipo_arr(beamset_id),
+ ram_bf_weights_mosi => ram_bf_weights_copi_arr(beamset_id),
+ ram_bf_weights_miso => ram_bf_weights_cipo_arr(beamset_id),
+ reg_bf_scale_mosi => reg_bf_scale_copi_arr(beamset_id),
+ reg_bf_scale_miso => reg_bf_scale_cipo_arr(beamset_id),
+ reg_hdr_dat_mosi => reg_hdr_dat_copi_arr(beamset_id),
+ reg_hdr_dat_miso => reg_hdr_dat_cipo_arr(beamset_id),
+ reg_dp_xonoff_mosi => reg_dp_xonoff_copi_arr(beamset_id),
+ reg_dp_xonoff_miso => reg_dp_xonoff_cipo_arr(beamset_id),
+ ram_st_bst_mosi => ram_st_bst_copi_arr(beamset_id),
+ ram_st_bst_miso => ram_st_bst_cipo_arr(beamset_id),
+ reg_stat_enable_mosi => reg_stat_enable_bst_copi_arr(beamset_id),
+ reg_stat_enable_miso => reg_stat_enable_bst_cipo_arr(beamset_id),
+ reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_bst_copi_arr(beamset_id),
+ reg_stat_hdr_dat_miso => reg_stat_hdr_dat_bst_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo_arr(beamset_id),
+
sdp_info => sdp_info,
gn_id => gn_id,
@@ -866,10 +884,10 @@ BEGIN
g_mult_addr_w => c_addr_w_ram_ss_ss_wide
)
PORT MAP (
- mosi => ram_ss_ss_wide_mosi,
- miso => ram_ss_ss_wide_miso,
- mosi_arr => ram_ss_ss_wide_mosi_arr,
- miso_arr => ram_ss_ss_wide_miso_arr
+ mosi => ram_ss_ss_wide_copi,
+ miso => ram_ss_ss_wide_cipo,
+ mosi_arr => ram_ss_ss_wide_copi_arr,
+ miso_arr => ram_ss_ss_wide_cipo_arr
);
u_mem_mux_ram_bf_weights : ENTITY common_lib.common_mem_mux
@@ -878,10 +896,10 @@ BEGIN
g_mult_addr_w => c_addr_w_ram_bf_weights
)
PORT MAP (
- mosi => ram_bf_weights_mosi,
- miso => ram_bf_weights_miso,
- mosi_arr => ram_bf_weights_mosi_arr,
- miso_arr => ram_bf_weights_miso_arr
+ mosi => ram_bf_weights_copi,
+ miso => ram_bf_weights_cipo,
+ mosi_arr => ram_bf_weights_copi_arr,
+ miso_arr => ram_bf_weights_cipo_arr
);
u_mem_mux_reg_bf_scale : ENTITY common_lib.common_mem_mux
@@ -890,10 +908,10 @@ BEGIN
g_mult_addr_w => c_addr_w_reg_bf_scale
)
PORT MAP (
- mosi => reg_bf_scale_mosi,
- miso => reg_bf_scale_miso,
- mosi_arr => reg_bf_scale_mosi_arr,
- miso_arr => reg_bf_scale_miso_arr
+ mosi => reg_bf_scale_copi,
+ miso => reg_bf_scale_cipo,
+ mosi_arr => reg_bf_scale_copi_arr,
+ miso_arr => reg_bf_scale_cipo_arr
);
u_mem_mux_reg_hdr_dat : ENTITY common_lib.common_mem_mux
@@ -902,10 +920,10 @@ BEGIN
g_mult_addr_w => c_addr_w_reg_hdr_dat
)
PORT MAP (
- mosi => reg_hdr_dat_mosi,
- miso => reg_hdr_dat_miso,
- mosi_arr => reg_hdr_dat_mosi_arr,
- miso_arr => reg_hdr_dat_miso_arr
+ mosi => reg_hdr_dat_copi,
+ miso => reg_hdr_dat_cipo,
+ mosi_arr => reg_hdr_dat_copi_arr,
+ miso_arr => reg_hdr_dat_cipo_arr
);
u_mem_mux_reg_dp_xonoff : ENTITY common_lib.common_mem_mux
@@ -914,10 +932,10 @@ BEGIN
g_mult_addr_w => c_addr_w_reg_dp_xonoff
)
PORT MAP (
- mosi => reg_dp_xonoff_mosi,
- miso => reg_dp_xonoff_miso,
- mosi_arr => reg_dp_xonoff_mosi_arr,
- miso_arr => reg_dp_xonoff_miso_arr
+ mosi => reg_dp_xonoff_copi,
+ miso => reg_dp_xonoff_cipo,
+ mosi_arr => reg_dp_xonoff_copi_arr,
+ miso_arr => reg_dp_xonoff_cipo_arr
);
u_mem_mux_ram_st_bst : ENTITY common_lib.common_mem_mux
@@ -926,10 +944,10 @@ BEGIN
g_mult_addr_w => c_addr_w_ram_st_bst
)
PORT MAP (
- mosi => ram_st_bst_mosi,
- miso => ram_st_bst_miso,
- mosi_arr => ram_st_bst_mosi_arr,
- miso_arr => ram_st_bst_miso_arr
+ mosi => ram_st_bst_copi,
+ miso => ram_st_bst_cipo,
+ mosi_arr => ram_st_bst_copi_arr,
+ miso_arr => ram_st_bst_cipo_arr
);
u_mem_mux_reg_stat_enable_bst : ENTITY common_lib.common_mem_mux
@@ -938,10 +956,10 @@ BEGIN
g_mult_addr_w => c_sdp_reg_stat_enable_addr_w
)
PORT MAP (
- mosi => reg_stat_enable_bst_mosi,
- miso => reg_stat_enable_bst_miso,
- mosi_arr => reg_stat_enable_bst_mosi_arr,
- miso_arr => reg_stat_enable_bst_miso_arr
+ mosi => reg_stat_enable_bst_copi,
+ miso => reg_stat_enable_bst_cipo,
+ mosi_arr => reg_stat_enable_bst_copi_arr,
+ miso_arr => reg_stat_enable_bst_cipo_arr
);
u_mem_mux_reg_stat_hdr_dat_bst : ENTITY common_lib.common_mem_mux
@@ -950,12 +968,24 @@ BEGIN
g_mult_addr_w => c_sdp_reg_stat_hdr_dat_addr_w
)
PORT MAP (
- mosi => reg_stat_hdr_dat_bst_mosi,
- miso => reg_stat_hdr_dat_bst_miso,
- mosi_arr => reg_stat_hdr_dat_bst_mosi_arr,
- miso_arr => reg_stat_hdr_dat_bst_miso_arr
+ mosi => reg_stat_hdr_dat_bst_copi,
+ miso => reg_stat_hdr_dat_bst_cipo,
+ mosi_arr => reg_stat_hdr_dat_bst_copi_arr,
+ miso_arr => reg_stat_hdr_dat_bst_cipo_arr
);
-
+
+ u_mem_mux_reg_bsn_monitor_v2_bst_offload : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
+ )
+ PORT MAP (
+ mosi => reg_bsn_monitor_v2_bst_offload_copi,
+ miso => reg_bsn_monitor_v2_bst_offload_cipo,
+ mosi_arr => reg_bsn_monitor_v2_bst_offload_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_bst_offload_cipo_arr
+ );
+
-----------------------------------------------------------------------------
-- DP MUX
-----------------------------------------------------------------------------
@@ -1008,11 +1038,11 @@ BEGIN
mm_rst => mm_rst,
mm_clk => mm_clk,
- reg_mac_mosi => reg_nw_10GbE_mac_mosi,
- reg_mac_miso => reg_nw_10GbE_mac_miso,
+ reg_mac_mosi => reg_nw_10GbE_mac_copi,
+ reg_mac_miso => reg_nw_10GbE_mac_cipo,
- reg_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
- reg_eth10g_miso => reg_nw_10GbE_eth10g_miso,
+ reg_eth10g_mosi => reg_nw_10GbE_eth10g_copi,
+ reg_eth10g_miso => reg_nw_10GbE_eth10g_cipo,
-- DP interface
dp_rst => dp_rst,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
index 45f4be06831c117b547a6c89da4c4cdc061fb3f6..db0124fcbe9e3657a8c1514cee857604bce6f05b 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
@@ -122,6 +122,10 @@ ENTITY sdp_statistics_offload IS
reg_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_hdr_dat_miso : OUT t_mem_miso;
+ -- Memory access bsn monitor udp offload
+ reg_bsn_monitor_v2_offload_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_offload_cipo : OUT t_mem_cipo;
+
-- Input timing regarding the integration interval of the statistics
in_sosi : IN t_dp_sosi;
@@ -212,6 +216,8 @@ ARCHITECTURE str OF sdp_statistics_offload IS
SIGNAL dp_offload_snk_in : t_dp_sosi;
SIGNAL dp_offload_snk_out : t_dp_siso;
+ SIGNAL udp_sosi : t_dp_sosi;
+
SIGNAL bsn_at_sync : STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
SIGNAL dp_header_info : STD_LOGIC_VECTOR(1023 DOWNTO 0):= (OTHERS => '0');
@@ -491,8 +497,40 @@ BEGIN
reg_hdr_dat_miso => reg_hdr_dat_miso,
snk_in_arr(0) => dp_offload_snk_in,
snk_out_arr(0) => dp_offload_snk_out,
- src_out_arr(0) => out_sosi,
+ src_out_arr(0) => udp_sosi,
src_in_arr(0) => out_siso,
hdr_fields_in_arr(0) => r.dp_header_info
);
+
+ out_sosi <= udp_sosi;
+
+ u_bsn_mon_udp : ENTITY dp_lib.mms_dp_bsn_monitor_v2
+ GENERIC MAP (
+ g_nof_streams => 1,
+ g_cross_clock_domain => TRUE,
+ g_sync_timeout => c_sdp_N_clk_per_sync,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_error_bi => 0,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_cnt_latency_w => c_word_w
+ )
+ PORT MAP (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_v2_offload_copi,
+ reg_miso => reg_bsn_monitor_v2_offload_cipo,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ref_sync => in_sosi.sync, -- using in_sosi sync instead of udp_sosi as it has no sync.
+
+ in_sosi_arr(0) => udp_sosi
+ );
+
+
+
+
END str;