From 2562d986abf7de6b5bfdce69ed08505532e7f11d Mon Sep 17 00:00:00 2001
From: Jonathan Hargreaves <hargreaves@astron.nl>
Date: Thu, 18 Dec 2014 14:27:38 +0000
Subject: [PATCH] final pinning qsf
---
.../build/quartus/unb2_pinning.qsf | 137 ++-
.../build/quartus/unb2_pinning_qsys.qsys | 158 +--
.../designs/unb2_pinning/src/ip/ddr4.qsys | 1062 +++++++++--------
.../unb2_pinning/src/ip/system_pll.qsys | 494 ++++----
.../unb2_pinning/src/ip/transceiver_phy.qsys | 506 ++++----
.../src/ip/transceiver_phy_24channel.qsys | 499 ++++----
.../unb2_pinning/src/ip/transceiver_pll.qsys | 158 +--
.../src/ip/transceiver_reset_controller.qsys | 121 +-
.../ip/transceiver_reset_controller_24.qsys | 114 +-
.../unb2_pinning/src/vhdl/unb2_pinning.vhd | 8 +-
10 files changed, 1711 insertions(+), 1546 deletions(-)
diff --git a/boards/uniboard2/designs/unb2_pinning/build/quartus/unb2_pinning.qsf b/boards/uniboard2/designs/unb2_pinning/build/quartus/unb2_pinning.qsf
index ce017f1c66..83baa15d5a 100644
--- a/boards/uniboard2/designs/unb2_pinning/build/quartus/unb2_pinning.qsf
+++ b/boards/uniboard2/designs/unb2_pinning/build/quartus/unb2_pinning.qsf
@@ -41,7 +41,7 @@ set_global_assignment -name FAMILY "Arria 10"
set_global_assignment -name TOP_LEVEL_ENTITY unb2_pinning
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:55:45 MARCH 13, 2014"
-set_global_assignment -name LAST_QUARTUS_VERSION 14.0
+set_global_assignment -name LAST_QUARTUS_VERSION 14.1.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
@@ -729,47 +729,47 @@ set_location_assignment PIN_AP44 -to RING_0_TX[0]
set_location_assignment PIN_AR42 -to RING_0_TX[1]
set_location_assignment PIN_AT44 -to RING_0_TX[2]
set_location_assignment PIN_AU42 -to RING_0_TX[3]
-set_location_assignment PIN_J38 -to RING_1_RX[0]
-set_location_assignment PIN_H40 -to RING_1_RX[1]
-set_location_assignment PIN_G38 -to RING_1_RX[2]
-set_location_assignment PIN_F40 -to RING_1_RX[3]
-set_location_assignment PIN_J42 -to RING_1_TX[0]
-set_location_assignment PIN_H44 -to RING_1_TX[1]
-set_location_assignment PIN_F44 -to RING_1_TX[2]
-set_location_assignment PIN_G42 -to RING_1_TX[3]
+set_location_assignment PIN_H40 -to RING_1_RX[0]
+set_location_assignment PIN_J38 -to RING_1_RX[1]
+set_location_assignment PIN_F40 -to RING_1_RX[2]
+set_location_assignment PIN_G38 -to RING_1_RX[3]
+set_location_assignment PIN_H44 -to RING_1_TX[0]
+set_location_assignment PIN_J42 -to RING_1_TX[1]
+set_location_assignment PIN_G42 -to RING_1_TX[2]
+set_location_assignment PIN_F44 -to RING_1_TX[3]
set_location_assignment PIN_AV40 -to RING_0_RX[4]
set_location_assignment PIN_AW38 -to RING_0_RX[5]
set_location_assignment PIN_AY40 -to RING_0_RX[6]
-set_location_assignment PIN_BB40 -to RING_0_RX[7]
-set_location_assignment PIN_BA38 -to RING_0_RX[8]
-set_location_assignment PIN_AY36 -to RING_0_RX[9]
-set_location_assignment PIN_BC38 -to RING_0_RX[10]
+set_location_assignment PIN_BA38 -to RING_0_RX[7]
+set_location_assignment PIN_BB40 -to RING_0_RX[8]
+set_location_assignment PIN_BC38 -to RING_0_RX[9]
+set_location_assignment PIN_AY36 -to RING_0_RX[10]
set_location_assignment PIN_BB36 -to RING_0_RX[11]
set_location_assignment PIN_AV44 -to RING_0_TX[4]
set_location_assignment PIN_AW42 -to RING_0_TX[5]
set_location_assignment PIN_AY44 -to RING_0_TX[6]
-set_location_assignment PIN_BA42 -to RING_0_TX[7]
-set_location_assignment PIN_BB44 -to RING_0_TX[8]
-set_location_assignment PIN_BC42 -to RING_0_TX[9]
-set_location_assignment PIN_BD40 -to RING_0_TX[10]
+set_location_assignment PIN_BB44 -to RING_0_TX[7]
+set_location_assignment PIN_BA42 -to RING_0_TX[8]
+set_location_assignment PIN_BD40 -to RING_0_TX[9]
+set_location_assignment PIN_BC42 -to RING_0_TX[10]
set_location_assignment PIN_BD36 -to RING_0_TX[11]
-set_location_assignment PIN_F36 -to RING_1_RX[4]
+set_location_assignment PIN_D40 -to RING_1_RX[4]
set_location_assignment PIN_E38 -to RING_1_RX[5]
-set_location_assignment PIN_E34 -to RING_1_RX[6]
-set_location_assignment PIN_D40 -to RING_1_RX[7]
-set_location_assignment PIN_D36 -to RING_1_RX[8]
-set_location_assignment PIN_C38 -to RING_1_RX[9]
-set_location_assignment PIN_C34 -to RING_1_RX[10]
-set_location_assignment PIN_B36 -to RING_1_RX[11]
-set_location_assignment PIN_B44 -to RING_1_TX[4]
+set_location_assignment PIN_F36 -to RING_1_RX[6]
+set_location_assignment PIN_C38 -to RING_1_RX[7]
+set_location_assignment PIN_B36 -to RING_1_RX[8]
+set_location_assignment PIN_D36 -to RING_1_RX[9]
+set_location_assignment PIN_E34 -to RING_1_RX[10]
+set_location_assignment PIN_C34 -to RING_1_RX[11]
+set_location_assignment PIN_E42 -to RING_1_TX[4]
set_location_assignment PIN_D44 -to RING_1_TX[5]
-set_location_assignment PIN_A38 -to RING_1_TX[6]
-set_location_assignment PIN_E42 -to RING_1_TX[7]
-set_location_assignment PIN_A42 -to RING_1_TX[8]
-set_location_assignment PIN_C42 -to RING_1_TX[9]
-set_location_assignment PIN_A34 -to RING_1_TX[10]
-set_location_assignment PIN_B40 -to RING_1_TX[11]
+set_location_assignment PIN_B44 -to RING_1_TX[6]
+set_location_assignment PIN_C42 -to RING_1_TX[7]
+set_location_assignment PIN_B40 -to RING_1_TX[8]
+set_location_assignment PIN_A42 -to RING_1_TX[9]
+set_location_assignment PIN_A38 -to RING_1_TX[10]
+set_location_assignment PIN_A34 -to RING_1_TX[11]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to BCK_RX[0]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "BCK_RX[0](n)"
@@ -1030,13 +1030,14 @@ set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to "RIN
set_location_assignment PIN_V9 -to BCK_REF_CLK
set_location_assignment PIN_V10 -to "BCK_REF_CLK(n)"
set_location_assignment PIN_AL32 -to CLKUSR
+set_location_assignment PIN_M16 -to MB_EVENT
#set_global_assignment -name DEVICE 10AX115U3F45I2LG
-#set_global_assignment -name DEVICE 10AX115U4F45I3SGES
-set_global_assignment -name DEVICE 10AX115U4F45I3SG
+set_global_assignment -name DEVICE 10AX115U4F45I3SGES
+#set_global_assignment -name DEVICE 10AX115U4F45I3SG
@@ -1547,10 +1548,10 @@ set_location_assignment PIN_BA4 -to "BCK_TX[45](n)"
set_location_assignment PIN_BC4 -to "BCK_TX[46](n)"
set_location_assignment PIN_BD10 -to "BCK_TX[47](n)"
set_location_assignment PIN_AY43 -to "RING_0_TX[6](n)"
-set_location_assignment PIN_BA41 -to "RING_0_TX[7](n)"
-set_location_assignment PIN_BB43 -to "RING_0_TX[8](n)"
-set_location_assignment PIN_BC41 -to "RING_0_TX[9](n)"
-set_location_assignment PIN_BD39 -to "RING_0_TX[10](n)"
+set_location_assignment PIN_BB43 -to "RING_0_TX[7](n)"
+set_location_assignment PIN_BA41 -to "RING_0_TX[8](n)"
+set_location_assignment PIN_BD39 -to "RING_0_TX[9](n)"
+set_location_assignment PIN_BC41 -to "RING_0_TX[10](n)"
set_location_assignment PIN_BD35 -to "RING_0_TX[11](n)"
set_location_assignment PIN_AP43 -to "RING_0_TX[0](n)"
set_location_assignment PIN_AR41 -to "RING_0_TX[1](n)"
@@ -1558,23 +1559,23 @@ set_location_assignment PIN_AT43 -to "RING_0_TX[2](n)"
set_location_assignment PIN_AU41 -to "RING_0_TX[3](n)"
set_location_assignment PIN_AV43 -to "RING_0_TX[4](n)"
set_location_assignment PIN_AW41 -to "RING_0_TX[5](n)"
-set_location_assignment PIN_C41 -to "RING_1_TX[9](n)"
-set_location_assignment PIN_A33 -to "RING_1_TX[10](n)"
-set_location_assignment PIN_B39 -to "RING_1_TX[11](n)"
-set_location_assignment PIN_H43 -to "RING_1_TX[1](n)"
-set_location_assignment PIN_F43 -to "RING_1_TX[2](n)"
-set_location_assignment PIN_G41 -to "RING_1_TX[3](n)"
-set_location_assignment PIN_B43 -to "RING_1_TX[4](n)"
+set_location_assignment PIN_A41 -to "RING_1_TX[9](n)"
+set_location_assignment PIN_A37 -to "RING_1_TX[10](n)"
+set_location_assignment PIN_A33 -to "RING_1_TX[11](n)"
+set_location_assignment PIN_J41 -to "RING_1_TX[1](n)"
+set_location_assignment PIN_G41 -to "RING_1_TX[2](n)"
+set_location_assignment PIN_F43 -to "RING_1_TX[3](n)"
+set_location_assignment PIN_E41 -to "RING_1_TX[4](n)"
set_location_assignment PIN_D43 -to "RING_1_TX[5](n)"
-set_location_assignment PIN_A37 -to "RING_1_TX[6](n)"
-set_location_assignment PIN_E41 -to "RING_1_TX[7](n)"
-set_location_assignment PIN_A41 -to "RING_1_TX[8](n)"
-set_location_assignment PIN_J41 -to "RING_1_TX[0](n)"
+set_location_assignment PIN_B43 -to "RING_1_TX[6](n)"
+set_location_assignment PIN_C41 -to "RING_1_TX[7](n)"
+set_location_assignment PIN_B39 -to "RING_1_TX[8](n)"
+set_location_assignment PIN_H43 -to "RING_1_TX[0](n)"
set_location_assignment PIN_AY39 -to "RING_0_RX[6](n)"
-set_location_assignment PIN_BB39 -to "RING_0_RX[7](n)"
-set_location_assignment PIN_BA37 -to "RING_0_RX[8](n)"
-set_location_assignment PIN_AY35 -to "RING_0_RX[9](n)"
-set_location_assignment PIN_BC37 -to "RING_0_RX[10](n)"
+set_location_assignment PIN_BA37 -to "RING_0_RX[7](n)"
+set_location_assignment PIN_BB39 -to "RING_0_RX[8](n)"
+set_location_assignment PIN_BC37 -to "RING_0_RX[9](n)"
+set_location_assignment PIN_AY35 -to "RING_0_RX[10](n)"
set_location_assignment PIN_BB35 -to "RING_0_RX[11](n)"
set_location_assignment PIN_AP39 -to "RING_0_RX[0](n)"
set_location_assignment PIN_AR37 -to "RING_0_RX[1](n)"
@@ -1582,18 +1583,18 @@ set_location_assignment PIN_AT39 -to "RING_0_RX[2](n)"
set_location_assignment PIN_AU37 -to "RING_0_RX[3](n)"
set_location_assignment PIN_AV39 -to "RING_0_RX[4](n)"
set_location_assignment PIN_AW37 -to "RING_0_RX[5](n)"
-set_location_assignment PIN_C37 -to "RING_1_RX[9](n)"
-set_location_assignment PIN_C33 -to "RING_1_RX[10](n)"
-set_location_assignment PIN_B35 -to "RING_1_RX[11](n)"
-set_location_assignment PIN_H39 -to "RING_1_RX[1](n)"
-set_location_assignment PIN_G37 -to "RING_1_RX[2](n)"
-set_location_assignment PIN_F39 -to "RING_1_RX[3](n)"
-set_location_assignment PIN_F35 -to "RING_1_RX[4](n)"
+set_location_assignment PIN_D35 -to "RING_1_RX[9](n)"
+set_location_assignment PIN_E33 -to "RING_1_RX[10](n)"
+set_location_assignment PIN_C33 -to "RING_1_RX[11](n)"
+set_location_assignment PIN_J37 -to "RING_1_RX[1](n)"
+set_location_assignment PIN_F39 -to "RING_1_RX[2](n)"
+set_location_assignment PIN_G37 -to "RING_1_RX[3](n)"
+set_location_assignment PIN_D39 -to "RING_1_RX[4](n)"
set_location_assignment PIN_E37 -to "RING_1_RX[5](n)"
-set_location_assignment PIN_E33 -to "RING_1_RX[6](n)"
-set_location_assignment PIN_D39 -to "RING_1_RX[7](n)"
-set_location_assignment PIN_D35 -to "RING_1_RX[8](n)"
-set_location_assignment PIN_J37 -to "RING_1_RX[0](n)"
+set_location_assignment PIN_F35 -to "RING_1_RX[6](n)"
+set_location_assignment PIN_C37 -to "RING_1_RX[7](n)"
+set_location_assignment PIN_B35 -to "RING_1_RX[8](n)"
+set_location_assignment PIN_H39 -to "RING_1_RX[0](n)"
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
@@ -1611,6 +1612,13 @@ set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1932
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "IBIS (Signal Integrity)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT IBIS -section_id eda_board_design_signal_integrity
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 5P0 -section_id eda_board_design_signal_integrity
+
+
+
+
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/MegaWizard/mem/ram_cr_cw.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/MegaWizard/mem/ram_crw_crw.vhd
set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_ram_crw_crw_a_stratix4.vhd
@@ -1652,8 +1660,5 @@ set_global_assignment -name SIP_FILE ../../src/ip/ddr4.sip
set_global_assignment -name VHDL_FILE ../../src/vhdl/unb2_pinning.vhd
set_global_assignment -name SOURCE_FILE db/unb2_pinning.cmp.rdb
set_global_assignment -name SDC_FILE ../../src/sdc/unb2_pinning.sdc
-set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "IBIS (Signal Integrity)"
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT IBIS -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 5P0 -section_id eda_board_design_signal_integrity
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/boards/uniboard2/designs/unb2_pinning/build/quartus/unb2_pinning_qsys.qsys b/boards/uniboard2/designs/unb2_pinning/build/quartus/unb2_pinning_qsys.qsys
index 974a2a14e4..9814d1bb7c 100644
--- a/boards/uniboard2/designs/unb2_pinning/build/quartus/unb2_pinning_qsys.qsys
+++ b/boards/uniboard2/designs/unb2_pinning/build/quartus/unb2_pinning_qsys.qsys
@@ -116,43 +116,43 @@
type = "int";
}
}
- element avs_i2c_master_4.control
+ element avs_i2c_master_7.control
{
datum baseAddress
{
- value = "96328";
+ value = "96304";
type = "String";
}
}
- element avs_i2c_master_1.control
+ element avs_i2c_master_2.control
{
datum baseAddress
{
- value = "96352";
+ value = "96344";
type = "String";
}
}
- element avs_i2c_master_2.control
+ element avs_i2c_master_3.control
{
datum baseAddress
{
- value = "96344";
+ value = "96336";
type = "String";
}
}
- element avs_i2c_master_3.control
+ element avs_i2c_master_11.control
{
datum baseAddress
{
- value = "96336";
+ value = "96272";
type = "String";
}
}
- element avs_i2c_master_9.control
+ element avs_i2c_master_6.control
{
datum baseAddress
{
- value = "96288";
+ value = "96312";
type = "String";
}
}
@@ -164,35 +164,35 @@
type = "String";
}
}
- element avs_i2c_master_10.control
+ element avs_i2c_master_8.control
{
datum baseAddress
{
- value = "96280";
+ value = "96296";
type = "String";
}
}
- element avs_i2c_master_7.control
+ element avs_i2c_master_4.control
{
datum baseAddress
{
- value = "96304";
+ value = "96328";
type = "String";
}
}
- element avs_i2c_master_6.control
+ element avs_i2c_master_1.control
{
datum baseAddress
{
- value = "96312";
+ value = "96352";
type = "String";
}
}
- element avs_i2c_master_11.control
+ element avs_i2c_master_10.control
{
datum baseAddress
{
- value = "96272";
+ value = "96280";
type = "String";
}
}
@@ -204,27 +204,27 @@
type = "String";
}
}
- element avs_i2c_master_8.control
+ element avs_i2c_master_9.control
{
datum baseAddress
{
- value = "96296";
+ value = "96288";
type = "String";
}
}
- element eth_tse_0.control_port
+ element eth_tse_1.control_port
{
datum baseAddress
{
- value = "72704";
+ value = "71680";
type = "String";
}
}
- element eth_tse_1.control_port
+ element eth_tse_0.control_port
{
datum baseAddress
{
- value = "71680";
+ value = "72704";
type = "String";
}
}
@@ -276,163 +276,163 @@
type = "int";
}
}
- element avs_i2c_master_7.protocol
+ element avs_i2c_master_4.protocol
{
datum baseAddress
{
- value = "80896";
+ value = "87040";
type = "String";
}
}
- element avs_i2c_master_8.protocol
+ element avs_i2c_master_1.protocol
{
datum baseAddress
{
- value = "78848";
+ value = "93184";
type = "String";
}
}
- element avs_i2c_master_2.protocol
+ element avs_i2c_master_5.protocol
{
datum baseAddress
{
- value = "91136";
+ value = "84992";
type = "String";
}
}
- element avs_i2c_master_5.protocol
+ element avs_i2c_master_6.protocol
{
datum baseAddress
{
- value = "84992";
+ value = "82944";
type = "String";
}
}
- element avs_i2c_master_11.protocol
+ element avs_i2c_master_7.protocol
{
datum baseAddress
{
- value = "70656";
+ value = "80896";
type = "String";
}
}
- element avs_i2c_master_10.protocol
+ element avs_i2c_master_0.protocol
{
datum baseAddress
{
- value = "74752";
+ value = "95232";
type = "String";
}
}
- element avs_i2c_master_3.protocol
+ element avs_i2c_master_9.protocol
{
datum baseAddress
{
- value = "89088";
+ value = "76800";
type = "String";
}
}
- element avs_i2c_master_4.protocol
+ element avs_i2c_master_3.protocol
{
datum baseAddress
{
- value = "87040";
+ value = "89088";
type = "String";
}
}
- element avs_i2c_master_0.protocol
+ element avs_i2c_master_11.protocol
{
datum baseAddress
{
- value = "95232";
+ value = "70656";
type = "String";
}
}
- element avs_i2c_master_6.protocol
+ element avs_i2c_master_8.protocol
{
datum baseAddress
{
- value = "82944";
+ value = "78848";
type = "String";
}
}
- element avs_i2c_master_9.protocol
+ element avs_i2c_master_10.protocol
{
datum baseAddress
{
- value = "76800";
+ value = "74752";
type = "String";
}
}
- element avs_i2c_master_1.protocol
+ element avs_i2c_master_2.protocol
{
datum baseAddress
{
- value = "93184";
+ value = "91136";
type = "String";
}
}
- element avs_i2c_master_2.result
+ element avs_i2c_master_4.result
{
datum baseAddress
{
- value = "90112";
+ value = "86016";
type = "String";
}
}
- element avs_i2c_master_9.result
+ element avs_i2c_master_7.result
{
datum baseAddress
{
- value = "75776";
+ value = "79872";
type = "String";
}
}
- element avs_i2c_master_8.result
+ element avs_i2c_master_3.result
{
datum baseAddress
{
- value = "77824";
+ value = "88064";
type = "String";
}
}
- element avs_i2c_master_11.result
+ element avs_i2c_master_5.result
{
datum baseAddress
{
- value = "69632";
+ value = "83968";
type = "String";
}
}
- element avs_i2c_master_5.result
+ element avs_i2c_master_1.result
{
datum baseAddress
{
- value = "83968";
+ value = "92160";
type = "String";
}
}
- element avs_i2c_master_4.result
+ element avs_i2c_master_2.result
{
datum baseAddress
{
- value = "86016";
+ value = "90112";
type = "String";
}
}
- element avs_i2c_master_10.result
+ element avs_i2c_master_9.result
{
datum baseAddress
{
- value = "73728";
+ value = "75776";
type = "String";
}
}
- element avs_i2c_master_3.result
+ element avs_i2c_master_0.result
{
datum baseAddress
{
- value = "88064";
+ value = "94208";
type = "String";
}
}
@@ -444,43 +444,43 @@
type = "String";
}
}
- element avs_i2c_master_7.result
+ element avs_i2c_master_10.result
{
datum baseAddress
{
- value = "79872";
+ value = "73728";
type = "String";
}
}
- element avs_i2c_master_0.result
+ element avs_i2c_master_11.result
{
datum baseAddress
{
- value = "94208";
+ value = "69632";
type = "String";
}
}
- element avs_i2c_master_1.result
+ element avs_i2c_master_8.result
{
datum baseAddress
{
- value = "92160";
+ value = "77824";
type = "String";
}
}
- element onchip_memory2_0.s1
+ element pio_0.s1
{
datum baseAddress
{
- value = "32768";
+ value = "96256";
type = "String";
}
}
- element pio_0.s1
+ element onchip_memory2_0.s1
{
datum baseAddress
{
- value = "96256";
+ value = "32768";
type = "String";
}
}
@@ -495,9 +495,9 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2SGES" />
+ <parameter name="device" value="10AX115U4F45I3SG" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
@@ -1113,7 +1113,7 @@
<parameter name="enable_timestamping" value="false" />
<parameter name="enable_ptp_1step" value="false" />
<parameter name="tstamp_fp_width" value="4" />
- <parameter name="AUTO_DEVICE" value="10AX115U3F45I2SGES" />
+ <parameter name="AUTO_DEVICE" value="10AX115U4F45I3SG" />
</module>
<module kind="altera_eth_tse" version="14.0" enabled="1" name="eth_tse_1">
<parameter name="deviceFamilyName" value="Arria 10" />
@@ -1152,7 +1152,7 @@
<parameter name="enable_timestamping" value="false" />
<parameter name="enable_ptp_1step" value="false" />
<parameter name="tstamp_fp_width" value="4" />
- <parameter name="AUTO_DEVICE" value="10AX115U3F45I2SGES" />
+ <parameter name="AUTO_DEVICE" value="10AX115U4F45I3SG" />
</module>
<module kind="altera_avalon_pio" version="14.0" enabled="1" name="pio_0">
<parameter name="bitClearingEdgeCapReg" value="false" />
@@ -1165,7 +1165,7 @@
<parameter name="resetValue" value="0" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
- <parameter name="width" value="11" />
+ <parameter name="width" value="12" />
<parameter name="clockRate" value="50000000" />
</module>
<module
diff --git a/boards/uniboard2/designs/unb2_pinning/src/ip/ddr4.qsys b/boards/uniboard2/designs/unb2_pinning/src/ip/ddr4.qsys
index dc77f66e32..ca062c9154 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/ip/ddr4.qsys
+++ b/boards/uniboard2/designs/unb2_pinning/src/ip/ddr4.qsys
@@ -11,6 +11,11 @@
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element ddr4_inst
{
@@ -23,7 +28,7 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U4F45I3SGES" />
+ <parameter name="device" value="10AX115U4F45I3SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
@@ -41,25 +46,40 @@
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
- name="global_reset_reset_sink"
- internal="ddr4_inst.global_reset_reset_sink"
- type="reset"
+ name="ctrl_amm_avalon_slave_0"
+ internal="ddr4_inst.ctrl_amm_avalon_slave_0"
+ type="avalon"
dir="end">
- <port name="global_reset_n" internal="global_reset_n" />
+ <port name="amm_ready_0" internal="amm_ready_0" />
+ <port name="amm_read_0" internal="amm_read_0" />
+ <port name="amm_write_0" internal="amm_write_0" />
+ <port name="amm_address_0" internal="amm_address_0" />
+ <port name="amm_readdata_0" internal="amm_readdata_0" />
+ <port name="amm_writedata_0" internal="amm_writedata_0" />
+ <port name="amm_burstcount_0" internal="amm_burstcount_0" />
+ <port name="amm_byteenable_0" internal="amm_byteenable_0" />
+ <port name="amm_readdatavalid_0" internal="amm_readdatavalid_0" />
</interface>
<interface
- name="pll_ref_clk_clock_sink"
- internal="ddr4_inst.pll_ref_clk_clock_sink"
+ name="emif_usr_clk_clock_source"
+ internal="ddr4_inst.emif_usr_clk_clock_source"
type="clock"
- dir="end">
- <port name="pll_ref_clk" internal="pll_ref_clk" />
+ dir="start">
+ <port name="emif_usr_clk" internal="emif_usr_clk" />
</interface>
<interface
- name="oct_conduit_end"
- internal="ddr4_inst.oct_conduit_end"
- type="conduit"
+ name="emif_usr_reset_reset_source"
+ internal="ddr4_inst.emif_usr_reset_reset_source"
+ type="reset"
+ dir="start">
+ <port name="emif_usr_reset_n" internal="emif_usr_reset_n" />
+ </interface>
+ <interface
+ name="global_reset_reset_sink"
+ internal="ddr4_inst.global_reset_reset_sink"
+ type="reset"
dir="end">
- <port name="oct_rzqin" internal="oct_rzqin" />
+ <port name="global_reset_n" internal="global_reset_n" />
</interface>
<interface
name="mem_conduit_end"
@@ -84,573 +104,659 @@
<port name="mem_dbi_n" internal="mem_dbi_n" />
</interface>
<interface
- name="status_conduit_end"
- internal="ddr4_inst.status_conduit_end"
+ name="oct_conduit_end"
+ internal="ddr4_inst.oct_conduit_end"
type="conduit"
dir="end">
- <port name="local_cal_success" internal="local_cal_success" />
- <port name="local_cal_fail" internal="local_cal_fail" />
- </interface>
- <interface
- name="emif_usr_reset_reset_source"
- internal="ddr4_inst.emif_usr_reset_reset_source"
- type="reset"
- dir="start">
- <port name="emif_usr_reset_n" internal="emif_usr_reset_n" />
+ <port name="oct_rzqin" internal="oct_rzqin" />
</interface>
<interface
- name="emif_usr_clk_clock_source"
- internal="ddr4_inst.emif_usr_clk_clock_source"
+ name="pll_ref_clk_clock_sink"
+ internal="ddr4_inst.pll_ref_clk_clock_sink"
type="clock"
- dir="start">
- <port name="emif_usr_clk" internal="emif_usr_clk" />
+ dir="end">
+ <port name="pll_ref_clk" internal="pll_ref_clk" />
</interface>
<interface
- name="ctrl_amm_avalon_slave_0"
- internal="ddr4_inst.ctrl_amm_avalon_slave_0"
- type="avalon"
+ name="status_conduit_end"
+ internal="ddr4_inst.status_conduit_end"
+ type="conduit"
dir="end">
- <port name="amm_ready_0" internal="amm_ready_0" />
- <port name="amm_read_0" internal="amm_read_0" />
- <port name="amm_write_0" internal="amm_write_0" />
- <port name="amm_address_0" internal="amm_address_0" />
- <port name="amm_readdata_0" internal="amm_readdata_0" />
- <port name="amm_writedata_0" internal="amm_writedata_0" />
- <port name="amm_burstcount_0" internal="amm_burstcount_0" />
- <port name="amm_byteenable_0" internal="amm_byteenable_0" />
- <port name="amm_readdatavalid_0" internal="amm_readdatavalid_0" />
+ <port name="local_cal_success" internal="local_cal_success" />
+ <port name="local_cal_fail" internal="local_cal_fail" />
</interface>
<module
+ name="ddr4_inst"
kind="altera_emif"
- version="14.0"
+ version="14.1"
enabled="1"
- name="ddr4_inst"
autoexport="1">
- <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="SYS_INFO_DEVICE" value="10AX115U4F45I3SGES" />
- <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="3" />
- <parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR4" />
- <parameter name="IS_ED_SLAVE" value="false" />
+ <parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR3_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR3_MAX_DQS_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR3_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_PKG+BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_DDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_USER_AC_ISI_NS" value="0.094" />
+ <parameter name="BOARD_DDR3_USER_AC_SLEW_RATE" value="1.0" />
+ <parameter name="BOARD_DDR3_USER_CK_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR3_USER_RCLK_ISI_NS" value="0.094" />
+ <parameter name="BOARD_DDR3_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR3_USER_RDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_DDR3_USER_RDATA_SLEW_RATE" value="2.5" />
+ <parameter name="BOARD_DDR3_USER_WCLK_ISI_NS" value="0.031" />
+ <parameter name="BOARD_DDR3_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR3_USER_WDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_DDR3_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR3_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_DDR3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_DDR4_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_DQS_TO_CK_SKEW_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED" value="true" />
+ <parameter name="BOARD_DDR4_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR4_MAX_DQS_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR4_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_PKG+BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_DDR4_SKEW_BETWEEN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_USER_AC_ISI_NS" value="0.094" />
+ <parameter name="BOARD_DDR4_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR4_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR4_USER_RCLK_ISI_NS" value="0.094" />
+ <parameter name="BOARD_DDR4_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR4_USER_RDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_DDR4_USER_RDATA_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR4_USER_WCLK_ISI_NS" value="0.031" />
+ <parameter name="BOARD_DDR4_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR4_USER_WDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_DDR4_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR4_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_DDR4_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_QDR2_AC_TO_K_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_D_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR2_MAX_K_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR2_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_PKG+BRD_SKEW_WITHIN_D_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_PKG+BRD_SKEW_WITHIN_Q_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_QDR2_USER_AC_ISI_NS" value="0.094" />
+ <parameter name="BOARD_QDR2_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USER_K_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR2_USER_RCLK_ISI_NS" value="0.094" />
+ <parameter name="BOARD_QDR2_USER_RCLK_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USER_RDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_QDR2_USER_RDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USER_WCLK_ISI_NS" value="0.031" />
+ <parameter name="BOARD_QDR2_USER_WDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_QDR2_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_QDR2_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_QDR4_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_DK_TO_CK_SKEW_NS" value="-0.02" />
+ <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR4_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR4_MAX_DK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR4_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_PKG+BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_QDR4_SKEW_BETWEEN_DK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR4_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR4_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR4_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_RDATA_SLEW_RATE" value="3.5" />
+ <parameter name="BOARD_QDR4_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR4_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR4_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_QDR4_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_RLD3_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_DK_TO_CK_SKEW_NS" value="-0.02" />
+ <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
+ <parameter name="BOARD_RLD3_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_RLD3_MAX_DK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_RLD3_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_PKG+BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_RLD3_SKEW_BETWEEN_DK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_USER_AC_ISI_NS" value="0.094" />
+ <parameter name="BOARD_RLD3_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_RLD3_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_RLD3_USER_RCLK_ISI_NS" value="0.094" />
+ <parameter name="BOARD_RLD3_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_RLD3_USER_RDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_RLD3_USER_RDATA_SLEW_RATE" value="3.5" />
+ <parameter name="BOARD_RLD3_USER_WCLK_ISI_NS" value="0.031" />
+ <parameter name="BOARD_RLD3_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_RLD3_USER_WDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_RLD3_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_RLD3_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_RLD3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="CTRL_DDR3_ADDR_ORDER_ENUM">DDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+ <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_CYCS" value="32" />
+ <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_EN" value="false" />
+ <parameter name="CTRL_DDR3_AUTO_PRECHARGE_EN" value="false" />
+ <parameter name="CTRL_DDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_DDR3_ECC_AUTO_CORRECTION_EN" value="false" />
+ <parameter name="CTRL_DDR3_ECC_EN" value="false" />
+ <parameter name="CTRL_DDR3_MMR_EN" value="false" />
+ <parameter name="CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_REORDER_EN" value="true" />
+ <parameter name="CTRL_DDR3_SELF_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR3_STARVE_LIMIT" value="63" />
+ <parameter name="CTRL_DDR3_USER_PRIORITY_EN" value="false" />
+ <parameter name="CTRL_DDR3_USER_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_ADDR_ORDER_ENUM">DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG</parameter>
+ <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_CYCS" value="32" />
+ <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_EN" value="false" />
+ <parameter name="CTRL_DDR4_AUTO_PRECHARGE_EN" value="false" />
+ <parameter name="CTRL_DDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_DDR4_ECC_AUTO_CORRECTION_EN" value="false" />
+ <parameter name="CTRL_DDR4_ECC_EN" value="false" />
+ <parameter name="CTRL_DDR4_MMR_EN" value="false" />
+ <parameter name="CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_REORDER_EN" value="true" />
+ <parameter name="CTRL_DDR4_SELF_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR4_STARVE_LIMIT" value="63" />
+ <parameter name="CTRL_DDR4_USER_PRIORITY_EN" value="false" />
+ <parameter name="CTRL_DDR4_USER_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
+ <parameter name="CTRL_QDR2_AVL_MAX_BURST_COUNT" value="4" />
+ <parameter name="CTRL_QDR2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
+ <parameter name="CTRL_QDR4_AVL_MAX_BURST_COUNT" value="4" />
+ <parameter name="CTRL_QDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_RLD2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_RLD3_ADDR_ORDER_ENUM">RLD3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+ <parameter name="CTRL_RLD3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="DIAG_BOARD_DELAY_CONFIG_STR" value="" />
+ <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_DDR3_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_DDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_DDR4_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_DDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_DDR4_SKIP_CA_DESKEW" value="false" />
+ <parameter name="DIAG_DDR4_SKIP_CA_LEVEL" value="false" />
+ <parameter name="DIAG_DDR4_SKIP_VREF_CAL" value="true" />
+ <parameter name="DIAG_ECLIPSE_DEBUG" value="false" />
+ <parameter name="DIAG_ENABLE_JTAG_UART" value="false" />
+ <parameter name="DIAG_EXPORT_VJI" value="false" />
+ <parameter name="DIAG_EXPOSE_DFT_SIGNALS" value="false" />
+ <parameter name="DIAG_EXTRA_CONFIGS" value="" />
+ <parameter name="DIAG_EX_DESIGN_ADD_TEST_EMIFS" value="" />
+ <parameter name="DIAG_FAST_SIM_OVERRIDE">FAST_SIM_OVERRIDE_DEFAULT</parameter>
+ <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_QDR2_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_QDR2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_QDR4_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_QDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_RLD2_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_RLD2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_RLD3_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_RLD3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_SYNTH_FOR_SIM" value="false" />
+ <parameter name="DIAG_TIMING_REGTEST_MODE" value="false" />
+ <parameter name="DIAG_USE_BOARD_DELAY_MODEL" value="false" />
+ <parameter name="DIAG_VERBOSE_IOAUX" value="false" />
<parameter name="INTERNAL_TESTING_MODE" value="false" />
- <parameter name="SYS_INFO_UNIQUE_ID">$${FILENAME}_ddr4_inst</parameter>
- <parameter name="PHY_DDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
- <parameter name="PHY_DDR3_MEM_CLK_FREQ_MHZ" value="1066.667" />
- <parameter name="PHY_DDR3_DEFAULT_REF_CLK_FREQ" value="false" />
- <parameter name="PHY_DDR3_USER_REF_CLK_FREQ_MHZ" value="133.333" />
- <parameter name="PHY_DDR3_REF_CLK_JITTER_PS" value="10.0" />
- <parameter name="PHY_DDR3_RATE_ENUM" value="RATE_QUARTER" />
- <parameter name="PHY_DDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
- <parameter name="PHY_DDR3_IO_VOLTAGE" value="1.5" />
- <parameter name="PHY_DDR3_DEFAULT_IO" value="true" />
- <parameter name="PHY_DDR3_USER_AC_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_DDR3_USER_AC_MODE_ENUM" value="unset" />
- <parameter name="PHY_DDR3_USER_CK_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_DDR3_USER_CK_MODE_ENUM" value="unset" />
- <parameter name="PHY_DDR3_USER_DATA_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_DDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
- <parameter name="PHY_DDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
- <parameter name="PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_DDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_DDR4_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
- <parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="900.0" />
- <parameter name="PHY_DDR4_DEFAULT_REF_CLK_FREQ" value="false" />
- <parameter name="PHY_DDR4_USER_REF_CLK_FREQ_MHZ" value="25.0" />
- <parameter name="PHY_DDR4_REF_CLK_JITTER_PS" value="10.0" />
- <parameter name="PHY_DDR4_RATE_ENUM" value="RATE_QUARTER" />
- <parameter name="PHY_DDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
- <parameter name="PHY_DDR4_IO_VOLTAGE" value="1.2" />
- <parameter name="PHY_DDR4_DEFAULT_IO" value="true" />
- <parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_DDR4_USER_AC_MODE_ENUM" value="unset" />
- <parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="unset" />
- <parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
- <parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
- <parameter name="PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_DDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_QDR2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
- <parameter name="PHY_QDR2_MEM_CLK_FREQ_MHZ" value="633.333" />
- <parameter name="PHY_QDR2_DEFAULT_REF_CLK_FREQ" value="true" />
- <parameter name="PHY_QDR2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
- <parameter name="PHY_QDR2_REF_CLK_JITTER_PS" value="10.0" />
- <parameter name="PHY_QDR2_RATE_ENUM" value="RATE_HALF" />
- <parameter name="PHY_QDR2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
- <parameter name="PHY_QDR2_IO_VOLTAGE" value="1.5" />
- <parameter name="PHY_QDR2_DEFAULT_IO" value="true" />
- <parameter name="PHY_QDR2_USER_AC_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_QDR2_USER_AC_MODE_ENUM" value="unset" />
- <parameter name="PHY_QDR2_USER_CK_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_QDR2_USER_CK_MODE_ENUM" value="unset" />
- <parameter name="PHY_QDR2_USER_DATA_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_QDR2_USER_DATA_OUT_MODE_ENUM" value="unset" />
- <parameter name="PHY_QDR2_USER_DATA_IN_MODE_ENUM" value="unset" />
- <parameter name="PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_QDR2_USER_RZQ_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_RLD2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
- <parameter name="PHY_RLD2_MEM_CLK_FREQ_MHZ" value="533.333" />
- <parameter name="PHY_RLD2_DEFAULT_REF_CLK_FREQ" value="true" />
- <parameter name="PHY_RLD2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
- <parameter name="PHY_RLD2_REF_CLK_JITTER_PS" value="10.0" />
- <parameter name="PHY_RLD2_RATE_ENUM" value="RATE_HALF" />
- <parameter name="PHY_RLD2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
- <parameter name="PHY_RLD2_IO_VOLTAGE" value="1.8" />
- <parameter name="PHY_RLD2_DEFAULT_IO" value="true" />
- <parameter name="PHY_RLD2_USER_AC_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_RLD2_USER_AC_MODE_ENUM" value="unset" />
- <parameter name="PHY_RLD2_USER_CK_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_RLD2_USER_CK_MODE_ENUM" value="unset" />
- <parameter name="PHY_RLD2_USER_DATA_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_RLD2_USER_DATA_OUT_MODE_ENUM" value="unset" />
- <parameter name="PHY_RLD2_USER_DATA_IN_MODE_ENUM" value="unset" />
- <parameter name="PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_RLD2_USER_RZQ_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_RLD3_CONFIG_ENUM" value="CONFIG_PHY_ONLY" />
- <parameter name="PHY_RLD3_MEM_CLK_FREQ_MHZ" value="1066.667" />
- <parameter name="PHY_RLD3_DEFAULT_REF_CLK_FREQ" value="true" />
- <parameter name="PHY_RLD3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
- <parameter name="PHY_RLD3_REF_CLK_JITTER_PS" value="10.0" />
- <parameter name="PHY_RLD3_RATE_ENUM" value="RATE_QUARTER" />
- <parameter name="PHY_RLD3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
- <parameter name="PHY_RLD3_IO_VOLTAGE" value="1.2" />
- <parameter name="PHY_RLD3_DEFAULT_IO" value="true" />
- <parameter name="PHY_RLD3_USER_AC_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_RLD3_USER_AC_MODE_ENUM" value="unset" />
- <parameter name="PHY_RLD3_USER_CK_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_RLD3_USER_CK_MODE_ENUM" value="unset" />
- <parameter name="PHY_RLD3_USER_DATA_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_RLD3_USER_DATA_OUT_MODE_ENUM" value="unset" />
- <parameter name="PHY_RLD3_USER_DATA_IN_MODE_ENUM" value="unset" />
- <parameter name="PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
- <parameter name="PHY_RLD3_USER_RZQ_IO_STD_ENUM" value="unset" />
- <parameter name="MEM_DDR3_FORMAT_ENUM" value="MEM_FORMAT_UDIMM" />
- <parameter name="MEM_DDR3_DQ_WIDTH" value="72" />
- <parameter name="MEM_DDR3_DQ_PER_DQS" value="8" />
- <parameter name="MEM_DDR3_DISCRETE_CS_WIDTH" value="1" />
- <parameter name="MEM_DDR3_NUM_OF_DIMMS" value="1" />
- <parameter name="MEM_DDR3_RANKS_PER_DIMM" value="1" />
+ <parameter name="IS_ED_SLAVE" value="false" />
+ <parameter name="MEM_DDR3_ALERT_N_DQS_GROUP" value="0" />
+ <parameter name="MEM_DDR3_ALERT_N_PLACEMENT_ENUM">DDR3_ALERT_N_PLACEMENT_AC_LANES</parameter>
+ <parameter name="MEM_DDR3_ASR_ENUM" value="DDR3_ASR_MANUAL" />
+ <parameter name="MEM_DDR3_ATCL_ENUM" value="DDR3_ATCL_DISABLED" />
+ <parameter name="MEM_DDR3_BANK_ADDR_WIDTH" value="3" />
+ <parameter name="MEM_DDR3_BL_ENUM" value="DDR3_BL_BL8" />
+ <parameter name="MEM_DDR3_BT_ENUM" value="DDR3_BT_SEQUENTIAL" />
<parameter name="MEM_DDR3_CKE_PER_DIMM" value="1" />
<parameter name="MEM_DDR3_CK_WIDTH" value="1" />
- <parameter name="MEM_DDR3_ROW_ADDR_WIDTH" value="14" />
<parameter name="MEM_DDR3_COL_ADDR_WIDTH" value="10" />
- <parameter name="MEM_DDR3_BANK_ADDR_WIDTH" value="3" />
+ <parameter name="MEM_DDR3_DISCRETE_CS_WIDTH" value="1" />
+ <parameter name="MEM_DDR3_DLL_EN" value="true" />
<parameter name="MEM_DDR3_DM_EN" value="true" />
- <parameter name="MEM_DDR3_MIRROR_ADDRESSING_EN" value="false" />
- <parameter name="MEM_DDR3_RDIMM_CONFIG" value="0000000000000000" />
+ <parameter name="MEM_DDR3_DQ_PER_DQS" value="8" />
+ <parameter name="MEM_DDR3_DQ_WIDTH" value="72" />
+ <parameter name="MEM_DDR3_DRV_STR_ENUM" value="DDR3_DRV_STR_RZQ_6" />
+ <parameter name="MEM_DDR3_FORMAT_ENUM" value="MEM_FORMAT_UDIMM" />
<parameter name="MEM_DDR3_LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
- <parameter name="MEM_DDR3_ALERT_N_PLACEMENT_ENUM">DDR3_ALERT_N_PLACEMENT_AC_LANES</parameter>
- <parameter name="MEM_DDR3_ALERT_N_DQS_GROUP" value="0" />
- <parameter name="MEM_DDR3_BL_ENUM" value="DDR3_BL_BL8" />
- <parameter name="MEM_DDR3_BT_ENUM" value="DDR3_BT_SEQUENTIAL" />
- <parameter name="MEM_DDR3_ASR_ENUM" value="DDR3_ASR_MANUAL" />
- <parameter name="MEM_DDR3_SRT_ENUM" value="DDR3_SRT_NORMAL" />
+ <parameter name="MEM_DDR3_MIRROR_ADDRESSING_EN" value="false" />
+ <parameter name="MEM_DDR3_NUM_OF_DIMMS" value="1" />
<parameter name="MEM_DDR3_PD_ENUM" value="DDR3_PD_OFF" />
- <parameter name="MEM_DDR3_DRV_STR_ENUM" value="DDR3_DRV_STR_RZQ_6" />
- <parameter name="MEM_DDR3_DLL_EN" value="true" />
+ <parameter name="MEM_DDR3_RANKS_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR3_RDIMM_CONFIG" value="0000000000000000" />
+ <parameter name="MEM_DDR3_ROW_ADDR_WIDTH" value="14" />
<parameter name="MEM_DDR3_RTT_NOM_ENUM">DDR3_RTT_NOM_ODT_DISABLED</parameter>
<parameter name="MEM_DDR3_RTT_WR_ENUM">DDR3_RTT_WR_ODT_DISABLED</parameter>
- <parameter name="MEM_DDR3_WTCL" value="6" />
- <parameter name="MEM_DDR3_ATCL_ENUM" value="DDR3_ATCL_DISABLED" />
- <parameter name="MEM_DDR3_TCL" value="7" />
- <parameter name="MEM_DDR3_USE_DEFAULT_ODT" value="true" />
- <parameter name="MEM_DDR3_R_ODTN_1X1" value="Rank 0" />
<parameter name="MEM_DDR3_R_ODT0_1X1" value="off" />
- <parameter name="MEM_DDR3_W_ODTN_1X1" value="Rank 0" />
- <parameter name="MEM_DDR3_W_ODT0_1X1" value="on" />
- <parameter name="MEM_DDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
<parameter name="MEM_DDR3_R_ODT0_2X2" value="off,on" />
- <parameter name="MEM_DDR3_R_ODT1_2X2" value="on,off" />
- <parameter name="MEM_DDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
- <parameter name="MEM_DDR3_W_ODT0_2X2" value="on,on" />
- <parameter name="MEM_DDR3_W_ODT1_2X2" value="on,on" />
- <parameter name="MEM_DDR3_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
<parameter name="MEM_DDR3_R_ODT0_4X2" value="off,off,on,on" />
- <parameter name="MEM_DDR3_R_ODT1_4X2" value="on,on,off,off" />
- <parameter name="MEM_DDR3_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
- <parameter name="MEM_DDR3_W_ODT0_4X2" value="off,off,on,on" />
- <parameter name="MEM_DDR3_W_ODT1_4X2" value="on,on,off,off" />
- <parameter name="MEM_DDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
<parameter name="MEM_DDR3_R_ODT0_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR3_R_ODT1_2X2" value="on,off" />
+ <parameter name="MEM_DDR3_R_ODT1_4X2" value="on,on,off,off" />
<parameter name="MEM_DDR3_R_ODT1_4X4" value="off,off,on,on" />
<parameter name="MEM_DDR3_R_ODT2_4X4" value="off,off,off,off" />
<parameter name="MEM_DDR3_R_ODT3_4X4" value="on,on,off,off" />
- <parameter name="MEM_DDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
- <parameter name="MEM_DDR3_W_ODT0_4X4" value="on,on,off,off" />
- <parameter name="MEM_DDR3_W_ODT1_4X4" value="off,off,on,on" />
- <parameter name="MEM_DDR3_W_ODT2_4X4" value="off,off,on,on" />
- <parameter name="MEM_DDR3_W_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_R_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR3_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
<parameter name="MEM_DDR3_SPEEDBIN_ENUM" value="DDR3_SPEEDBIN_2133" />
- <parameter name="MEM_DDR3_TIS_PS" value="60" />
- <parameter name="MEM_DDR3_TIS_AC_MV" value="135" />
- <parameter name="MEM_DDR3_TIH_PS" value="95" />
- <parameter name="MEM_DDR3_TIH_DC_MV" value="100" />
- <parameter name="MEM_DDR3_TDS_PS" value="53" />
- <parameter name="MEM_DDR3_TDS_AC_MV" value="135" />
- <parameter name="MEM_DDR3_TDH_PS" value="55" />
+ <parameter name="MEM_DDR3_SRT_ENUM" value="DDR3_SRT_NORMAL" />
+ <parameter name="MEM_DDR3_TCL" value="7" />
<parameter name="MEM_DDR3_TDH_DC_MV" value="100" />
- <parameter name="MEM_DDR3_TDQSQ_PS" value="75" />
- <parameter name="MEM_DDR3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_DDR3_TDH_PS" value="55" />
<parameter name="MEM_DDR3_TDQSCK_PS" value="180" />
+ <parameter name="MEM_DDR3_TDQSQ_PS" value="75" />
<parameter name="MEM_DDR3_TDQSS_CYC" value="0.27" />
- <parameter name="MEM_DDR3_TQSH_CYC" value="0.4" />
<parameter name="MEM_DDR3_TDSH_CYC" value="0.18" />
- <parameter name="MEM_DDR3_TWLS_PS" value="125.0" />
- <parameter name="MEM_DDR3_TWLH_PS" value="125.0" />
<parameter name="MEM_DDR3_TDSS_CYC" value="0.18" />
+ <parameter name="MEM_DDR3_TDS_AC_MV" value="135" />
+ <parameter name="MEM_DDR3_TDS_PS" value="53" />
+ <parameter name="MEM_DDR3_TFAW_NS" value="25.0" />
+ <parameter name="MEM_DDR3_TIH_DC_MV" value="100" />
+ <parameter name="MEM_DDR3_TIH_PS" value="95" />
<parameter name="MEM_DDR3_TINIT_US" value="500" />
+ <parameter name="MEM_DDR3_TIS_AC_MV" value="135" />
+ <parameter name="MEM_DDR3_TIS_PS" value="60" />
<parameter name="MEM_DDR3_TMRD_CK_CYC" value="4" />
+ <parameter name="MEM_DDR3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_DDR3_TQSH_CYC" value="0.4" />
<parameter name="MEM_DDR3_TRAS_NS" value="33.0" />
<parameter name="MEM_DDR3_TRCD_NS" value="13.09" />
- <parameter name="MEM_DDR3_TRP_NS" value="13.09" />
<parameter name="MEM_DDR3_TREFI_US" value="7.8" />
<parameter name="MEM_DDR3_TRFC_NS" value="160.0" />
- <parameter name="MEM_DDR3_TWR_NS" value="15.0" />
- <parameter name="MEM_DDR3_TWTR_CYC" value="4" />
- <parameter name="MEM_DDR3_TFAW_NS" value="25.0" />
+ <parameter name="MEM_DDR3_TRP_NS" value="13.09" />
<parameter name="MEM_DDR3_TRRD_CYC" value="6" />
<parameter name="MEM_DDR3_TRTP_CYC" value="8" />
- <parameter name="MEM_DDR4_FORMAT_ENUM" value="MEM_FORMAT_SODIMM" />
- <parameter name="MEM_DDR4_DQ_WIDTH" value="72" />
- <parameter name="MEM_DDR4_DQ_PER_DQS" value="8" />
- <parameter name="MEM_DDR4_DISCRETE_CS_WIDTH" value="1" />
- <parameter name="MEM_DDR4_NUM_OF_DIMMS" value="1" />
- <parameter name="MEM_DDR4_RANKS_PER_DIMM" value="2" />
- <parameter name="MEM_DDR4_CKE_PER_DIMM" value="1" />
- <parameter name="MEM_DDR4_CK_WIDTH" value="2" />
- <parameter name="MEM_DDR4_ROW_ADDR_WIDTH" value="15" />
- <parameter name="MEM_DDR4_COL_ADDR_WIDTH" value="10" />
+ <parameter name="MEM_DDR3_TWLH_PS" value="125.0" />
+ <parameter name="MEM_DDR3_TWLS_PS" value="125.0" />
+ <parameter name="MEM_DDR3_TWR_NS" value="15.0" />
+ <parameter name="MEM_DDR3_TWTR_CYC" value="4" />
+ <parameter name="MEM_DDR3_USE_DEFAULT_ODT" value="true" />
+ <parameter name="MEM_DDR3_WTCL" value="6" />
+ <parameter name="MEM_DDR3_W_ODT0_1X1" value="on" />
+ <parameter name="MEM_DDR3_W_ODT0_2X2" value="on,on" />
+ <parameter name="MEM_DDR3_W_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT0_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODT1_2X2" value="on,on" />
+ <parameter name="MEM_DDR3_W_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT2_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR3_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_AC_PARITY_LATENCY">DDR4_AC_PARITY_LATENCY_DISABLE</parameter>
+ <parameter name="MEM_DDR4_AC_PERSISTENT_ERROR" value="false" />
+ <parameter name="MEM_DDR4_ALERT_N_AC_LANE" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_AC_PIN" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_DQS_GROUP" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_PLACEMENT_ENUM">DDR4_ALERT_N_PLACEMENT_DATA_LANES</parameter>
+ <parameter name="MEM_DDR4_ALERT_PAR_EN" value="true" />
+ <parameter name="MEM_DDR4_ASR_ENUM">DDR4_ASR_MANUAL_NORMAL</parameter>
+ <parameter name="MEM_DDR4_ATCL_ENUM" value="DDR4_ATCL_DISABLED" />
<parameter name="MEM_DDR4_BANK_ADDR_WIDTH" value="2" />
<parameter name="MEM_DDR4_BANK_GROUP_WIDTH" value="2" />
+ <parameter name="MEM_DDR4_BL_ENUM" value="DDR4_BL_BL8" />
+ <parameter name="MEM_DDR4_BT_ENUM" value="DDR4_BT_SEQUENTIAL" />
+ <parameter name="MEM_DDR4_CAL_MODE" value="0" />
<parameter name="MEM_DDR4_CHIP_ID_WIDTH" value="0" />
+ <parameter name="MEM_DDR4_CKE_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR4_CK_WIDTH" value="2" />
+ <parameter name="MEM_DDR4_COL_ADDR_WIDTH" value="10" />
+ <parameter name="MEM_DDR4_DEFAULT_VREFOUT" value="true" />
+ <parameter name="MEM_DDR4_DISCRETE_CS_WIDTH" value="1" />
+ <parameter name="MEM_DDR4_DLL_EN" value="true" />
<parameter name="MEM_DDR4_DM_EN" value="true" />
- <parameter name="MEM_DDR4_ALERT_PAR_EN" value="true" />
- <parameter name="MEM_DDR4_ALERT_N_PLACEMENT_ENUM">DDR4_ALERT_N_PLACEMENT_DATA_LANES</parameter>
- <parameter name="MEM_DDR4_ALERT_N_DQS_GROUP" value="0" />
- <parameter name="MEM_DDR4_ALERT_N_AC_LANE" value="0" />
- <parameter name="MEM_DDR4_ALERT_N_AC_PIN" value="0" />
- <parameter name="MEM_DDR4_MIRROR_ADDRESSING_EN" value="false" />
- <parameter name="MEM_DDR4_RDIMM_CONFIG" value="0000000000000000" />
- <parameter name="MEM_DDR4_LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
- <parameter name="MEM_DDR4_WRITE_CRC" value="false" />
- <parameter name="MEM_DDR4_GEARDOWN" value="DDR4_GEARDOWN_HR" />
- <parameter name="MEM_DDR4_PER_DRAM_ADDR" value="false" />
- <parameter name="MEM_DDR4_TEMP_SENSOR_READOUT" value="false" />
+ <parameter name="MEM_DDR4_DQ_PER_DQS" value="8" />
+ <parameter name="MEM_DDR4_DQ_WIDTH" value="72" />
+ <parameter name="MEM_DDR4_DRV_STR_ENUM" value="DDR4_DRV_STR_RZQ_7" />
<parameter name="MEM_DDR4_FINE_GRANULARITY_REFRESH">DDR4_FINE_REFRESH_FIXED_1X</parameter>
- <parameter name="MEM_DDR4_WRITE_CMD_LATENCY" value="4" />
- <parameter name="MEM_DDR4_MPR_READ_FORMAT">DDR4_MPR_READ_FORMAT_SERIAL</parameter>
- <parameter name="MEM_DDR4_MAX_POWERDOWN" value="false" />
- <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE">DDR4_TEMP_CONTROLLED_RFSH_NORMAL</parameter>
- <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA" value="false" />
+ <parameter name="MEM_DDR4_FORMAT_ENUM" value="MEM_FORMAT_SODIMM" />
+ <parameter name="MEM_DDR4_GEARDOWN" value="DDR4_GEARDOWN_HR" />
<parameter name="MEM_DDR4_INTERNAL_VREFDQ_MONITOR" value="false" />
- <parameter name="MEM_DDR4_CAL_MODE" value="0" />
- <parameter name="MEM_DDR4_SELF_RFSH_ABORT" value="false" />
- <parameter name="MEM_DDR4_READ_PREAMBLE_TRAINING" value="false" />
- <parameter name="MEM_DDR4_READ_PREAMBLE" value="1" />
- <parameter name="MEM_DDR4_WRITE_PREAMBLE" value="1" />
- <parameter name="MEM_DDR4_AC_PARITY_LATENCY">DDR4_AC_PARITY_LATENCY_DISABLE</parameter>
- <parameter name="MEM_DDR4_ODT_IN_POWERDOWN" value="true" />
- <parameter name="MEM_DDR4_RTT_PARK">DDR4_RTT_PARK_ODT_DISABLED</parameter>
- <parameter name="MEM_DDR4_AC_PERSISTENT_ERROR" value="false" />
- <parameter name="MEM_DDR4_WRITE_DBI" value="false" />
+ <parameter name="MEM_DDR4_LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
+ <parameter name="MEM_DDR4_MAX_POWERDOWN" value="false" />
+ <parameter name="MEM_DDR4_MIRROR_ADDRESSING_EN" value="false" />
+ <parameter name="MEM_DDR4_MPR_READ_FORMAT">DDR4_MPR_READ_FORMAT_SERIAL</parameter>
+ <parameter name="MEM_DDR4_NUM_OF_DIMMS" value="1" />
+ <parameter name="MEM_DDR4_ODT_IN_POWERDOWN" value="true" />
+ <parameter name="MEM_DDR4_PER_DRAM_ADDR" value="false" />
+ <parameter name="MEM_DDR4_RANKS_PER_DIMM" value="2" />
+ <parameter name="MEM_DDR4_RDIMM_CONFIG" value="0000000000000000" />
<parameter name="MEM_DDR4_READ_DBI" value="false" />
- <parameter name="MEM_DDR4_VREFDQ_TRAINING_VALUE" value="60.0" />
- <parameter name="MEM_DDR4_VREFDQ_TRAINING_RANGE">DDR4_VREFDQ_TRAINING_RANGE_1</parameter>
- <parameter name="MEM_DDR4_BL_ENUM" value="DDR4_BL_BL8" />
- <parameter name="MEM_DDR4_BT_ENUM" value="DDR4_BT_SEQUENTIAL" />
- <parameter name="MEM_DDR4_ASR_ENUM">DDR4_ASR_MANUAL_NORMAL</parameter>
- <parameter name="MEM_DDR4_DRV_STR_ENUM" value="DDR4_DRV_STR_RZQ_7" />
- <parameter name="MEM_DDR4_DLL_EN" value="true" />
+ <parameter name="MEM_DDR4_READ_PREAMBLE" value="1" />
+ <parameter name="MEM_DDR4_READ_PREAMBLE_TRAINING" value="false" />
+ <parameter name="MEM_DDR4_ROW_ADDR_WIDTH" value="15" />
<parameter name="MEM_DDR4_RTT_NOM_ENUM" value="DDR4_RTT_NOM_RZQ_4" />
+ <parameter name="MEM_DDR4_RTT_PARK">DDR4_RTT_PARK_ODT_DISABLED</parameter>
<parameter name="MEM_DDR4_RTT_WR_ENUM" value="DDR4_RTT_WR_RZQ_2" />
- <parameter name="MEM_DDR4_WTCL" value="18" />
- <parameter name="MEM_DDR4_ATCL_ENUM" value="DDR4_ATCL_DISABLED" />
- <parameter name="MEM_DDR4_TCL" value="18" />
- <parameter name="MEM_DDR4_USE_DEFAULT_ODT" value="true" />
- <parameter name="MEM_DDR4_R_ODTN_1X1" value="Rank 0" />
<parameter name="MEM_DDR4_R_ODT0_1X1" value="off" />
- <parameter name="MEM_DDR4_W_ODTN_1X1" value="Rank 0" />
- <parameter name="MEM_DDR4_W_ODT0_1X1" value="on" />
- <parameter name="MEM_DDR4_R_ODTN_2X2" value="Rank 0,Rank 1" />
<parameter name="MEM_DDR4_R_ODT0_2X2" value="off,on" />
- <parameter name="MEM_DDR4_R_ODT1_2X2" value="on,off" />
- <parameter name="MEM_DDR4_W_ODTN_2X2" value="Rank 0,Rank 1" />
- <parameter name="MEM_DDR4_W_ODT0_2X2" value="on,on" />
- <parameter name="MEM_DDR4_W_ODT1_2X2" value="on,on" />
- <parameter name="MEM_DDR4_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
<parameter name="MEM_DDR4_R_ODT0_4X2" value="off,off,on,on" />
- <parameter name="MEM_DDR4_R_ODT1_4X2" value="on,on,off,off" />
- <parameter name="MEM_DDR4_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
- <parameter name="MEM_DDR4_W_ODT0_4X2" value="off,off,on,on" />
- <parameter name="MEM_DDR4_W_ODT1_4X2" value="on,on,off,off" />
- <parameter name="MEM_DDR4_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
<parameter name="MEM_DDR4_R_ODT0_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR4_R_ODT1_2X2" value="on,off" />
+ <parameter name="MEM_DDR4_R_ODT1_4X2" value="on,on,off,off" />
<parameter name="MEM_DDR4_R_ODT1_4X4" value="off,off,on,on" />
<parameter name="MEM_DDR4_R_ODT2_4X4" value="off,off,off,off" />
<parameter name="MEM_DDR4_R_ODT3_4X4" value="on,on,off,off" />
- <parameter name="MEM_DDR4_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
- <parameter name="MEM_DDR4_W_ODT0_4X4" value="on,on,off,off" />
- <parameter name="MEM_DDR4_W_ODT1_4X4" value="off,off,on,on" />
- <parameter name="MEM_DDR4_W_ODT2_4X4" value="off,off,on,on" />
- <parameter name="MEM_DDR4_W_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_R_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR4_R_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR4_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_SELF_RFSH_ABORT" value="false" />
<parameter name="MEM_DDR4_SPEEDBIN_ENUM" value="DDR4_SPEEDBIN_2400" />
- <parameter name="MEM_DDR4_TIS_PS" value="60" />
- <parameter name="MEM_DDR4_TIS_AC_MV" value="100" />
- <parameter name="MEM_DDR4_TIH_PS" value="95" />
- <parameter name="MEM_DDR4_TIH_DC_MV" value="75" />
+ <parameter name="MEM_DDR4_TCCD_L_CYC" value="5" />
+ <parameter name="MEM_DDR4_TCCD_S_CYC" value="4" />
+ <parameter name="MEM_DDR4_TCL" value="18" />
<parameter name="MEM_DDR4_TDIVW_DJ_CYC" value="0.1" />
- <parameter name="MEM_DDR4_VDIVW_TOTAL" value="136" />
- <parameter name="MEM_DDR4_TDQSQ_PS" value="75" />
- <parameter name="MEM_DDR4_TQH_CYC" value="0.38" />
<parameter name="MEM_DDR4_TDQSCK_PS" value="180" />
+ <parameter name="MEM_DDR4_TDQSQ_PS" value="75" />
<parameter name="MEM_DDR4_TDQSS_CYC" value="0.27" />
- <parameter name="MEM_DDR4_TQSH_CYC" value="0.38" />
<parameter name="MEM_DDR4_TDSH_CYC" value="0.18" />
<parameter name="MEM_DDR4_TDSS_CYC" value="0.18" />
- <parameter name="MEM_DDR4_TWLS_PS" value="122.0" />
- <parameter name="MEM_DDR4_TWLH_PS" value="122.0" />
+ <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA" value="false" />
+ <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE">DDR4_TEMP_CONTROLLED_RFSH_NORMAL</parameter>
+ <parameter name="MEM_DDR4_TEMP_SENSOR_READOUT" value="false" />
+ <parameter name="MEM_DDR4_TFAW_NS" value="25.0" />
+ <parameter name="MEM_DDR4_TIH_DC_MV" value="75" />
+ <parameter name="MEM_DDR4_TIH_PS" value="95" />
<parameter name="MEM_DDR4_TINIT_US" value="500" />
+ <parameter name="MEM_DDR4_TIS_AC_MV" value="100" />
+ <parameter name="MEM_DDR4_TIS_PS" value="60" />
<parameter name="MEM_DDR4_TMRD_CK_CYC" value="8" />
+ <parameter name="MEM_DDR4_TQH_CYC" value="0.38" />
+ <parameter name="MEM_DDR4_TQSH_CYC" value="0.38" />
<parameter name="MEM_DDR4_TRAS_NS" value="33.0" />
<parameter name="MEM_DDR4_TRCD_NS" value="14.06" />
- <parameter name="MEM_DDR4_TRP_NS" value="14.06" />
<parameter name="MEM_DDR4_TREFI_US" value="7.8" />
<parameter name="MEM_DDR4_TRFC_NS" value="160.0" />
+ <parameter name="MEM_DDR4_TRP_NS" value="14.06" />
+ <parameter name="MEM_DDR4_TRRD_L_CYC" value="5" />
+ <parameter name="MEM_DDR4_TRRD_S_CYC" value="4" />
+ <parameter name="MEM_DDR4_TWLH_PS" value="122.0" />
+ <parameter name="MEM_DDR4_TWLS_PS" value="122.0" />
<parameter name="MEM_DDR4_TWR_NS" value="15.0" />
<parameter name="MEM_DDR4_TWTR_L_CYC" value="4" />
<parameter name="MEM_DDR4_TWTR_S_CYC" value="2" />
- <parameter name="MEM_DDR4_TFAW_NS" value="25.0" />
- <parameter name="MEM_DDR4_TRRD_L_CYC" value="5" />
- <parameter name="MEM_DDR4_TRRD_S_CYC" value="4" />
- <parameter name="MEM_DDR4_TCCD_L_CYC" value="5" />
- <parameter name="MEM_DDR4_TCCD_S_CYC" value="4" />
- <parameter name="MEM_DDR4_TRTP_CYC" value="8" />
- <parameter name="MEM_QDR2_WIDTH_EXPANDED" value="false" />
- <parameter name="MEM_QDR2_DATA_PER_DEVICE" value="36" />
+ <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_RANGE">DDR4_VREFDQ_TRAINING_RANGE_1</parameter>
+ <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_VALUE" value="60.0" />
+ <parameter name="MEM_DDR4_USE_DEFAULT_ODT" value="true" />
+ <parameter name="MEM_DDR4_VDIVW_TOTAL" value="136" />
+ <parameter name="MEM_DDR4_WRITE_CRC" value="false" />
+ <parameter name="MEM_DDR4_WRITE_DBI" value="false" />
+ <parameter name="MEM_DDR4_WRITE_PREAMBLE" value="1" />
+ <parameter name="MEM_DDR4_WTCL" value="18" />
+ <parameter name="MEM_DDR4_W_ODT0_1X1" value="on" />
+ <parameter name="MEM_DDR4_W_ODT0_2X2" value="on,on" />
+ <parameter name="MEM_DDR4_W_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT0_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODT1_2X2" value="on,on" />
+ <parameter name="MEM_DDR4_W_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT2_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR4_W_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR4_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
<parameter name="MEM_QDR2_ADDR_WIDTH" value="19" />
- <parameter name="MEM_QDR2_BWS_EN" value="true" />
<parameter name="MEM_QDR2_BL" value="4" />
+ <parameter name="MEM_QDR2_BWS_EN" value="true" />
+ <parameter name="MEM_QDR2_DATA_PER_DEVICE" value="36" />
+ <parameter name="MEM_QDR2_INTERNAL_JITTER_NS" value="0.08" />
<parameter name="MEM_QDR2_SPEEDBIN_ENUM" value="QDR2_SPEEDBIN_633" />
+ <parameter name="MEM_QDR2_TCCQO_NS" value="0.45" />
+ <parameter name="MEM_QDR2_TCQDOH_NS" value="-0.09" />
+ <parameter name="MEM_QDR2_TCQD_NS" value="0.09" />
+ <parameter name="MEM_QDR2_TCQH_NS" value="0.71" />
+ <parameter name="MEM_QDR2_THA_NS" value="0.18" />
+ <parameter name="MEM_QDR2_THD_NS" value="0.18" />
<parameter name="MEM_QDR2_TRL_CYC" value="2.5" />
<parameter name="MEM_QDR2_TSA_NS" value="0.23" />
- <parameter name="MEM_QDR2_THA_NS" value="0.18" />
<parameter name="MEM_QDR2_TSD_NS" value="0.23" />
- <parameter name="MEM_QDR2_THD_NS" value="0.18" />
- <parameter name="MEM_QDR2_TCQD_NS" value="0.09" />
- <parameter name="MEM_QDR2_TCQDOH_NS" value="-0.09" />
- <parameter name="MEM_QDR2_INTERNAL_JITTER_NS" value="0.08" />
- <parameter name="MEM_QDR2_TCQH_NS" value="0.71" />
- <parameter name="MEM_QDR2_TCCQO_NS" value="0.45" />
- <parameter name="MEM_RLD2_WIDTH_EXPANDED" value="false" />
- <parameter name="MEM_RLD2_DQ_PER_DEVICE" value="9" />
+ <parameter name="MEM_QDR2_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_QDR4_AC_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_ADDR_INV_ENA" value="false" />
+ <parameter name="MEM_QDR4_ADDR_WIDTH" value="21" />
+ <parameter name="MEM_QDR4_CK_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_DATA_INV_ENA" value="false" />
+ <parameter name="MEM_QDR4_DATA_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_DQ_PER_PORT_PER_DEVICE" value="36" />
+ <parameter name="MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
+ <parameter name="MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
+ <parameter name="MEM_QDR4_SPEEDBIN_ENUM" value="QDR4_SPEEDBIN_2133" />
+ <parameter name="MEM_QDR4_TAH_PS" value="125" />
+ <parameter name="MEM_QDR4_TAS_PS" value="125" />
+ <parameter name="MEM_QDR4_TCH_PS" value="150" />
+ <parameter name="MEM_QDR4_TCKDK_MAX_PS" value="150" />
+ <parameter name="MEM_QDR4_TCKDK_MIN_PS" value="-150" />
+ <parameter name="MEM_QDR4_TCKQK_MAX_PS" value="225" />
+ <parameter name="MEM_QDR4_TCS_PS" value="150" />
+ <parameter name="MEM_QDR4_TIH_PS" value="125" />
+ <parameter name="MEM_QDR4_TIS_PS" value="125" />
+ <parameter name="MEM_QDR4_TQH_CYC" value="0.4" />
+ <parameter name="MEM_QDR4_TQKQ_MAX_PS" value="75" />
+ <parameter name="MEM_QDR4_WIDTH_EXPANDED" value="false" />
<parameter name="MEM_RLD2_ADDR_WIDTH" value="21" />
<parameter name="MEM_RLD2_BANK_ADDR_WIDTH" value="3" />
- <parameter name="MEM_RLD2_DM_EN" value="true" />
<parameter name="MEM_RLD2_BL" value="4" />
<parameter name="MEM_RLD2_CONFIG_ENUM">RLD2_CONFIG_TRC_8_TRL_8_TWL_9</parameter>
+ <parameter name="MEM_RLD2_DM_EN" value="true" />
+ <parameter name="MEM_RLD2_DQ_PER_DEVICE" value="9" />
<parameter name="MEM_RLD2_DRIVE_IMPEDENCE_ENUM">RLD2_DRIVE_IMPEDENCE_INTERNAL_50</parameter>
<parameter name="MEM_RLD2_ODT_MODE_ENUM" value="RLD2_ODT_ON" />
- <parameter name="MEM_RLD2_SPEEDBIN_ENUM" value="RLD2_SPEEDBIN_18" />
<parameter name="MEM_RLD2_REFRESH_INTERVAL_US" value="0.24" />
- <parameter name="MEM_RLD2_TCKH_CYC" value="0.45" />
- <parameter name="MEM_RLD2_TQKH_HCYC" value="0.9" />
- <parameter name="MEM_RLD2_TAS_NS" value="0.3" />
+ <parameter name="MEM_RLD2_SPEEDBIN_ENUM" value="RLD2_SPEEDBIN_18" />
<parameter name="MEM_RLD2_TAH_NS" value="0.3" />
- <parameter name="MEM_RLD2_TDS_NS" value="0.17" />
- <parameter name="MEM_RLD2_TDH_NS" value="0.17" />
- <parameter name="MEM_RLD2_TQKQ_MAX_NS" value="0.12" />
- <parameter name="MEM_RLD2_TQKQ_MIN_NS" value="-0.12" />
+ <parameter name="MEM_RLD2_TAS_NS" value="0.3" />
<parameter name="MEM_RLD2_TCKDK_MAX_NS" value="0.3" />
<parameter name="MEM_RLD2_TCKDK_MIN_NS" value="-0.3" />
+ <parameter name="MEM_RLD2_TCKH_CYC" value="0.45" />
<parameter name="MEM_RLD2_TCKQK_MAX_NS" value="0.2" />
- <parameter name="MEM_RLD3_WIDTH_EXPANDED" value="false" />
- <parameter name="MEM_RLD3_DEPTH_EXPANDED" value="false" />
- <parameter name="MEM_RLD3_DQ_PER_DEVICE" value="36" />
+ <parameter name="MEM_RLD2_TDH_NS" value="0.17" />
+ <parameter name="MEM_RLD2_TDS_NS" value="0.17" />
+ <parameter name="MEM_RLD2_TQKH_HCYC" value="0.9" />
+ <parameter name="MEM_RLD2_TQKQ_MAX_NS" value="0.12" />
+ <parameter name="MEM_RLD2_TQKQ_MIN_NS" value="-0.12" />
+ <parameter name="MEM_RLD2_WIDTH_EXPANDED" value="false" />
<parameter name="MEM_RLD3_ADDR_WIDTH" value="20" />
+ <parameter name="MEM_RLD3_AREF_PROTOCOL_ENUM" value="RLD3_AREF_BAC" />
<parameter name="MEM_RLD3_BANK_ADDR_WIDTH" value="4" />
- <parameter name="MEM_RLD3_DM_EN" value="true" />
<parameter name="MEM_RLD3_BL" value="2" />
<parameter name="MEM_RLD3_DATA_LATENCY_MODE_ENUM" value="RLD3_DL_RL16_WL17" />
- <parameter name="MEM_RLD3_T_RC_MODE_ENUM" value="RLD3_TRC_9" />
- <parameter name="MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM">RLD3_OUTPUT_DRIVE_40</parameter>
+ <parameter name="MEM_RLD3_DEPTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD3_DM_EN" value="true" />
+ <parameter name="MEM_RLD3_DQ_PER_DEVICE" value="36" />
<parameter name="MEM_RLD3_ODT_MODE_ENUM" value="RLD3_ODT_40" />
- <parameter name="MEM_RLD3_AREF_PROTOCOL_ENUM" value="RLD3_AREF_BAC" />
- <parameter name="MEM_RLD3_WRITE_PROTOCOL_ENUM" value="RLD3_WRITE_1BANK" />
+ <parameter name="MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM">RLD3_OUTPUT_DRIVE_40</parameter>
<parameter name="MEM_RLD3_SPEEDBIN_ENUM" value="RLD3_SPEEDBIN_093E" />
- <parameter name="MEM_RLD3_TDS_PS" value="-30" />
- <parameter name="MEM_RLD3_TDH_PS" value="5" />
- <parameter name="MEM_RLD3_TQKQ_MAX_PS" value="75" />
- <parameter name="MEM_RLD3_TQH_CYC" value="0.38" />
<parameter name="MEM_RLD3_TCKDK_MAX_CYC" value="0.27" />
<parameter name="MEM_RLD3_TCKDK_MIN_CYC" value="-0.27" />
<parameter name="MEM_RLD3_TCKQK_MAX_PS" value="135" />
- <parameter name="MEM_RLD3_TIS_PS" value="85" />
+ <parameter name="MEM_RLD3_TDH_PS" value="5" />
+ <parameter name="MEM_RLD3_TDS_PS" value="-30" />
<parameter name="MEM_RLD3_TIH_PS" value="65" />
- <parameter name="BOARD_DDR3_USE_DEFAULT_SLEW_RATES" value="true" />
- <parameter name="BOARD_DDR3_USE_DEFAULT_ISI_VALUES" value="true" />
- <parameter name="BOARD_DDR3_USER_CK_SLEW_RATE" value="2.0" />
- <parameter name="BOARD_DDR3_USER_AC_SLEW_RATE" value="1.0" />
- <parameter name="BOARD_DDR3_USER_RCLK_SLEW_RATE" value="4.0" />
- <parameter name="BOARD_DDR3_USER_WCLK_SLEW_RATE" value="4.0" />
- <parameter name="BOARD_DDR3_USER_RDATA_SLEW_RATE" value="2.5" />
- <parameter name="BOARD_DDR3_USER_WDATA_SLEW_RATE" value="2.0" />
- <parameter name="BOARD_DDR3_USER_AC_ISI_NS" value="0.094" />
- <parameter name="BOARD_DDR3_USER_RCLK_ISI_NS" value="0.094" />
- <parameter name="BOARD_DDR3_USER_WCLK_ISI_NS" value="0.031" />
- <parameter name="BOARD_DDR3_USER_RDATA_ISI_NS" value="0.063" />
- <parameter name="BOARD_DDR3_USER_WDATA_ISI_NS" value="0.063" />
- <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
- <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
- <parameter name="BOARD_DDR3_PKG+BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
- <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
- <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
- <parameter name="BOARD_DDR3_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
- <parameter name="BOARD_DDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
- <parameter name="BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
- <parameter name="BOARD_DDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
- <parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
- <parameter name="BOARD_DDR3_MAX_CK_DELAY_NS" value="0.6" />
- <parameter name="BOARD_DDR3_MAX_DQS_DELAY_NS" value="0.6" />
- <parameter name="BOARD_DDR4_USE_DEFAULT_SLEW_RATES" value="true" />
- <parameter name="BOARD_DDR4_USE_DEFAULT_ISI_VALUES" value="true" />
- <parameter name="BOARD_DDR4_USER_CK_SLEW_RATE" value="4.0" />
- <parameter name="BOARD_DDR4_USER_AC_SLEW_RATE" value="2.0" />
- <parameter name="BOARD_DDR4_USER_RCLK_SLEW_RATE" value="4.0" />
- <parameter name="BOARD_DDR4_USER_WCLK_SLEW_RATE" value="4.0" />
- <parameter name="BOARD_DDR4_USER_RDATA_SLEW_RATE" value="4.0" />
- <parameter name="BOARD_DDR4_USER_WDATA_SLEW_RATE" value="2.0" />
- <parameter name="BOARD_DDR4_USER_AC_ISI_NS" value="0.094" />
- <parameter name="BOARD_DDR4_USER_RCLK_ISI_NS" value="0.094" />
- <parameter name="BOARD_DDR4_USER_WCLK_ISI_NS" value="0.031" />
- <parameter name="BOARD_DDR4_USER_RDATA_ISI_NS" value="0.063" />
- <parameter name="BOARD_DDR4_USER_WDATA_ISI_NS" value="0.063" />
- <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED" value="true" />
- <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
- <parameter name="BOARD_DDR4_PKG+BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
- <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
- <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
- <parameter name="BOARD_DDR4_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
- <parameter name="BOARD_DDR4_DQS_TO_CK_SKEW_NS" value="0.02" />
- <parameter name="BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
- <parameter name="BOARD_DDR4_SKEW_BETWEEN_DQS_NS" value="0.02" />
- <parameter name="BOARD_DDR4_AC_TO_CK_SKEW_NS" value="0.0" />
- <parameter name="BOARD_DDR4_MAX_CK_DELAY_NS" value="0.6" />
- <parameter name="BOARD_DDR4_MAX_DQS_DELAY_NS" value="0.6" />
- <parameter name="BOARD_QDR2_USE_DEFAULT_SLEW_RATES" value="true" />
- <parameter name="BOARD_QDR2_USE_DEFAULT_ISI_VALUES" value="true" />
- <parameter name="BOARD_QDR2_USER_K_SLEW_RATE" value="4.0" />
- <parameter name="BOARD_QDR2_USER_AC_SLEW_RATE" value="2.0" />
- <parameter name="BOARD_QDR2_USER_RCLK_SLEW_RATE" value="2.0" />
- <parameter name="BOARD_QDR2_USER_RDATA_SLEW_RATE" value="2.0" />
- <parameter name="BOARD_QDR2_USER_WDATA_SLEW_RATE" value="2.0" />
- <parameter name="BOARD_QDR2_USER_AC_ISI_NS" value="0.094" />
- <parameter name="BOARD_QDR2_USER_RCLK_ISI_NS" value="0.094" />
- <parameter name="BOARD_QDR2_USER_WCLK_ISI_NS" value="0.031" />
- <parameter name="BOARD_QDR2_USER_RDATA_ISI_NS" value="0.063" />
- <parameter name="BOARD_QDR2_USER_WDATA_ISI_NS" value="0.063" />
- <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED" value="false" />
- <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED" value="false" />
- <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
- <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
- <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_D_NS" value="0.02" />
- <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
- <parameter name="BOARD_QDR2_PKG+BRD_SKEW_WITHIN_Q_NS" value="0.02" />
- <parameter name="BOARD_QDR2_PKG+BRD_SKEW_WITHIN_D_NS" value="0.02" />
- <parameter name="BOARD_QDR2_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
- <parameter name="BOARD_QDR2_AC_TO_K_SKEW_NS" value="0.0" />
- <parameter name="BOARD_RLD3_USE_DEFAULT_SLEW_RATES" value="true" />
- <parameter name="BOARD_RLD3_USE_DEFAULT_ISI_VALUES" value="true" />
- <parameter name="BOARD_RLD3_USER_CK_SLEW_RATE" value="4.0" />
- <parameter name="BOARD_RLD3_USER_AC_SLEW_RATE" value="2.0" />
- <parameter name="BOARD_RLD3_USER_RCLK_SLEW_RATE" value="4.0" />
- <parameter name="BOARD_RLD3_USER_WCLK_SLEW_RATE" value="4.0" />
- <parameter name="BOARD_RLD3_USER_RDATA_SLEW_RATE" value="3.5" />
- <parameter name="BOARD_RLD3_USER_WDATA_SLEW_RATE" value="2.0" />
- <parameter name="BOARD_RLD3_USER_AC_ISI_NS" value="0.094" />
- <parameter name="BOARD_RLD3_USER_RCLK_ISI_NS" value="0.094" />
- <parameter name="BOARD_RLD3_USER_WCLK_ISI_NS" value="0.031" />
- <parameter name="BOARD_RLD3_USER_RDATA_ISI_NS" value="0.063" />
- <parameter name="BOARD_RLD3_USER_WDATA_ISI_NS" value="0.063" />
- <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
- <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
- <parameter name="BOARD_RLD3_PKG+BRD_SKEW_WITHIN_QK_NS" value="0.02" />
- <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
- <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
- <parameter name="BOARD_RLD3_PKG+BRD_SKEW_WITHIN_AC_NS" value="0.02" />
- <parameter name="BOARD_RLD3_DK_TO_CK_SKEW_NS" value="-0.02" />
- <parameter name="BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
- <parameter name="BOARD_RLD3_SKEW_BETWEEN_DK_NS" value="0.02" />
- <parameter name="BOARD_RLD3_AC_TO_CK_SKEW_NS" value="0.0" />
- <parameter name="BOARD_RLD3_MAX_CK_DELAY_NS" value="0.6" />
- <parameter name="BOARD_RLD3_MAX_DK_DELAY_NS" value="0.6" />
- <parameter name="CTRL_DDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
- <parameter name="CTRL_DDR3_SELF_REFRESH_EN" value="false" />
- <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_EN" value="false" />
- <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_CYCS" value="32" />
- <parameter name="CTRL_DDR3_USER_REFRESH_EN" value="false" />
- <parameter name="CTRL_DDR3_USER_PRIORITY_EN" value="false" />
- <parameter name="CTRL_DDR3_AUTO_PRECHARGE_EN" value="false" />
- <parameter name="CTRL_DDR3_ADDR_ORDER_ENUM">DDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
- <parameter name="CTRL_DDR3_ECC_EN" value="false" />
- <parameter name="CTRL_DDR3_ECC_AUTO_CORRECTION_EN" value="false" />
- <parameter name="CTRL_DDR3_REORDER_EN" value="true" />
- <parameter name="CTRL_DDR3_STARVE_LIMIT" value="63" />
- <parameter name="CTRL_DDR3_MMR_EN" value="false" />
- <parameter name="CTRL_DDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
- <parameter name="CTRL_DDR4_SELF_REFRESH_EN" value="false" />
- <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_EN" value="false" />
- <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_CYCS" value="32" />
- <parameter name="CTRL_DDR4_USER_REFRESH_EN" value="false" />
- <parameter name="CTRL_DDR4_USER_PRIORITY_EN" value="false" />
- <parameter name="CTRL_DDR4_AUTO_PRECHARGE_EN" value="false" />
- <parameter name="CTRL_DDR4_ADDR_ORDER_ENUM">DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG</parameter>
- <parameter name="CTRL_DDR4_ECC_EN" value="false" />
- <parameter name="CTRL_DDR4_ECC_AUTO_CORRECTION_EN" value="false" />
- <parameter name="CTRL_DDR4_REORDER_EN" value="true" />
- <parameter name="CTRL_DDR4_STARVE_LIMIT" value="63" />
- <parameter name="CTRL_DDR4_MMR_EN" value="false" />
- <parameter name="CTRL_QDR2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
- <parameter name="CTRL_QDR2_AVL_MAX_BURST_COUNT" value="4" />
- <parameter name="CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
- <parameter name="CTRL_RLD2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
- <parameter name="CTRL_RLD3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
- <parameter name="CTRL_RLD3_ADDR_ORDER_ENUM">RLD3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
- <parameter name="DIAG_TIMING_REGTEST_MODE" value="false" />
- <parameter name="DIAG_SYNTH_FOR_SIM" value="false" />
- <parameter name="DIAG_ECLIPSE_DEBUG" value="false" />
- <parameter name="DIAG_EXPORT_VJI" value="false" />
- <parameter name="DIAG_EX_DESIGN_ADD_TEST_EMIFS" value="" />
- <parameter name="DIAG_EXPOSE_DFT_SIGNALS" value="false" />
- <parameter name="DIAG_EXTRA_CONFIGS" value="" />
- <parameter name="DIAG_USE_BOARD_DELAY_MODEL" value="false" />
- <parameter name="DIAG_BOARD_DELAY_CONFIG_STR" value="" />
- <parameter name="DIAG_DDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
- <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
- <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="true" />
- <parameter name="DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
- <parameter name="DIAG_DDR3_INTERFACE_ID" value="0" />
- <parameter name="DIAG_DDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
- <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
- <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
- <parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
- <parameter name="DIAG_DDR4_INTERFACE_ID" value="0" />
- <parameter name="DIAG_DDR4_SKIP_VREF_CAL" value="true" />
- <parameter name="DIAG_QDR2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
- <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
- <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="true" />
- <parameter name="DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
- <parameter name="DIAG_QDR2_INTERFACE_ID" value="0" />
- <parameter name="DIAG_RLD2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
- <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
- <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="true" />
- <parameter name="DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
- <parameter name="DIAG_RLD2_INTERFACE_ID" value="0" />
- <parameter name="DIAG_RLD3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
- <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
- <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="true" />
- <parameter name="DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
- <parameter name="DIAG_RLD3_INTERFACE_ID" value="0" />
+ <parameter name="MEM_RLD3_TIS_PS" value="85" />
+ <parameter name="MEM_RLD3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_RLD3_TQKQ_MAX_PS" value="75" />
+ <parameter name="MEM_RLD3_T_RC_MODE_ENUM" value="RLD3_TRC_9" />
+ <parameter name="MEM_RLD3_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD3_WRITE_PROTOCOL_ENUM" value="RLD3_WRITE_1BANK" />
+ <parameter name="PHY_DDR3_CAL_ADDR0" value="0" />
+ <parameter name="PHY_DDR3_CAL_ADDR1" value="8" />
+ <parameter name="PHY_DDR3_CAL_ENABLE_NON_DES" value="true" />
+ <parameter name="PHY_DDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+ <parameter name="PHY_DDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_DDR3_DEFAULT_IO" value="true" />
+ <parameter name="PHY_DDR3_DEFAULT_REF_CLK_FREQ" value="false" />
+ <parameter name="PHY_DDR3_IO_VOLTAGE" value="1.5" />
+ <parameter name="PHY_DDR3_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_DDR3_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_DDR3_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_DDR3_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_REF_CLK_FREQ_MHZ" value="133.333" />
+ <parameter name="PHY_DDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+ <parameter name="PHY_DDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_DDR4_DEFAULT_IO" value="true" />
+ <parameter name="PHY_DDR4_DEFAULT_REF_CLK_FREQ" value="false" />
+ <parameter name="PHY_DDR4_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="900.0" />
+ <parameter name="PHY_DDR4_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_DDR4_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_DDR4_STARTING_VREFIN" value="70.0" />
+ <parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_REF_CLK_FREQ_MHZ" value="25.0" />
+ <parameter name="PHY_DDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_QDR2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_QDR2_DEFAULT_IO" value="true" />
+ <parameter name="PHY_QDR2_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_QDR2_IO_VOLTAGE" value="1.5" />
+ <parameter name="PHY_QDR2_MEM_CLK_FREQ_MHZ" value="633.333" />
+ <parameter name="PHY_QDR2_RATE_ENUM" value="RATE_HALF" />
+ <parameter name="PHY_QDR2_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_QDR2_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_QDR2_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_QDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_QDR4_DEFAULT_IO" value="true" />
+ <parameter name="PHY_QDR4_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_QDR4_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_QDR4_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_QDR4_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_QDR4_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_QDR4_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_QDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_RLD2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_RLD2_DEFAULT_IO" value="true" />
+ <parameter name="PHY_RLD2_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_RLD2_IO_VOLTAGE" value="1.8" />
+ <parameter name="PHY_RLD2_MEM_CLK_FREQ_MHZ" value="533.333" />
+ <parameter name="PHY_RLD2_RATE_ENUM" value="RATE_HALF" />
+ <parameter name="PHY_RLD2_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_RLD2_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_RLD2_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_CONFIG_ENUM" value="CONFIG_PHY_ONLY" />
+ <parameter name="PHY_RLD3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_RLD3_DEFAULT_IO" value="true" />
+ <parameter name="PHY_RLD3_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_RLD3_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_RLD3_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_RLD3_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_RLD3_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_RLD3_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_RLD3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR4" />
+ <parameter name="SYS_INFO_DEVICE" value="10AX115U4F45I3SG" />
+ <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="3" />
+ <parameter name="SYS_INFO_UNIQUE_ID">$${FILENAME}_ddr4_inst</parameter>
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
diff --git a/boards/uniboard2/designs/unb2_pinning/src/ip/system_pll.qsys b/boards/uniboard2/designs/unb2_pinning/src/ip/system_pll.qsys
index 49b19e83da..8f76e9b367 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/ip/system_pll.qsys
+++ b/boards/uniboard2/designs/unb2_pinning/src/ip/system_pll.qsys
@@ -6,21 +6,31 @@
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
- categories="" />
+ categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element system_pll_inst
{
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2SGES" />
+ <parameter name="device" value="10AX115U4F45I3SG" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
@@ -36,14 +46,18 @@
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
- name="outclk2"
- internal="system_pll_inst.outclk2"
+ name="locked"
+ internal="system_pll_inst.locked"
+ type="conduit"
+ dir="end">
+ <port name="locked" internal="locked" />
+ </interface>
+ <interface
+ name="outclk0"
+ internal="system_pll_inst.outclk0"
type="clock"
dir="start">
- <port name="outclk_2" internal="outclk_2" />
- </interface>
- <interface name="reset" internal="system_pll_inst.reset" type="reset" dir="end">
- <port name="rst" internal="rst" />
+ <port name="outclk_0" internal="outclk_0" />
</interface>
<interface
name="outclk1"
@@ -52,6 +66,13 @@
dir="start">
<port name="outclk_1" internal="outclk_1" />
</interface>
+ <interface
+ name="outclk2"
+ internal="system_pll_inst.outclk2"
+ type="clock"
+ dir="start">
+ <port name="outclk_2" internal="outclk_2" />
+ </interface>
<interface
name="refclk"
internal="system_pll_inst.refclk"
@@ -59,80 +80,110 @@
dir="end">
<port name="refclk" internal="refclk" />
</interface>
- <interface
- name="outclk0"
- internal="system_pll_inst.outclk0"
- type="clock"
- dir="start">
- <port name="outclk_0" internal="outclk_0" />
- </interface>
- <interface
- name="locked"
- internal="system_pll_inst.locked"
- type="conduit"
- dir="end">
- <port name="locked" internal="locked" />
+ <interface name="reset" internal="system_pll_inst.reset" type="reset" dir="end">
+ <port name="rst" internal="rst" />
</interface>
<module
+ name="system_pll_inst"
kind="altera_iopll"
- version="14.0"
+ version="14.1"
enabled="1"
- name="system_pll_inst"
autoexport="1">
- <parameter name="gui_en_reconf" value="false" />
- <parameter name="gui_en_dps_ports" value="false" />
- <parameter name="gui_pll_mode" value="Integer-N PLL" />
- <parameter name="gui_reference_clock_frequency" value="25.0" />
- <parameter name="gui_fractional_cout" value="32" />
- <parameter name="gui_dsm_out_sel" value="1st_order" />
- <parameter name="gui_use_locked" value="true" />
- <parameter name="gui_en_adv_params" value="false" />
- <parameter name="gui_pll_bandwidth_preset" value="Low" />
- <parameter name="gui_pll_auto_reset" value="false" />
- <parameter name="gui_en_lvds_ports" value="false" />
- <parameter name="gui_operation_mode" value="direct" />
- <parameter name="gui_feedback_clock" value="Global Clock" />
- <parameter name="gui_refclk_switch" value="false" />
- <parameter name="gui_refclk1_frequency" value="100.0" />
- <parameter name="gui_en_phout_ports" value="false" />
- <parameter name="gui_phout_division" value="1" />
- <parameter name="gui_en_extclkout_ports" value="false" />
- <parameter name="gui_number_of_clocks" value="3" />
- <parameter name="gui_multiply_factor" value="1" />
- <parameter name="gui_divide_factor_n" value="1" />
- <parameter name="gui_frac_multiply_factor" value="1" />
- <parameter name="gui_fix_vco_frequency" value="false" />
- <parameter name="gui_fixed_vco_frequency" value="600.0" />
- <parameter name="gui_enable_output_counter_cascading" value="false" />
- <parameter name="gui_mif_generate" value="false" />
- <parameter name="gui_device_speed_grade" value="1" />
- <parameter name="system_info_device_family" value="Arria 10" />
- <parameter name="system_info_device_component" value="10AX115U3F45I2SGES" />
- <parameter name="system_info_device_speed_grade" value="" />
<parameter name="gui_active_clk" value="false" />
- <parameter name="gui_clk_bad" value="false" />
- <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
- <parameter name="gui_switchover_delay" value="0" />
- <parameter name="gui_enable_cascade_out" value="false" />
+ <parameter name="gui_actual_duty_cycle0" value="50.0" />
+ <parameter name="gui_actual_duty_cycle1" value="50.0" />
+ <parameter name="gui_actual_duty_cycle10" value="50.0" />
+ <parameter name="gui_actual_duty_cycle11" value="50.0" />
+ <parameter name="gui_actual_duty_cycle12" value="50.0" />
+ <parameter name="gui_actual_duty_cycle13" value="50.0" />
+ <parameter name="gui_actual_duty_cycle14" value="50.0" />
+ <parameter name="gui_actual_duty_cycle15" value="50.0" />
+ <parameter name="gui_actual_duty_cycle16" value="50.0" />
+ <parameter name="gui_actual_duty_cycle17" value="50.0" />
+ <parameter name="gui_actual_duty_cycle2" value="50.0" />
+ <parameter name="gui_actual_duty_cycle3" value="50.0" />
+ <parameter name="gui_actual_duty_cycle4" value="50.0" />
+ <parameter name="gui_actual_duty_cycle5" value="50.0" />
+ <parameter name="gui_actual_duty_cycle6" value="50.0" />
+ <parameter name="gui_actual_duty_cycle7" value="50.0" />
+ <parameter name="gui_actual_duty_cycle8" value="50.0" />
+ <parameter name="gui_actual_duty_cycle9" value="50.0" />
+ <parameter name="gui_actual_output_clock_frequency0" value="0.0" />
+ <parameter name="gui_actual_output_clock_frequency1" value="0.0" />
+ <parameter name="gui_actual_output_clock_frequency10" value="0.0" />
+ <parameter name="gui_actual_output_clock_frequency11" value="0.0" />
+ <parameter name="gui_actual_output_clock_frequency12" value="0.0" />
+ <parameter name="gui_actual_output_clock_frequency13" value="0.0" />
+ <parameter name="gui_actual_output_clock_frequency14" value="0.0" />
+ <parameter name="gui_actual_output_clock_frequency15" value="0.0" />
+ <parameter name="gui_actual_output_clock_frequency16" value="0.0" />
+ <parameter name="gui_actual_output_clock_frequency17" value="0.0" />
+ <parameter name="gui_actual_output_clock_frequency2" value="0.0" />
+ <parameter name="gui_actual_output_clock_frequency3" value="0.0" />
+ <parameter name="gui_actual_output_clock_frequency4" value="0.0" />
+ <parameter name="gui_actual_output_clock_frequency5" value="0.0" />
+ <parameter name="gui_actual_output_clock_frequency6" value="0.0" />
+ <parameter name="gui_actual_output_clock_frequency7" value="0.0" />
+ <parameter name="gui_actual_output_clock_frequency8" value="0.0" />
+ <parameter name="gui_actual_output_clock_frequency9" value="0.0" />
+ <parameter name="gui_actual_phase_shift0" value="0.0" />
+ <parameter name="gui_actual_phase_shift1" value="0.0" />
+ <parameter name="gui_actual_phase_shift10" value="0.0" />
+ <parameter name="gui_actual_phase_shift11" value="0.0" />
+ <parameter name="gui_actual_phase_shift12" value="0.0" />
+ <parameter name="gui_actual_phase_shift13" value="0.0" />
+ <parameter name="gui_actual_phase_shift14" value="0.0" />
+ <parameter name="gui_actual_phase_shift15" value="0.0" />
+ <parameter name="gui_actual_phase_shift16" value="0.0" />
+ <parameter name="gui_actual_phase_shift17" value="0.0" />
+ <parameter name="gui_actual_phase_shift2" value="0.0" />
+ <parameter name="gui_actual_phase_shift3" value="0.0" />
+ <parameter name="gui_actual_phase_shift4" value="0.0" />
+ <parameter name="gui_actual_phase_shift5" value="0.0" />
+ <parameter name="gui_actual_phase_shift6" value="0.0" />
+ <parameter name="gui_actual_phase_shift7" value="0.0" />
+ <parameter name="gui_actual_phase_shift8" value="0.0" />
+ <parameter name="gui_actual_phase_shift9" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg0" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg1" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg10" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg11" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg12" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg13" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg14" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg15" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg16" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg17" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg2" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg3" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg4" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg5" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg6" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg7" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg8" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg9" value="0.0" />
+ <parameter name="gui_cascade_counter0" value="false" />
+ <parameter name="gui_cascade_counter1" value="false" />
+ <parameter name="gui_cascade_counter10" value="false" />
+ <parameter name="gui_cascade_counter11" value="false" />
+ <parameter name="gui_cascade_counter12" value="false" />
+ <parameter name="gui_cascade_counter13" value="false" />
+ <parameter name="gui_cascade_counter14" value="false" />
+ <parameter name="gui_cascade_counter15" value="false" />
+ <parameter name="gui_cascade_counter16" value="false" />
+ <parameter name="gui_cascade_counter17" value="false" />
+ <parameter name="gui_cascade_counter2" value="false" />
+ <parameter name="gui_cascade_counter3" value="false" />
+ <parameter name="gui_cascade_counter4" value="false" />
+ <parameter name="gui_cascade_counter5" value="false" />
+ <parameter name="gui_cascade_counter6" value="false" />
+ <parameter name="gui_cascade_counter7" value="false" />
+ <parameter name="gui_cascade_counter8" value="false" />
+ <parameter name="gui_cascade_counter9" value="false" />
<parameter name="gui_cascade_outclk_index" value="0" />
- <parameter name="gui_enable_cascade_in" value="false" />
- <parameter name="gui_pll_cascading_mode" value="adjpllin" />
- <parameter name="gui_enable_mif_dps" value="false" />
- <parameter name="gui_dps_cntr" value="C0" />
- <parameter name="gui_dps_num" value="1" />
- <parameter name="gui_dps_dir" value="Positive" />
- <parameter name="gui_extclkout_0_source" value="C0" />
- <parameter name="gui_extclkout_1_source" value="C0" />
+ <parameter name="gui_clk_bad" value="false" />
<parameter name="gui_clock_name_global0" value="false" />
<parameter name="gui_clock_name_global1" value="false" />
- <parameter name="gui_clock_name_global2" value="false" />
- <parameter name="gui_clock_name_global3" value="false" />
- <parameter name="gui_clock_name_global4" value="false" />
- <parameter name="gui_clock_name_global5" value="false" />
- <parameter name="gui_clock_name_global6" value="false" />
- <parameter name="gui_clock_name_global7" value="false" />
- <parameter name="gui_clock_name_global8" value="false" />
- <parameter name="gui_clock_name_global9" value="false" />
<parameter name="gui_clock_name_global10" value="false" />
<parameter name="gui_clock_name_global11" value="false" />
<parameter name="gui_clock_name_global12" value="false" />
@@ -141,16 +192,16 @@
<parameter name="gui_clock_name_global15" value="false" />
<parameter name="gui_clock_name_global16" value="false" />
<parameter name="gui_clock_name_global17" value="false" />
+ <parameter name="gui_clock_name_global2" value="false" />
+ <parameter name="gui_clock_name_global3" value="false" />
+ <parameter name="gui_clock_name_global4" value="false" />
+ <parameter name="gui_clock_name_global5" value="false" />
+ <parameter name="gui_clock_name_global6" value="false" />
+ <parameter name="gui_clock_name_global7" value="false" />
+ <parameter name="gui_clock_name_global8" value="false" />
+ <parameter name="gui_clock_name_global9" value="false" />
<parameter name="gui_clock_name_string0" value="" />
<parameter name="gui_clock_name_string1" value="" />
- <parameter name="gui_clock_name_string2" value="" />
- <parameter name="gui_clock_name_string3" value="" />
- <parameter name="gui_clock_name_string4" value="" />
- <parameter name="gui_clock_name_string5" value="" />
- <parameter name="gui_clock_name_string6" value="" />
- <parameter name="gui_clock_name_string7" value="" />
- <parameter name="gui_clock_name_string8" value="" />
- <parameter name="gui_clock_name_string9" value="" />
<parameter name="gui_clock_name_string10" value="" />
<parameter name="gui_clock_name_string11" value="" />
<parameter name="gui_clock_name_string12" value="" />
@@ -159,16 +210,17 @@
<parameter name="gui_clock_name_string15" value="" />
<parameter name="gui_clock_name_string16" value="" />
<parameter name="gui_clock_name_string17" value="" />
+ <parameter name="gui_clock_name_string2" value="" />
+ <parameter name="gui_clock_name_string3" value="" />
+ <parameter name="gui_clock_name_string4" value="" />
+ <parameter name="gui_clock_name_string5" value="" />
+ <parameter name="gui_clock_name_string6" value="" />
+ <parameter name="gui_clock_name_string7" value="" />
+ <parameter name="gui_clock_name_string8" value="" />
+ <parameter name="gui_clock_name_string9" value="" />
+ <parameter name="gui_device_speed_grade" value="1" />
<parameter name="gui_divide_factor_c0" value="1" />
<parameter name="gui_divide_factor_c1" value="1" />
- <parameter name="gui_divide_factor_c2" value="1" />
- <parameter name="gui_divide_factor_c3" value="1" />
- <parameter name="gui_divide_factor_c4" value="1" />
- <parameter name="gui_divide_factor_c5" value="1" />
- <parameter name="gui_divide_factor_c6" value="1" />
- <parameter name="gui_divide_factor_c7" value="1" />
- <parameter name="gui_divide_factor_c8" value="1" />
- <parameter name="gui_divide_factor_c9" value="1" />
<parameter name="gui_divide_factor_c10" value="1" />
<parameter name="gui_divide_factor_c11" value="1" />
<parameter name="gui_divide_factor_c12" value="1" />
@@ -177,34 +229,60 @@
<parameter name="gui_divide_factor_c15" value="1" />
<parameter name="gui_divide_factor_c16" value="1" />
<parameter name="gui_divide_factor_c17" value="1" />
- <parameter name="gui_cascade_counter0" value="false" />
- <parameter name="gui_cascade_counter1" value="false" />
- <parameter name="gui_cascade_counter2" value="false" />
- <parameter name="gui_cascade_counter3" value="false" />
- <parameter name="gui_cascade_counter4" value="false" />
- <parameter name="gui_cascade_counter5" value="false" />
- <parameter name="gui_cascade_counter6" value="false" />
- <parameter name="gui_cascade_counter7" value="false" />
- <parameter name="gui_cascade_counter8" value="false" />
- <parameter name="gui_cascade_counter9" value="false" />
- <parameter name="gui_cascade_counter10" value="false" />
- <parameter name="gui_cascade_counter11" value="false" />
- <parameter name="gui_cascade_counter12" value="false" />
- <parameter name="gui_cascade_counter13" value="false" />
- <parameter name="gui_cascade_counter14" value="false" />
- <parameter name="gui_cascade_counter15" value="false" />
- <parameter name="gui_cascade_counter16" value="false" />
- <parameter name="gui_cascade_counter17" value="false" />
+ <parameter name="gui_divide_factor_c2" value="1" />
+ <parameter name="gui_divide_factor_c3" value="1" />
+ <parameter name="gui_divide_factor_c4" value="1" />
+ <parameter name="gui_divide_factor_c5" value="1" />
+ <parameter name="gui_divide_factor_c6" value="1" />
+ <parameter name="gui_divide_factor_c7" value="1" />
+ <parameter name="gui_divide_factor_c8" value="1" />
+ <parameter name="gui_divide_factor_c9" value="1" />
+ <parameter name="gui_divide_factor_n" value="1" />
+ <parameter name="gui_dps_cntr" value="C0" />
+ <parameter name="gui_dps_dir" value="Positive" />
+ <parameter name="gui_dps_num" value="1" />
+ <parameter name="gui_dsm_out_sel" value="1st_order" />
+ <parameter name="gui_duty_cycle0" value="50.0" />
+ <parameter name="gui_duty_cycle1" value="50.0" />
+ <parameter name="gui_duty_cycle10" value="50.0" />
+ <parameter name="gui_duty_cycle11" value="50.0" />
+ <parameter name="gui_duty_cycle12" value="50.0" />
+ <parameter name="gui_duty_cycle13" value="50.0" />
+ <parameter name="gui_duty_cycle14" value="50.0" />
+ <parameter name="gui_duty_cycle15" value="50.0" />
+ <parameter name="gui_duty_cycle16" value="50.0" />
+ <parameter name="gui_duty_cycle17" value="50.0" />
+ <parameter name="gui_duty_cycle2" value="50.0" />
+ <parameter name="gui_duty_cycle3" value="50.0" />
+ <parameter name="gui_duty_cycle4" value="50.0" />
+ <parameter name="gui_duty_cycle5" value="50.0" />
+ <parameter name="gui_duty_cycle6" value="50.0" />
+ <parameter name="gui_duty_cycle7" value="50.0" />
+ <parameter name="gui_duty_cycle8" value="50.0" />
+ <parameter name="gui_duty_cycle9" value="50.0" />
+ <parameter name="gui_en_adv_params" value="false" />
+ <parameter name="gui_en_dps_ports" value="false" />
+ <parameter name="gui_en_extclkout_ports" value="false" />
+ <parameter name="gui_en_lvds_ports" value="false" />
+ <parameter name="gui_en_phout_ports" value="false" />
+ <parameter name="gui_en_reconf" value="false" />
+ <parameter name="gui_enable_cascade_in" value="false" />
+ <parameter name="gui_enable_cascade_out" value="false" />
+ <parameter name="gui_enable_mif_dps" value="false" />
+ <parameter name="gui_enable_output_counter_cascading" value="false" />
+ <parameter name="gui_extclkout_0_source" value="C0" />
+ <parameter name="gui_extclkout_1_source" value="C0" />
+ <parameter name="gui_feedback_clock" value="Global Clock" />
+ <parameter name="gui_fix_vco_frequency" value="false" />
+ <parameter name="gui_fixed_vco_frequency" value="600.0" />
+ <parameter name="gui_frac_multiply_factor" value="1" />
+ <parameter name="gui_fractional_cout" value="32" />
+ <parameter name="gui_mif_generate" value="false" />
+ <parameter name="gui_multiply_factor" value="1" />
+ <parameter name="gui_number_of_clocks" value="3" />
+ <parameter name="gui_operation_mode" value="direct" />
<parameter name="gui_output_clock_frequency0" value="100.0" />
<parameter name="gui_output_clock_frequency1" value="300.0" />
- <parameter name="gui_output_clock_frequency2" value="125.0" />
- <parameter name="gui_output_clock_frequency3" value="100.0" />
- <parameter name="gui_output_clock_frequency4" value="100.0" />
- <parameter name="gui_output_clock_frequency5" value="100.0" />
- <parameter name="gui_output_clock_frequency6" value="100.0" />
- <parameter name="gui_output_clock_frequency7" value="100.0" />
- <parameter name="gui_output_clock_frequency8" value="100.0" />
- <parameter name="gui_output_clock_frequency9" value="100.0" />
<parameter name="gui_output_clock_frequency10" value="100.0" />
<parameter name="gui_output_clock_frequency11" value="100.0" />
<parameter name="gui_output_clock_frequency12" value="100.0" />
@@ -213,52 +291,16 @@
<parameter name="gui_output_clock_frequency15" value="100.0" />
<parameter name="gui_output_clock_frequency16" value="100.0" />
<parameter name="gui_output_clock_frequency17" value="100.0" />
- <parameter name="gui_actual_output_clock_frequency0" value="0.0" />
- <parameter name="gui_actual_output_clock_frequency1" value="0.0" />
- <parameter name="gui_actual_output_clock_frequency2" value="0.0" />
- <parameter name="gui_actual_output_clock_frequency3" value="0.0" />
- <parameter name="gui_actual_output_clock_frequency4" value="0.0" />
- <parameter name="gui_actual_output_clock_frequency5" value="0.0" />
- <parameter name="gui_actual_output_clock_frequency6" value="0.0" />
- <parameter name="gui_actual_output_clock_frequency7" value="0.0" />
- <parameter name="gui_actual_output_clock_frequency8" value="0.0" />
- <parameter name="gui_actual_output_clock_frequency9" value="0.0" />
- <parameter name="gui_actual_output_clock_frequency10" value="0.0" />
- <parameter name="gui_actual_output_clock_frequency11" value="0.0" />
- <parameter name="gui_actual_output_clock_frequency12" value="0.0" />
- <parameter name="gui_actual_output_clock_frequency13" value="0.0" />
- <parameter name="gui_actual_output_clock_frequency14" value="0.0" />
- <parameter name="gui_actual_output_clock_frequency15" value="0.0" />
- <parameter name="gui_actual_output_clock_frequency16" value="0.0" />
- <parameter name="gui_actual_output_clock_frequency17" value="0.0" />
- <parameter name="gui_ps_units0" value="ps" />
- <parameter name="gui_ps_units1" value="ps" />
- <parameter name="gui_ps_units2" value="ps" />
- <parameter name="gui_ps_units3" value="ps" />
- <parameter name="gui_ps_units4" value="ps" />
- <parameter name="gui_ps_units5" value="ps" />
- <parameter name="gui_ps_units6" value="ps" />
- <parameter name="gui_ps_units7" value="ps" />
- <parameter name="gui_ps_units8" value="ps" />
- <parameter name="gui_ps_units9" value="ps" />
- <parameter name="gui_ps_units10" value="ps" />
- <parameter name="gui_ps_units11" value="ps" />
- <parameter name="gui_ps_units12" value="ps" />
- <parameter name="gui_ps_units13" value="ps" />
- <parameter name="gui_ps_units14" value="ps" />
- <parameter name="gui_ps_units15" value="ps" />
- <parameter name="gui_ps_units16" value="ps" />
- <parameter name="gui_ps_units17" value="ps" />
+ <parameter name="gui_output_clock_frequency2" value="125.0" />
+ <parameter name="gui_output_clock_frequency3" value="100.0" />
+ <parameter name="gui_output_clock_frequency4" value="100.0" />
+ <parameter name="gui_output_clock_frequency5" value="100.0" />
+ <parameter name="gui_output_clock_frequency6" value="100.0" />
+ <parameter name="gui_output_clock_frequency7" value="100.0" />
+ <parameter name="gui_output_clock_frequency8" value="100.0" />
+ <parameter name="gui_output_clock_frequency9" value="100.0" />
<parameter name="gui_phase_shift0" value="0.0" />
<parameter name="gui_phase_shift1" value="0.0" />
- <parameter name="gui_phase_shift2" value="0.0" />
- <parameter name="gui_phase_shift3" value="0.0" />
- <parameter name="gui_phase_shift4" value="0.0" />
- <parameter name="gui_phase_shift5" value="0.0" />
- <parameter name="gui_phase_shift6" value="0.0" />
- <parameter name="gui_phase_shift7" value="0.0" />
- <parameter name="gui_phase_shift8" value="0.0" />
- <parameter name="gui_phase_shift9" value="0.0" />
<parameter name="gui_phase_shift10" value="0.0" />
<parameter name="gui_phase_shift11" value="0.0" />
<parameter name="gui_phase_shift12" value="0.0" />
@@ -267,16 +309,16 @@
<parameter name="gui_phase_shift15" value="0.0" />
<parameter name="gui_phase_shift16" value="0.0" />
<parameter name="gui_phase_shift17" value="0.0" />
+ <parameter name="gui_phase_shift2" value="0.0" />
+ <parameter name="gui_phase_shift3" value="0.0" />
+ <parameter name="gui_phase_shift4" value="0.0" />
+ <parameter name="gui_phase_shift5" value="0.0" />
+ <parameter name="gui_phase_shift6" value="0.0" />
+ <parameter name="gui_phase_shift7" value="0.0" />
+ <parameter name="gui_phase_shift8" value="0.0" />
+ <parameter name="gui_phase_shift9" value="0.0" />
<parameter name="gui_phase_shift_deg0" value="0.0" />
<parameter name="gui_phase_shift_deg1" value="0.0" />
- <parameter name="gui_phase_shift_deg2" value="0.0" />
- <parameter name="gui_phase_shift_deg3" value="0.0" />
- <parameter name="gui_phase_shift_deg4" value="0.0" />
- <parameter name="gui_phase_shift_deg5" value="0.0" />
- <parameter name="gui_phase_shift_deg6" value="0.0" />
- <parameter name="gui_phase_shift_deg7" value="0.0" />
- <parameter name="gui_phase_shift_deg8" value="0.0" />
- <parameter name="gui_phase_shift_deg9" value="0.0" />
<parameter name="gui_phase_shift_deg10" value="0.0" />
<parameter name="gui_phase_shift_deg11" value="0.0" />
<parameter name="gui_phase_shift_deg12" value="0.0" />
@@ -285,81 +327,49 @@
<parameter name="gui_phase_shift_deg15" value="0.0" />
<parameter name="gui_phase_shift_deg16" value="0.0" />
<parameter name="gui_phase_shift_deg17" value="0.0" />
- <parameter name="gui_actual_phase_shift0" value="0.0" />
- <parameter name="gui_actual_phase_shift1" value="0.0" />
- <parameter name="gui_actual_phase_shift2" value="0.0" />
- <parameter name="gui_actual_phase_shift3" value="0.0" />
- <parameter name="gui_actual_phase_shift4" value="0.0" />
- <parameter name="gui_actual_phase_shift5" value="0.0" />
- <parameter name="gui_actual_phase_shift6" value="0.0" />
- <parameter name="gui_actual_phase_shift7" value="0.0" />
- <parameter name="gui_actual_phase_shift8" value="0.0" />
- <parameter name="gui_actual_phase_shift9" value="0.0" />
- <parameter name="gui_actual_phase_shift10" value="0.0" />
- <parameter name="gui_actual_phase_shift11" value="0.0" />
- <parameter name="gui_actual_phase_shift12" value="0.0" />
- <parameter name="gui_actual_phase_shift13" value="0.0" />
- <parameter name="gui_actual_phase_shift14" value="0.0" />
- <parameter name="gui_actual_phase_shift15" value="0.0" />
- <parameter name="gui_actual_phase_shift16" value="0.0" />
- <parameter name="gui_actual_phase_shift17" value="0.0" />
- <parameter name="gui_actual_phase_shift_deg0" value="0.0" />
- <parameter name="gui_actual_phase_shift_deg1" value="0.0" />
- <parameter name="gui_actual_phase_shift_deg2" value="0.0" />
- <parameter name="gui_actual_phase_shift_deg3" value="0.0" />
- <parameter name="gui_actual_phase_shift_deg4" value="0.0" />
- <parameter name="gui_actual_phase_shift_deg5" value="0.0" />
- <parameter name="gui_actual_phase_shift_deg6" value="0.0" />
- <parameter name="gui_actual_phase_shift_deg7" value="0.0" />
- <parameter name="gui_actual_phase_shift_deg8" value="0.0" />
- <parameter name="gui_actual_phase_shift_deg9" value="0.0" />
- <parameter name="gui_actual_phase_shift_deg10" value="0.0" />
- <parameter name="gui_actual_phase_shift_deg11" value="0.0" />
- <parameter name="gui_actual_phase_shift_deg12" value="0.0" />
- <parameter name="gui_actual_phase_shift_deg13" value="0.0" />
- <parameter name="gui_actual_phase_shift_deg14" value="0.0" />
- <parameter name="gui_actual_phase_shift_deg15" value="0.0" />
- <parameter name="gui_actual_phase_shift_deg16" value="0.0" />
- <parameter name="gui_actual_phase_shift_deg17" value="0.0" />
- <parameter name="gui_duty_cycle0" value="50.0" />
- <parameter name="gui_duty_cycle1" value="50.0" />
- <parameter name="gui_duty_cycle2" value="50.0" />
- <parameter name="gui_duty_cycle3" value="50.0" />
- <parameter name="gui_duty_cycle4" value="50.0" />
- <parameter name="gui_duty_cycle5" value="50.0" />
- <parameter name="gui_duty_cycle6" value="50.0" />
- <parameter name="gui_duty_cycle7" value="50.0" />
- <parameter name="gui_duty_cycle8" value="50.0" />
- <parameter name="gui_duty_cycle9" value="50.0" />
- <parameter name="gui_duty_cycle10" value="50.0" />
- <parameter name="gui_duty_cycle11" value="50.0" />
- <parameter name="gui_duty_cycle12" value="50.0" />
- <parameter name="gui_duty_cycle13" value="50.0" />
- <parameter name="gui_duty_cycle14" value="50.0" />
- <parameter name="gui_duty_cycle15" value="50.0" />
- <parameter name="gui_duty_cycle16" value="50.0" />
- <parameter name="gui_duty_cycle17" value="50.0" />
- <parameter name="gui_actual_duty_cycle0" value="50.0" />
- <parameter name="gui_actual_duty_cycle1" value="50.0" />
- <parameter name="gui_actual_duty_cycle2" value="50.0" />
- <parameter name="gui_actual_duty_cycle3" value="50.0" />
- <parameter name="gui_actual_duty_cycle4" value="50.0" />
- <parameter name="gui_actual_duty_cycle5" value="50.0" />
- <parameter name="gui_actual_duty_cycle6" value="50.0" />
- <parameter name="gui_actual_duty_cycle7" value="50.0" />
- <parameter name="gui_actual_duty_cycle8" value="50.0" />
- <parameter name="gui_actual_duty_cycle9" value="50.0" />
- <parameter name="gui_actual_duty_cycle10" value="50.0" />
- <parameter name="gui_actual_duty_cycle11" value="50.0" />
- <parameter name="gui_actual_duty_cycle12" value="50.0" />
- <parameter name="gui_actual_duty_cycle13" value="50.0" />
- <parameter name="gui_actual_duty_cycle14" value="50.0" />
- <parameter name="gui_actual_duty_cycle15" value="50.0" />
- <parameter name="gui_actual_duty_cycle16" value="50.0" />
- <parameter name="gui_actual_duty_cycle17" value="50.0" />
- <parameter name="AUTO_REFCLK_CLOCK_RATE" value="-1" />
+ <parameter name="gui_phase_shift_deg2" value="0.0" />
+ <parameter name="gui_phase_shift_deg3" value="0.0" />
+ <parameter name="gui_phase_shift_deg4" value="0.0" />
+ <parameter name="gui_phase_shift_deg5" value="0.0" />
+ <parameter name="gui_phase_shift_deg6" value="0.0" />
+ <parameter name="gui_phase_shift_deg7" value="0.0" />
+ <parameter name="gui_phase_shift_deg8" value="0.0" />
+ <parameter name="gui_phase_shift_deg9" value="0.0" />
+ <parameter name="gui_phout_division" value="1" />
+ <parameter name="gui_pll_auto_reset" value="false" />
+ <parameter name="gui_pll_bandwidth_preset" value="Low" />
+ <parameter name="gui_pll_cascading_mode" value="adjpllin" />
+ <parameter name="gui_pll_mode" value="Integer-N PLL" />
+ <parameter name="gui_ps_units0" value="ps" />
+ <parameter name="gui_ps_units1" value="ps" />
+ <parameter name="gui_ps_units10" value="ps" />
+ <parameter name="gui_ps_units11" value="ps" />
+ <parameter name="gui_ps_units12" value="ps" />
+ <parameter name="gui_ps_units13" value="ps" />
+ <parameter name="gui_ps_units14" value="ps" />
+ <parameter name="gui_ps_units15" value="ps" />
+ <parameter name="gui_ps_units16" value="ps" />
+ <parameter name="gui_ps_units17" value="ps" />
+ <parameter name="gui_ps_units2" value="ps" />
+ <parameter name="gui_ps_units3" value="ps" />
+ <parameter name="gui_ps_units4" value="ps" />
+ <parameter name="gui_ps_units5" value="ps" />
+ <parameter name="gui_ps_units6" value="ps" />
+ <parameter name="gui_ps_units7" value="ps" />
+ <parameter name="gui_ps_units8" value="ps" />
+ <parameter name="gui_ps_units9" value="ps" />
+ <parameter name="gui_refclk1_frequency" value="100.0" />
+ <parameter name="gui_refclk_switch" value="false" />
+ <parameter name="gui_reference_clock_frequency" value="25.0" />
+ <parameter name="gui_switchover_delay" value="0" />
+ <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+ <parameter name="gui_use_locked" value="true" />
+ <parameter name="system_info_device_component" value="10AX115U4F45I3SG" />
+ <parameter name="system_info_device_family" value="Arria 10" />
+ <parameter name="system_info_device_speed_grade" value="3" />
+ <parameter name="system_part_trait_speed_grade" value="2" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
diff --git a/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_phy.qsys b/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_phy.qsys
index c4b730b001..5aba4471b0 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_phy.qsys
+++ b/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_phy.qsys
@@ -6,21 +6,31 @@
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
- categories="" />
+ categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element transceiver_phy_inst
{
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2SGES" />
+ <parameter name="device" value="10AX115U4F45I3SG" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
@@ -36,74 +46,67 @@
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
- name="tx_analogreset"
- internal="transceiver_phy_inst.tx_analogreset"
- type="conduit"
- dir="end">
- <port name="tx_analogreset" internal="tx_analogreset" />
- </interface>
- <interface
- name="tx_digitalreset"
- internal="transceiver_phy_inst.tx_digitalreset"
+ name="rx_analogreset"
+ internal="transceiver_phy_inst.rx_analogreset"
type="conduit"
dir="end">
- <port name="tx_digitalreset" internal="tx_digitalreset" />
+ <port name="rx_analogreset" internal="rx_analogreset" />
</interface>
<interface
- name="rx_analogreset"
- internal="transceiver_phy_inst.rx_analogreset"
+ name="rx_cal_busy"
+ internal="transceiver_phy_inst.rx_cal_busy"
type="conduit"
dir="end">
- <port name="rx_analogreset" internal="rx_analogreset" />
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
</interface>
<interface
- name="rx_digitalreset"
- internal="transceiver_phy_inst.rx_digitalreset"
+ name="rx_cdr_refclk0"
+ internal="transceiver_phy_inst.rx_cdr_refclk0"
type="conduit"
dir="end">
- <port name="rx_digitalreset" internal="rx_digitalreset" />
+ <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
</interface>
<interface
- name="tx_cal_busy"
- internal="transceiver_phy_inst.tx_cal_busy"
+ name="rx_clkout"
+ internal="transceiver_phy_inst.rx_clkout"
type="conduit"
dir="end">
- <port name="tx_cal_busy" internal="tx_cal_busy" />
+ <port name="rx_clkout" internal="rx_clkout" />
</interface>
<interface
- name="rx_cal_busy"
- internal="transceiver_phy_inst.rx_cal_busy"
+ name="rx_control"
+ internal="transceiver_phy_inst.rx_control"
type="conduit"
dir="end">
- <port name="rx_cal_busy" internal="rx_cal_busy" />
+ <port name="rx_control" internal="rx_control" />
</interface>
<interface
- name="tx_serial_clk0"
- internal="transceiver_phy_inst.tx_serial_clk0"
+ name="rx_coreclkin"
+ internal="transceiver_phy_inst.rx_coreclkin"
type="conduit"
dir="end">
- <port name="tx_serial_clk0" internal="tx_serial_clk0" />
+ <port name="rx_coreclkin" internal="rx_coreclkin" />
</interface>
<interface
- name="rx_cdr_refclk0"
- internal="transceiver_phy_inst.rx_cdr_refclk0"
+ name="rx_digitalreset"
+ internal="transceiver_phy_inst.rx_digitalreset"
type="conduit"
dir="end">
- <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
</interface>
<interface
- name="tx_serial_data"
- internal="transceiver_phy_inst.tx_serial_data"
+ name="rx_enh_blk_lock"
+ internal="transceiver_phy_inst.rx_enh_blk_lock"
type="conduit"
dir="end">
- <port name="tx_serial_data" internal="tx_serial_data" />
+ <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
</interface>
<interface
- name="rx_serial_data"
- internal="transceiver_phy_inst.rx_serial_data"
+ name="rx_enh_data_valid"
+ internal="transceiver_phy_inst.rx_enh_data_valid"
type="conduit"
dir="end">
- <port name="rx_serial_data" internal="rx_serial_data" />
+ <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
</interface>
<interface
name="rx_is_lockedtodata"
@@ -113,39 +116,39 @@
<port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
</interface>
<interface
- name="tx_coreclkin"
- internal="transceiver_phy_inst.tx_coreclkin"
+ name="rx_parallel_data"
+ internal="transceiver_phy_inst.rx_parallel_data"
type="conduit"
dir="end">
- <port name="tx_coreclkin" internal="tx_coreclkin" />
+ <port name="rx_parallel_data" internal="rx_parallel_data" />
</interface>
<interface
- name="rx_coreclkin"
- internal="transceiver_phy_inst.rx_coreclkin"
+ name="rx_serial_data"
+ internal="transceiver_phy_inst.rx_serial_data"
type="conduit"
dir="end">
- <port name="rx_coreclkin" internal="rx_coreclkin" />
+ <port name="rx_serial_data" internal="rx_serial_data" />
</interface>
<interface
- name="tx_clkout"
- internal="transceiver_phy_inst.tx_clkout"
+ name="tx_analogreset"
+ internal="transceiver_phy_inst.tx_analogreset"
type="conduit"
dir="end">
- <port name="tx_clkout" internal="tx_clkout" />
+ <port name="tx_analogreset" internal="tx_analogreset" />
</interface>
<interface
- name="rx_clkout"
- internal="transceiver_phy_inst.rx_clkout"
+ name="tx_cal_busy"
+ internal="transceiver_phy_inst.tx_cal_busy"
type="conduit"
dir="end">
- <port name="rx_clkout" internal="rx_clkout" />
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
</interface>
<interface
- name="tx_parallel_data"
- internal="transceiver_phy_inst.tx_parallel_data"
+ name="tx_clkout"
+ internal="transceiver_phy_inst.tx_clkout"
type="conduit"
dir="end">
- <port name="tx_parallel_data" internal="tx_parallel_data" />
+ <port name="tx_clkout" internal="tx_clkout" />
</interface>
<interface
name="tx_control"
@@ -155,46 +158,53 @@
<port name="tx_control" internal="tx_control" />
</interface>
<interface
- name="tx_err_ins"
- internal="transceiver_phy_inst.tx_err_ins"
+ name="tx_coreclkin"
+ internal="transceiver_phy_inst.tx_coreclkin"
type="conduit"
dir="end">
- <port name="tx_err_ins" internal="tx_err_ins" />
+ <port name="tx_coreclkin" internal="tx_coreclkin" />
</interface>
<interface
- name="unused_tx_parallel_data"
- internal="transceiver_phy_inst.unused_tx_parallel_data"
+ name="tx_digitalreset"
+ internal="transceiver_phy_inst.tx_digitalreset"
type="conduit"
dir="end">
- <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
</interface>
<interface
- name="unused_tx_control"
- internal="transceiver_phy_inst.unused_tx_control"
+ name="tx_enh_data_valid"
+ internal="transceiver_phy_inst.tx_enh_data_valid"
type="conduit"
dir="end">
- <port name="unused_tx_control" internal="unused_tx_control" />
+ <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
</interface>
<interface
- name="rx_parallel_data"
- internal="transceiver_phy_inst.rx_parallel_data"
+ name="tx_err_ins"
+ internal="transceiver_phy_inst.tx_err_ins"
type="conduit"
dir="end">
- <port name="rx_parallel_data" internal="rx_parallel_data" />
+ <port name="tx_err_ins" internal="tx_err_ins" />
</interface>
<interface
- name="rx_control"
- internal="transceiver_phy_inst.rx_control"
+ name="tx_parallel_data"
+ internal="transceiver_phy_inst.tx_parallel_data"
type="conduit"
dir="end">
- <port name="rx_control" internal="rx_control" />
+ <port name="tx_parallel_data" internal="tx_parallel_data" />
</interface>
<interface
- name="unused_rx_parallel_data"
- internal="transceiver_phy_inst.unused_rx_parallel_data"
+ name="tx_serial_clk0"
+ internal="transceiver_phy_inst.tx_serial_clk0"
type="conduit"
dir="end">
- <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
+ <port name="tx_serial_clk0" internal="tx_serial_clk0" />
+ </interface>
+ <interface
+ name="tx_serial_data"
+ internal="transceiver_phy_inst.tx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_data" internal="tx_serial_data" />
</interface>
<interface
name="unused_rx_control"
@@ -204,226 +214,180 @@
<port name="unused_rx_control" internal="unused_rx_control" />
</interface>
<interface
- name="tx_enh_data_valid"
- internal="transceiver_phy_inst.tx_enh_data_valid"
+ name="unused_rx_parallel_data"
+ internal="transceiver_phy_inst.unused_rx_parallel_data"
type="conduit"
dir="end">
- <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
+ <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
</interface>
<interface
- name="rx_enh_data_valid"
- internal="transceiver_phy_inst.rx_enh_data_valid"
+ name="unused_tx_control"
+ internal="transceiver_phy_inst.unused_tx_control"
type="conduit"
dir="end">
- <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
+ <port name="unused_tx_control" internal="unused_tx_control" />
</interface>
<interface
- name="rx_enh_blk_lock"
- internal="transceiver_phy_inst.rx_enh_blk_lock"
+ name="unused_tx_parallel_data"
+ internal="transceiver_phy_inst.unused_tx_parallel_data"
type="conduit"
dir="end">
- <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
+ <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
</interface>
<module
+ name="transceiver_phy_inst"
kind="altera_xcvr_native_a10"
- version="14.0"
+ version="14.1"
enabled="1"
- name="transceiver_phy_inst"
autoexport="1">
- <parameter name="device_family" value="Arria 10" />
- <parameter name="device" value="10AX115U3F45I2SGES" />
- <parameter name="design_environment" value="NATIVE" />
- <parameter name="message_level" value="error" />
- <parameter name="support_mode" value="user_mode" />
- <parameter name="protocol_mode" value="teng_baser_mode" />
- <parameter name="pma_mode" value="basic" />
- <parameter name="duplex_mode" value="duplex" />
- <parameter name="channels" value="48" />
- <parameter name="set_data_rate" value="10312.5" />
- <parameter name="rcfg_iface_enable" value="0" />
- <parameter name="enable_simple_interface" value="1" />
- <parameter name="enable_split_interface" value="0" />
- <parameter name="set_enable_calibration" value="0" />
- <parameter name="enable_transparent_pcs" value="0" />
- <parameter name="enable_parallel_loopback" value="0" />
+ <parameter name="base_device" value="NIGHTFURY5ES" />
<parameter name="bonded_mode" value="not_bonded" />
- <parameter name="set_pcs_bonding_master" value="Auto" />
- <parameter name="tx_pma_clk_div" value="1" />
- <parameter name="plls" value="1" />
- <parameter name="pll_select" value="0" />
- <parameter name="enable_port_tx_pma_clkout" value="0" />
- <parameter name="enable_port_tx_pma_div_clkout" value="0" />
- <parameter name="tx_pma_div_clkout_divider" value="33" />
- <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
- <parameter name="enable_port_tx_pma_elecidle" value="0" />
- <parameter name="enable_port_tx_pma_qpipullup" value="0" />
- <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
- <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
- <parameter name="enable_port_tx_pma_rxfound" value="0" />
- <parameter name="enable_port_rx_seriallpbken_tx" value="0" />
<parameter name="cdr_refclk_cnt" value="1" />
<parameter name="cdr_refclk_select" value="0" />
- <parameter name="set_cdr_refclk_freq" value="644.531250" />
- <parameter name="rx_ppm_detect_threshold" value="100" />
- <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
- <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
- <parameter name="rx_pma_dfe_fixed_taps" value="3" />
- <parameter name="enable_rx_pma_floatingtap" value="0" />
- <parameter name="enable_ports_adaptation" value="0" />
+ <parameter name="channels" value="48" />
+ <parameter name="design_environment" value="NATIVE" />
+ <parameter name="device" value="10AX115U4F45I3SG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="duplex_mode" value="duplex" />
+ <parameter name="enable_hard_reset" value="0" />
+ <parameter name="enable_hip" value="0" />
+ <parameter name="enable_parallel_loopback" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
+ <parameter name="enable_port_pipe_rx_polarity" value="0" />
+ <parameter name="enable_port_rx_enh_bitslip" value="0" />
+ <parameter name="enable_port_rx_enh_blk_lock" value="1" />
+ <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
+ <parameter name="enable_port_rx_enh_crc32_err" value="0" />
+ <parameter name="enable_port_rx_enh_data_valid" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_del" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_empty" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_full" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_insert" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
+ <parameter name="enable_port_rx_enh_frame" value="0" />
+ <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_rx_enh_frame_lock" value="0" />
+ <parameter name="enable_port_rx_enh_highber" value="0" />
+ <parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
+ <parameter name="enable_port_rx_is_lockedtodata" value="1" />
+ <parameter name="enable_port_rx_is_lockedtoref" value="0" />
<parameter name="enable_port_rx_pma_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_clkslip" value="0" />
<parameter name="enable_port_rx_pma_div_clkout" value="0" />
- <parameter name="rx_pma_div_clkout_divider" value="0" />
<parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
- <parameter name="enable_port_rx_pma_clkslip" value="0" />
<parameter name="enable_port_rx_pma_qpipullup" value="0" />
- <parameter name="enable_port_rx_is_lockedtodata" value="1" />
- <parameter name="enable_port_rx_is_lockedtoref" value="0" />
- <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
- <parameter name="enable_ports_rx_manual_ppm" value="0" />
- <parameter name="enable_port_rx_signaldetect" value="0" />
+ <parameter name="enable_port_rx_polinv" value="0" />
<parameter name="enable_port_rx_seriallpbken" value="0" />
- <parameter name="enable_ports_rx_prbs" value="0" />
- <parameter name="std_pcs_pma_width" value="10" />
- <parameter name="std_low_latency_bypass_enable" value="0" />
- <parameter name="enable_hip" value="0" />
- <parameter name="enable_hard_reset" value="0" />
- <parameter name="set_hip_cal_en" value="0" />
- <parameter name="std_tx_pcfifo_mode" value="low_latency" />
- <parameter name="std_rx_pcfifo_mode" value="low_latency" />
- <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
- <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
- <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
+ <parameter name="enable_port_rx_seriallpbken_tx" value="0" />
+ <parameter name="enable_port_rx_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
+ <parameter name="enable_port_rx_std_bitslip" value="0" />
+ <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_rx_std_byterev_ena" value="0" />
<parameter name="enable_port_rx_std_pcfifo_empty" value="0" />
- <parameter name="std_tx_byte_ser_mode" value="Disabled" />
- <parameter name="std_rx_byte_deser_mode" value="Disabled" />
- <parameter name="std_tx_8b10b_enable" value="1" />
- <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
- <parameter name="std_rx_8b10b_enable" value="1" />
- <parameter name="std_rx_rmfifo_mode" value="disabled" />
- <parameter name="std_rx_rmfifo_pattern_n" value="0" />
- <parameter name="std_rx_rmfifo_pattern_p" value="0" />
- <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
<parameter name="enable_port_rx_std_rmfifo_empty" value="0" />
- <parameter name="pcie_rate_match" value="Bypass" />
- <parameter name="std_tx_bitslip_enable" value="0" />
- <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
- <parameter name="std_rx_word_aligner_mode">synchronous state machine</parameter>
- <parameter name="std_rx_word_aligner_pattern_len" value="7" />
- <parameter name="std_rx_word_aligner_pattern" value="124" />
- <parameter name="std_rx_word_aligner_rknumber" value="3" />
- <parameter name="std_rx_word_aligner_renumber" value="3" />
- <parameter name="std_rx_word_aligner_rgnumber" value="3" />
- <parameter name="std_rx_word_aligner_rvnumber" value="0" />
- <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
- <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_signaldetect" value="0" />
<parameter name="enable_port_rx_std_wa_a1a2size" value="0" />
- <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
- <parameter name="enable_port_rx_std_bitslip" value="0" />
- <parameter name="std_tx_bitrev_enable" value="0" />
- <parameter name="std_tx_byterev_enable" value="0" />
- <parameter name="std_tx_polinv_enable" value="0" />
+ <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
+ <parameter name="enable_port_tx_enh_bitslip" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_empty" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_full" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_pempty" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_pfull" value="0" />
+ <parameter name="enable_port_tx_enh_frame" value="0" />
+ <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
+ <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_tx_pma_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_elecidle" value="0" />
+ <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_tx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_tx_pma_rxfound" value="0" />
+ <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
<parameter name="enable_port_tx_polinv" value="0" />
- <parameter name="std_rx_bitrev_enable" value="0" />
- <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
- <parameter name="std_rx_byterev_enable" value="0" />
- <parameter name="enable_port_rx_std_byterev_ena" value="0" />
- <parameter name="std_rx_polinv_enable" value="0" />
- <parameter name="enable_port_rx_polinv" value="0" />
- <parameter name="enable_port_rx_std_signaldetect" value="0" />
- <parameter name="enable_ports_pipe_sw" value="0" />
- <parameter name="enable_ports_pipe_hclk" value="0" />
+ <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
+ <parameter name="enable_ports_adaptation" value="0" />
<parameter name="enable_ports_pipe_g3_analog" value="0" />
+ <parameter name="enable_ports_pipe_hclk" value="0" />
<parameter name="enable_ports_pipe_rx_elecidle" value="0" />
- <parameter name="enable_port_pipe_rx_polarity" value="0" />
+ <parameter name="enable_ports_pipe_sw" value="0" />
+ <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
+ <parameter name="enable_ports_rx_manual_ppm" value="0" />
+ <parameter name="enable_ports_rx_prbs" value="0" />
+ <parameter name="enable_rx_pma_floatingtap" value="0" />
+ <parameter name="enable_simple_interface" value="1" />
+ <parameter name="enable_split_interface" value="0" />
+ <parameter name="enable_transparent_pcs" value="0" />
+ <parameter name="enh_low_latency_enable" value="0" />
<parameter name="enh_pcs_pma_width" value="32" />
<parameter name="enh_pld_pcs_width" value="66" />
- <parameter name="enh_low_latency_enable" value="0" />
- <parameter name="enh_rxtxfifo_double_width" value="0" />
- <parameter name="enh_txfifo_mode" value="Phase compensation" />
- <parameter name="enh_txfifo_pfull" value="11" />
- <parameter name="enh_txfifo_pempty" value="2" />
- <parameter name="enable_port_tx_enh_fifo_full" value="0" />
- <parameter name="enable_port_tx_enh_fifo_pfull" value="0" />
- <parameter name="enable_port_tx_enh_fifo_empty" value="0" />
- <parameter name="enable_port_tx_enh_fifo_pempty" value="0" />
- <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
- <parameter name="enh_rxfifo_mode" value="10GBase-R" />
- <parameter name="enh_rxfifo_pfull" value="23" />
- <parameter name="enh_rxfifo_pempty" value="2" />
- <parameter name="enh_rxfifo_align_del" value="0" />
- <parameter name="enh_rxfifo_control_del" value="0" />
- <parameter name="enable_port_rx_enh_data_valid" value="1" />
- <parameter name="enable_port_rx_enh_fifo_full" value="0" />
- <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
- <parameter name="enable_port_rx_enh_fifo_empty" value="0" />
- <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
- <parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
- <parameter name="enable_port_rx_enh_fifo_del" value="0" />
- <parameter name="enable_port_rx_enh_fifo_insert" value="0" />
- <parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
- <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
- <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
- <parameter name="enh_tx_frmgen_enable" value="0" />
- <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
- <parameter name="enh_tx_frmgen_burst_enable" value="0" />
- <parameter name="enable_port_tx_enh_frame" value="0" />
- <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
- <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
- <parameter name="enh_rx_frmsync_enable" value="0" />
- <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
- <parameter name="enable_port_rx_enh_frame" value="0" />
- <parameter name="enable_port_rx_enh_frame_lock" value="0" />
- <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
- <parameter name="enh_tx_crcgen_enable" value="0" />
- <parameter name="enh_tx_crcerr_enable" value="0" />
- <parameter name="enh_rx_crcchk_enable" value="0" />
- <parameter name="enable_port_rx_enh_crc32_err" value="0" />
- <parameter name="enable_port_rx_enh_highber" value="0" />
- <parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
- <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
- <parameter name="enh_tx_64b66b_enable" value="1" />
<parameter name="enh_rx_64b66b_enable" value="1" />
- <parameter name="enh_tx_sh_err" value="0" />
- <parameter name="enh_tx_scram_enable" value="1" />
- <parameter name="enh_tx_scram_seed" value="288230376151711743" />
+ <parameter name="enh_rx_bitslip_enable" value="0" />
+ <parameter name="enh_rx_blksync_enable" value="1" />
+ <parameter name="enh_rx_crcchk_enable" value="0" />
<parameter name="enh_rx_descram_enable" value="1" />
- <parameter name="enh_tx_dispgen_enable" value="0" />
<parameter name="enh_rx_dispchk_enable" value="0" />
- <parameter name="enh_rx_blksync_enable" value="1" />
- <parameter name="enable_port_rx_enh_blk_lock" value="1" />
- <parameter name="enh_tx_bitslip_enable" value="0" />
- <parameter name="enh_tx_polinv_enable" value="0" />
- <parameter name="enh_rx_bitslip_enable" value="0" />
- <parameter name="enh_rx_polinv_enable" value="0" />
- <parameter name="enable_port_tx_enh_bitslip" value="0" />
- <parameter name="enable_port_rx_enh_bitslip" value="0" />
+ <parameter name="enh_rx_frmsync_enable" value="0" />
+ <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
<parameter name="enh_rx_krfec_err_mark_enable" value="0" />
<parameter name="enh_rx_krfec_err_mark_type" value="10G" />
+ <parameter name="enh_rx_polinv_enable" value="0" />
+ <parameter name="enh_rxfifo_align_del" value="0" />
+ <parameter name="enh_rxfifo_control_del" value="0" />
+ <parameter name="enh_rxfifo_mode" value="10GBase-R" />
+ <parameter name="enh_rxfifo_pempty" value="2" />
+ <parameter name="enh_rxfifo_pfull" value="23" />
+ <parameter name="enh_rxtxfifo_double_width" value="0" />
+ <parameter name="enh_tx_64b66b_enable" value="1" />
+ <parameter name="enh_tx_bitslip_enable" value="0" />
+ <parameter name="enh_tx_crcerr_enable" value="0" />
+ <parameter name="enh_tx_crcgen_enable" value="0" />
+ <parameter name="enh_tx_dispgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_burst_enable" value="0" />
+ <parameter name="enh_tx_frmgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
<parameter name="enh_tx_krfec_burst_err_enable" value="0" />
<parameter name="enh_tx_krfec_burst_err_len" value="1" />
- <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
- <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
- <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
- <parameter name="pcs_direct_width" value="8" />
- <parameter name="generate_docs" value="1" />
+ <parameter name="enh_tx_polinv_enable" value="0" />
+ <parameter name="enh_tx_randomdispbit_enable" value="0" />
+ <parameter name="enh_tx_scram_enable" value="1" />
+ <parameter name="enh_tx_scram_seed" value="288230376151711743" />
+ <parameter name="enh_tx_sh_err" value="0" />
+ <parameter name="enh_txfifo_mode" value="Phase compensation" />
+ <parameter name="enh_txfifo_pempty" value="2" />
+ <parameter name="enh_txfifo_pfull" value="11" />
<parameter name="generate_add_hdl_instance_example" value="0" />
- <parameter name="validation_rule_select" value="" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="number_physical_bonding_clocks" value="1" />
+ <parameter name="pcie_rate_match" value="Bypass" />
+ <parameter name="pcs_direct_width" value="8" />
+ <parameter name="pll_select" value="0" />
+ <parameter name="plls" value="1" />
+ <parameter name="pma_mode" value="basic" />
+ <parameter name="protocol_mode" value="teng_baser_mode" />
+ <parameter name="rapid_validate" value="0" />
<parameter name="rcfg_enable" value="0" />
- <parameter name="rcfg_shared" value="0" />
- <parameter name="rcfg_jtag_enable" value="0" />
- <parameter name="set_embedded_debug_enable" value="0" />
- <parameter name="set_capability_reg_enable" value="0" />
- <parameter name="set_user_identifier" value="0" />
- <parameter name="set_csr_soft_logic_enable" value="0" />
- <parameter name="set_prbs_soft_logic_enable" value="0" />
<parameter name="rcfg_file_prefix">altera_xcvr_native_a10</parameter>
- <parameter name="rcfg_sv_file_enable" value="0" />
<parameter name="rcfg_h_file_enable" value="0" />
+ <parameter name="rcfg_iface_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="0" />
<parameter name="rcfg_mif_file_enable" value="0" />
<parameter name="rcfg_multi_enable" value="0" />
- <parameter name="rcfg_reduced_files_enable" value="0" />
<parameter name="rcfg_profile_cnt" value="2" />
- <parameter name="rcfg_profile_select" value="1" />
<parameter name="rcfg_profile_data0" value="" />
<parameter name="rcfg_profile_data1" value="" />
<parameter name="rcfg_profile_data2" value="" />
@@ -432,8 +396,58 @@
<parameter name="rcfg_profile_data5" value="" />
<parameter name="rcfg_profile_data6" value="" />
<parameter name="rcfg_profile_data7" value="" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_reduced_files_enable" value="0" />
+ <parameter name="rcfg_shared" value="0" />
+ <parameter name="rcfg_sv_file_enable" value="0" />
+ <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
+ <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
+ <parameter name="rx_pma_dfe_fixed_taps" value="3" />
+ <parameter name="rx_pma_div_clkout_divider" value="0" />
+ <parameter name="rx_ppm_detect_threshold" value="100" />
+ <parameter name="set_capability_reg_enable" value="0" />
+ <parameter name="set_cdr_refclk_freq" value="644.531250" />
+ <parameter name="set_csr_soft_logic_enable" value="0" />
+ <parameter name="set_data_rate" value="10312.5" />
+ <parameter name="set_embedded_debug_enable" value="0" />
+ <parameter name="set_enable_calibration" value="0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_pcs_bonding_master" value="Auto" />
+ <parameter name="set_prbs_soft_logic_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="std_low_latency_bypass_enable" value="0" />
+ <parameter name="std_pcs_pma_width" value="10" />
+ <parameter name="std_rx_8b10b_enable" value="1" />
+ <parameter name="std_rx_bitrev_enable" value="0" />
+ <parameter name="std_rx_byte_deser_mode" value="Disabled" />
+ <parameter name="std_rx_byterev_enable" value="0" />
+ <parameter name="std_rx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_rx_polinv_enable" value="0" />
+ <parameter name="std_rx_rmfifo_mode" value="disabled" />
+ <parameter name="std_rx_rmfifo_pattern_n" value="0" />
+ <parameter name="std_rx_rmfifo_pattern_p" value="0" />
+ <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
+ <parameter name="std_rx_word_aligner_mode">synchronous state machine</parameter>
+ <parameter name="std_rx_word_aligner_pattern" value="124" />
+ <parameter name="std_rx_word_aligner_pattern_len" value="7" />
+ <parameter name="std_rx_word_aligner_renumber" value="3" />
+ <parameter name="std_rx_word_aligner_rgnumber" value="3" />
+ <parameter name="std_rx_word_aligner_rknumber" value="3" />
+ <parameter name="std_rx_word_aligner_rvnumber" value="0" />
+ <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
+ <parameter name="std_tx_8b10b_enable" value="1" />
+ <parameter name="std_tx_bitrev_enable" value="0" />
+ <parameter name="std_tx_bitslip_enable" value="0" />
+ <parameter name="std_tx_byte_ser_mode" value="Disabled" />
+ <parameter name="std_tx_byterev_enable" value="0" />
+ <parameter name="std_tx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_tx_polinv_enable" value="0" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="tx_pma_clk_div" value="1" />
+ <parameter name="tx_pma_div_clkout_divider" value="33" />
+ <parameter name="validation_rule_select" value="" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
diff --git a/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_phy_24channel.qsys b/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_phy_24channel.qsys
index 303946d001..3e40cb1d42 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_phy_24channel.qsys
+++ b/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_phy_24channel.qsys
@@ -11,6 +11,11 @@
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element transceiver_phy_inst
{
@@ -23,9 +28,9 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2SGES" />
+ <parameter name="device" value="10AX115U4F45I3SG" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
@@ -41,74 +46,67 @@
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
- name="tx_analogreset"
- internal="transceiver_phy_inst.tx_analogreset"
- type="conduit"
- dir="end">
- <port name="tx_analogreset" internal="tx_analogreset" />
- </interface>
- <interface
- name="tx_digitalreset"
- internal="transceiver_phy_inst.tx_digitalreset"
+ name="rx_analogreset"
+ internal="transceiver_phy_inst.rx_analogreset"
type="conduit"
dir="end">
- <port name="tx_digitalreset" internal="tx_digitalreset" />
+ <port name="rx_analogreset" internal="rx_analogreset" />
</interface>
<interface
- name="rx_analogreset"
- internal="transceiver_phy_inst.rx_analogreset"
+ name="rx_cal_busy"
+ internal="transceiver_phy_inst.rx_cal_busy"
type="conduit"
dir="end">
- <port name="rx_analogreset" internal="rx_analogreset" />
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
</interface>
<interface
- name="rx_digitalreset"
- internal="transceiver_phy_inst.rx_digitalreset"
+ name="rx_cdr_refclk0"
+ internal="transceiver_phy_inst.rx_cdr_refclk0"
type="conduit"
dir="end">
- <port name="rx_digitalreset" internal="rx_digitalreset" />
+ <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
</interface>
<interface
- name="tx_cal_busy"
- internal="transceiver_phy_inst.tx_cal_busy"
+ name="rx_clkout"
+ internal="transceiver_phy_inst.rx_clkout"
type="conduit"
dir="end">
- <port name="tx_cal_busy" internal="tx_cal_busy" />
+ <port name="rx_clkout" internal="rx_clkout" />
</interface>
<interface
- name="rx_cal_busy"
- internal="transceiver_phy_inst.rx_cal_busy"
+ name="rx_control"
+ internal="transceiver_phy_inst.rx_control"
type="conduit"
dir="end">
- <port name="rx_cal_busy" internal="rx_cal_busy" />
+ <port name="rx_control" internal="rx_control" />
</interface>
<interface
- name="tx_serial_clk0"
- internal="transceiver_phy_inst.tx_serial_clk0"
+ name="rx_coreclkin"
+ internal="transceiver_phy_inst.rx_coreclkin"
type="conduit"
dir="end">
- <port name="tx_serial_clk0" internal="tx_serial_clk0" />
+ <port name="rx_coreclkin" internal="rx_coreclkin" />
</interface>
<interface
- name="rx_cdr_refclk0"
- internal="transceiver_phy_inst.rx_cdr_refclk0"
+ name="rx_digitalreset"
+ internal="transceiver_phy_inst.rx_digitalreset"
type="conduit"
dir="end">
- <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
</interface>
<interface
- name="tx_serial_data"
- internal="transceiver_phy_inst.tx_serial_data"
+ name="rx_enh_blk_lock"
+ internal="transceiver_phy_inst.rx_enh_blk_lock"
type="conduit"
dir="end">
- <port name="tx_serial_data" internal="tx_serial_data" />
+ <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
</interface>
<interface
- name="rx_serial_data"
- internal="transceiver_phy_inst.rx_serial_data"
+ name="rx_enh_data_valid"
+ internal="transceiver_phy_inst.rx_enh_data_valid"
type="conduit"
dir="end">
- <port name="rx_serial_data" internal="rx_serial_data" />
+ <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
</interface>
<interface
name="rx_is_lockedtodata"
@@ -118,39 +116,39 @@
<port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
</interface>
<interface
- name="tx_coreclkin"
- internal="transceiver_phy_inst.tx_coreclkin"
+ name="rx_parallel_data"
+ internal="transceiver_phy_inst.rx_parallel_data"
type="conduit"
dir="end">
- <port name="tx_coreclkin" internal="tx_coreclkin" />
+ <port name="rx_parallel_data" internal="rx_parallel_data" />
</interface>
<interface
- name="rx_coreclkin"
- internal="transceiver_phy_inst.rx_coreclkin"
+ name="rx_serial_data"
+ internal="transceiver_phy_inst.rx_serial_data"
type="conduit"
dir="end">
- <port name="rx_coreclkin" internal="rx_coreclkin" />
+ <port name="rx_serial_data" internal="rx_serial_data" />
</interface>
<interface
- name="tx_clkout"
- internal="transceiver_phy_inst.tx_clkout"
+ name="tx_analogreset"
+ internal="transceiver_phy_inst.tx_analogreset"
type="conduit"
dir="end">
- <port name="tx_clkout" internal="tx_clkout" />
+ <port name="tx_analogreset" internal="tx_analogreset" />
</interface>
<interface
- name="rx_clkout"
- internal="transceiver_phy_inst.rx_clkout"
+ name="tx_cal_busy"
+ internal="transceiver_phy_inst.tx_cal_busy"
type="conduit"
dir="end">
- <port name="rx_clkout" internal="rx_clkout" />
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
</interface>
<interface
- name="tx_parallel_data"
- internal="transceiver_phy_inst.tx_parallel_data"
+ name="tx_clkout"
+ internal="transceiver_phy_inst.tx_clkout"
type="conduit"
dir="end">
- <port name="tx_parallel_data" internal="tx_parallel_data" />
+ <port name="tx_clkout" internal="tx_clkout" />
</interface>
<interface
name="tx_control"
@@ -160,46 +158,53 @@
<port name="tx_control" internal="tx_control" />
</interface>
<interface
- name="tx_err_ins"
- internal="transceiver_phy_inst.tx_err_ins"
+ name="tx_coreclkin"
+ internal="transceiver_phy_inst.tx_coreclkin"
type="conduit"
dir="end">
- <port name="tx_err_ins" internal="tx_err_ins" />
+ <port name="tx_coreclkin" internal="tx_coreclkin" />
</interface>
<interface
- name="unused_tx_parallel_data"
- internal="transceiver_phy_inst.unused_tx_parallel_data"
+ name="tx_digitalreset"
+ internal="transceiver_phy_inst.tx_digitalreset"
type="conduit"
dir="end">
- <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
</interface>
<interface
- name="unused_tx_control"
- internal="transceiver_phy_inst.unused_tx_control"
+ name="tx_enh_data_valid"
+ internal="transceiver_phy_inst.tx_enh_data_valid"
type="conduit"
dir="end">
- <port name="unused_tx_control" internal="unused_tx_control" />
+ <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
</interface>
<interface
- name="rx_parallel_data"
- internal="transceiver_phy_inst.rx_parallel_data"
+ name="tx_err_ins"
+ internal="transceiver_phy_inst.tx_err_ins"
type="conduit"
dir="end">
- <port name="rx_parallel_data" internal="rx_parallel_data" />
+ <port name="tx_err_ins" internal="tx_err_ins" />
</interface>
<interface
- name="rx_control"
- internal="transceiver_phy_inst.rx_control"
+ name="tx_parallel_data"
+ internal="transceiver_phy_inst.tx_parallel_data"
type="conduit"
dir="end">
- <port name="rx_control" internal="rx_control" />
+ <port name="tx_parallel_data" internal="tx_parallel_data" />
</interface>
<interface
- name="unused_rx_parallel_data"
- internal="transceiver_phy_inst.unused_rx_parallel_data"
+ name="tx_serial_clk0"
+ internal="transceiver_phy_inst.tx_serial_clk0"
type="conduit"
dir="end">
- <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
+ <port name="tx_serial_clk0" internal="tx_serial_clk0" />
+ </interface>
+ <interface
+ name="tx_serial_data"
+ internal="transceiver_phy_inst.tx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_data" internal="tx_serial_data" />
</interface>
<interface
name="unused_rx_control"
@@ -209,226 +214,180 @@
<port name="unused_rx_control" internal="unused_rx_control" />
</interface>
<interface
- name="tx_enh_data_valid"
- internal="transceiver_phy_inst.tx_enh_data_valid"
+ name="unused_rx_parallel_data"
+ internal="transceiver_phy_inst.unused_rx_parallel_data"
type="conduit"
dir="end">
- <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
+ <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
</interface>
<interface
- name="rx_enh_data_valid"
- internal="transceiver_phy_inst.rx_enh_data_valid"
+ name="unused_tx_control"
+ internal="transceiver_phy_inst.unused_tx_control"
type="conduit"
dir="end">
- <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
+ <port name="unused_tx_control" internal="unused_tx_control" />
</interface>
<interface
- name="rx_enh_blk_lock"
- internal="transceiver_phy_inst.rx_enh_blk_lock"
+ name="unused_tx_parallel_data"
+ internal="transceiver_phy_inst.unused_tx_parallel_data"
type="conduit"
dir="end">
- <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
+ <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
</interface>
<module
+ name="transceiver_phy_inst"
kind="altera_xcvr_native_a10"
- version="14.0"
+ version="14.1"
enabled="1"
- name="transceiver_phy_inst"
autoexport="1">
- <parameter name="device_family" value="Arria 10" />
- <parameter name="device" value="10AX115U3F45I2SGES" />
- <parameter name="design_environment" value="NATIVE" />
- <parameter name="message_level" value="error" />
- <parameter name="support_mode" value="user_mode" />
- <parameter name="protocol_mode" value="teng_baser_mode" />
- <parameter name="pma_mode" value="basic" />
- <parameter name="duplex_mode" value="duplex" />
- <parameter name="channels" value="24" />
- <parameter name="set_data_rate" value="10312.5" />
- <parameter name="rcfg_iface_enable" value="0" />
- <parameter name="enable_simple_interface" value="1" />
- <parameter name="enable_split_interface" value="0" />
- <parameter name="set_enable_calibration" value="0" />
- <parameter name="enable_transparent_pcs" value="0" />
- <parameter name="enable_parallel_loopback" value="0" />
+ <parameter name="base_device" value="NIGHTFURY5ES" />
<parameter name="bonded_mode" value="not_bonded" />
- <parameter name="set_pcs_bonding_master" value="Auto" />
- <parameter name="tx_pma_clk_div" value="1" />
- <parameter name="plls" value="1" />
- <parameter name="pll_select" value="0" />
- <parameter name="enable_port_tx_pma_clkout" value="0" />
- <parameter name="enable_port_tx_pma_div_clkout" value="0" />
- <parameter name="tx_pma_div_clkout_divider" value="33" />
- <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
- <parameter name="enable_port_tx_pma_elecidle" value="0" />
- <parameter name="enable_port_tx_pma_qpipullup" value="0" />
- <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
- <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
- <parameter name="enable_port_tx_pma_rxfound" value="0" />
- <parameter name="enable_port_rx_seriallpbken_tx" value="0" />
<parameter name="cdr_refclk_cnt" value="1" />
<parameter name="cdr_refclk_select" value="0" />
- <parameter name="set_cdr_refclk_freq" value="644.531250" />
- <parameter name="rx_ppm_detect_threshold" value="100" />
- <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
- <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
- <parameter name="rx_pma_dfe_fixed_taps" value="3" />
- <parameter name="enable_rx_pma_floatingtap" value="0" />
- <parameter name="enable_ports_adaptation" value="0" />
+ <parameter name="channels" value="24" />
+ <parameter name="design_environment" value="NATIVE" />
+ <parameter name="device" value="10AX115U4F45I3SG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="duplex_mode" value="duplex" />
+ <parameter name="enable_hard_reset" value="0" />
+ <parameter name="enable_hip" value="0" />
+ <parameter name="enable_parallel_loopback" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
+ <parameter name="enable_port_pipe_rx_polarity" value="0" />
+ <parameter name="enable_port_rx_enh_bitslip" value="0" />
+ <parameter name="enable_port_rx_enh_blk_lock" value="1" />
+ <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
+ <parameter name="enable_port_rx_enh_crc32_err" value="0" />
+ <parameter name="enable_port_rx_enh_data_valid" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_del" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_empty" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_full" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_insert" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
+ <parameter name="enable_port_rx_enh_frame" value="0" />
+ <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_rx_enh_frame_lock" value="0" />
+ <parameter name="enable_port_rx_enh_highber" value="0" />
+ <parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
+ <parameter name="enable_port_rx_is_lockedtodata" value="1" />
+ <parameter name="enable_port_rx_is_lockedtoref" value="0" />
<parameter name="enable_port_rx_pma_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_clkslip" value="0" />
<parameter name="enable_port_rx_pma_div_clkout" value="0" />
- <parameter name="rx_pma_div_clkout_divider" value="0" />
<parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
- <parameter name="enable_port_rx_pma_clkslip" value="0" />
<parameter name="enable_port_rx_pma_qpipullup" value="0" />
- <parameter name="enable_port_rx_is_lockedtodata" value="1" />
- <parameter name="enable_port_rx_is_lockedtoref" value="0" />
- <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
- <parameter name="enable_ports_rx_manual_ppm" value="0" />
- <parameter name="enable_port_rx_signaldetect" value="0" />
+ <parameter name="enable_port_rx_polinv" value="0" />
<parameter name="enable_port_rx_seriallpbken" value="0" />
- <parameter name="enable_ports_rx_prbs" value="0" />
- <parameter name="std_pcs_pma_width" value="10" />
- <parameter name="std_low_latency_bypass_enable" value="0" />
- <parameter name="enable_hip" value="0" />
- <parameter name="enable_hard_reset" value="0" />
- <parameter name="set_hip_cal_en" value="0" />
- <parameter name="std_tx_pcfifo_mode" value="low_latency" />
- <parameter name="std_rx_pcfifo_mode" value="low_latency" />
- <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
- <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
- <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
+ <parameter name="enable_port_rx_seriallpbken_tx" value="0" />
+ <parameter name="enable_port_rx_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
+ <parameter name="enable_port_rx_std_bitslip" value="0" />
+ <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_rx_std_byterev_ena" value="0" />
<parameter name="enable_port_rx_std_pcfifo_empty" value="0" />
- <parameter name="std_tx_byte_ser_mode" value="Disabled" />
- <parameter name="std_rx_byte_deser_mode" value="Disabled" />
- <parameter name="std_tx_8b10b_enable" value="1" />
- <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
- <parameter name="std_rx_8b10b_enable" value="1" />
- <parameter name="std_rx_rmfifo_mode" value="disabled" />
- <parameter name="std_rx_rmfifo_pattern_n" value="0" />
- <parameter name="std_rx_rmfifo_pattern_p" value="0" />
- <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
<parameter name="enable_port_rx_std_rmfifo_empty" value="0" />
- <parameter name="pcie_rate_match" value="Bypass" />
- <parameter name="std_tx_bitslip_enable" value="0" />
- <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
- <parameter name="std_rx_word_aligner_mode">synchronous state machine</parameter>
- <parameter name="std_rx_word_aligner_pattern_len" value="7" />
- <parameter name="std_rx_word_aligner_pattern" value="124" />
- <parameter name="std_rx_word_aligner_rknumber" value="3" />
- <parameter name="std_rx_word_aligner_renumber" value="3" />
- <parameter name="std_rx_word_aligner_rgnumber" value="3" />
- <parameter name="std_rx_word_aligner_rvnumber" value="0" />
- <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
- <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_signaldetect" value="0" />
<parameter name="enable_port_rx_std_wa_a1a2size" value="0" />
- <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
- <parameter name="enable_port_rx_std_bitslip" value="0" />
- <parameter name="std_tx_bitrev_enable" value="0" />
- <parameter name="std_tx_byterev_enable" value="0" />
- <parameter name="std_tx_polinv_enable" value="0" />
+ <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
+ <parameter name="enable_port_tx_enh_bitslip" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_empty" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_full" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_pempty" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_pfull" value="0" />
+ <parameter name="enable_port_tx_enh_frame" value="0" />
+ <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
+ <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_tx_pma_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_elecidle" value="0" />
+ <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_tx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_tx_pma_rxfound" value="0" />
+ <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
<parameter name="enable_port_tx_polinv" value="0" />
- <parameter name="std_rx_bitrev_enable" value="0" />
- <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
- <parameter name="std_rx_byterev_enable" value="0" />
- <parameter name="enable_port_rx_std_byterev_ena" value="0" />
- <parameter name="std_rx_polinv_enable" value="0" />
- <parameter name="enable_port_rx_polinv" value="0" />
- <parameter name="enable_port_rx_std_signaldetect" value="0" />
- <parameter name="enable_ports_pipe_sw" value="0" />
- <parameter name="enable_ports_pipe_hclk" value="0" />
+ <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
+ <parameter name="enable_ports_adaptation" value="0" />
<parameter name="enable_ports_pipe_g3_analog" value="0" />
+ <parameter name="enable_ports_pipe_hclk" value="0" />
<parameter name="enable_ports_pipe_rx_elecidle" value="0" />
- <parameter name="enable_port_pipe_rx_polarity" value="0" />
+ <parameter name="enable_ports_pipe_sw" value="0" />
+ <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
+ <parameter name="enable_ports_rx_manual_ppm" value="0" />
+ <parameter name="enable_ports_rx_prbs" value="0" />
+ <parameter name="enable_rx_pma_floatingtap" value="0" />
+ <parameter name="enable_simple_interface" value="1" />
+ <parameter name="enable_split_interface" value="0" />
+ <parameter name="enable_transparent_pcs" value="0" />
+ <parameter name="enh_low_latency_enable" value="0" />
<parameter name="enh_pcs_pma_width" value="32" />
<parameter name="enh_pld_pcs_width" value="66" />
- <parameter name="enh_low_latency_enable" value="0" />
- <parameter name="enh_rxtxfifo_double_width" value="0" />
- <parameter name="enh_txfifo_mode" value="Phase compensation" />
- <parameter name="enh_txfifo_pfull" value="11" />
- <parameter name="enh_txfifo_pempty" value="2" />
- <parameter name="enable_port_tx_enh_fifo_full" value="0" />
- <parameter name="enable_port_tx_enh_fifo_pfull" value="0" />
- <parameter name="enable_port_tx_enh_fifo_empty" value="0" />
- <parameter name="enable_port_tx_enh_fifo_pempty" value="0" />
- <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
- <parameter name="enh_rxfifo_mode" value="10GBase-R" />
- <parameter name="enh_rxfifo_pfull" value="23" />
- <parameter name="enh_rxfifo_pempty" value="2" />
- <parameter name="enh_rxfifo_align_del" value="0" />
- <parameter name="enh_rxfifo_control_del" value="0" />
- <parameter name="enable_port_rx_enh_data_valid" value="1" />
- <parameter name="enable_port_rx_enh_fifo_full" value="0" />
- <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
- <parameter name="enable_port_rx_enh_fifo_empty" value="0" />
- <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
- <parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
- <parameter name="enable_port_rx_enh_fifo_del" value="0" />
- <parameter name="enable_port_rx_enh_fifo_insert" value="0" />
- <parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
- <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
- <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
- <parameter name="enh_tx_frmgen_enable" value="0" />
- <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
- <parameter name="enh_tx_frmgen_burst_enable" value="0" />
- <parameter name="enable_port_tx_enh_frame" value="0" />
- <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
- <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
- <parameter name="enh_rx_frmsync_enable" value="0" />
- <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
- <parameter name="enable_port_rx_enh_frame" value="0" />
- <parameter name="enable_port_rx_enh_frame_lock" value="0" />
- <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
- <parameter name="enh_tx_crcgen_enable" value="0" />
- <parameter name="enh_tx_crcerr_enable" value="0" />
- <parameter name="enh_rx_crcchk_enable" value="0" />
- <parameter name="enable_port_rx_enh_crc32_err" value="0" />
- <parameter name="enable_port_rx_enh_highber" value="0" />
- <parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
- <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
- <parameter name="enh_tx_64b66b_enable" value="1" />
<parameter name="enh_rx_64b66b_enable" value="1" />
- <parameter name="enh_tx_sh_err" value="0" />
- <parameter name="enh_tx_scram_enable" value="1" />
- <parameter name="enh_tx_scram_seed" value="288230376151711743" />
+ <parameter name="enh_rx_bitslip_enable" value="0" />
+ <parameter name="enh_rx_blksync_enable" value="1" />
+ <parameter name="enh_rx_crcchk_enable" value="0" />
<parameter name="enh_rx_descram_enable" value="1" />
- <parameter name="enh_tx_dispgen_enable" value="0" />
<parameter name="enh_rx_dispchk_enable" value="0" />
- <parameter name="enh_rx_blksync_enable" value="1" />
- <parameter name="enable_port_rx_enh_blk_lock" value="1" />
- <parameter name="enh_tx_bitslip_enable" value="0" />
- <parameter name="enh_tx_polinv_enable" value="0" />
- <parameter name="enh_rx_bitslip_enable" value="0" />
- <parameter name="enh_rx_polinv_enable" value="0" />
- <parameter name="enable_port_tx_enh_bitslip" value="0" />
- <parameter name="enable_port_rx_enh_bitslip" value="0" />
+ <parameter name="enh_rx_frmsync_enable" value="0" />
+ <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
<parameter name="enh_rx_krfec_err_mark_enable" value="0" />
<parameter name="enh_rx_krfec_err_mark_type" value="10G" />
+ <parameter name="enh_rx_polinv_enable" value="0" />
+ <parameter name="enh_rxfifo_align_del" value="0" />
+ <parameter name="enh_rxfifo_control_del" value="0" />
+ <parameter name="enh_rxfifo_mode" value="10GBase-R" />
+ <parameter name="enh_rxfifo_pempty" value="2" />
+ <parameter name="enh_rxfifo_pfull" value="23" />
+ <parameter name="enh_rxtxfifo_double_width" value="0" />
+ <parameter name="enh_tx_64b66b_enable" value="1" />
+ <parameter name="enh_tx_bitslip_enable" value="0" />
+ <parameter name="enh_tx_crcerr_enable" value="0" />
+ <parameter name="enh_tx_crcgen_enable" value="0" />
+ <parameter name="enh_tx_dispgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_burst_enable" value="0" />
+ <parameter name="enh_tx_frmgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
<parameter name="enh_tx_krfec_burst_err_enable" value="0" />
<parameter name="enh_tx_krfec_burst_err_len" value="1" />
- <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
- <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
- <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
- <parameter name="pcs_direct_width" value="8" />
- <parameter name="generate_docs" value="1" />
+ <parameter name="enh_tx_polinv_enable" value="0" />
+ <parameter name="enh_tx_randomdispbit_enable" value="0" />
+ <parameter name="enh_tx_scram_enable" value="1" />
+ <parameter name="enh_tx_scram_seed" value="288230376151711743" />
+ <parameter name="enh_tx_sh_err" value="0" />
+ <parameter name="enh_txfifo_mode" value="Phase compensation" />
+ <parameter name="enh_txfifo_pempty" value="2" />
+ <parameter name="enh_txfifo_pfull" value="11" />
<parameter name="generate_add_hdl_instance_example" value="0" />
- <parameter name="validation_rule_select" value="" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="number_physical_bonding_clocks" value="1" />
+ <parameter name="pcie_rate_match" value="Bypass" />
+ <parameter name="pcs_direct_width" value="8" />
+ <parameter name="pll_select" value="0" />
+ <parameter name="plls" value="1" />
+ <parameter name="pma_mode" value="basic" />
+ <parameter name="protocol_mode" value="teng_baser_mode" />
+ <parameter name="rapid_validate" value="0" />
<parameter name="rcfg_enable" value="0" />
- <parameter name="rcfg_shared" value="0" />
- <parameter name="rcfg_jtag_enable" value="0" />
- <parameter name="set_embedded_debug_enable" value="0" />
- <parameter name="set_capability_reg_enable" value="0" />
- <parameter name="set_user_identifier" value="0" />
- <parameter name="set_csr_soft_logic_enable" value="0" />
- <parameter name="set_prbs_soft_logic_enable" value="0" />
<parameter name="rcfg_file_prefix">altera_xcvr_native_a10</parameter>
- <parameter name="rcfg_sv_file_enable" value="0" />
<parameter name="rcfg_h_file_enable" value="0" />
+ <parameter name="rcfg_iface_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="0" />
<parameter name="rcfg_mif_file_enable" value="0" />
<parameter name="rcfg_multi_enable" value="0" />
- <parameter name="rcfg_reduced_files_enable" value="0" />
<parameter name="rcfg_profile_cnt" value="2" />
- <parameter name="rcfg_profile_select" value="1" />
<parameter name="rcfg_profile_data0" value="" />
<parameter name="rcfg_profile_data1" value="" />
<parameter name="rcfg_profile_data2" value="" />
@@ -437,8 +396,58 @@
<parameter name="rcfg_profile_data5" value="" />
<parameter name="rcfg_profile_data6" value="" />
<parameter name="rcfg_profile_data7" value="" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_reduced_files_enable" value="0" />
+ <parameter name="rcfg_shared" value="0" />
+ <parameter name="rcfg_sv_file_enable" value="0" />
+ <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
+ <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
+ <parameter name="rx_pma_dfe_fixed_taps" value="3" />
+ <parameter name="rx_pma_div_clkout_divider" value="0" />
+ <parameter name="rx_ppm_detect_threshold" value="100" />
+ <parameter name="set_capability_reg_enable" value="0" />
+ <parameter name="set_cdr_refclk_freq" value="644.531250" />
+ <parameter name="set_csr_soft_logic_enable" value="0" />
+ <parameter name="set_data_rate" value="10312.5" />
+ <parameter name="set_embedded_debug_enable" value="0" />
+ <parameter name="set_enable_calibration" value="0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_pcs_bonding_master" value="Auto" />
+ <parameter name="set_prbs_soft_logic_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="std_low_latency_bypass_enable" value="0" />
+ <parameter name="std_pcs_pma_width" value="10" />
+ <parameter name="std_rx_8b10b_enable" value="1" />
+ <parameter name="std_rx_bitrev_enable" value="0" />
+ <parameter name="std_rx_byte_deser_mode" value="Disabled" />
+ <parameter name="std_rx_byterev_enable" value="0" />
+ <parameter name="std_rx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_rx_polinv_enable" value="0" />
+ <parameter name="std_rx_rmfifo_mode" value="disabled" />
+ <parameter name="std_rx_rmfifo_pattern_n" value="0" />
+ <parameter name="std_rx_rmfifo_pattern_p" value="0" />
+ <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
+ <parameter name="std_rx_word_aligner_mode">synchronous state machine</parameter>
+ <parameter name="std_rx_word_aligner_pattern" value="124" />
+ <parameter name="std_rx_word_aligner_pattern_len" value="7" />
+ <parameter name="std_rx_word_aligner_renumber" value="3" />
+ <parameter name="std_rx_word_aligner_rgnumber" value="3" />
+ <parameter name="std_rx_word_aligner_rknumber" value="3" />
+ <parameter name="std_rx_word_aligner_rvnumber" value="0" />
+ <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
+ <parameter name="std_tx_8b10b_enable" value="1" />
+ <parameter name="std_tx_bitrev_enable" value="0" />
+ <parameter name="std_tx_bitslip_enable" value="0" />
+ <parameter name="std_tx_byte_ser_mode" value="Disabled" />
+ <parameter name="std_tx_byterev_enable" value="0" />
+ <parameter name="std_tx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_tx_polinv_enable" value="0" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="tx_pma_clk_div" value="1" />
+ <parameter name="tx_pma_div_clkout_divider" value="33" />
+ <parameter name="validation_rule_select" value="" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
diff --git a/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_pll.qsys b/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_pll.qsys
index 178dcd50d0..a2264c824a 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_pll.qsys
+++ b/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_pll.qsys
@@ -6,21 +6,31 @@
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
- categories="" />
+ categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element transceiver_pll_inst
{
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2SGES" />
+ <parameter name="device" value="10AX115U4F45I3SG" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
@@ -36,18 +46,25 @@
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
- name="pll_powerdown"
- internal="transceiver_pll_inst.pll_powerdown"
+ name="mcgb_rst"
+ internal="transceiver_pll_inst.mcgb_rst"
type="conduit"
dir="end">
- <port name="pll_powerdown" internal="pll_powerdown" />
+ <port name="mcgb_rst" internal="mcgb_rst" />
</interface>
<interface
- name="pll_refclk0"
- internal="transceiver_pll_inst.pll_refclk0"
- type="clock"
+ name="mcgb_serial_clk"
+ internal="transceiver_pll_inst.mcgb_serial_clk"
+ type="hssi_serial_clock"
+ dir="start">
+ <port name="mcgb_serial_clk" internal="mcgb_serial_clk" />
+ </interface>
+ <interface
+ name="pll_cal_busy"
+ internal="transceiver_pll_inst.pll_cal_busy"
+ type="conduit"
dir="end">
- <port name="pll_refclk0" internal="pll_refclk0" />
+ <port name="pll_cal_busy" internal="pll_cal_busy" />
</interface>
<interface
name="pll_locked"
@@ -57,98 +74,85 @@
<port name="pll_locked" internal="pll_locked" />
</interface>
<interface
- name="pll_cal_busy"
- internal="transceiver_pll_inst.pll_cal_busy"
+ name="pll_powerdown"
+ internal="transceiver_pll_inst.pll_powerdown"
type="conduit"
dir="end">
- <port name="pll_cal_busy" internal="pll_cal_busy" />
+ <port name="pll_powerdown" internal="pll_powerdown" />
</interface>
<interface
- name="mcgb_rst"
- internal="transceiver_pll_inst.mcgb_rst"
- type="conduit"
+ name="pll_refclk0"
+ internal="transceiver_pll_inst.pll_refclk0"
+ type="clock"
dir="end">
- <port name="mcgb_rst" internal="mcgb_rst" />
- </interface>
- <interface
- name="mcgb_serial_clk"
- internal="transceiver_pll_inst.mcgb_serial_clk"
- type="hssi_serial_clock"
- dir="start">
- <port name="mcgb_serial_clk" internal="mcgb_serial_clk" />
+ <port name="pll_refclk0" internal="pll_refclk0" />
</interface>
<module
+ name="transceiver_pll_inst"
kind="altera_xcvr_atx_pll_a10"
- version="14.0"
+ version="14.1"
enabled="1"
- name="transceiver_pll_inst"
autoexport="1">
- <parameter name="rcfg_debug" value="0" />
+ <parameter name="base_device" value="NIGHTFURY5ES" />
+ <parameter name="bw_sel" value="low" />
+ <parameter name="device" value="10AX115U4F45I3SG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="enable_16G_path" value="0" />
+ <parameter name="enable_8G_path" value="0" />
+ <parameter name="enable_bonding_clks" value="0" />
+ <parameter name="enable_cascade_out" value="0" />
+ <parameter name="enable_debug_ports_parameters" value="0" />
+ <parameter name="enable_fb_comp_bonding" value="0" />
+ <parameter name="enable_fractional" value="0" />
+ <parameter name="enable_hfreq_clk" value="1" />
+ <parameter name="enable_hip_cal_done_port" value="0" />
+ <parameter name="enable_mcgb" value="1" />
+ <parameter name="enable_mcgb_pcie_clksw" value="0" />
+ <parameter name="enable_pcie_clk" value="0" />
+ <parameter name="enable_pld_atx_cal_busy_port" value="1" />
+ <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
<parameter name="enable_pll_reconfig" value="0" />
- <parameter name="rcfg_jtag_enable" value="0" />
- <parameter name="set_embedded_debug_enable" value="0" />
- <parameter name="set_capability_reg_enable" value="0" />
- <parameter name="set_user_identifier" value="0" />
- <parameter name="set_csr_soft_logic_enable" value="0" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="mcgb_aux_clkin_cnt" value="0" />
+ <parameter name="mcgb_div" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="pma_width" value="64" />
+ <parameter name="primary_pll_buffer">GX clock output buffer</parameter>
+ <parameter name="prot_mode" value="Basic" />
+ <parameter name="rcfg_debug" value="0" />
<parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
- <parameter name="rcfg_sv_file_enable" value="0" />
<parameter name="rcfg_h_file_enable" value="0" />
- <parameter name="rcfg_txt_file_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="0" />
<parameter name="rcfg_mif_file_enable" value="0" />
<parameter name="rcfg_multi_enable" value="0" />
- <parameter name="rcfg_profile_cnt" value="2" />
- <parameter name="rcfg_profile_select" value="1" />
<parameter name="rcfg_param_vals1" value="" />
<parameter name="rcfg_param_vals2" value="" />
- <parameter name="generate_docs" value="1" />
- <parameter name="generate_add_hdl_instance_example" value="0" />
- <parameter name="device_family" value="Arria 10" />
- <parameter name="device" value="10AX115U3F45I2SGES" />
- <parameter name="test_mode" value="0" />
- <parameter name="enable_pld_atx_cal_busy_port" value="1" />
- <parameter name="enable_debug_ports_parameters" value="0" />
- <parameter name="support_mode" value="user_mode" />
- <parameter name="message_level" value="error" />
- <parameter name="prot_mode" value="Basic" />
- <parameter name="bw_sel" value="low" />
+ <parameter name="rcfg_profile_cnt" value="2" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_sv_file_enable" value="0" />
+ <parameter name="rcfg_txt_file_enable" value="0" />
<parameter name="refclk_cnt" value="1" />
<parameter name="refclk_index" value="0" />
- <parameter name="silicon_rev" value="false" />
- <parameter name="primary_pll_buffer">GX clock output buffer</parameter>
- <parameter name="enable_8G_path" value="0" />
- <parameter name="enable_16G_path" value="0" />
- <parameter name="enable_pcie_clk" value="0" />
- <parameter name="enable_cascade_out" value="0" />
- <parameter name="enable_hip_cal_done_port" value="0" />
- <parameter name="set_hip_cal_en" value="0" />
<parameter name="select_manual_config" value="0" />
- <parameter name="set_output_clock_frequency" value="5156.25" />
- <parameter name="enable_fractional" value="0" />
+ <parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
<parameter name="set_auto_reference_clock_frequency" value="644.53125" />
- <parameter name="set_manual_reference_clock_frequency" value="100.0" />
+ <parameter name="set_capability_reg_enable" value="0" />
+ <parameter name="set_csr_soft_logic_enable" value="0" />
<parameter name="set_fref_clock_frequency" value="100.0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_k_counter" value="1" />
+ <parameter name="set_l_counter" value="2" />
<parameter name="set_m_counter" value="1" />
+ <parameter name="set_manual_reference_clock_frequency" value="100.0" />
+ <parameter name="set_output_clock_frequency" value="5156.25" />
<parameter name="set_ref_clk_div" value="1" />
- <parameter name="set_l_counter" value="2" />
- <parameter name="set_k_counter" value="1" />
- <parameter name="enable_mcgb" value="1" />
- <parameter name="mcgb_div" value="1" />
- <parameter name="enable_hfreq_clk" value="1" />
- <parameter name="enable_mcgb_pcie_clksw" value="0" />
- <parameter name="mcgb_aux_clkin_cnt" value="0" />
- <parameter name="enable_bonding_clks" value="0" />
- <parameter name="enable_fb_comp_bonding" value="0" />
- <parameter name="pma_width" value="64" />
- <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
- <parameter name="AUTO_PLL_REFCLK0_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_PLL_REFCLK1_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_PLL_REFCLK2_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_PLL_REFCLK3_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_PLL_REFCLK4_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_RECONFIG_CLK0_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_RECONFIG_CLK1_CLOCK_RATE" value="-1" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="silicon_rev" value="false" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="test_mode" value="0" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
diff --git a/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_reset_controller.qsys b/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_reset_controller.qsys
index dc0a29763e..77cf8efc4b 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_reset_controller.qsys
+++ b/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_reset_controller.qsys
@@ -6,21 +6,31 @@
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
- categories="" />
+ categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element transceiver_reset_controller_inst
{
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2SGES" />
+ <parameter name="device" value="10AX115U4F45I3SG" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
@@ -43,11 +53,11 @@
<port name="clock" internal="clock" />
</interface>
<interface
- name="reset"
- internal="transceiver_reset_controller_inst.reset"
- type="reset"
+ name="pll_locked"
+ internal="transceiver_reset_controller_inst.pll_locked"
+ type="conduit"
dir="end">
- <port name="reset" internal="reset" />
+ <port name="pll_locked" internal="pll_locked" />
</interface>
<interface
name="pll_powerdown"
@@ -57,110 +67,111 @@
<port name="pll_powerdown" internal="pll_powerdown" />
</interface>
<interface
- name="tx_analogreset"
- internal="transceiver_reset_controller_inst.tx_analogreset"
+ name="pll_select"
+ internal="transceiver_reset_controller_inst.pll_select"
type="conduit"
dir="end">
- <port name="tx_analogreset" internal="tx_analogreset" />
+ <port name="pll_select" internal="pll_select" />
</interface>
<interface
- name="tx_digitalreset"
- internal="transceiver_reset_controller_inst.tx_digitalreset"
- type="conduit"
+ name="reset"
+ internal="transceiver_reset_controller_inst.reset"
+ type="reset"
dir="end">
- <port name="tx_digitalreset" internal="tx_digitalreset" />
+ <port name="reset" internal="reset" />
</interface>
<interface
- name="tx_ready"
- internal="transceiver_reset_controller_inst.tx_ready"
+ name="rx_analogreset"
+ internal="transceiver_reset_controller_inst.rx_analogreset"
type="conduit"
dir="end">
- <port name="tx_ready" internal="tx_ready" />
+ <port name="rx_analogreset" internal="rx_analogreset" />
</interface>
<interface
- name="pll_locked"
- internal="transceiver_reset_controller_inst.pll_locked"
+ name="rx_cal_busy"
+ internal="transceiver_reset_controller_inst.rx_cal_busy"
type="conduit"
dir="end">
- <port name="pll_locked" internal="pll_locked" />
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
</interface>
<interface
- name="pll_select"
- internal="transceiver_reset_controller_inst.pll_select"
+ name="rx_digitalreset"
+ internal="transceiver_reset_controller_inst.rx_digitalreset"
type="conduit"
dir="end">
- <port name="pll_select" internal="pll_select" />
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
</interface>
<interface
- name="tx_cal_busy"
- internal="transceiver_reset_controller_inst.tx_cal_busy"
+ name="rx_is_lockedtodata"
+ internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
type="conduit"
dir="end">
- <port name="tx_cal_busy" internal="tx_cal_busy" />
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
</interface>
<interface
- name="rx_analogreset"
- internal="transceiver_reset_controller_inst.rx_analogreset"
+ name="rx_ready"
+ internal="transceiver_reset_controller_inst.rx_ready"
type="conduit"
dir="end">
- <port name="rx_analogreset" internal="rx_analogreset" />
+ <port name="rx_ready" internal="rx_ready" />
</interface>
<interface
- name="rx_digitalreset"
- internal="transceiver_reset_controller_inst.rx_digitalreset"
+ name="tx_analogreset"
+ internal="transceiver_reset_controller_inst.tx_analogreset"
type="conduit"
dir="end">
- <port name="rx_digitalreset" internal="rx_digitalreset" />
+ <port name="tx_analogreset" internal="tx_analogreset" />
</interface>
<interface
- name="rx_ready"
- internal="transceiver_reset_controller_inst.rx_ready"
+ name="tx_cal_busy"
+ internal="transceiver_reset_controller_inst.tx_cal_busy"
type="conduit"
dir="end">
- <port name="rx_ready" internal="rx_ready" />
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
</interface>
<interface
- name="rx_is_lockedtodata"
- internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
+ name="tx_digitalreset"
+ internal="transceiver_reset_controller_inst.tx_digitalreset"
type="conduit"
dir="end">
- <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
</interface>
<interface
- name="rx_cal_busy"
- internal="transceiver_reset_controller_inst.rx_cal_busy"
+ name="tx_ready"
+ internal="transceiver_reset_controller_inst.tx_ready"
type="conduit"
dir="end">
- <port name="rx_cal_busy" internal="rx_cal_busy" />
+ <port name="tx_ready" internal="tx_ready" />
</interface>
<module
+ name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
- version="14.0"
+ version="14.1"
enabled="1"
- name="transceiver_reset_controller_inst"
autoexport="1">
<parameter name="CHANNELS" value="48" />
<parameter name="PLLS" value="1" />
- <parameter name="SYS_CLK_IN_MHZ" value="200" />
- <parameter name="SYNCHRONIZE_RESET" value="1" />
<parameter name="REDUCED_SIM_TIME" value="1" />
- <parameter name="gui_split_interfaces" value="0" />
- <parameter name="TX_PLL_ENABLE" value="1" />
- <parameter name="T_PLL_POWERDOWN" value="1000" />
+ <parameter name="RX_ENABLE" value="1" />
+ <parameter name="RX_PER_CHANNEL" value="0" />
<parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+ <parameter name="SYNCHRONIZE_RESET" value="1" />
+ <parameter name="SYS_CLK_IN_MHZ" value="200" />
<parameter name="TX_ENABLE" value="1" />
<parameter name="TX_PER_CHANNEL" value="0" />
- <parameter name="gui_tx_auto_reset" value="1" />
- <parameter name="T_TX_DIGITALRESET" value="20" />
+ <parameter name="TX_PLL_ENABLE" value="1" />
<parameter name="T_PLL_LOCK_HYST" value="0" />
- <parameter name="RX_ENABLE" value="1" />
- <parameter name="RX_PER_CHANNEL" value="0" />
- <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="T_PLL_POWERDOWN" value="1000" />
<parameter name="T_RX_ANALOGRESET" value="40" />
<parameter name="T_RX_DIGITALRESET" value="4000" />
- <parameter name="AUTO_CLOCK_CLOCK_RATE" value="-1" />
+ <parameter name="T_TX_DIGITALRESET" value="20" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="gui_pll_cal_busy" value="0" />
+ <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="gui_split_interfaces" value="0" />
+ <parameter name="gui_tx_auto_reset" value="1" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
diff --git a/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_reset_controller_24.qsys b/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_reset_controller_24.qsys
index 6255b47535..b42df57aa1 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_reset_controller_24.qsys
+++ b/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_reset_controller_24.qsys
@@ -11,6 +11,11 @@
{
element $${FILENAME}
{
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
}
element transceiver_reset_controller_inst
{
@@ -23,9 +28,9 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2SGES" />
+ <parameter name="device" value="10AX115U4F45I3SG" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
@@ -48,11 +53,11 @@
<port name="clock" internal="clock" />
</interface>
<interface
- name="reset"
- internal="transceiver_reset_controller_inst.reset"
- type="reset"
+ name="pll_locked"
+ internal="transceiver_reset_controller_inst.pll_locked"
+ type="conduit"
dir="end">
- <port name="reset" internal="reset" />
+ <port name="pll_locked" internal="pll_locked" />
</interface>
<interface
name="pll_powerdown"
@@ -62,110 +67,111 @@
<port name="pll_powerdown" internal="pll_powerdown" />
</interface>
<interface
- name="tx_analogreset"
- internal="transceiver_reset_controller_inst.tx_analogreset"
+ name="pll_select"
+ internal="transceiver_reset_controller_inst.pll_select"
type="conduit"
dir="end">
- <port name="tx_analogreset" internal="tx_analogreset" />
+ <port name="pll_select" internal="pll_select" />
</interface>
<interface
- name="tx_digitalreset"
- internal="transceiver_reset_controller_inst.tx_digitalreset"
- type="conduit"
+ name="reset"
+ internal="transceiver_reset_controller_inst.reset"
+ type="reset"
dir="end">
- <port name="tx_digitalreset" internal="tx_digitalreset" />
+ <port name="reset" internal="reset" />
</interface>
<interface
- name="tx_ready"
- internal="transceiver_reset_controller_inst.tx_ready"
+ name="rx_analogreset"
+ internal="transceiver_reset_controller_inst.rx_analogreset"
type="conduit"
dir="end">
- <port name="tx_ready" internal="tx_ready" />
+ <port name="rx_analogreset" internal="rx_analogreset" />
</interface>
<interface
- name="pll_locked"
- internal="transceiver_reset_controller_inst.pll_locked"
+ name="rx_cal_busy"
+ internal="transceiver_reset_controller_inst.rx_cal_busy"
type="conduit"
dir="end">
- <port name="pll_locked" internal="pll_locked" />
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
</interface>
<interface
- name="pll_select"
- internal="transceiver_reset_controller_inst.pll_select"
+ name="rx_digitalreset"
+ internal="transceiver_reset_controller_inst.rx_digitalreset"
type="conduit"
dir="end">
- <port name="pll_select" internal="pll_select" />
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
</interface>
<interface
- name="tx_cal_busy"
- internal="transceiver_reset_controller_inst.tx_cal_busy"
+ name="rx_is_lockedtodata"
+ internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
type="conduit"
dir="end">
- <port name="tx_cal_busy" internal="tx_cal_busy" />
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
</interface>
<interface
- name="rx_analogreset"
- internal="transceiver_reset_controller_inst.rx_analogreset"
+ name="rx_ready"
+ internal="transceiver_reset_controller_inst.rx_ready"
type="conduit"
dir="end">
- <port name="rx_analogreset" internal="rx_analogreset" />
+ <port name="rx_ready" internal="rx_ready" />
</interface>
<interface
- name="rx_digitalreset"
- internal="transceiver_reset_controller_inst.rx_digitalreset"
+ name="tx_analogreset"
+ internal="transceiver_reset_controller_inst.tx_analogreset"
type="conduit"
dir="end">
- <port name="rx_digitalreset" internal="rx_digitalreset" />
+ <port name="tx_analogreset" internal="tx_analogreset" />
</interface>
<interface
- name="rx_ready"
- internal="transceiver_reset_controller_inst.rx_ready"
+ name="tx_cal_busy"
+ internal="transceiver_reset_controller_inst.tx_cal_busy"
type="conduit"
dir="end">
- <port name="rx_ready" internal="rx_ready" />
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
</interface>
<interface
- name="rx_is_lockedtodata"
- internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
+ name="tx_digitalreset"
+ internal="transceiver_reset_controller_inst.tx_digitalreset"
type="conduit"
dir="end">
- <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
</interface>
<interface
- name="rx_cal_busy"
- internal="transceiver_reset_controller_inst.rx_cal_busy"
+ name="tx_ready"
+ internal="transceiver_reset_controller_inst.tx_ready"
type="conduit"
dir="end">
- <port name="rx_cal_busy" internal="rx_cal_busy" />
+ <port name="tx_ready" internal="tx_ready" />
</interface>
<module
+ name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
- version="14.0"
+ version="14.1"
enabled="1"
- name="transceiver_reset_controller_inst"
autoexport="1">
<parameter name="CHANNELS" value="24" />
<parameter name="PLLS" value="1" />
- <parameter name="SYS_CLK_IN_MHZ" value="200" />
- <parameter name="SYNCHRONIZE_RESET" value="1" />
<parameter name="REDUCED_SIM_TIME" value="1" />
- <parameter name="gui_split_interfaces" value="0" />
- <parameter name="TX_PLL_ENABLE" value="1" />
- <parameter name="T_PLL_POWERDOWN" value="1000" />
+ <parameter name="RX_ENABLE" value="1" />
+ <parameter name="RX_PER_CHANNEL" value="0" />
<parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+ <parameter name="SYNCHRONIZE_RESET" value="1" />
+ <parameter name="SYS_CLK_IN_MHZ" value="200" />
<parameter name="TX_ENABLE" value="1" />
<parameter name="TX_PER_CHANNEL" value="0" />
- <parameter name="gui_tx_auto_reset" value="1" />
- <parameter name="T_TX_DIGITALRESET" value="20" />
+ <parameter name="TX_PLL_ENABLE" value="1" />
<parameter name="T_PLL_LOCK_HYST" value="0" />
- <parameter name="RX_ENABLE" value="1" />
- <parameter name="RX_PER_CHANNEL" value="0" />
- <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="T_PLL_POWERDOWN" value="1000" />
<parameter name="T_RX_ANALOGRESET" value="40" />
<parameter name="T_RX_DIGITALRESET" value="4000" />
- <parameter name="AUTO_CLOCK_CLOCK_RATE" value="0" />
+ <parameter name="T_TX_DIGITALRESET" value="20" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="gui_pll_cal_busy" value="0" />
+ <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="gui_split_interfaces" value="0" />
+ <parameter name="gui_tx_auto_reset" value="1" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
diff --git a/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd b/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
index ace0c1dd50..052ffc1fac 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
+++ b/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
@@ -50,6 +50,7 @@ ENTITY unb2_pinning IS
-- SO-DIMM DDR4 Memory Bank i2c (common)
MB_SCL : inout std_logic;
MB_SDA : inout std_logic;
+ MB_EVENT : in std_logic;
-- SO-DIMM DDR4 Memory Bank I
MB_I_RZQ : in STD_LOGIC;
MB_I_REF_CLK : in STD_LOGIC; -- External reference clock
@@ -363,7 +364,7 @@ architecture str of unb2_pinning is
eth_tse_1_pcs_ref_clk_clock_connection_clk : in std_logic := 'X'; -- clk
eth_tse_1_serial_connection_rxp_0 : in std_logic := 'X'; -- rxp
eth_tse_1_serial_connection_txp_0 : out std_logic; -- txp
- pio_0_external_connection_export : in std_logic_vector(10 downto 0) := (others => 'X') -- export
+ pio_0_external_connection_export : in std_logic_vector(11 downto 0) := (others => 'X') -- export
);
end component unb2_pinning_qsys;
@@ -469,7 +470,7 @@ architecture str of unb2_pinning is
signal testio_out : std_logic_vector(5 downto 0);
signal qsfp_led_out : std_logic_vector(11 downto 0);
signal bck_err_out : std_logic_vector(2 downto 0);
- signal ver_id_pmbusalert : std_logic_vector(10 downto 0);
+ signal ver_id_pmbusalert : std_logic_vector(11 downto 0);
begin
@@ -954,7 +955,6 @@ begin
bck_err_out(1) <= bck_err_in(0);
bck_err_out(0) <= bck_err_in(2);
-
- ver_id_pmbusalert <= version & id & pmbus_alert;
+ ver_id_pmbusalert <= version & id & pmbus_alert & mb_event;
end str;
--
GitLab