diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip
index 25835ed8fbfe521845560e0023eabadc1b251454..39357e6ed8b9e7c91febbd9e1554e1fbf3c7caa7 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip
@@ -1081,7 +1081,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>19</ipxact:right>
+ <ipxact:right>23</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -2237,7 +2237,7 @@
<ipxact:parameter parameterId="dataAddrWidth" type="int">
<ipxact:name>dataAddrWidth</ipxact:name>
<ipxact:displayName>dataAddrWidth</ipxact:displayName>
- <ipxact:value>20</ipxact:value>
+ <ipxact:value>24</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="tightlyCoupledDataMaster0AddrWidth" type="int">
<ipxact:name>tightlyCoupledDataMaster0AddrWidth</ipxact:name>
@@ -2302,7 +2302,7 @@
<ipxact:parameter parameterId="dataSlaveMapParam" type="string">
<ipxact:name>dataSlaveMapParam</ipxact:name>
<ipxact:displayName>dataSlaveMapParam</ipxact:displayName>
- <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='jesd204b.mem' start='0x40000' end='0x44000' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x48000' end='0x48400' datawidth='32' /><slave name='reg_wg.mem' start='0x4C000' end='0x4C100' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x4C100' end='0x4C110' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x4C110' end='0x4C118' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x4C120' end='0x4C140' datawidth='32' /><slave name='ram_wg.mem' start='0x50000' end='0x60000' datawidth='32' /><slave name='reg_diag_data_buffer_jesd.mem' start='0x60000' end='0x64000' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x64000' end='0x68000' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x68000' end='0x68100' datawidth='32' /><slave name='ram_aduh_monitor.mem' start='0x70000' end='0x74000' datawidth='32' /><slave name='ram_diag_data_buffer_jesd.mem' start='0x80000' end='0xC0000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0xC0000' end='0x100000' datawidth='32' /></address-map></ipxact:value>
+ <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='jesd204b.mem' start='0x40000' end='0x44000' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x48000' end='0x48400' datawidth='32' /><slave name='reg_wg.mem' start='0x4C000' end='0x4C100' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x4C100' end='0x4C110' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x4C110' end='0x4C118' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x4C120' end='0x4C140' datawidth='32' /><slave name='ram_wg.mem' start='0x50000' end='0x60000' datawidth='32' /><slave name='reg_diag_data_buffer_jesd.mem' start='0x60000' end='0x64000' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x64000' end='0x68000' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x68000' end='0x68100' datawidth='32' /><slave name='ram_aduh_monitor.mem' start='0x70000' end='0x74000' datawidth='32' /><slave name='ram_diag_data_buffer_jesd.mem' start='0x80000' end='0xC0000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="tightlyCoupledDataMaster0MapParam" type="string">
<ipxact:name>tightlyCoupledDataMaster0MapParam</ipxact:name>
@@ -2452,7 +2452,7 @@
</ipxact:parameter>
<ipxact:parameter parameterId="embeddedsw.CMacro.DATA_ADDR_WIDTH" type="string">
<ipxact:name>embeddedsw.CMacro.DATA_ADDR_WIDTH</ipxact:name>
- <ipxact:value>20</ipxact:value>
+ <ipxact:value>24</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="embeddedsw.CMacro.DCACHE_LINE_SIZE" type="string">
<ipxact:name>embeddedsw.CMacro.DCACHE_LINE_SIZE</ipxact:name>
@@ -2663,6 +2663,9 @@
type = "String";
}
}
+ element qsys_lofar2_unb2b_adc_cpu_0
+ {
+ }
}
</ipxact:value>
</ipxact:parameter>
@@ -2756,7 +2759,7 @@
<name>d_address</name>
<role>address</role>
<direction>Output</direction>
- <width>20</width>
+ <width>24</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -3589,11 +3592,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x40000' end='0x44000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x48000' end='0x48400' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x4C000' end='0x4C100' datawidth='32' /&gt;&lt;slave name='reg_bsn_source.mem' start='0x4C100' end='0x4C110' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x4C110' end='0x4C118' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x4C120' end='0x4C140' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0x50000' end='0x60000' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_jesd.mem' start='0x60000' end='0x64000' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x64000' end='0x68000' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x68000' end='0x68100' datawidth='32' /&gt;&lt;slave name='ram_aduh_monitor.mem' start='0x70000' end='0x74000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_jesd.mem' start='0x80000' end='0xC0000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0xC0000' end='0x100000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x40000' end='0x44000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x48000' end='0x48400' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x4C000' end='0x4C100' datawidth='32' /&gt;&lt;slave name='reg_bsn_source.mem' start='0x4C100' end='0x4C110' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x4C110' end='0x4C118' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x4C120' end='0x4C140' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0x50000' end='0x60000' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_jesd.mem' start='0x60000' end='0x64000' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x64000' end='0x68000' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x68000' end='0x68100' datawidth='32' /&gt;&lt;slave name='ram_aduh_monitor.mem' start='0x70000' end='0x74000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_jesd.mem' start='0x80000' end='0xC0000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>20</value>
+ <value>24</value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.ip
index c8cfd35db3c11359524f5f011335176b0a7a17d0..a5e46ab46028fc70395566fd59141e38610dc286 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.ip
@@ -2,7 +2,7 @@
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
<ipxact:library>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn</ipxact:library>
- <ipxact:name>qsys_lofar2_unb2b_adc_ram_wg</ipxact:name>
+ <ipxact:name>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -139,7 +139,7 @@
<ipxact:parameter parameterId="addressSpan" type="string">
<ipxact:name>addressSpan</ipxact:name>
<ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>262144</ipxact:value>
+ <ipxact:value>8388608</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="addressUnits" type="string">
<ipxact:name>addressUnits</ipxact:name>
@@ -667,7 +667,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>15</ipxact:right>
+ <ipxact:right>20</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -773,7 +773,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>15</ipxact:right>
+ <ipxact:right>20</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -860,7 +860,7 @@
<ipxact:parameter parameterId="g_adr_w" type="int">
<ipxact:name>g_adr_w</ipxact:name>
<ipxact:displayName>g_adr_w</ipxact:displayName>
- <ipxact:value>16</ipxact:value>
+ <ipxact:value>21</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="g_dat_w" type="int">
<ipxact:name>g_dat_w</ipxact:name>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_lofar2_unb2b_adc_ram_wg
+ element qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn
{
}
}
@@ -997,7 +997,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>16</width>
+ <width>21</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1066,7 +1066,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>262144</value>
+ <value>8388608</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1295,7 +1295,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>16</width>
+ <width>21</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1462,11 +1462,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x800000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>18</value>
+ <value>23</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc.sdc b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc.sdc
index a3fe57ee4e31219d1b1f7667b66899497d909b74..c8a94bcfde100798fd4e56e1050bac3fa577c2f8 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc.sdc
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc.sdc
@@ -95,3 +95,7 @@ set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*c
set_false_path -from [get_clocks {*core_pll|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*core_pll|frame_clk}]
set_false_path -from [get_clocks {*core_pll|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+
+# Constraint on the SYSREF input pin
+# Adjust this to account for any board trace difference between SYSREF and REFCLK
+set_input_delay -clock BCK_REF_CLK 0 [get_ports JESD204B_SYSREF]
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/qsys_lofar2_unb2b_adc.qsys b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/qsys_lofar2_unb2b_adc.qsys
index e60b7a1addebff53a70392b8f86cdc5a0ec10b58..4c14db56aa5e96f27af5b705fd9df43419bef9f3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/qsys_lofar2_unb2b_adc.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/qsys_lofar2_unb2b_adc.qsys
@@ -213,7 +213,7 @@
{
datum baseAddress
{
- value = "786432";
+ value = "8388608";
type = "String";
}
}
@@ -5156,7 +5156,7 @@
<name>d_address</name>
<role>address</role>
<direction>Output</direction>
- <width>20</width>
+ <width>24</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -6358,7 +6358,7 @@
<name>d_address</name>
<role>address</role>
<direction>Output</direction>
- <width>20</width>
+ <width>24</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -7193,7 +7193,7 @@
</entry>
<entry>
<key>embeddedsw.CMacro.DATA_ADDR_WIDTH</key>
- <value>20</value>
+ <value>24</value>
</entry>
<entry>
<key>embeddedsw.CMacro.DCACHE_LINE_SIZE</key>
@@ -8498,7 +8498,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jesd204b.ip</parameter>
+ <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jesd204b.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -14893,7 +14893,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_aduh_monitor.ip</parameter>
+ <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_aduh_monitor.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -14916,7 +14916,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>16</width>
+ <width>21</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14980,7 +14980,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>16</width>
+ <width>21</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15049,7 +15049,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>262144</value>
+ <value>8388608</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -15455,11 +15455,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x800000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>18</value>
+ <value>23</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -15488,17 +15488,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>21</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -15507,28 +15507,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -15541,11 +15540,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -15559,7 +15560,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>16</width>
+ <width>21</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15598,17 +15599,21 @@
</ports>
<assignments>
<assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>false</value>
+ <value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>false</value>
+ <value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
- <value>false</value>
+ <value>0</value>
</entry>
</assignmentValueMap>
</assignments>
@@ -15624,7 +15629,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>262144</value>
+ <value>8388608</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -15648,6 +15653,7 @@
</entry>
<entry>
<key>bridgedAddressOffset</key>
+ <value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
@@ -15780,12 +15786,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -15812,17 +15818,17 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -15844,17 +15850,17 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
- <width>16</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -15876,14 +15882,14 @@
</parameters>
</interface>
<interface>
- <name>write</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -15895,30 +15901,31 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>writedata</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -15928,24 +15935,22 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -15972,14 +15977,14 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -16029,7 +16034,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.ip</parameter>
+ <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -16624,17 +16629,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>16</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -16643,28 +16648,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -16677,11 +16681,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -16734,17 +16740,21 @@
</ports>
<assignments>
<assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>false</value>
+ <value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>false</value>
+ <value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
- <value>false</value>
+ <value>0</value>
</entry>
</assignmentValueMap>
</assignments>
@@ -16784,6 +16794,7 @@
</entry>
<entry>
<key>bridgedAddressOffset</key>
+ <value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
@@ -16916,12 +16927,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -16948,17 +16959,17 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -16980,17 +16991,17 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
- <width>16</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -17012,14 +17023,14 @@
</parameters>
</interface>
<interface>
- <name>write</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -17031,30 +17042,31 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>writedata</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -17064,24 +17076,22 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -17108,14 +17118,14 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -17165,7 +17175,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.ip</parameter>
+ <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -18306,7 +18316,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg.ip</parameter>
+ <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -19447,7 +19457,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_aduh_monitor.ip</parameter>
+ <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_aduh_monitor.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -20588,7 +20598,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_monitor_input.ip</parameter>
+ <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_monitor_input.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -21729,7 +21739,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_scheduler.ip</parameter>
+ <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_scheduler.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -22870,7 +22880,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_source.ip</parameter>
+ <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_source.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -24011,7 +24021,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buffer_bsn.ip</parameter>
+ <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buffer_bsn.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -24606,17 +24616,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>12</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -24625,28 +24635,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -24659,11 +24668,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -24716,17 +24727,21 @@
</ports>
<assignments>
<assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>false</value>
+ <value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>false</value>
+ <value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
- <value>false</value>
+ <value>0</value>
</entry>
</assignmentValueMap>
</assignments>
@@ -24766,6 +24781,7 @@
</entry>
<entry>
<key>bridgedAddressOffset</key>
+ <value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
@@ -24898,12 +24914,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -24930,17 +24946,17 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -24962,17 +24978,17 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
- <width>12</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -24994,14 +25010,14 @@
</parameters>
</interface>
<interface>
- <name>write</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -25013,30 +25029,31 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>writedata</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -25046,24 +25063,22 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -25090,14 +25105,14 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -25147,7 +25162,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.ip</parameter>
+ <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -26288,7 +26303,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_shiftram.ip</parameter>
+ <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_shiftram.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -39980,7 +39995,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg.ip</parameter>
+ <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -42897,7 +42912,7 @@
start="cpu_0.data_master"
end="ram_diag_data_buffer_bsn.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000c0000" />
+ <parameter name="baseAddress" value="0x00800000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
index 79405773c74135b778f5a10be375ba70bc57d76a..c1ae8cd5e19365be69d56c49c43ffc369504024a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
@@ -440,7 +440,7 @@ BEGIN
ram_diag_data_buf_bsn_clk_export => OPEN,
ram_diag_data_buf_bsn_reset_export => OPEN,
- ram_diag_data_buf_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(16-1 DOWNTO 0),
+ ram_diag_data_buf_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(21-1 DOWNTO 0),
ram_diag_data_buf_bsn_write_export => ram_diag_data_buf_bsn_mosi.wr,
ram_diag_data_buf_bsn_writedata_export => ram_diag_data_buf_bsn_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_diag_data_buf_bsn_read_export => ram_diag_data_buf_bsn_mosi.rd,
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
index 2894ca55e4d73e521d026f154b371d1808c9d0d5..0854467d066cef308f0a5304497c1be879ae39ca 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
@@ -41,7 +41,7 @@ USE work.lofar2_unb2b_adc_pkg.ALL;
ENTITY node_adc_input_and_timing IS
GENERIC (
g_technology : NATURAL := c_tech_arria10_e1sg;
- g_buf_nof_data : NATURAL := 8192; --1024;
+ g_buf_nof_data : NATURAL := 131072; --8192; --1024;
g_nof_streams : NATURAL := 12;
g_nof_sync_n : NATURAL := 4; -- Three ADCs per RCU share a sync
g_aduh_buffer_nof_symbols : NATURAL := 512; -- Default 512
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
index be030d7be84c9b58540aa735df6ea56de91cb8a0..a2b690117989b8108e02c4e6d774048cb43393fb 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
@@ -228,7 +228,7 @@ PACKAGE qsys_lofar2_unb2b_adc_pkg IS
reg_aduh_monitor_reset_export : out std_logic; -- export
reg_aduh_monitor_write_export : out std_logic; -- export
reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_bsn_address_export : out std_logic_vector(15 downto 0); -- export
+ ram_diag_data_buf_bsn_address_export : out std_logic_vector(20 downto 0); -- export
ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
ram_diag_data_buf_bsn_read_export : out std_logic; -- export
ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/quartus/TOPLEVEL_FPGA.qsf b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/quartus/TOPLEVEL_FPGA.qsf
index 905d4998f3eebd104b29da9f2f7afe6ea5efaf79..c975ed5cf123c94314fdccf1ecfe66b6e0ce0020 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/quartus/TOPLEVEL_FPGA.qsf
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/quartus/TOPLEVEL_FPGA.qsf
@@ -80,6 +80,7 @@ set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
set_location_assignment PIN_K15 -to CLK
set_location_assignment PIN_J15 -to "CLK(n)"
set_location_assignment PIN_N12 -to ETH_CLK
+set_location_assignment PIN_M12 -to ETH_CLK1
set_location_assignment PIN_K14 -to PPS
set_location_assignment PIN_J14 -to "PPS(n)"
set_location_assignment PIN_Y36 -to SA_CLK
@@ -209,6 +210,7 @@ set_location_assignment PIN_L28 -to MB_II_OU.reset_n
set_location_assignment PIN_J27 -to MB_II_IN.oct_rzqin
set_location_assignment PIN_F27 -to MB_II_OU.a[14]
set_instance_assignment -name IO_STANDARD "1.8 V" -to ETH_CLK
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ETH_CLK1
set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[0]
set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGIN[0](n)"
set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[1]
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/quartus/TOPLEVEL_FPGA_JESD.qsf b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/quartus/TOPLEVEL_FPGA_JESD.qsf
index 8f88388e0f3d8635bc242444f0b1314ada914447..b116b47f6a0b58174acd72fe8414ddf21dc77f17 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/quartus/TOPLEVEL_FPGA_JESD.qsf
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning/quartus/TOPLEVEL_FPGA_JESD.qsf
@@ -80,6 +80,9 @@ set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
set_location_assignment PIN_K15 -to CLK
set_location_assignment PIN_J15 -to "CLK(n)"
set_location_assignment PIN_N12 -to ETH_CLK
+#set_location_assignment PIN_M12 -to ETH_CLK1
+#set_location_assignment PIN_K15 -to ETH_CLK1
+set_location_assignment PIN_AK33 -to ETH_CLK1
set_location_assignment PIN_K14 -to PPS
set_location_assignment PIN_J14 -to "PPS(n)"
set_location_assignment PIN_Y36 -to SA_CLK
@@ -209,6 +212,7 @@ set_location_assignment PIN_L28 -to MB_II_OU.reset_n
set_location_assignment PIN_J27 -to MB_II_IN.oct_rzqin
set_location_assignment PIN_F27 -to MB_II_OU.a[14]
set_instance_assignment -name IO_STANDARD "1.8 V" -to ETH_CLK
+set_instance_assignment -name IO_STANDARD "1.8 V" -to ETH_CLK1
set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[0]
set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGIN[0](n)"
set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[1]
@@ -272,12 +276,16 @@ set_location_assignment PIN_BB30 -to WDI
set_location_assignment PIN_AT31 -to QSFP_RST
set_location_assignment PIN_K12 -to ETH_SGIN[0]
set_location_assignment PIN_J12 -to "ETH_SGIN[0](n)"
-set_location_assignment PIN_M16 -to ETH_SGIN[1]
-set_location_assignment PIN_L16 -to "ETH_SGIN[1](n)"
+#set_location_assignment PIN_M16 -to ETH_SGIN[1]
+#set_location_assignment PIN_L16 -to "ETH_SGIN[1](n)"
+set_location_assignment PIN_AF33 -to ETH_SGIN[1]
+set_location_assignment PIN_AE33 -to "ETH_SGIN[1](n)"
set_location_assignment PIN_H13 -to ETH_SGOUT[0]
set_location_assignment PIN_H12 -to "ETH_SGOUT[0](n)"
-set_location_assignment PIN_L15 -to ETH_SGOUT[1]
-set_location_assignment PIN_M15 -to "ETH_SGOUT[1](n)"
+#set_location_assignment PIN_L15 -to ETH_SGOUT[1]
+#set_location_assignment PIN_M15 -to "ETH_SGOUT[1](n)"
+set_location_assignment PIN_AW31 -to ETH_SGOUT[1]
+set_location_assignment PIN_AV31 -to "ETH_SGOUT[1](n)"
set_instance_assignment -name IO_STANDARD LVDS -to PPS
set_instance_assignment -name IO_STANDARD LVDS -to "PPS(n)"
set_location_assignment PIN_B9 -to BCK_RX[0]
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning_jesd204b/unb2c_test_pinning_jesd204b.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning_jesd204b/unb2c_test_pinning_jesd204b.vhd
index efb4a7eda28b0d092d713c7e94cbdcbfca513576..325e548cf24289c9ba7fbad692ac5a1cd4e80116 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning_jesd204b/unb2c_test_pinning_jesd204b.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_pinning_jesd204b/unb2c_test_pinning_jesd204b.vhd
@@ -59,6 +59,7 @@ ENTITY unb2c_test_pinning_jesd204b IS
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC;
+ ETH_CLK1 : IN STD_LOGIC;
ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
@@ -160,6 +161,7 @@ BEGIN
-- 1GbE Control Interface
ETH_clk => ETH_clk,
+ ETH_clk1 => ETH_clk1,
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT,
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
index c1d4ad2e0dd483e068fc1d4f3aea48b45a6e51d8..b194971094051ed4aa5e7ffd761e589ee4dd316b 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
@@ -68,7 +68,8 @@ ENTITY unb2c_test IS
SENS_SD : INOUT STD_LOGIC;
-- 1GbE Control Interface
- ETH_CLK : IN STD_LOGIC;
+ ETH_CLK : IN STD_LOGIC := '0';
+ ETH_CLK1 : IN STD_LOGIC;
ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
@@ -468,7 +469,7 @@ BEGIN
g_revision_id => g_revision_id,
g_fw_version => c_fw_version,
g_mm_clk_freq => sel_a_b(g_sim,c_unb2c_board_mm_clk_freq_25M,c_unb2c_board_mm_clk_freq_125M),
- g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
+ g_eth_clk_freq => c_unb2c_board_eth_clk_freq_25M, --c_unb2c_board_eth_clk_freq_125M,
g_aux => c_unb2c_board_aux,
g_udp_offload => c_use_1GbE_I_UDP,
g_udp_offload_nof_streams => c_nof_streams_1GbE_UDP,
@@ -855,8 +856,8 @@ BEGIN
END GENERATE;
-- Instantiate a second 1G Eth to check pinning
- --gen_eth_II: IF c_use_1GbE_II=TRUE GENERATE
- gen_eth_II: IF FALSE GENERATE
+ gen_eth_II: IF c_use_1GbE_II=TRUE GENERATE
+ --gen_eth_II: IF FALSE GENERATE
u_eth : ENTITY eth_lib.eth
GENERIC MAP (
@@ -869,8 +870,8 @@ BEGIN
-- Clocks and reset
mm_rst => mm_rst, -- use reset from QSYS
mm_clk => mm_clk, -- use mm_clk direct
- eth_clk => xo_ethclk, -- 125 MHz clock
--- eth_clk => ETH_CLK, -- try direct connection to the pin
+-- eth_clk => xo_ethclk, -- 125 MHz clock
+ eth_clk => ETH_CLK1, -- try direct connection to the pin
st_rst => dp_rst,
st_clk => dp_clk,
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
index 2d2db8edf768156d7d85d81ccb6fb2a4a96b6c82..2289cd9135b573f87772681d0644a82eb03dafe1 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
@@ -123,6 +123,7 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
SIGNAL jesd204b_rx_somf_arr : STD_LOGIC_VECTOR(c_jesd204b_rx_somf_w*g_nof_streams-1 DOWNTO 0);
SIGNAL jesd204b_sync_n_internal_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ SIGNAL jesd204b_sync_n_combined_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-- Component declarations for the IP blocks
@@ -372,17 +373,19 @@ BEGIN
END GENERATE;
-----------------------------------------------------------------------------
- -- Reclock sysref
+ -- Reclock sysref and the sync_n output
-----------------------------------------------------------------------------
p_reclocksysref : PROCESS (rxlink_clk, core_pll_locked)
BEGIN
IF core_pll_locked = '0' THEN
jesd204b_sysref_1 <= '0';
jesd204b_sysref_2 <= '0';
+ jesd204b_sync_n_arr <= (others => '0');
ELSE
IF rising_edge(rxlink_clk) THEN
jesd204b_sysref_1 <= jesd204b_sysref;
jesd204b_sysref_2 <= jesd204b_sysref_1;
+ jesd204b_sync_n_arr <= jesd204b_sync_n_combined_arr;
END IF;
END IF;
END PROCESS;
@@ -453,7 +456,7 @@ BEGIN
-- Group the SYNC_N outputs
-----------------------------------------------------------------------------
gen_group_sync_n : FOR i IN 0 TO g_nof_sync_n-1 GENERATE
- jesd204b_sync_n_arr(i) <= vector_and(jesd204b_sync_n_internal_arr(c_nof_sync_n_per_group*i+c_nof_sync_n_per_group-1 downto c_nof_sync_n_per_group*i));
+ jesd204b_sync_n_combined_arr(i) <= vector_and(jesd204b_sync_n_internal_arr(c_nof_sync_n_per_group*i+c_nof_sync_n_per_group-1 downto c_nof_sync_n_per_group*i));
END GENERATE;
-----------------------------------------------------------------------------
diff --git a/libraries/technology/jesd204b/hdllib.cfg b/libraries/technology/jesd204b/hdllib.cfg
index 26c30b19cb5fbf3936010a78cb3a2aba00046c15..7dba91f1aa18f80e256c455e29b2a01cc87c84d7 100644
--- a/libraries/technology/jesd204b/hdllib.cfg
+++ b/libraries/technology/jesd204b/hdllib.cfg
@@ -21,7 +21,7 @@ test_bench_files =
# tb_tb_tech_jesd204b.vhd
regression_test_vhdl =
-# tb_tb_tech_jesd204b.vhd
+ tb_tech_jesd204b.vhd
[modelsim_project_file]
diff --git a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
index adcdb65460580bd456dccd86843410a7f9d60e8c..a062d9626f82f51dab852006c22609cafb8bb1b9 100644
--- a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
+++ b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
@@ -23,6 +23,7 @@
-- Description:
-- Includes 3 JESD transmit sources to test multichannel syncronization
-- Relative delays between TX and RX channels can be varied by editing c_delay_*
+-- Used default technology e1sg
-- ToDo: Make a tb_tb to run several test cases automatically
-- Usage:
-- Load sim # check that design can load in vsim
@@ -448,8 +449,9 @@ BEGIN
-- Simulation end
------------------------------------------------------------------------------
--sim_done <= '0', '1' AFTER 1 us;
- sim_done <= '0';
+ sim_done <= '1' when rx_sosi_arr(0).valid = '1' and rx_sosi_arr(1).valid = '1' and rx_sosi_arr(2).valid = '1' else '0';
+ tb_end <= '0', '1' after 110 us;
- proc_common_stop_simulation(TRUE, jesd204b_sampclk, sim_done, tb_end);
+ proc_common_stop_simulation(TRUE, 1000, jesd204b_sampclk, sim_done, tb_end);
END tb;