diff --git a/applications/lofar2/libraries/ddrctrl/hdllib.cfg b/applications/lofar2/libraries/ddrctrl/hdllib.cfg
index ba8457f096cdfc6b3e1bbefff4d1fedc16d69766..53fe5f5958c0cf866e1870d4ed11367b023c7df5 100644
--- a/applications/lofar2/libraries/ddrctrl/hdllib.cfg
+++ b/applications/lofar2/libraries/ddrctrl/hdllib.cfg
@@ -9,6 +9,7 @@ synth_files =
src/vhdl/ddrctrl_input_pack.vhd
src/vhdl/ddrctrl_input_repack.vhd
src/vhdl/ddrctrl_input.vhd
+ src/vhdl/ddrctrl_controller.vhd
src/vhdl/ddrctrl.vhd
test_bench_files =
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index 30daea0b17a4df52370db092ee7762949c0de007..e24344df83a4fc634179dea7d83932802c79b93f 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -59,8 +59,7 @@ ENTITY ddrctrl IS
mm_rst : IN STD_LOGIC := '0';
in_sosi_arr : IN t_dp_sosi_arr; -- input data
wr_not_rd : IN STD_LOGIC := '0';
- out_of : OUT NATURAL; -- amount of internal overflow this output
- out_adr : OUT NATURAL;
+ stop_in : IN STD_LOGIC := '0';
term_ctrl_out : OUT t_tech_ddr3_phy_terminationcontrol;
@@ -87,12 +86,14 @@ ARCHITECTURE str OF ddrctrl IS
CONSTANT c_rd_fifo_depth : NATURAL := 256; -- defined at DDR side of the FIFO, >=16 AND > max number of rd burst sizes (so > c_rd_fifo_af_margin), default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
-- signals for connecting the components
- SIGNAL adr : NATURAL := 0;
SIGNAL ctrl_clk : STD_LOGIC;
SIGNAL ctrl_rst : STD_LOGIC;
+ SIGNAL out_of : NATURAL := 0;
+ SIGNAL out_sosi : t_dp_sosi := c_dp_sosi_init;
+ SIGNAL out_adr : NATURAL := 0;
+ SIGNAL dvr_mosi : t_mem_ctlr_mosi := c_mem_ctlr_mosi_rst;
SIGNAL wr_sosi : t_dp_sosi := c_dp_sosi_init;
SIGNAL rd_siso : t_dp_siso := c_dp_siso_rst;
- SIGNAL dvr_mosi : t_mem_ctlr_mosi;
BEGIN
@@ -111,8 +112,8 @@ BEGIN
rst => rst,
in_sosi_arr => in_sosi_arr,
out_of => out_of,
- out_sosi => wr_sosi,
- out_adr => adr
+ out_sosi => out_sosi,
+ out_adr => out_adr
);
-- functions as a fifo buffer for input data into the sdram stick. also manages input to sdram stick.
@@ -189,4 +190,24 @@ BEGIN
phy4_ou => phy4_ou
);
+ -- controller of ddrctrl
+ u_ddrctrl_controller : ENTITY work.ddrctrl_controller
+ GENERIC MAP(
+ g_tech_ddr => g_tech_ddr
+ )
+ PORT MAP(
+ clk => clk,
+ rst => rst,
+
+ out_of => out_of,
+ out_sosi => out_sosi,
+ out_adr => out_adr,
+
+ dvr_mosi => dvr_mosi,
+ wr_sosi => wr_sosi,
+ rd_siso => rd_siso,
+
+ stop_in => stop_in
+ );
+
END str;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index b517bdf4d2029d3ac159b409c4e708c054ac1f8f..4a86d593bc4239b8c62c08551e5fcae927eead35 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -27,15 +27,18 @@
-- https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
--
-LIBRARY IEEE, dp_lib;
+LIBRARY IEEE, dp_lib, common_lib, tech_ddr_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE dp_lib.dp_stream_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY ddrctrl_controller IS
GENERIC (
- g_max_adr : NATURAL;
+ g_tech_ddr : t_c_tech_ddr
);
PORT (
clk : IN STD_LOGIC;
@@ -52,7 +55,7 @@ ENTITY ddrctrl_controller IS
rd_siso : OUT t_dp_siso;
-- ddrctrl
- stop_in : IN STD_LOGIC;
+ stop_in : IN STD_LOGIC
);
END ddrctrl_controller;
@@ -69,13 +72,20 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
-- record for readability
TYPE t_reg IS RECORD
- state : t_state; -- the state the process is currently in;
+ -- state of program
+ state : t_state;
+
+ -- signals
+ stop_adr : NATURAL;
+ stopped : STD_LOGIC;
+
+ -- output
dvr_mosi : t_mem_ctlr_mosi;
wr_sosi : t_dp_sosi;
rd_siso : t_dp_siso;
END RECORD;
- CONSTANT c_t_reg_init : t_reg := (RESET, c_mem_ctlr_mosi_init, c_dp_sosi_init, c_dp_siso_rst);
+ CONSTANT c_t_reg_init : t_reg := (RESET, 0, '0', c_mem_ctlr_mosi_rst, c_dp_sosi_init, c_dp_siso_rst);
-- signals for readability
@@ -87,77 +97,67 @@ BEGIN
q_reg <= d_reg WHEN rising_edge(clk);
-- put the input data into c_v and fill the output vector from c_v
- p_state : PROCESS(q_reg, rst)
+ p_state : PROCESS(q_reg, rst, out_of, out_sosi, out_adr)
VARIABLE v : t_reg;
BEGIN
v := q_reg;
-
CASE q_reg.state IS
- WHEN RESET =>
- v := c_t_reg_init;
-
- WHEN
-
- END CASE;
-
-
-
-
-
-
-
-
-
-
+ WHEN RESET =>
+ v := c_t_reg_init;
- p_burst : PROCESS(adr)
- BEGIN
- IF TO_UVEC(adr, c_adr_w)(c_bitshift_adr-1 DOWNTO 0) = c_zeros THEN
- dvr_mosi.burstbegin <= '1';
- IF adr = 0 THEN
- dvr_mosi.address <= TO_UVEC(c_max_adr-c_burstsize, dvr_mosi.address'length);
+ WHEN WRITING =>
+ IF TO_UVEC(out_adr, c_adr_w)(c_bitshift_adr-1 DOWNTO 0) = c_zeros THEN -- if adr mod 64 = 0
+ v.dvr_mosi.burstbegin := '1';
+ IF out_adr = 0 THEN
+ v.dvr_mosi.address := TO_UVEC(c_max_adr-c_burstsize, dvr_mosi.address'length);
+ ELSE
+ v.dvr_mosi.address := TO_UVEC(out_adr-c_burstsize, dvr_mosi.address'length);
+ END IF;
ELSE
- dvr_mosi.address <= TO_UVEC(adr-c_burstsize, dvr_mosi.address'length);
+ v.dvr_mosi.burstbegin := '0';
END IF;
- ELSE
- dvr_mosi.burstbegin <= '0';
- END IF;
- END PROCESS;
-
- dvr_mosi.burstsize <= TO_UVEC(c_burstsize, dvr_mosi.burstsize'length);
- dvr_mosi.wr <= wr_not_rd;
- dvr_mosi.rd <= NOT wr_not_rd;
-
+ v.dvr_mosi.burstsize := TO_UVEC(c_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+ WHEN STOP_WRITING =>
+ IF (out_adr + (c_max_adr / 2) >= c_max_adr) THEN
+ v.stop_adr := out_adr - (c_max_adr / 2);
+ ELSE
+ v.stop_adr := out_adr + (c_max_adr / 2);
+ END IF;
+ IF (stop_in = '1' AND out_adr = v.stop_adr) THEN
+ --stop_out <= '1';
+ v.dvr_mosi.address := TO_UVEC(out_adr, dvr_mosi.address'length);
+ ELSE
+ --stop_out <= '0';
+ END IF;
+ WHEN OTHERS =>
+ v := c_t_reg_init;
- IF rising_edge(stop_in) THEN
- IF (current_adr + (g_max_adr / 2) >= g_max_adr)
- adr <= current_adr - (g_max_adr / 2);
- ELSE
- adr <= current_adr + (g_max_adr / 2);
- current_adr : PROCESS(current_adr)
- BEGIN
+ END CASE;
- IF (stop_in = '1' AND current_adr = adr) THEN
- stop_out <= '1';
- adr_out = current_adr;
+ IF rst = '1' THEN
+ v.state := RESET;
+ ELSIF stop_in = '1' THEN
+ v.state := STOP_WRITING;
ELSE
- stop_out <= '0';
+ v.state := WRITING;
END IF;
END PROCESS;
END rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
index 6c13daed698e9128bda0ace8391784f9a6d14d8d..1c0f45653e7e0d4613a98d6b8509b6ab06c08d4a 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
@@ -170,8 +170,6 @@ BEGIN
mm_rst => mm_rst,
in_sosi_arr => in_sosi_arr,
wr_not_rd => wr_not_rd,
- out_of => open,
- out_adr => open,
--PHY
phy3_io => phy3_io,