diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/hdllib.cfg b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..a33fdab9ee363248109f0b6641c4a5ae2d1307fe
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/hdllib.cfg
@@ -0,0 +1,36 @@
+hdl_lib_name = compaandesign_com_bunny_static_split2rtl_functions_1
+hdl_library_clause_name = compaandesign_com_bunny_static_split2rtl_functions_1_lib
+hdl_lib_uses_synth = compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1 
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+	src/vhdl/compaan_outlinedproc0.vhd
+	src/vhdl/compaan_outlinedproc0_pipeline.vhd
+	src/vhdl/increaseFrameCount.vhd
+	src/vhdl/increaseFrameCount_pipeline.vhd
+	src/vhdl/split64to2t32.vhd
+	src/vhdl/split64to2t32_pipeline.vhd
+	src/vhdl/deserialize32to4t8.vhd
+	src/vhdl/deserialize32to4t8_pipeline.vhd
+	src/vhdl/compaan_outlinedproc2.vhd
+	src/vhdl/compaan_outlinedproc2_pipeline.vhd
+	src/vhdl/compaan_outlinedproc3.vhd
+	src/vhdl/compaan_outlinedproc3_pipeline.vhd
+	src/vhdl/invert_image.vhd
+	src/vhdl/invert_image_pipeline.vhd
+	src/vhdl/compaan_outlinedproc4.vhd
+	src/vhdl/compaan_outlinedproc4_pipeline.vhd
+	src/vhdl/serialize4t8to32.vhd
+	src/vhdl/serialize4t8to32_pipeline.vhd
+	src/vhdl/merge2t32to64.vhd
+	src/vhdl/merge2t32to64_pipeline.vhd
+	src/vhdl/compaan_outlinedproc6.vhd
+	src/vhdl/compaan_outlinedproc6_pipeline.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc0.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc0.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3752cc86cd534864749694a354d069548f36ac7c
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc0.vhd
@@ -0,0 +1,161 @@
+-- File automatically generated by KpnMapper
+-- This file descibes the orignal Function
+-- Function "compaan_outlinedproc0"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+
+entity compaan_outlinedproc0 is
+   generic (
+      STIM_DIR   : string  := "bla";
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1;
+      CNTR_QUANT : natural := 32;
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST   : in  std_logic;
+      CLK   : in  std_logic;
+      -- Inputs 
+      ip_tmp1  : in  std_logic_vector(63 downto 0);
+      EXIST : in  std_logic_vector(0 downto 0);
+      READF : out std_logic_vector(0 downto 0);
+      -- Iterators 
+      it_i : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+      -- Outputs 
+      op_tmp0 : out std_logic_vector(63 downto 0);
+      FULL  : in  std_logic_vector(0 downto 0);
+      WRITEF: out std_logic_vector(0 downto 0);
+      --
+      STOP_RD : in  std_logic;
+      STOP_WR : in  std_logic;
+      ERROR   : out std_logic
+   );
+end compaan_outlinedproc0;
+
+architecture RTL of compaan_outlinedproc0 is
+
+   component compaan_outlinedproc0_pipeline is
+      generic (
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1; 
+         CNTR_QUANT : natural := 32; 
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST   : in std_logic;
+         CLK   : in std_logic;
+         -- Inputs 
+         ip_tmp1  : in  std_logic_vector(63 downto 0);  
+         -- Iterators 
+         it_i : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+         -- Outputs 
+         op_tmp0 : out std_logic_vector(63 downto 0);
+
+         ENi   : in  std_logic;
+         EN    : in  std_logic_vector(c_STAGES-1 downto 0);
+         STALL_FRONT  : out std_logic_vector(c_STAGES-1 downto 0);
+         STALL_BACK   : out std_logic_vector(c_STAGES-1 downto 0);
+         ERROR : out std_logic
+      );
+   end component;
+
+   component CONTROLLER is
+      generic ( 
+         N_STAGES  : natural := 1;
+         BLOCKING  : natural := 0
+      ); 
+      port (
+         READ      : out std_logic;
+         EXIST     : in  std_logic;
+         WRITE     : out std_logic;
+         FULL      : in  std_logic;
+         --
+         ENABLE_EX    : out std_logic_vector(N_STAGES-1 downto 0);
+         STALL_FRONT  : in  std_logic_vector(N_STAGES-1 downto 0);
+         STALL_BACK   : in  std_logic_vector(N_STAGES-1 downto 0);
+         --
+         CLK       : in  std_logic;
+         RST       : in  std_logic
+      );
+   end component;
+
+   constant c_BLOCKING : natural := 1;
+
+   signal sl_EXIST : std_logic;
+   signal sl_READ  : std_logic;
+   signal sl_FULL  : std_logic;
+   signal sl_WRITE : std_logic;
+   signal sl_EN    : std_logic_vector(c_STAGES-1 downto 0);
+   signal sl_STALL_FRONT  : std_logic_vector(c_STAGES-1 downto 0);
+   signal sl_STALL_BACK   : std_logic_vector(c_STAGES-1 downto 0);
+   --
+
+   --
+
+   --
+
+begin
+
+   -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
+   sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
+   -- Functional Evaluation. Only when all signals are high, we can set READF high.
+   READF    <= (READF'range =>sl_READ);
+   sl_FULL  <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
+   WRITEF   <= (WRITEF'range=>sl_WRITE);
+
+   PIPELINE : compaan_outlinedproc0_pipeline
+   generic map (
+         STIM_DIR      => STIM_DIR,
+         c_STAGES      => c_STAGES,
+         N_CNTRS       => N_CNTRS,
+         CNTR_QUANT    => CNTR_QUANT,
+         CNTR_WIDTH    => CNTR_WIDTH
+   )
+   port map (
+      CLK   => CLK,
+      RST   => RST,
+      -- Inputs 
+      ip_tmp1 => ip_tmp1,
+      -- Iterators 
+      it_i => it_i,
+      -- Outputs 
+      op_tmp0 => op_tmp0,
+      --
+      ENi         => sl_READ,
+      EN          => sl_EN,
+      STALL_FRONT => sl_STALL_FRONT,
+      STALL_BACK  => sl_STALL_BACK,
+      ERROR       => ERROR
+   );
+
+   CTRL : CONTROLLER
+   generic map (
+      N_STAGES   => c_STAGES,
+      BLOCKING   => c_BLOCKING
+   )
+   port map (
+      RST        => RST,
+      CLK        => CLK,
+      READ       => sl_READ,
+      EXIST      => sl_EXIST,
+      --
+      ENABLE_EX   => sl_EN,
+      STALL_FRONT => sl_STALL_FRONT,
+      STALL_BACK  => sl_STALL_BACK,
+      --
+      WRITE      => sl_WRITE,
+      FULL       => sl_FULL
+   );
+
+end RTL;
+
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc0_pipeline.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc0_pipeline.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e4e2bbc7d4af14a9edb9b55baf91fce518bf2d5e
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc0_pipeline.vhd
@@ -0,0 +1,91 @@
+-- File automatically generated by KpnMapper
+-- This file defines a template for pipelined function implementation
+-- Function "compaan_outlinedproc0"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+
+entity compaan_outlinedproc0_pipeline is
+   generic (
+      STIM_DIR   : string  := "bla";
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1;
+      CNTR_QUANT : natural := 32;
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST   : in  std_logic;
+      CLK   : in  std_logic;
+      -- Inputs 
+      ip_tmp1  : in  std_logic_vector(63 downto 0);
+      -- Iterators 
+      it_i : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+      -- Outputs 
+      op_tmp0 : out std_logic_vector(63 downto 0);
+      --
+      ENi   : in  std_logic;
+      EN    : in  std_logic_vector(c_STAGES-1 downto 0);
+      STALL_FRONT  : out std_logic_vector(c_STAGES-1 downto 0);
+      STALL_BACK   : out std_logic_vector(c_STAGES-1 downto 0);
+      ERROR : out std_logic
+   );
+end compaan_outlinedproc0_pipeline;
+
+architecture RTL of compaan_outlinedproc0_pipeline is
+--
+    constant error_int : integer := -1;
+    constant reset_int : std_logic_vector(0 downto 0) := b"0";
+    -- Input registers
+    signal ipr_tmp1 : std_logic_vector(63 downto 0);
+
+    -- Iterator registers 
+    signal itr_i : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+    -- Output signals
+
+    --
+    -- Your pipeline signals
+    --
+    -- STAGE_0
+    signal s0_tmp1 : std_logic_vector(63 downto 0);
+    signal r0_tmp1 : std_logic_vector(63 downto 0);
+
+begin
+
+    PIPE_REGS : process(CLK)
+    begin
+        if rising_edge(CLK) then
+            if (RST='1') then
+                -- Something to reset?
+            else
+                if( ENi = '1' ) then
+                    -- Input Registers 
+                    ipr_tmp1 <= ip_tmp1;
+                    -- Iterator Registers 
+                    itr_i <= it_i;
+                end if;
+                -- Pipeline Depth: 1 stages
+                -- STAGE_0
+                if( EN(0) = '1' ) then
+                    r0_tmp1 <= s0_tmp1;
+                end if;
+            end if;
+        end if;
+    end process;    -- PIPE_REGS
+    --
+    -- Output
+    op_tmp0 <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_tmp1), op_tmp0'Length));
+    --
+    -- PIPE_COMB:
+    s0_tmp1 <= ipr_tmp1;
+    --
+    STALL_FRONT  <= (others=>'0');
+    STALL_BACK   <= (others=>'0');
+    ERROR <= '0';
+end RTL;
+
+
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc2.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc2.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..dd5b885e6f89cfd419e9e0390beeeaee9e5ce361
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc2.vhd
@@ -0,0 +1,167 @@
+-- File automatically generated by KpnMapper
+-- This file descibes the orignal Function
+-- Function "compaan_outlinedproc2"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+
+entity compaan_outlinedproc2 is
+   generic (
+      STIM_DIR   : string  := "bla";
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1;
+      CNTR_QUANT : natural := 32;
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST   : in  std_logic;
+      CLK   : in  std_logic;
+      -- Inputs 
+      ip_tmp1  : in  std_logic_vector(7 downto 0);
+      EXIST : in  std_logic_vector(0 downto 0);
+      READF : out std_logic_vector(0 downto 0);
+      -- Iterators 
+      it_color : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+      it_j : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+      it_i : in  std_logic_vector(CNTR_WIDTH(2)-1 downto 0);
+      -- Outputs 
+      op_tmp0 : out std_logic_vector(7 downto 0);
+      FULL  : in  std_logic_vector(0 downto 0);
+      WRITEF: out std_logic_vector(0 downto 0);
+      --
+      STOP_RD : in  std_logic;
+      STOP_WR : in  std_logic;
+      ERROR   : out std_logic
+   );
+end compaan_outlinedproc2;
+
+architecture RTL of compaan_outlinedproc2 is
+
+   component compaan_outlinedproc2_pipeline is
+      generic (
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1; 
+         CNTR_QUANT : natural := 32; 
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST   : in std_logic;
+         CLK   : in std_logic;
+         -- Inputs 
+         ip_tmp1  : in  std_logic_vector(7 downto 0);  
+         -- Iterators 
+         it_color : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+         it_j : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+         it_i : in  std_logic_vector(CNTR_WIDTH(2)-1 downto 0);
+         -- Outputs 
+         op_tmp0 : out std_logic_vector(7 downto 0);
+
+         ENi   : in  std_logic;
+         EN    : in  std_logic_vector(c_STAGES-1 downto 0);
+         STALL_FRONT  : out std_logic_vector(c_STAGES-1 downto 0);
+         STALL_BACK   : out std_logic_vector(c_STAGES-1 downto 0);
+         ERROR : out std_logic
+      );
+   end component;
+
+   component CONTROLLER is
+      generic ( 
+         N_STAGES  : natural := 1;
+         BLOCKING  : natural := 0
+      ); 
+      port (
+         READ      : out std_logic;
+         EXIST     : in  std_logic;
+         WRITE     : out std_logic;
+         FULL      : in  std_logic;
+         --
+         ENABLE_EX    : out std_logic_vector(N_STAGES-1 downto 0);
+         STALL_FRONT  : in  std_logic_vector(N_STAGES-1 downto 0);
+         STALL_BACK   : in  std_logic_vector(N_STAGES-1 downto 0);
+         --
+         CLK       : in  std_logic;
+         RST       : in  std_logic
+      );
+   end component;
+
+   constant c_BLOCKING : natural := 1;
+
+   signal sl_EXIST : std_logic;
+   signal sl_READ  : std_logic;
+   signal sl_FULL  : std_logic;
+   signal sl_WRITE : std_logic;
+   signal sl_EN    : std_logic_vector(c_STAGES-1 downto 0);
+   signal sl_STALL_FRONT  : std_logic_vector(c_STAGES-1 downto 0);
+   signal sl_STALL_BACK   : std_logic_vector(c_STAGES-1 downto 0);
+   --
+
+   --
+
+   --
+
+begin
+
+   -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
+   sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
+   -- Functional Evaluation. Only when all signals are high, we can set READF high.
+   READF    <= (READF'range =>sl_READ);
+   sl_FULL  <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
+   WRITEF   <= (WRITEF'range=>sl_WRITE);
+
+   PIPELINE : compaan_outlinedproc2_pipeline
+   generic map (
+         STIM_DIR      => STIM_DIR,
+         c_STAGES      => c_STAGES,
+         N_CNTRS       => N_CNTRS,
+         CNTR_QUANT    => CNTR_QUANT,
+         CNTR_WIDTH    => CNTR_WIDTH
+   )
+   port map (
+      CLK   => CLK,
+      RST   => RST,
+      -- Inputs 
+      ip_tmp1 => ip_tmp1,
+      -- Iterators 
+      it_color => it_color,
+      it_j => it_j,
+      it_i => it_i,
+      -- Outputs 
+      op_tmp0 => op_tmp0,
+      --
+      ENi         => sl_READ,
+      EN          => sl_EN,
+      STALL_FRONT => sl_STALL_FRONT,
+      STALL_BACK  => sl_STALL_BACK,
+      ERROR       => ERROR
+   );
+
+   CTRL : CONTROLLER
+   generic map (
+      N_STAGES   => c_STAGES,
+      BLOCKING   => c_BLOCKING
+   )
+   port map (
+      RST        => RST,
+      CLK        => CLK,
+      READ       => sl_READ,
+      EXIST      => sl_EXIST,
+      --
+      ENABLE_EX   => sl_EN,
+      STALL_FRONT => sl_STALL_FRONT,
+      STALL_BACK  => sl_STALL_BACK,
+      --
+      WRITE      => sl_WRITE,
+      FULL       => sl_FULL
+   );
+
+end RTL;
+
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc2_pipeline.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc2_pipeline.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a6c20b30f8051a149a726fe50055fd947db3f3a1
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc2_pipeline.vhd
@@ -0,0 +1,97 @@
+-- File automatically generated by KpnMapper
+-- This file defines a template for pipelined function implementation
+-- Function "compaan_outlinedproc2"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+
+entity compaan_outlinedproc2_pipeline is
+   generic (
+      STIM_DIR   : string  := "bla";
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1;
+      CNTR_QUANT : natural := 32;
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST   : in  std_logic;
+      CLK   : in  std_logic;
+      -- Inputs 
+      ip_tmp1  : in  std_logic_vector(7 downto 0);
+      -- Iterators 
+      it_color : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+      it_j : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+      it_i : in  std_logic_vector(CNTR_WIDTH(2)-1 downto 0);
+      -- Outputs 
+      op_tmp0 : out std_logic_vector(7 downto 0);
+      --
+      ENi   : in  std_logic;
+      EN    : in  std_logic_vector(c_STAGES-1 downto 0);
+      STALL_FRONT  : out std_logic_vector(c_STAGES-1 downto 0);
+      STALL_BACK   : out std_logic_vector(c_STAGES-1 downto 0);
+      ERROR : out std_logic
+   );
+end compaan_outlinedproc2_pipeline;
+
+architecture RTL of compaan_outlinedproc2_pipeline is
+--
+    constant error_int : integer := -1;
+    constant reset_int : std_logic_vector(0 downto 0) := b"0";
+    -- Input registers
+    signal ipr_tmp1 : std_logic_vector(7 downto 0);
+
+    -- Iterator registers 
+    signal itr_color : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+    signal itr_j : std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+    signal itr_i : std_logic_vector(CNTR_WIDTH(2)-1 downto 0);
+    -- Output signals
+
+    --
+    -- Your pipeline signals
+    --
+    -- STAGE_0
+    signal s0_tmp1 : std_logic_vector(7 downto 0);
+    signal r0_tmp1 : std_logic_vector(7 downto 0);
+
+begin
+
+    PIPE_REGS : process(CLK)
+    begin
+        if rising_edge(CLK) then
+            if (RST='1') then
+                -- Something to reset?
+            else
+                if( ENi = '1' ) then
+                    -- Input Registers 
+                    ipr_tmp1 <= ip_tmp1;
+                    -- Iterator Registers 
+                    itr_color <= it_color;
+                    itr_j <= it_j;
+                    itr_i <= it_i;
+                end if;
+                -- Pipeline Depth: 1 stages
+                -- STAGE_0
+                if( EN(0) = '1' ) then
+                    r0_tmp1 <= s0_tmp1;
+                end if;
+            end if;
+        end if;
+    end process;    -- PIPE_REGS
+    --
+    -- Output
+    op_tmp0 <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_tmp1), op_tmp0'Length));
+    --
+    -- PIPE_COMB:
+    s0_tmp1 <= ipr_tmp1;
+    --
+    STALL_FRONT  <= (others=>'0');
+    STALL_BACK   <= (others=>'0');
+    ERROR <= '0';
+end RTL;
+
+
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc3.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc3.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..bfe0c683207c9f35478a0d144455b126d60d6234
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc3.vhd
@@ -0,0 +1,167 @@
+-- File automatically generated by KpnMapper
+-- This file descibes the orignal Function
+-- Function "compaan_outlinedproc3"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+
+entity compaan_outlinedproc3 is
+   generic (
+      STIM_DIR   : string  := "bla";
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1;
+      CNTR_QUANT : natural := 32;
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST   : in  std_logic;
+      CLK   : in  std_logic;
+      -- Inputs 
+      ip_tmp1  : in  std_logic_vector(7 downto 0);
+      EXIST : in  std_logic_vector(0 downto 0);
+      READF : out std_logic_vector(0 downto 0);
+      -- Iterators 
+      it_color : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+      it_j : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+      it_i : in  std_logic_vector(CNTR_WIDTH(2)-1 downto 0);
+      -- Outputs 
+      op_tmp0 : out std_logic_vector(7 downto 0);
+      FULL  : in  std_logic_vector(0 downto 0);
+      WRITEF: out std_logic_vector(0 downto 0);
+      --
+      STOP_RD : in  std_logic;
+      STOP_WR : in  std_logic;
+      ERROR   : out std_logic
+   );
+end compaan_outlinedproc3;
+
+architecture RTL of compaan_outlinedproc3 is
+
+   component compaan_outlinedproc3_pipeline is
+      generic (
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1; 
+         CNTR_QUANT : natural := 32; 
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST   : in std_logic;
+         CLK   : in std_logic;
+         -- Inputs 
+         ip_tmp1  : in  std_logic_vector(7 downto 0);  
+         -- Iterators 
+         it_color : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+         it_j : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+         it_i : in  std_logic_vector(CNTR_WIDTH(2)-1 downto 0);
+         -- Outputs 
+         op_tmp0 : out std_logic_vector(7 downto 0);
+
+         ENi   : in  std_logic;
+         EN    : in  std_logic_vector(c_STAGES-1 downto 0);
+         STALL_FRONT  : out std_logic_vector(c_STAGES-1 downto 0);
+         STALL_BACK   : out std_logic_vector(c_STAGES-1 downto 0);
+         ERROR : out std_logic
+      );
+   end component;
+
+   component CONTROLLER is
+      generic ( 
+         N_STAGES  : natural := 1;
+         BLOCKING  : natural := 0
+      ); 
+      port (
+         READ      : out std_logic;
+         EXIST     : in  std_logic;
+         WRITE     : out std_logic;
+         FULL      : in  std_logic;
+         --
+         ENABLE_EX    : out std_logic_vector(N_STAGES-1 downto 0);
+         STALL_FRONT  : in  std_logic_vector(N_STAGES-1 downto 0);
+         STALL_BACK   : in  std_logic_vector(N_STAGES-1 downto 0);
+         --
+         CLK       : in  std_logic;
+         RST       : in  std_logic
+      );
+   end component;
+
+   constant c_BLOCKING : natural := 1;
+
+   signal sl_EXIST : std_logic;
+   signal sl_READ  : std_logic;
+   signal sl_FULL  : std_logic;
+   signal sl_WRITE : std_logic;
+   signal sl_EN    : std_logic_vector(c_STAGES-1 downto 0);
+   signal sl_STALL_FRONT  : std_logic_vector(c_STAGES-1 downto 0);
+   signal sl_STALL_BACK   : std_logic_vector(c_STAGES-1 downto 0);
+   --
+
+   --
+
+   --
+
+begin
+
+   -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
+   sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
+   -- Functional Evaluation. Only when all signals are high, we can set READF high.
+   READF    <= (READF'range =>sl_READ);
+   sl_FULL  <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
+   WRITEF   <= (WRITEF'range=>sl_WRITE);
+
+   PIPELINE : compaan_outlinedproc3_pipeline
+   generic map (
+         STIM_DIR      => STIM_DIR,
+         c_STAGES      => c_STAGES,
+         N_CNTRS       => N_CNTRS,
+         CNTR_QUANT    => CNTR_QUANT,
+         CNTR_WIDTH    => CNTR_WIDTH
+   )
+   port map (
+      CLK   => CLK,
+      RST   => RST,
+      -- Inputs 
+      ip_tmp1 => ip_tmp1,
+      -- Iterators 
+      it_color => it_color,
+      it_j => it_j,
+      it_i => it_i,
+      -- Outputs 
+      op_tmp0 => op_tmp0,
+      --
+      ENi         => sl_READ,
+      EN          => sl_EN,
+      STALL_FRONT => sl_STALL_FRONT,
+      STALL_BACK  => sl_STALL_BACK,
+      ERROR       => ERROR
+   );
+
+   CTRL : CONTROLLER
+   generic map (
+      N_STAGES   => c_STAGES,
+      BLOCKING   => c_BLOCKING
+   )
+   port map (
+      RST        => RST,
+      CLK        => CLK,
+      READ       => sl_READ,
+      EXIST      => sl_EXIST,
+      --
+      ENABLE_EX   => sl_EN,
+      STALL_FRONT => sl_STALL_FRONT,
+      STALL_BACK  => sl_STALL_BACK,
+      --
+      WRITE      => sl_WRITE,
+      FULL       => sl_FULL
+   );
+
+end RTL;
+
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc3_pipeline.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc3_pipeline.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1083d1ed24b8ef252cb5ab0d6f739b1ea37c6e0c
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc3_pipeline.vhd
@@ -0,0 +1,97 @@
+-- File automatically generated by KpnMapper
+-- This file defines a template for pipelined function implementation
+-- Function "compaan_outlinedproc3"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+
+entity compaan_outlinedproc3_pipeline is
+   generic (
+      STIM_DIR   : string  := "bla";
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1;
+      CNTR_QUANT : natural := 32;
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST   : in  std_logic;
+      CLK   : in  std_logic;
+      -- Inputs 
+      ip_tmp1  : in  std_logic_vector(7 downto 0);
+      -- Iterators 
+      it_color : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+      it_j : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+      it_i : in  std_logic_vector(CNTR_WIDTH(2)-1 downto 0);
+      -- Outputs 
+      op_tmp0 : out std_logic_vector(7 downto 0);
+      --
+      ENi   : in  std_logic;
+      EN    : in  std_logic_vector(c_STAGES-1 downto 0);
+      STALL_FRONT  : out std_logic_vector(c_STAGES-1 downto 0);
+      STALL_BACK   : out std_logic_vector(c_STAGES-1 downto 0);
+      ERROR : out std_logic
+   );
+end compaan_outlinedproc3_pipeline;
+
+architecture RTL of compaan_outlinedproc3_pipeline is
+--
+    constant error_int : integer := -1;
+    constant reset_int : std_logic_vector(0 downto 0) := b"0";
+    -- Input registers
+    signal ipr_tmp1 : std_logic_vector(7 downto 0);
+
+    -- Iterator registers 
+    signal itr_color : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+    signal itr_j : std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+    signal itr_i : std_logic_vector(CNTR_WIDTH(2)-1 downto 0);
+    -- Output signals
+
+    --
+    -- Your pipeline signals
+    --
+    -- STAGE_0
+    signal s0_tmp1 : std_logic_vector(7 downto 0);
+    signal r0_tmp1 : std_logic_vector(7 downto 0);
+
+begin
+
+    PIPE_REGS : process(CLK)
+    begin
+        if rising_edge(CLK) then
+            if (RST='1') then
+                -- Something to reset?
+            else
+                if( ENi = '1' ) then
+                    -- Input Registers 
+                    ipr_tmp1 <= ip_tmp1;
+                    -- Iterator Registers 
+                    itr_color <= it_color;
+                    itr_j <= it_j;
+                    itr_i <= it_i;
+                end if;
+                -- Pipeline Depth: 1 stages
+                -- STAGE_0
+                if( EN(0) = '1' ) then
+                    r0_tmp1 <= s0_tmp1;
+                end if;
+            end if;
+        end if;
+    end process;    -- PIPE_REGS
+    --
+    -- Output
+    op_tmp0 <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_tmp1), op_tmp0'Length));
+    --
+    -- PIPE_COMB:
+    s0_tmp1 <= ipr_tmp1;
+    --
+    STALL_FRONT  <= (others=>'0');
+    STALL_BACK   <= (others=>'0');
+    ERROR <= '0';
+end RTL;
+
+
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc4.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc4.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5c2b716078cd9be4113ebf2aaa18f2de60ae6d95
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc4.vhd
@@ -0,0 +1,167 @@
+-- File automatically generated by KpnMapper
+-- This file descibes the orignal Function
+-- Function "compaan_outlinedproc4"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+
+entity compaan_outlinedproc4 is
+   generic (
+      STIM_DIR   : string  := "bla";
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1;
+      CNTR_QUANT : natural := 32;
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST   : in  std_logic;
+      CLK   : in  std_logic;
+      -- Inputs 
+      ip_tmp1  : in  std_logic_vector(7 downto 0);
+      EXIST : in  std_logic_vector(0 downto 0);
+      READF : out std_logic_vector(0 downto 0);
+      -- Iterators 
+      it_color : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+      it_j : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+      it_i : in  std_logic_vector(CNTR_WIDTH(2)-1 downto 0);
+      -- Outputs 
+      op_tmp0 : out std_logic_vector(7 downto 0);
+      FULL  : in  std_logic_vector(0 downto 0);
+      WRITEF: out std_logic_vector(0 downto 0);
+      --
+      STOP_RD : in  std_logic;
+      STOP_WR : in  std_logic;
+      ERROR   : out std_logic
+   );
+end compaan_outlinedproc4;
+
+architecture RTL of compaan_outlinedproc4 is
+
+   component compaan_outlinedproc4_pipeline is
+      generic (
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1; 
+         CNTR_QUANT : natural := 32; 
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST   : in std_logic;
+         CLK   : in std_logic;
+         -- Inputs 
+         ip_tmp1  : in  std_logic_vector(7 downto 0);  
+         -- Iterators 
+         it_color : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+         it_j : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+         it_i : in  std_logic_vector(CNTR_WIDTH(2)-1 downto 0);
+         -- Outputs 
+         op_tmp0 : out std_logic_vector(7 downto 0);
+
+         ENi   : in  std_logic;
+         EN    : in  std_logic_vector(c_STAGES-1 downto 0);
+         STALL_FRONT  : out std_logic_vector(c_STAGES-1 downto 0);
+         STALL_BACK   : out std_logic_vector(c_STAGES-1 downto 0);
+         ERROR : out std_logic
+      );
+   end component;
+
+   component CONTROLLER is
+      generic ( 
+         N_STAGES  : natural := 1;
+         BLOCKING  : natural := 0
+      ); 
+      port (
+         READ      : out std_logic;
+         EXIST     : in  std_logic;
+         WRITE     : out std_logic;
+         FULL      : in  std_logic;
+         --
+         ENABLE_EX    : out std_logic_vector(N_STAGES-1 downto 0);
+         STALL_FRONT  : in  std_logic_vector(N_STAGES-1 downto 0);
+         STALL_BACK   : in  std_logic_vector(N_STAGES-1 downto 0);
+         --
+         CLK       : in  std_logic;
+         RST       : in  std_logic
+      );
+   end component;
+
+   constant c_BLOCKING : natural := 1;
+
+   signal sl_EXIST : std_logic;
+   signal sl_READ  : std_logic;
+   signal sl_FULL  : std_logic;
+   signal sl_WRITE : std_logic;
+   signal sl_EN    : std_logic_vector(c_STAGES-1 downto 0);
+   signal sl_STALL_FRONT  : std_logic_vector(c_STAGES-1 downto 0);
+   signal sl_STALL_BACK   : std_logic_vector(c_STAGES-1 downto 0);
+   --
+
+   --
+
+   --
+
+begin
+
+   -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
+   sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
+   -- Functional Evaluation. Only when all signals are high, we can set READF high.
+   READF    <= (READF'range =>sl_READ);
+   sl_FULL  <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
+   WRITEF   <= (WRITEF'range=>sl_WRITE);
+
+   PIPELINE : compaan_outlinedproc4_pipeline
+   generic map (
+         STIM_DIR      => STIM_DIR,
+         c_STAGES      => c_STAGES,
+         N_CNTRS       => N_CNTRS,
+         CNTR_QUANT    => CNTR_QUANT,
+         CNTR_WIDTH    => CNTR_WIDTH
+   )
+   port map (
+      CLK   => CLK,
+      RST   => RST,
+      -- Inputs 
+      ip_tmp1 => ip_tmp1,
+      -- Iterators 
+      it_color => it_color,
+      it_j => it_j,
+      it_i => it_i,
+      -- Outputs 
+      op_tmp0 => op_tmp0,
+      --
+      ENi         => sl_READ,
+      EN          => sl_EN,
+      STALL_FRONT => sl_STALL_FRONT,
+      STALL_BACK  => sl_STALL_BACK,
+      ERROR       => ERROR
+   );
+
+   CTRL : CONTROLLER
+   generic map (
+      N_STAGES   => c_STAGES,
+      BLOCKING   => c_BLOCKING
+   )
+   port map (
+      RST        => RST,
+      CLK        => CLK,
+      READ       => sl_READ,
+      EXIST      => sl_EXIST,
+      --
+      ENABLE_EX   => sl_EN,
+      STALL_FRONT => sl_STALL_FRONT,
+      STALL_BACK  => sl_STALL_BACK,
+      --
+      WRITE      => sl_WRITE,
+      FULL       => sl_FULL
+   );
+
+end RTL;
+
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc4_pipeline.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc4_pipeline.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a5155a300149c4b0dd41f5eed6aad2345a529cb4
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc4_pipeline.vhd
@@ -0,0 +1,97 @@
+-- File automatically generated by KpnMapper
+-- This file defines a template for pipelined function implementation
+-- Function "compaan_outlinedproc4"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+
+entity compaan_outlinedproc4_pipeline is
+   generic (
+      STIM_DIR   : string  := "bla";
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1;
+      CNTR_QUANT : natural := 32;
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST   : in  std_logic;
+      CLK   : in  std_logic;
+      -- Inputs 
+      ip_tmp1  : in  std_logic_vector(7 downto 0);
+      -- Iterators 
+      it_color : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+      it_j : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+      it_i : in  std_logic_vector(CNTR_WIDTH(2)-1 downto 0);
+      -- Outputs 
+      op_tmp0 : out std_logic_vector(7 downto 0);
+      --
+      ENi   : in  std_logic;
+      EN    : in  std_logic_vector(c_STAGES-1 downto 0);
+      STALL_FRONT  : out std_logic_vector(c_STAGES-1 downto 0);
+      STALL_BACK   : out std_logic_vector(c_STAGES-1 downto 0);
+      ERROR : out std_logic
+   );
+end compaan_outlinedproc4_pipeline;
+
+architecture RTL of compaan_outlinedproc4_pipeline is
+--
+    constant error_int : integer := -1;
+    constant reset_int : std_logic_vector(0 downto 0) := b"0";
+    -- Input registers
+    signal ipr_tmp1 : std_logic_vector(7 downto 0);
+
+    -- Iterator registers 
+    signal itr_color : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+    signal itr_j : std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+    signal itr_i : std_logic_vector(CNTR_WIDTH(2)-1 downto 0);
+    -- Output signals
+
+    --
+    -- Your pipeline signals
+    --
+    -- STAGE_0
+    signal s0_tmp1 : std_logic_vector(7 downto 0);
+    signal r0_tmp1 : std_logic_vector(7 downto 0);
+
+begin
+
+    PIPE_REGS : process(CLK)
+    begin
+        if rising_edge(CLK) then
+            if (RST='1') then
+                -- Something to reset?
+            else
+                if( ENi = '1' ) then
+                    -- Input Registers 
+                    ipr_tmp1 <= ip_tmp1;
+                    -- Iterator Registers 
+                    itr_color <= it_color;
+                    itr_j <= it_j;
+                    itr_i <= it_i;
+                end if;
+                -- Pipeline Depth: 1 stages
+                -- STAGE_0
+                if( EN(0) = '1' ) then
+                    r0_tmp1 <= s0_tmp1;
+                end if;
+            end if;
+        end if;
+    end process;    -- PIPE_REGS
+    --
+    -- Output
+    op_tmp0 <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_tmp1), op_tmp0'Length));
+    --
+    -- PIPE_COMB:
+    s0_tmp1 <= ipr_tmp1;
+    --
+    STALL_FRONT  <= (others=>'0');
+    STALL_BACK   <= (others=>'0');
+    ERROR <= '0';
+end RTL;
+
+
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc6.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc6.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1733a372779950ecc6bf0850dbd96fa15a407495
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc6.vhd
@@ -0,0 +1,161 @@
+-- File automatically generated by KpnMapper
+-- This file descibes the orignal Function
+-- Function "compaan_outlinedproc6"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+
+entity compaan_outlinedproc6 is
+   generic (
+      STIM_DIR   : string  := "bla";
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1;
+      CNTR_QUANT : natural := 32;
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST   : in  std_logic;
+      CLK   : in  std_logic;
+      -- Inputs 
+      ip_tmp1  : in  std_logic_vector(63 downto 0);
+      EXIST : in  std_logic_vector(0 downto 0);
+      READF : out std_logic_vector(0 downto 0);
+      -- Iterators 
+      it_x : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+      -- Outputs 
+      op_tmp0 : out std_logic_vector(63 downto 0);
+      FULL  : in  std_logic_vector(0 downto 0);
+      WRITEF: out std_logic_vector(0 downto 0);
+      --
+      STOP_RD : in  std_logic;
+      STOP_WR : in  std_logic;
+      ERROR   : out std_logic
+   );
+end compaan_outlinedproc6;
+
+architecture RTL of compaan_outlinedproc6 is
+
+   component compaan_outlinedproc6_pipeline is
+      generic (
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1; 
+         CNTR_QUANT : natural := 32; 
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST   : in std_logic;
+         CLK   : in std_logic;
+         -- Inputs 
+         ip_tmp1  : in  std_logic_vector(63 downto 0);  
+         -- Iterators 
+         it_x : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+         -- Outputs 
+         op_tmp0 : out std_logic_vector(63 downto 0);
+
+         ENi   : in  std_logic;
+         EN    : in  std_logic_vector(c_STAGES-1 downto 0);
+         STALL_FRONT  : out std_logic_vector(c_STAGES-1 downto 0);
+         STALL_BACK   : out std_logic_vector(c_STAGES-1 downto 0);
+         ERROR : out std_logic
+      );
+   end component;
+
+   component CONTROLLER is
+      generic ( 
+         N_STAGES  : natural := 1;
+         BLOCKING  : natural := 0
+      ); 
+      port (
+         READ      : out std_logic;
+         EXIST     : in  std_logic;
+         WRITE     : out std_logic;
+         FULL      : in  std_logic;
+         --
+         ENABLE_EX    : out std_logic_vector(N_STAGES-1 downto 0);
+         STALL_FRONT  : in  std_logic_vector(N_STAGES-1 downto 0);
+         STALL_BACK   : in  std_logic_vector(N_STAGES-1 downto 0);
+         --
+         CLK       : in  std_logic;
+         RST       : in  std_logic
+      );
+   end component;
+
+   constant c_BLOCKING : natural := 1;
+
+   signal sl_EXIST : std_logic;
+   signal sl_READ  : std_logic;
+   signal sl_FULL  : std_logic;
+   signal sl_WRITE : std_logic;
+   signal sl_EN    : std_logic_vector(c_STAGES-1 downto 0);
+   signal sl_STALL_FRONT  : std_logic_vector(c_STAGES-1 downto 0);
+   signal sl_STALL_BACK   : std_logic_vector(c_STAGES-1 downto 0);
+   --
+
+   --
+
+   --
+
+begin
+
+   -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
+   sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
+   -- Functional Evaluation. Only when all signals are high, we can set READF high.
+   READF    <= (READF'range =>sl_READ);
+   sl_FULL  <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
+   WRITEF   <= (WRITEF'range=>sl_WRITE);
+
+   PIPELINE : compaan_outlinedproc6_pipeline
+   generic map (
+         STIM_DIR      => STIM_DIR,
+         c_STAGES      => c_STAGES,
+         N_CNTRS       => N_CNTRS,
+         CNTR_QUANT    => CNTR_QUANT,
+         CNTR_WIDTH    => CNTR_WIDTH
+   )
+   port map (
+      CLK   => CLK,
+      RST   => RST,
+      -- Inputs 
+      ip_tmp1 => ip_tmp1,
+      -- Iterators 
+      it_x => it_x,
+      -- Outputs 
+      op_tmp0 => op_tmp0,
+      --
+      ENi         => sl_READ,
+      EN          => sl_EN,
+      STALL_FRONT => sl_STALL_FRONT,
+      STALL_BACK  => sl_STALL_BACK,
+      ERROR       => ERROR
+   );
+
+   CTRL : CONTROLLER
+   generic map (
+      N_STAGES   => c_STAGES,
+      BLOCKING   => c_BLOCKING
+   )
+   port map (
+      RST        => RST,
+      CLK        => CLK,
+      READ       => sl_READ,
+      EXIST      => sl_EXIST,
+      --
+      ENABLE_EX   => sl_EN,
+      STALL_FRONT => sl_STALL_FRONT,
+      STALL_BACK  => sl_STALL_BACK,
+      --
+      WRITE      => sl_WRITE,
+      FULL       => sl_FULL
+   );
+
+end RTL;
+
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc6_pipeline.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc6_pipeline.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2ad2e489227765b2625ad079a2893a0da32cd846
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc6_pipeline.vhd
@@ -0,0 +1,91 @@
+-- File automatically generated by KpnMapper
+-- This file defines a template for pipelined function implementation
+-- Function "compaan_outlinedproc6"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+
+entity compaan_outlinedproc6_pipeline is
+   generic (
+      STIM_DIR   : string  := "bla";
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1;
+      CNTR_QUANT : natural := 32;
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST   : in  std_logic;
+      CLK   : in  std_logic;
+      -- Inputs 
+      ip_tmp1  : in  std_logic_vector(63 downto 0);
+      -- Iterators 
+      it_x : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+      -- Outputs 
+      op_tmp0 : out std_logic_vector(63 downto 0);
+      --
+      ENi   : in  std_logic;
+      EN    : in  std_logic_vector(c_STAGES-1 downto 0);
+      STALL_FRONT  : out std_logic_vector(c_STAGES-1 downto 0);
+      STALL_BACK   : out std_logic_vector(c_STAGES-1 downto 0);
+      ERROR : out std_logic
+   );
+end compaan_outlinedproc6_pipeline;
+
+architecture RTL of compaan_outlinedproc6_pipeline is
+--
+    constant error_int : integer := -1;
+    constant reset_int : std_logic_vector(0 downto 0) := b"0";
+    -- Input registers
+    signal ipr_tmp1 : std_logic_vector(63 downto 0);
+
+    -- Iterator registers 
+    signal itr_x : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+    -- Output signals
+
+    --
+    -- Your pipeline signals
+    --
+    -- STAGE_0
+    signal s0_tmp1 : std_logic_vector(63 downto 0);
+    signal r0_tmp1 : std_logic_vector(63 downto 0);
+
+begin
+
+    PIPE_REGS : process(CLK)
+    begin
+        if rising_edge(CLK) then
+            if (RST='1') then
+                -- Something to reset?
+            else
+                if( ENi = '1' ) then
+                    -- Input Registers 
+                    ipr_tmp1 <= ip_tmp1;
+                    -- Iterator Registers 
+                    itr_x <= it_x;
+                end if;
+                -- Pipeline Depth: 1 stages
+                -- STAGE_0
+                if( EN(0) = '1' ) then
+                    r0_tmp1 <= s0_tmp1;
+                end if;
+            end if;
+        end if;
+    end process;    -- PIPE_REGS
+    --
+    -- Output
+    op_tmp0 <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_tmp1), op_tmp0'Length));
+    --
+    -- PIPE_COMB:
+    s0_tmp1 <= ipr_tmp1;
+    --
+    STALL_FRONT  <= (others=>'0');
+    STALL_BACK   <= (others=>'0');
+    ERROR <= '0';
+end RTL;
+
+
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/deserialize32to4t8.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/deserialize32to4t8.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..37d54e1f18e6aecb9fcac827d405487b32b4badd
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/deserialize32to4t8.vhd
@@ -0,0 +1,176 @@
+-- File automatically generated by KpnMapper
+-- This file descibes the orignal Function
+-- Function "deserialize32to4t8"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+
+entity deserialize32to4t8 is
+   generic (
+      STIM_DIR   : string  := "bla";
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1;
+      CNTR_QUANT : natural := 32;
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST   : in  std_logic;
+      CLK   : in  std_logic;
+      -- Inputs 
+      ip_stimin  : in  std_logic_vector(31 downto 0);
+      EXIST : in  std_logic_vector(0 downto 0);
+      READF : out std_logic_vector(0 downto 0);
+      -- Iterators 
+      it_j : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+      it_i : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+      -- Outputs 
+      op_out0 : out std_logic_vector(7 downto 0);
+      op_out1 : out std_logic_vector(7 downto 0);
+      op_out2 : out std_logic_vector(7 downto 0);
+      op_out3 : out std_logic_vector(7 downto 0);
+      FULL  : in  std_logic_vector(3 downto 0);
+      WRITEF: out std_logic_vector(3 downto 0);
+      --
+      STOP_RD : in  std_logic;
+      STOP_WR : in  std_logic;
+      ERROR   : out std_logic
+   );
+end deserialize32to4t8;
+
+architecture RTL of deserialize32to4t8 is
+
+   component deserialize32to4t8_pipeline is
+      generic (
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1; 
+         CNTR_QUANT : natural := 32; 
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST   : in std_logic;
+         CLK   : in std_logic;
+         -- Inputs 
+         ip_stimin  : in  std_logic_vector(31 downto 0);  
+         -- Iterators 
+         it_j : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+         it_i : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+         -- Outputs 
+         op_out0 : out std_logic_vector(7 downto 0);
+         op_out1 : out std_logic_vector(7 downto 0);
+         op_out2 : out std_logic_vector(7 downto 0);
+         op_out3 : out std_logic_vector(7 downto 0);
+
+         ENi   : in  std_logic;
+         EN    : in  std_logic_vector(c_STAGES-1 downto 0);
+         STALL_FRONT  : out std_logic_vector(c_STAGES-1 downto 0);
+         STALL_BACK   : out std_logic_vector(c_STAGES-1 downto 0);
+         ERROR : out std_logic
+      );
+   end component;
+
+   component CONTROLLER is
+      generic ( 
+         N_STAGES  : natural := 1;
+         BLOCKING  : natural := 0
+      ); 
+      port (
+         READ      : out std_logic;
+         EXIST     : in  std_logic;
+         WRITE     : out std_logic;
+         FULL      : in  std_logic;
+         --
+         ENABLE_EX    : out std_logic_vector(N_STAGES-1 downto 0);
+         STALL_FRONT  : in  std_logic_vector(N_STAGES-1 downto 0);
+         STALL_BACK   : in  std_logic_vector(N_STAGES-1 downto 0);
+         --
+         CLK       : in  std_logic;
+         RST       : in  std_logic
+      );
+   end component;
+
+   constant c_BLOCKING : natural := 1;
+
+   signal sl_EXIST : std_logic;
+   signal sl_READ  : std_logic;
+   signal sl_FULL  : std_logic;
+   signal sl_WRITE : std_logic;
+   signal sl_EN    : std_logic_vector(c_STAGES-1 downto 0);
+   signal sl_STALL_FRONT  : std_logic_vector(c_STAGES-1 downto 0);
+   signal sl_STALL_BACK   : std_logic_vector(c_STAGES-1 downto 0);
+   --
+
+   --
+
+
+
+
+   --
+
+begin
+
+   -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
+   sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
+   -- Functional Evaluation. Only when all signals are high, we can set READF high.
+   READF    <= (READF'range =>sl_READ);
+   sl_FULL  <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
+   WRITEF   <= (WRITEF'range=>sl_WRITE);
+
+   PIPELINE : deserialize32to4t8_pipeline
+   generic map (
+         STIM_DIR      => STIM_DIR,
+         c_STAGES      => c_STAGES,
+         N_CNTRS       => N_CNTRS,
+         CNTR_QUANT    => CNTR_QUANT,
+         CNTR_WIDTH    => CNTR_WIDTH
+   )
+   port map (
+      CLK   => CLK,
+      RST   => RST,
+      -- Inputs 
+      ip_stimin => ip_stimin,
+      -- Iterators 
+      it_j => it_j,
+      it_i => it_i,
+      -- Outputs 
+      op_out0 => op_out0,
+      op_out1 => op_out1,
+      op_out2 => op_out2,
+      op_out3 => op_out3,
+      --
+      ENi         => sl_READ,
+      EN          => sl_EN,
+      STALL_FRONT => sl_STALL_FRONT,
+      STALL_BACK  => sl_STALL_BACK,
+      ERROR       => ERROR
+   );
+
+   CTRL : CONTROLLER
+   generic map (
+      N_STAGES   => c_STAGES,
+      BLOCKING   => c_BLOCKING
+   )
+   port map (
+      RST        => RST,
+      CLK        => CLK,
+      READ       => sl_READ,
+      EXIST      => sl_EXIST,
+      --
+      ENABLE_EX   => sl_EN,
+      STALL_FRONT => sl_STALL_FRONT,
+      STALL_BACK  => sl_STALL_BACK,
+      --
+      WRITE      => sl_WRITE,
+      FULL       => sl_FULL
+   );
+
+end RTL;
+
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/deserialize32to4t8_pipeline.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/deserialize32to4t8_pipeline.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..904c45135ce337218c15f445cfe5f32530448524
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/deserialize32to4t8_pipeline.vhd
@@ -0,0 +1,109 @@
+-- File automatically generated by KpnMapper
+-- This file defines a template for pipelined function implementation
+-- Function "deserialize32to4t8"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+
+entity deserialize32to4t8_pipeline is
+   generic (
+      STIM_DIR   : string  := "bla";
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1;
+      CNTR_QUANT : natural := 32;
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST   : in  std_logic;
+      CLK   : in  std_logic;
+      -- Inputs 
+      ip_stimin  : in  std_logic_vector(31 downto 0);
+      -- Iterators 
+      it_j : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+      it_i : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+      -- Outputs 
+      op_out0 : out std_logic_vector(7 downto 0);
+      op_out1 : out std_logic_vector(7 downto 0);
+      op_out2 : out std_logic_vector(7 downto 0);
+      op_out3 : out std_logic_vector(7 downto 0);
+      --
+      ENi   : in  std_logic;
+      EN    : in  std_logic_vector(c_STAGES-1 downto 0);
+      STALL_FRONT  : out std_logic_vector(c_STAGES-1 downto 0);
+      STALL_BACK   : out std_logic_vector(c_STAGES-1 downto 0);
+      ERROR : out std_logic
+   );
+end deserialize32to4t8_pipeline;
+
+architecture RTL of deserialize32to4t8_pipeline is
+--
+    constant error_int : integer := -1;
+    constant reset_int : std_logic_vector(0 downto 0) := b"0";
+    -- Input registers
+    signal ipr_stimin : std_logic_vector(31 downto 0);
+
+    -- Iterator registers 
+    signal itr_j : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+    signal itr_i : std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+    --
+
+    signal r0_img_i_0 : std_logic_vector(7 downto 0);
+    signal r0_img_i_1 : std_logic_vector(7 downto 0);
+    signal r0_img_i_2 : std_logic_vector(7 downto 0);
+    signal r0_img_i_3 : std_logic_vector(7 downto 0);
+
+    --
+    -- Your pipeline signals
+    --
+    -- STAGE_0
+    signal s0_stimin : std_logic_vector(31 downto 0);
+    signal r0_stimin : std_logic_vector(31 downto 0);
+
+begin
+
+    PIPE_REGS : process(CLK)
+    begin
+        if rising_edge(CLK) then
+            if (RST='1') then
+                -- Something to reset?
+            else
+                if( ENi = '1' ) then
+                    -- Input Registers 
+                    ipr_stimin <= ip_stimin;
+                    -- Iterator Registers 
+                    itr_j <= it_j;
+                    itr_i <= it_i;
+                end if;
+                -- Pipeline Depth: 1 stages
+                -- STAGE_0
+                if( EN(0) = '1' ) then
+                    -- r0_stimin <= s0_stimin;
+                    r0_img_i_0 <= s0_stimin(7 downto 0);
+                    r0_img_i_1 <= s0_stimin(15 downto 8);
+                    r0_img_i_2 <= s0_stimin(23 downto 16);
+                    r0_img_i_3 <= s0_stimin(31 downto 24);
+                end if;
+            end if;
+        end if;
+    end process;    -- PIPE_REGS
+    --
+    -- Output
+    op_out0 <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_img_i_0), op_out0'Length));
+    op_out1 <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_img_i_1), op_out1'Length));
+    op_out2 <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_img_i_2), op_out2'Length));
+    op_out3 <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_img_i_3), op_out3'Length));
+    --
+    -- PIPE_COMB:
+    s0_stimin <= ipr_stimin;
+    --
+    STALL_FRONT  <= (others=>'0');
+    STALL_BACK   <= (others=>'0');
+    ERROR <= '0';
+end RTL;
+
+
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/get_header_pipeline.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/get_header_pipeline.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8535ae811c4486d13caa766f5a582a815f26b33e
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/get_header_pipeline.vhd
@@ -0,0 +1,93 @@
+-- File automatically generated by KpnMapper
+-- This file defines a template for pipelined function implementation
+-- Function "get_header"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+
+entity get_header_pipeline is
+   generic (
+      STIM_DIR   : string  := "bla";
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1;
+      CNTR_QUANT : natural := 32;
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST   : in  std_logic;
+      CLK   : in  std_logic;
+      --  Non Syncronized Parameters
+      rf_split_x     : in  std_logic_vector( 32-1 downto 0); -- input
+      -- Inputs 
+      ip_x  : in  std_logic_vector(63 downto 0);
+      -- Iterators 
+      it_i : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+      -- Outputs 
+      op_SPLIT : out std_logic_vector(31 downto 0);
+      --
+      ENi   : in  std_logic;
+      EN    : in  std_logic_vector(c_STAGES-1 downto 0);
+      STALL_FRONT  : out std_logic_vector(c_STAGES-1 downto 0);
+      STALL_BACK   : out std_logic_vector(c_STAGES-1 downto 0);
+      ERROR : out std_logic
+   );
+end get_header_pipeline;
+
+architecture RTL of get_header_pipeline is
+--
+    constant error_int : integer := -1;
+    constant reset_int : std_logic_vector(0 downto 0) := b"0";
+    -- Input registers
+    signal ipr_x : std_logic_vector(63 downto 0);
+
+    -- Iterator registers 
+    signal itr_i : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+    -- Output signals
+
+    --
+    -- Your pipeline signals
+    --
+    -- STAGE_0
+    signal s0_x : std_logic_vector(63 downto 0);
+    signal r0_x : std_logic_vector(63 downto 0);
+
+begin
+
+    PIPE_REGS : process(CLK)
+    begin
+        if rising_edge(CLK) then
+            if (RST='1') then
+                -- Something to reset?
+            else
+                if( ENi = '1' ) then
+                    -- Input Registers 
+                    ipr_x <= ip_x;
+                    -- Iterator Registers 
+                    itr_i <= it_i;
+                end if;
+                -- Pipeline Depth: 1 stages
+                -- STAGE_0
+                if( EN(0) = '1' ) then
+                    r0_x <= s0_x;
+                end if;
+            end if;
+        end if;
+    end process;    -- PIPE_REGS
+    --
+    -- Output
+    op_SPLIT <= rf_split_x;
+    --
+    -- PIPE_COMB:
+    s0_x <= ipr_x;
+    --
+    STALL_FRONT  <= (others=>'0');
+    STALL_BACK   <= (others=>'0');
+    ERROR <= '0';
+end RTL;
+
+
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/increaseFrameCount.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/increaseFrameCount.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..eeafc77a67c6b230f074ba687b6c498c4b33f867
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/increaseFrameCount.vhd
@@ -0,0 +1,160 @@
+-- File automatically generated by KpnMapper
+-- This file descibes the orignal Function
+-- Function "increaseFrameCount"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+
+entity increaseFrameCount is
+   generic (
+      STIM_DIR   : string  := "bla";
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1;
+      CNTR_QUANT : natural := 32;
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST   : in  std_logic;
+      CLK   : in  std_logic;
+      --  Non Syncronized Parameters
+      rf_count     : out  std_logic_vector( 32-1 downto 0); -- output
+      -- Inputs 
+      ip_pixel  : in  std_logic_vector(63 downto 0);
+      EXIST : in  std_logic_vector(0 downto 0);
+      READF : out std_logic_vector(0 downto 0);
+      -- Iterators 
+      it_i : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+      -- Outputs 
+      --
+      STOP_RD : in  std_logic;
+      STOP_WR : in  std_logic;
+      ERROR   : out std_logic
+   );
+end increaseFrameCount;
+
+architecture RTL of increaseFrameCount is
+
+   component increaseFrameCount_pipeline is
+      generic (
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1; 
+         CNTR_QUANT : natural := 32; 
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST   : in std_logic;
+         CLK   : in std_logic;
+      --  Non Syncronized Parameters
+      rf_count     : out std_logic_vector( 32-1 downto 0); --output
+         -- Inputs 
+         ip_pixel  : in  std_logic_vector(63 downto 0);  
+         -- Iterators 
+         it_i : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+         -- Outputs 
+
+         ENi   : in  std_logic;
+         EN    : in  std_logic_vector(c_STAGES-1 downto 0);
+         STALL_FRONT  : out std_logic_vector(c_STAGES-1 downto 0);
+         STALL_BACK   : out std_logic_vector(c_STAGES-1 downto 0);
+         ERROR : out std_logic
+      );
+   end component;
+
+   component CONTROLLER is
+      generic ( 
+         N_STAGES  : natural := 1;
+         BLOCKING  : natural := 0
+      ); 
+      port (
+         READ      : out std_logic;
+         EXIST     : in  std_logic;
+         WRITE     : out std_logic;
+         FULL      : in  std_logic;
+         --
+         ENABLE_EX    : out std_logic_vector(N_STAGES-1 downto 0);
+         STALL_FRONT  : in  std_logic_vector(N_STAGES-1 downto 0);
+         STALL_BACK   : in  std_logic_vector(N_STAGES-1 downto 0);
+         --
+         CLK       : in  std_logic;
+         RST       : in  std_logic
+      );
+   end component;
+
+   constant c_BLOCKING : natural := 1;
+
+   signal sl_EXIST : std_logic;
+   signal sl_READ  : std_logic;
+   signal sl_FULL  : std_logic;
+   signal sl_WRITE : std_logic;
+   signal sl_EN    : std_logic_vector(c_STAGES-1 downto 0);
+   signal sl_STALL_FRONT  : std_logic_vector(c_STAGES-1 downto 0);
+   signal sl_STALL_BACK   : std_logic_vector(c_STAGES-1 downto 0);
+   --
+
+   --
+   --
+
+begin
+
+   -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
+   sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
+   -- Functional Evaluation. Only when all signals are high, we can set READF high.
+   READF    <= (READF'range =>sl_READ);
+   sl_FULL  <= '0';
+
+   PIPELINE : increaseFrameCount_pipeline
+   generic map (
+         STIM_DIR      => STIM_DIR,
+         c_STAGES      => c_STAGES,
+         N_CNTRS       => N_CNTRS,
+         CNTR_QUANT    => CNTR_QUANT,
+         CNTR_WIDTH    => CNTR_WIDTH
+   )
+   port map (
+      CLK   => CLK,
+      RST   => RST,
+      --  Non Syncronized Parameters
+      rf_count     => rf_count,
+      -- Inputs 
+      ip_pixel => ip_pixel,
+      -- Iterators 
+      it_i => it_i,
+      -- Outputs 
+      --
+      ENi         => sl_READ,
+      EN          => sl_EN,
+      STALL_FRONT => sl_STALL_FRONT,
+      STALL_BACK  => sl_STALL_BACK,
+      ERROR       => ERROR
+   );
+
+   CTRL : CONTROLLER
+   generic map (
+      N_STAGES   => c_STAGES,
+      BLOCKING   => c_BLOCKING
+   )
+   port map (
+      RST        => RST,
+      CLK        => CLK,
+      READ       => sl_READ,
+      EXIST      => sl_EXIST,
+      --
+      ENABLE_EX   => sl_EN,
+      STALL_FRONT => sl_STALL_FRONT,
+      STALL_BACK  => sl_STALL_BACK,
+      --
+      WRITE      => sl_WRITE,
+      FULL       => sl_FULL
+   );
+
+end RTL;
+
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/increaseFrameCount_pipeline.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/increaseFrameCount_pipeline.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..172436ec1c48f322052588f1307fccd1453ae262
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/increaseFrameCount_pipeline.vhd
@@ -0,0 +1,97 @@
+-- File automatically generated by KpnMapper
+-- This file defines a template for pipelined function implementation
+-- Function "increaseFrameCount"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+
+entity increaseFrameCount_pipeline is
+   generic (
+      STIM_DIR   : string  := "bla";
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1;
+      CNTR_QUANT : natural := 32;
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST   : in  std_logic;
+      CLK   : in  std_logic;
+      --  Non Syncronized Parameters
+      rf_count     : out   std_logic_vector( 32-1 downto 0); -- output
+      -- Inputs 
+      ip_pixel  : in  std_logic_vector(63 downto 0);
+      -- Iterators 
+      it_i : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+      -- Outputs 
+      --
+      ENi   : in  std_logic;
+      EN    : in  std_logic_vector(c_STAGES-1 downto 0);
+      STALL_FRONT  : out std_logic_vector(c_STAGES-1 downto 0);
+      STALL_BACK   : out std_logic_vector(c_STAGES-1 downto 0);
+      ERROR : out std_logic
+   );
+end increaseFrameCount_pipeline;
+
+architecture RTL of increaseFrameCount_pipeline is
+--
+    constant error_int : integer := -1;
+    constant reset_int : std_logic_vector(0 downto 0) := b"0";
+    -- Input registers
+    signal ipr_pixel : std_logic_vector(63 downto 0);
+
+    -- Iterator registers 
+    signal itr_i : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+    --
+    --
+    -- Your pipeline signals
+    --
+    -- STAGE_0
+    signal s0_pixel : std_logic_vector(63 downto 0);
+    signal r0_pixel : std_logic_vector(63 downto 0);
+
+	signal count_n : integer;
+	
+begin
+
+    PIPE_REGS : process(CLK)
+    begin
+        if rising_edge(CLK) then
+            if (RST='1') then
+                -- Something to reset?
+                count_n <= 0;
+            else
+                if( ENi = '1' ) then
+                    -- Input Registers 
+                    ipr_pixel <= ip_pixel;
+                    -- Iterator Registers 
+                    itr_i <= it_i;
+                end if;
+                -- Pipeline Depth: 1 stages
+                -- STAGE_0
+                if( EN(0) = '1' ) then
+                    r0_pixel <= s0_pixel;
+                    count_n <= count_n + 1;	
+                end if;
+            end if;
+        end if;
+    end process;    -- PIPE_REGS
+    --
+    -- Output
+    --
+    -- PIPE_COMB:
+    s0_pixel <= ipr_pixel;
+    rf_count <= std_logic_vector(to_unsigned(count_n,rf_count'length));
+    
+    
+    --
+    STALL_FRONT  <= (others=>'0');
+    STALL_BACK   <= (others=>'0');
+    ERROR <= '0';
+end RTL;
+
+
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/invert_image.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/invert_image.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..cb6fab442401bc8e566858daf38f37881c0ae1b7
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/invert_image.vhd
@@ -0,0 +1,173 @@
+-- File automatically generated by KpnMapper
+-- This file descibes the orignal Function
+-- Function "invert_image"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+
+entity invert_image is
+   generic (
+      STIM_DIR   : string  := "bla";
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1;
+      CNTR_QUANT : natural := 32;
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST   : in  std_logic;
+      CLK   : in  std_logic;
+      --  Non Syncronized Parameters
+      rf_brightness     : in  std_logic_vector( 32-1 downto 0); -- input
+      -- Inputs 
+      ip_x  : in  std_logic_vector(7 downto 0);
+      EXIST : in  std_logic_vector(0 downto 0);
+      READF : out std_logic_vector(0 downto 0);
+      -- Iterators 
+      it_color : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+      it_j : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+      it_i : in  std_logic_vector(CNTR_WIDTH(2)-1 downto 0);
+      -- Outputs 
+      op_return_value : out std_logic_vector(7 downto 0);
+      FULL  : in  std_logic_vector(0 downto 0);
+      WRITEF: out std_logic_vector(0 downto 0);
+      --
+      STOP_RD : in  std_logic;
+      STOP_WR : in  std_logic;
+      ERROR   : out std_logic
+   );
+end invert_image;
+
+architecture RTL of invert_image is
+
+   component invert_image_pipeline is
+      generic (
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1; 
+         CNTR_QUANT : natural := 32; 
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST   : in std_logic;
+         CLK   : in std_logic;
+      --  Non Syncronized Parameters
+      rf_brightness     : in  std_logic_vector( 32-1 downto 0); --input
+         -- Inputs 
+         ip_x  : in  std_logic_vector(7 downto 0);  
+         -- Iterators 
+         it_color : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+         it_j : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+         it_i : in  std_logic_vector(CNTR_WIDTH(2)-1 downto 0);
+         -- Outputs 
+         op_return_value : out std_logic_vector(7 downto 0);
+
+         ENi   : in  std_logic;
+         EN    : in  std_logic_vector(c_STAGES-1 downto 0);
+         STALL_FRONT  : out std_logic_vector(c_STAGES-1 downto 0);
+         STALL_BACK   : out std_logic_vector(c_STAGES-1 downto 0);
+         ERROR : out std_logic
+      );
+   end component;
+
+   component CONTROLLER is
+      generic ( 
+         N_STAGES  : natural := 1;
+         BLOCKING  : natural := 0
+      ); 
+      port (
+         READ      : out std_logic;
+         EXIST     : in  std_logic;
+         WRITE     : out std_logic;
+         FULL      : in  std_logic;
+         --
+         ENABLE_EX    : out std_logic_vector(N_STAGES-1 downto 0);
+         STALL_FRONT  : in  std_logic_vector(N_STAGES-1 downto 0);
+         STALL_BACK   : in  std_logic_vector(N_STAGES-1 downto 0);
+         --
+         CLK       : in  std_logic;
+         RST       : in  std_logic
+      );
+   end component;
+
+   constant c_BLOCKING : natural := 1;
+
+   signal sl_EXIST : std_logic;
+   signal sl_READ  : std_logic;
+   signal sl_FULL  : std_logic;
+   signal sl_WRITE : std_logic;
+   signal sl_EN    : std_logic_vector(c_STAGES-1 downto 0);
+   signal sl_STALL_FRONT  : std_logic_vector(c_STAGES-1 downto 0);
+   signal sl_STALL_BACK   : std_logic_vector(c_STAGES-1 downto 0);
+   --
+
+   --
+
+   --
+
+begin
+
+   -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
+   sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
+   -- Functional Evaluation. Only when all signals are high, we can set READF high.
+   READF    <= (READF'range =>sl_READ);
+   sl_FULL  <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
+   WRITEF   <= (WRITEF'range=>sl_WRITE);
+
+   PIPELINE : invert_image_pipeline
+   generic map (
+         STIM_DIR      => STIM_DIR,
+         c_STAGES      => c_STAGES,
+         N_CNTRS       => N_CNTRS,
+         CNTR_QUANT    => CNTR_QUANT,
+         CNTR_WIDTH    => CNTR_WIDTH
+   )
+   port map (
+      CLK   => CLK,
+      RST   => RST,
+      --  Non Syncronized Parameters
+      rf_brightness     => rf_brightness,
+      -- Inputs 
+      ip_x => ip_x,
+      -- Iterators 
+      it_color => it_color,
+      it_j => it_j,
+      it_i => it_i,
+      -- Outputs 
+      op_return_value => op_return_value,
+      --
+      ENi         => sl_READ,
+      EN          => sl_EN,
+      STALL_FRONT => sl_STALL_FRONT,
+      STALL_BACK  => sl_STALL_BACK,
+      ERROR       => ERROR
+   );
+
+   CTRL : CONTROLLER
+   generic map (
+      N_STAGES   => c_STAGES,
+      BLOCKING   => c_BLOCKING
+   )
+   port map (
+      RST        => RST,
+      CLK        => CLK,
+      READ       => sl_READ,
+      EXIST      => sl_EXIST,
+      --
+      ENABLE_EX   => sl_EN,
+      STALL_FRONT => sl_STALL_FRONT,
+      STALL_BACK  => sl_STALL_BACK,
+      --
+      WRITE      => sl_WRITE,
+      FULL       => sl_FULL
+   );
+
+end RTL;
+
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/invert_image_pipeline.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/invert_image_pipeline.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..bd61e5f450efaa06fcdf5fa22abe2670644622ad
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/invert_image_pipeline.vhd
@@ -0,0 +1,130 @@
+-- File automatically generated by KpnMapper
+-- This file defines a template for pipelined function implementation
+-- Function "invert_image"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+
+entity invert_image_pipeline is
+   generic (
+      STIM_DIR   : string  := "bla";
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1;
+      CNTR_QUANT : natural := 32;
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST   : in  std_logic;
+      CLK   : in  std_logic;
+      --  Non Syncronized Parameters
+      rf_brightness     : in  std_logic_vector( 32-1 downto 0); -- input
+      -- Inputs 
+      ip_x  : in  std_logic_vector(7 downto 0);
+      -- Iterators 
+      it_color : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+      it_j : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+      it_i : in  std_logic_vector(CNTR_WIDTH(2)-1 downto 0);
+      -- Outputs 
+      op_return_value : out std_logic_vector(7 downto 0);
+      --
+      ENi   : in  std_logic;
+      EN    : in  std_logic_vector(c_STAGES-1 downto 0);
+      STALL_FRONT  : out std_logic_vector(c_STAGES-1 downto 0);
+      STALL_BACK   : out std_logic_vector(c_STAGES-1 downto 0);
+      ERROR : out std_logic
+   );
+end invert_image_pipeline;
+
+architecture RTL of invert_image_pipeline is
+--
+    constant error_int : integer := -1;
+    constant reset_int : std_logic_vector(0 downto 0) := b"0";
+    -- Input registers
+    signal ipr_x : std_logic_vector(7 downto 0);
+
+    -- Iterator registers 
+    signal itr_color : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+    signal itr_j : std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+    signal itr_i : std_logic_vector(CNTR_WIDTH(2)-1 downto 0);
+    --
+
+    --
+    -- Your pipeline signals
+    --
+    -- STAGE_0
+    signal s0_x : std_logic_vector(7 downto 0);
+    signal r0_x : std_logic_vector(7 downto 0);
+    --
+    -- STAGE_1
+    signal s1_x : std_logic_vector(7 downto 0);
+    signal r1_x : std_logic_vector(7 downto 0);
+    --
+    -- STAGE_2
+    signal s2_x : std_logic_vector(7 downto 0);
+    signal r2_x : std_logic_vector(7 downto 0);
+    
+	  signal value1 : integer;
+	  signal value2 : integer;
+	  signal value3 : integer;
+	  signal brightness : integer;
+begin
+
+    PIPE_REGS : process(CLK)
+    begin
+        if rising_edge(CLK) then
+            if (RST='1') then
+                -- Something to reset?
+                					 value1 <= 0;
+					 value2 <= 0;
+					 value3 <= 0;
+            else
+                if( ENi = '1' ) then
+                    -- Input Registers 
+                    ipr_x <= ip_x;
+                    -- Iterator Registers 
+                    itr_color <= it_color;
+                    itr_j <= it_j;
+                    itr_i <= it_i;
+                end if;
+                -- Pipeline Depth: 3 stages
+                -- STAGE_0
+                if( EN(0) = '1' ) then
+                    r0_x <= s0_x;
+                    value1 <= to_integer(signed(ipr_x));		
+                end if;
+                -- STAGE_1
+                if( EN(1) = '1' ) then
+                    r1_x <= s1_x;
+                    value2 <= value1 / 128;
+                end if;
+                -- STAGE_2
+                if( EN(2) = '1' ) then
+                    r2_x <= s2_x;
+                    value3 <= value2 * brightness;
+                end if;
+            end if;
+        end if;
+    end process;    -- PIPE_REGS
+    --
+    -- Output
+    op_return_value <= std_logic_vector(to_signed(value3,op_return_value'length));
+    --
+    -- PIPE_COMB:
+    s0_x <= ipr_x;
+    s1_x <= r0_x;
+    s2_x <= r1_x;
+    --
+    brightness <= to_integer(signed(rf_brightness));
+    --
+    
+    STALL_FRONT  <= (others=>'0');
+    STALL_BACK   <= (others=>'0');
+    ERROR <= '0';
+end RTL;
+
+
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/merge2t32to64.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/merge2t32to64.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a8f2079df4c8f952c61c966e554b4bd8d36815b7
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/merge2t32to64.vhd
@@ -0,0 +1,168 @@
+-- File automatically generated by KpnMapper
+-- This file descibes the orignal Function
+-- Function "merge2t32to64"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+
+entity merge2t32to64 is
+   generic (
+      STIM_DIR   : string  := "bla";
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1;
+      CNTR_QUANT : natural := 32;
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST   : in  std_logic;
+      CLK   : in  std_logic;
+      -- Inputs 
+      ip_in0  : in  std_logic_vector(31 downto 0);
+      ip_in1  : in  std_logic_vector(31 downto 0);
+      EXIST : in  std_logic_vector(1 downto 0);
+      READF : out std_logic_vector(1 downto 0);
+      -- Iterators 
+      it_j : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+      it_i : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+      -- Outputs 
+      op_result : out std_logic_vector(63 downto 0);
+      FULL  : in  std_logic_vector(0 downto 0);
+      WRITEF: out std_logic_vector(0 downto 0);
+      --
+      STOP_RD : in  std_logic;
+      STOP_WR : in  std_logic;
+      ERROR   : out std_logic
+   );
+end merge2t32to64;
+
+architecture RTL of merge2t32to64 is
+
+   component merge2t32to64_pipeline is
+      generic (
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1; 
+         CNTR_QUANT : natural := 32; 
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST   : in std_logic;
+         CLK   : in std_logic;
+         -- Inputs 
+         ip_in0  : in  std_logic_vector(31 downto 0);  
+         ip_in1  : in  std_logic_vector(31 downto 0);  
+         -- Iterators 
+         it_j : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+         it_i : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+         -- Outputs 
+         op_result : out std_logic_vector(63 downto 0);
+
+         ENi   : in  std_logic;
+         EN    : in  std_logic_vector(c_STAGES-1 downto 0);
+         STALL_FRONT  : out std_logic_vector(c_STAGES-1 downto 0);
+         STALL_BACK   : out std_logic_vector(c_STAGES-1 downto 0);
+         ERROR : out std_logic
+      );
+   end component;
+
+   component CONTROLLER is
+      generic ( 
+         N_STAGES  : natural := 1;
+         BLOCKING  : natural := 0
+      ); 
+      port (
+         READ      : out std_logic;
+         EXIST     : in  std_logic;
+         WRITE     : out std_logic;
+         FULL      : in  std_logic;
+         --
+         ENABLE_EX    : out std_logic_vector(N_STAGES-1 downto 0);
+         STALL_FRONT  : in  std_logic_vector(N_STAGES-1 downto 0);
+         STALL_BACK   : in  std_logic_vector(N_STAGES-1 downto 0);
+         --
+         CLK       : in  std_logic;
+         RST       : in  std_logic
+      );
+   end component;
+
+   constant c_BLOCKING : natural := 1;
+
+   signal sl_EXIST : std_logic;
+   signal sl_READ  : std_logic;
+   signal sl_FULL  : std_logic;
+   signal sl_WRITE : std_logic;
+   signal sl_EN    : std_logic_vector(c_STAGES-1 downto 0);
+   signal sl_STALL_FRONT  : std_logic_vector(c_STAGES-1 downto 0);
+   signal sl_STALL_BACK   : std_logic_vector(c_STAGES-1 downto 0);
+   --
+
+
+   --
+
+   --
+
+begin
+
+   -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
+   sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
+   -- Functional Evaluation. Only when all signals are high, we can set READF high.
+   READF    <= (READF'range =>sl_READ);
+   sl_FULL  <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
+   WRITEF   <= (WRITEF'range=>sl_WRITE);
+
+   PIPELINE : merge2t32to64_pipeline
+   generic map (
+         STIM_DIR      => STIM_DIR,
+         c_STAGES      => c_STAGES,
+         N_CNTRS       => N_CNTRS,
+         CNTR_QUANT    => CNTR_QUANT,
+         CNTR_WIDTH    => CNTR_WIDTH
+   )
+   port map (
+      CLK   => CLK,
+      RST   => RST,
+      -- Inputs 
+      ip_in0 => ip_in0,
+      ip_in1 => ip_in1,
+      -- Iterators 
+      it_j => it_j,
+      it_i => it_i,
+      -- Outputs 
+      op_result => op_result,
+      --
+      ENi         => sl_READ,
+      EN          => sl_EN,
+      STALL_FRONT => sl_STALL_FRONT,
+      STALL_BACK  => sl_STALL_BACK,
+      ERROR       => ERROR
+   );
+
+   CTRL : CONTROLLER
+   generic map (
+      N_STAGES   => c_STAGES,
+      BLOCKING   => c_BLOCKING
+   )
+   port map (
+      RST        => RST,
+      CLK        => CLK,
+      READ       => sl_READ,
+      EXIST      => sl_EXIST,
+      --
+      ENABLE_EX   => sl_EN,
+      STALL_FRONT => sl_STALL_FRONT,
+      STALL_BACK  => sl_STALL_BACK,
+      --
+      WRITE      => sl_WRITE,
+      FULL       => sl_FULL
+   );
+
+end RTL;
+
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/merge2t32to64_pipeline.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/merge2t32to64_pipeline.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a232391e3c8a8d16472e070779e6e8a6fdae7349
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/merge2t32to64_pipeline.vhd
@@ -0,0 +1,104 @@
+-- File automatically generated by KpnMapper
+-- This file defines a template for pipelined function implementation
+-- Function "merge2t32to64"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+
+entity merge2t32to64_pipeline is
+   generic (
+      STIM_DIR   : string  := "bla";
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1;
+      CNTR_QUANT : natural := 32;
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST   : in  std_logic;
+      CLK   : in  std_logic;
+      -- Inputs 
+      ip_in0  : in  std_logic_vector(31 downto 0);
+      ip_in1  : in  std_logic_vector(31 downto 0);
+      -- Iterators 
+      it_j : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+      it_i : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+      -- Outputs 
+      op_result : out std_logic_vector(63 downto 0);
+      --
+      ENi   : in  std_logic;
+      EN    : in  std_logic_vector(c_STAGES-1 downto 0);
+      STALL_FRONT  : out std_logic_vector(c_STAGES-1 downto 0);
+      STALL_BACK   : out std_logic_vector(c_STAGES-1 downto 0);
+      ERROR : out std_logic
+   );
+end merge2t32to64_pipeline;
+
+architecture RTL of merge2t32to64_pipeline is
+--
+    constant error_int : integer := -1;
+    constant reset_int : std_logic_vector(0 downto 0) := b"0";
+    -- Input registers
+    signal ipr_in0 : std_logic_vector(31 downto 0);
+
+    signal ipr_in1 : std_logic_vector(31 downto 0);
+
+    -- Iterator registers 
+    signal itr_j : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+    signal itr_i : std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+    --
+
+    --
+    -- Your pipeline signals
+    --
+    -- STAGE_0
+    signal s0_in0 : std_logic_vector(31 downto 0);
+    signal r0_in0 : std_logic_vector(31 downto 0);
+    signal s0_in1 : std_logic_vector(31 downto 0);
+    signal r0_in1 : std_logic_vector(31 downto 0);
+    
+    signal r0_img_i : std_logic_vector(63 downto 0);
+
+begin
+
+    PIPE_REGS : process(CLK)
+    begin
+        if rising_edge(CLK) then
+            if (RST='1') then
+                -- Something to reset?
+            else
+                if( ENi = '1' ) then
+                    -- Input Registers 
+                    ipr_in0 <= ip_in0;
+                    ipr_in1 <= ip_in1;
+                    -- Iterator Registers 
+                    itr_j <= it_j;
+                    itr_i <= it_i;
+                end if;
+                -- Pipeline Depth: 1 stages
+                -- STAGE_0
+                if( EN(0) = '1' ) then                  
+                    r0_img_i(31 downto 0) <= s0_in0;
+                    r0_img_i(63 downto 32) <= s0_in1;
+                end if;
+            end if;
+        end if;
+    end process;    -- PIPE_REGS
+    --
+    -- Output
+    op_result <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_img_i), op_result'Length));
+    --
+    -- PIPE_COMB:
+    s0_in0 <= ipr_in0;
+    s0_in1 <= ipr_in1;
+    --
+    STALL_FRONT  <= (others=>'0');
+    STALL_BACK   <= (others=>'0');
+    ERROR <= '0';
+end RTL;
+
+
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/serialize4t8to32.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/serialize4t8to32.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1b2b7c77684309dcc2d65ca7a930eb3c4e886257
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/serialize4t8to32.vhd
@@ -0,0 +1,176 @@
+-- File automatically generated by KpnMapper
+-- This file descibes the orignal Function
+-- Function "serialize4t8to32"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+
+entity serialize4t8to32 is
+   generic (
+      STIM_DIR   : string  := "bla";
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1;
+      CNTR_QUANT : natural := 32;
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST   : in  std_logic;
+      CLK   : in  std_logic;
+      -- Inputs 
+      ip_in0  : in  std_logic_vector(7 downto 0);
+      ip_in1  : in  std_logic_vector(7 downto 0);
+      ip_in2  : in  std_logic_vector(7 downto 0);
+      ip_in3  : in  std_logic_vector(7 downto 0);
+      EXIST : in  std_logic_vector(3 downto 0);
+      READF : out std_logic_vector(3 downto 0);
+      -- Iterators 
+      it_j : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+      it_i : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+      -- Outputs 
+      op_result : out std_logic_vector(31 downto 0);
+      FULL  : in  std_logic_vector(0 downto 0);
+      WRITEF: out std_logic_vector(0 downto 0);
+      --
+      STOP_RD : in  std_logic;
+      STOP_WR : in  std_logic;
+      ERROR   : out std_logic
+   );
+end serialize4t8to32;
+
+architecture RTL of serialize4t8to32 is
+
+   component serialize4t8to32_pipeline is
+      generic (
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1; 
+         CNTR_QUANT : natural := 32; 
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST   : in std_logic;
+         CLK   : in std_logic;
+         -- Inputs 
+         ip_in0  : in  std_logic_vector(7 downto 0);  
+         ip_in1  : in  std_logic_vector(7 downto 0);  
+         ip_in2  : in  std_logic_vector(7 downto 0);  
+         ip_in3  : in  std_logic_vector(7 downto 0);  
+         -- Iterators 
+         it_j : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+         it_i : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+         -- Outputs 
+         op_result : out std_logic_vector(31 downto 0);
+
+         ENi   : in  std_logic;
+         EN    : in  std_logic_vector(c_STAGES-1 downto 0);
+         STALL_FRONT  : out std_logic_vector(c_STAGES-1 downto 0);
+         STALL_BACK   : out std_logic_vector(c_STAGES-1 downto 0);
+         ERROR : out std_logic
+      );
+   end component;
+
+   component CONTROLLER is
+      generic ( 
+         N_STAGES  : natural := 1;
+         BLOCKING  : natural := 0
+      ); 
+      port (
+         READ      : out std_logic;
+         EXIST     : in  std_logic;
+         WRITE     : out std_logic;
+         FULL      : in  std_logic;
+         --
+         ENABLE_EX    : out std_logic_vector(N_STAGES-1 downto 0);
+         STALL_FRONT  : in  std_logic_vector(N_STAGES-1 downto 0);
+         STALL_BACK   : in  std_logic_vector(N_STAGES-1 downto 0);
+         --
+         CLK       : in  std_logic;
+         RST       : in  std_logic
+      );
+   end component;
+
+   constant c_BLOCKING : natural := 1;
+
+   signal sl_EXIST : std_logic;
+   signal sl_READ  : std_logic;
+   signal sl_FULL  : std_logic;
+   signal sl_WRITE : std_logic;
+   signal sl_EN    : std_logic_vector(c_STAGES-1 downto 0);
+   signal sl_STALL_FRONT  : std_logic_vector(c_STAGES-1 downto 0);
+   signal sl_STALL_BACK   : std_logic_vector(c_STAGES-1 downto 0);
+   --
+
+
+
+
+   --
+
+   --
+
+begin
+
+   -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
+   sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
+   -- Functional Evaluation. Only when all signals are high, we can set READF high.
+   READF    <= (READF'range =>sl_READ);
+   sl_FULL  <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
+   WRITEF   <= (WRITEF'range=>sl_WRITE);
+
+   PIPELINE : serialize4t8to32_pipeline
+   generic map (
+         STIM_DIR      => STIM_DIR,
+         c_STAGES      => c_STAGES,
+         N_CNTRS       => N_CNTRS,
+         CNTR_QUANT    => CNTR_QUANT,
+         CNTR_WIDTH    => CNTR_WIDTH
+   )
+   port map (
+      CLK   => CLK,
+      RST   => RST,
+      -- Inputs 
+      ip_in0 => ip_in0,
+      ip_in1 => ip_in1,
+      ip_in2 => ip_in2,
+      ip_in3 => ip_in3,
+      -- Iterators 
+      it_j => it_j,
+      it_i => it_i,
+      -- Outputs 
+      op_result => op_result,
+      --
+      ENi         => sl_READ,
+      EN          => sl_EN,
+      STALL_FRONT => sl_STALL_FRONT,
+      STALL_BACK  => sl_STALL_BACK,
+      ERROR       => ERROR
+   );
+
+   CTRL : CONTROLLER
+   generic map (
+      N_STAGES   => c_STAGES,
+      BLOCKING   => c_BLOCKING
+   )
+   port map (
+      RST        => RST,
+      CLK        => CLK,
+      READ       => sl_READ,
+      EXIST      => sl_EXIST,
+      --
+      ENABLE_EX   => sl_EN,
+      STALL_FRONT => sl_STALL_FRONT,
+      STALL_BACK  => sl_STALL_BACK,
+      --
+      WRITE      => sl_WRITE,
+      FULL       => sl_FULL
+   );
+
+end RTL;
+
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/serialize4t8to32_pipeline.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/serialize4t8to32_pipeline.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4708552435b85ea129efd7bf8e0fa54e17e26037
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/serialize4t8to32_pipeline.vhd
@@ -0,0 +1,120 @@
+-- File automatically generated by KpnMapper
+-- This file defines a template for pipelined function implementation
+-- Function "serialize4t8to32"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+
+entity serialize4t8to32_pipeline is
+   generic (
+      STIM_DIR   : string  := "bla";
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1;
+      CNTR_QUANT : natural := 32;
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST   : in  std_logic;
+      CLK   : in  std_logic;
+      -- Inputs 
+      ip_in0  : in  std_logic_vector(7 downto 0);
+      ip_in1  : in  std_logic_vector(7 downto 0);
+      ip_in2  : in  std_logic_vector(7 downto 0);
+      ip_in3  : in  std_logic_vector(7 downto 0);
+      -- Iterators 
+      it_j : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+      it_i : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+      -- Outputs 
+      op_result : out std_logic_vector(31 downto 0);
+      --
+      ENi   : in  std_logic;
+      EN    : in  std_logic_vector(c_STAGES-1 downto 0);
+      STALL_FRONT  : out std_logic_vector(c_STAGES-1 downto 0);
+      STALL_BACK   : out std_logic_vector(c_STAGES-1 downto 0);
+      ERROR : out std_logic
+   );
+end serialize4t8to32_pipeline;
+
+architecture RTL of serialize4t8to32_pipeline is
+--
+    constant error_int : integer := -1;
+    constant reset_int : std_logic_vector(0 downto 0) := b"0";
+    -- Input registers
+    signal ipr_in0 : std_logic_vector(7 downto 0);
+
+    signal ipr_in1 : std_logic_vector(7 downto 0);
+
+    signal ipr_in2 : std_logic_vector(7 downto 0);
+
+    signal ipr_in3 : std_logic_vector(7 downto 0);
+
+    -- Iterator registers 
+    signal itr_j : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+    signal itr_i : std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+    --
+
+    --
+    -- Your pipeline signals
+    --
+    -- STAGE_0
+    signal s0_in0 : std_logic_vector(7 downto 0);
+    signal r0_in0 : std_logic_vector(7 downto 0);
+    signal s0_in1 : std_logic_vector(7 downto 0);
+    signal r0_in1 : std_logic_vector(7 downto 0);
+    signal s0_in2 : std_logic_vector(7 downto 0);
+    signal r0_in2 : std_logic_vector(7 downto 0);
+    signal s0_in3 : std_logic_vector(7 downto 0);
+    signal r0_in3 : std_logic_vector(7 downto 0);
+
+	signal r0_img_i : std_logic_vector(31 downto 0);
+	
+begin
+
+    PIPE_REGS : process(CLK)
+    begin
+        if rising_edge(CLK) then
+            if (RST='1') then
+                -- Something to reset?
+            else
+                if( ENi = '1' ) then
+                    -- Input Registers 
+                    ipr_in0 <= ip_in0;
+                    ipr_in1 <= ip_in1;
+                    ipr_in2 <= ip_in2;
+                    ipr_in3 <= ip_in3;
+                    -- Iterator Registers 
+                    itr_j <= it_j;
+                    itr_i <= it_i;
+                end if;
+                -- Pipeline Depth: 1 stages
+                -- STAGE_0
+                if( EN(0) = '1' ) then
+                    r0_img_i(7 downto 0) <= s0_in0;
+                    r0_img_i(15 downto 8) <= s0_in1;
+                    r0_img_i(23 downto 16) <= s0_in2;
+                    r0_img_i(31 downto 24) <= s0_in3;
+                end if;
+            end if;
+        end if;
+    end process;    -- PIPE_REGS
+    --
+    -- Output
+    op_result <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_img_i), op_result'Length));
+    --
+    -- PIPE_COMB:
+    s0_in0 <= ipr_in0;
+    s0_in1 <= ipr_in1;
+    s0_in2 <= ipr_in2;
+    s0_in3 <= ipr_in3;
+    --
+    STALL_FRONT  <= (others=>'0');
+    STALL_BACK   <= (others=>'0');
+    ERROR <= '0';
+end RTL;
+
+
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/split64to2t32.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/split64to2t32.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b01aab04c5a9738faed31d9dfc9342e6446d83a3
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/split64to2t32.vhd
@@ -0,0 +1,168 @@
+-- File automatically generated by KpnMapper
+-- This file descibes the orignal Function
+-- Function "split64to2t32"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+
+entity split64to2t32 is
+   generic (
+      STIM_DIR   : string  := "bla";
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1;
+      CNTR_QUANT : natural := 32;
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST   : in  std_logic;
+      CLK   : in  std_logic;
+      -- Inputs 
+      ip_stimin  : in  std_logic_vector(63 downto 0);
+      EXIST : in  std_logic_vector(0 downto 0);
+      READF : out std_logic_vector(0 downto 0);
+      -- Iterators 
+      it_j : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+      it_i : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+      -- Outputs 
+      op_out0 : out std_logic_vector(31 downto 0);
+      op_out1 : out std_logic_vector(31 downto 0);
+      FULL  : in  std_logic_vector(1 downto 0);
+      WRITEF: out std_logic_vector(1 downto 0);
+      --
+      STOP_RD : in  std_logic;
+      STOP_WR : in  std_logic;
+      ERROR   : out std_logic
+   );
+end split64to2t32;
+
+architecture RTL of split64to2t32 is
+
+   component split64to2t32_pipeline is
+      generic (
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1; 
+         CNTR_QUANT : natural := 32; 
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST   : in std_logic;
+         CLK   : in std_logic;
+         -- Inputs 
+         ip_stimin  : in  std_logic_vector(63 downto 0);  
+         -- Iterators 
+         it_j : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+         it_i : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+         -- Outputs 
+         op_out0 : out std_logic_vector(31 downto 0);
+         op_out1 : out std_logic_vector(31 downto 0);
+
+         ENi   : in  std_logic;
+         EN    : in  std_logic_vector(c_STAGES-1 downto 0);
+         STALL_FRONT  : out std_logic_vector(c_STAGES-1 downto 0);
+         STALL_BACK   : out std_logic_vector(c_STAGES-1 downto 0);
+         ERROR : out std_logic
+      );
+   end component;
+
+   component CONTROLLER is
+      generic ( 
+         N_STAGES  : natural := 1;
+         BLOCKING  : natural := 0
+      ); 
+      port (
+         READ      : out std_logic;
+         EXIST     : in  std_logic;
+         WRITE     : out std_logic;
+         FULL      : in  std_logic;
+         --
+         ENABLE_EX    : out std_logic_vector(N_STAGES-1 downto 0);
+         STALL_FRONT  : in  std_logic_vector(N_STAGES-1 downto 0);
+         STALL_BACK   : in  std_logic_vector(N_STAGES-1 downto 0);
+         --
+         CLK       : in  std_logic;
+         RST       : in  std_logic
+      );
+   end component;
+
+   constant c_BLOCKING : natural := 1;
+
+   signal sl_EXIST : std_logic;
+   signal sl_READ  : std_logic;
+   signal sl_FULL  : std_logic;
+   signal sl_WRITE : std_logic;
+   signal sl_EN    : std_logic_vector(c_STAGES-1 downto 0);
+   signal sl_STALL_FRONT  : std_logic_vector(c_STAGES-1 downto 0);
+   signal sl_STALL_BACK   : std_logic_vector(c_STAGES-1 downto 0);
+   --
+
+   --
+
+
+   --
+
+begin
+
+   -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
+   sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
+   -- Functional Evaluation. Only when all signals are high, we can set READF high.
+   READF    <= (READF'range =>sl_READ);
+   sl_FULL  <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
+   WRITEF   <= (WRITEF'range=>sl_WRITE);
+
+   PIPELINE : split64to2t32_pipeline
+   generic map (
+         STIM_DIR      => STIM_DIR,
+         c_STAGES      => c_STAGES,
+         N_CNTRS       => N_CNTRS,
+         CNTR_QUANT    => CNTR_QUANT,
+         CNTR_WIDTH    => CNTR_WIDTH
+   )
+   port map (
+      CLK   => CLK,
+      RST   => RST,
+      -- Inputs 
+      ip_stimin => ip_stimin,
+      -- Iterators 
+      it_j => it_j,
+      it_i => it_i,
+      -- Outputs 
+      op_out0 => op_out0,
+      op_out1 => op_out1,
+      --
+      ENi         => sl_READ,
+      EN          => sl_EN,
+      STALL_FRONT => sl_STALL_FRONT,
+      STALL_BACK  => sl_STALL_BACK,
+      ERROR       => ERROR
+   );
+
+   CTRL : CONTROLLER
+   generic map (
+      N_STAGES   => c_STAGES,
+      BLOCKING   => c_BLOCKING
+   )
+   port map (
+      RST        => RST,
+      CLK        => CLK,
+      READ       => sl_READ,
+      EXIST      => sl_EXIST,
+      --
+      ENABLE_EX   => sl_EN,
+      STALL_FRONT => sl_STALL_FRONT,
+      STALL_BACK  => sl_STALL_BACK,
+      --
+      WRITE      => sl_WRITE,
+      FULL       => sl_FULL
+   );
+
+end RTL;
+
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/split64to2t32_pipeline.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/split64to2t32_pipeline.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d1580704ee4c75ad81771ac450bcca876ec3b4d3
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/split64to2t32_pipeline.vhd
@@ -0,0 +1,101 @@
+-- File automatically generated by KpnMapper
+-- This file defines a template for pipelined function implementation
+-- Function "split64to2t32"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+
+entity split64to2t32_pipeline is
+   generic (
+      STIM_DIR   : string  := "bla";
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1;
+      CNTR_QUANT : natural := 32;
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST   : in  std_logic;
+      CLK   : in  std_logic;
+      -- Inputs 
+      ip_stimin  : in  std_logic_vector(63 downto 0);
+      -- Iterators 
+      it_j : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+      it_i : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+      -- Outputs 
+      op_out0 : out std_logic_vector(31 downto 0);
+      op_out1 : out std_logic_vector(31 downto 0);
+      --
+      ENi   : in  std_logic;
+      EN    : in  std_logic_vector(c_STAGES-1 downto 0);
+      STALL_FRONT  : out std_logic_vector(c_STAGES-1 downto 0);
+      STALL_BACK   : out std_logic_vector(c_STAGES-1 downto 0);
+      ERROR : out std_logic
+   );
+end split64to2t32_pipeline;
+
+architecture RTL of split64to2t32_pipeline is
+--
+    constant error_int : integer := -1;
+    constant reset_int : std_logic_vector(0 downto 0) := b"0";
+    -- Input registers
+    signal ipr_stimin : std_logic_vector(63 downto 0);
+
+    -- Iterator registers 
+    signal itr_j : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+    signal itr_i : std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+    --
+
+	signal r0_img_i_0 : std_logic_vector(31 downto 0);
+    signal r0_img_i_1 : std_logic_vector(31 downto 0);
+    
+    --
+    -- Your pipeline signals
+    --
+    -- STAGE_0
+    signal s0_stimin : std_logic_vector(63 downto 0);
+    signal r0_stimin : std_logic_vector(63 downto 0);
+
+begin
+
+    PIPE_REGS : process(CLK)
+    begin
+        if rising_edge(CLK) then
+            if (RST='1') then
+                -- Something to reset?
+            else
+                if( ENi = '1' ) then
+                    -- Input Registers 
+                    ipr_stimin <= ip_stimin;
+                    -- Iterator Registers 
+                    itr_j <= it_j;
+                    itr_i <= it_i;
+                end if;
+                -- Pipeline Depth: 1 stages
+                -- STAGE_0
+                if( EN(0) = '1' ) then
+                    -- r0_stimin <= s0_stimin;
+                    r0_img_i_0 <= s0_stimin(31 downto 0);
+                    r0_img_i_1 <= s0_stimin(63 downto 32);
+                end if;
+            end if;
+        end if;
+    end process;    -- PIPE_REGS
+    --
+    -- Output
+    op_out0 <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_img_i_0), op_out0'Length));
+    op_out1 <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(r0_img_i_1), op_out1'Length));
+    --
+    -- PIPE_COMB:
+    s0_stimin <= ipr_stimin;
+    --
+    STALL_FRONT  <= (others=>'0');
+    STALL_BACK   <= (others=>'0');
+    ERROR <= '0';
+end RTL;
+
+
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_10/hdllib.cfg b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_10/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..de57a3d2bdd28e8bb8915b8fd954db4c80bdc6ac
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_10/hdllib.cfg
@@ -0,0 +1,18 @@
+hdl_lib_name = compaandesign_com_bunny_static_split2rtl_hwn_nd_10_1
+hdl_library_clause_name = compaandesign_com_bunny_static_split2rtl_hwn_nd_10_1_lib
+hdl_lib_uses_synth = compaandesign_com_bunny_static_split2rtl_functions_1 compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1 compaandesign_com_common_extern_connector_1 
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+	src/vhdl/bunny_static_split2rtl_hwn_nd_10_execution_unit.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_10_eval_logic_rd.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_10_eval_logic_wr.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_10.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_10/src/vhdl/bunny_static_split2rtl_hwn_nd_10.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_10/src/vhdl/bunny_static_split2rtl_hwn_nd_10.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c45903b92bb1d6e58968d48bea6139bef5e5b01f
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_10/src/vhdl/bunny_static_split2rtl_hwn_nd_10.vhd
@@ -0,0 +1,500 @@
+-- HWN Entity File automatically generated by KpnMapper (writeHdlHWNodeFile)
+-- Top level file for a Hardware Accelerator
+-- Function "compaan_outlinedproc4"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+library compaandesign_com_common_extern_connector_1_lib;
+use compaandesign_com_common_extern_connector_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_10 is
+   generic (
+      STIM_DIR   : string  := "bla";
+      RESET_HIGH : natural := 1;
+      PAR_WIDTH  : natural := 16;
+      QUANT      : natural := 32;
+      WRAP       : boolean := true
+   );
+   port (
+
+      -- Dataflow input interfaces
+      -- ED_11 : in_0
+      ND_10IP_11_Rd    : out std_logic;
+      ND_10IP_11_Din   : in  std_logic_vector(7 downto 0);
+      ND_10IP_11_Exist : in  std_logic; 
+      ND_10IP_11_CLK   : out std_logic;
+      ND_10IP_11_CTRL  : in  std_logic;
+
+      -- ED_12 : in_0
+      ND_10IP_12_Rd    : out std_logic;
+      ND_10IP_12_Din   : in  std_logic_vector(7 downto 0);
+      ND_10IP_12_Exist : in  std_logic; 
+      ND_10IP_12_CLK   : out std_logic;
+      ND_10IP_12_CTRL  : in  std_logic;
+
+      -- Dataflow Control Input interfaces
+      -- Dataflow output interfaces
+      -- ED_13 : out_0
+      ND_10OP_1_Wr   : out std_logic;
+      ND_10OP_1_Dout : out std_logic_vector(7 downto 0);
+      ND_10OP_1_Full : in  std_logic;
+      ND_10OP_1_CLK  : out std_logic;
+      ND_10OP_1_CTRL : out std_logic;
+
+      -- ED_14 : out_0
+      ND_10OP_1_d1_Wr   : out std_logic;
+      ND_10OP_1_d1_Dout : out std_logic_vector(7 downto 0);
+      ND_10OP_1_d1_Full : in  std_logic;
+      ND_10OP_1_d1_CLK  : out std_logic;
+      ND_10OP_1_d1_CTRL : out std_logic;
+
+      -- ED_15 : out_0
+      ND_10OP_1_d2_Wr   : out std_logic;
+      ND_10OP_1_d2_Dout : out std_logic_vector(7 downto 0);
+      ND_10OP_1_d2_Full : in  std_logic;
+      ND_10OP_1_d2_CLK  : out std_logic;
+      ND_10OP_1_d2_CTRL : out std_logic;
+
+      PARAM_DT : in  std_logic_vector(PAR_WIDTH+10-1 downto 0);
+      PARAM_LD : in  std_logic;
+
+      RST      : in  std_logic;
+      CLK      : in  std_logic;
+      STOP     : out std_logic;
+      ERROR    : out std_logic;
+      BLOCK_RD : out std_logic
+   );
+end bunny_static_split2rtl_hwn_nd_10;
+
+architecture RTL of bunny_static_split2rtl_hwn_nd_10 is
+   --
+   -- ====================================
+   -- =     Constants declaration        =
+   -- ====================================
+   -- Setting the parameters of the HW Node
+   constant c_IN_PORTS     : natural := 2; -- number of input ports of a HW node
+   constant c_OUT_PORTS    : natural := 3; -- number of output ports of a HW node
+   constant c_IN_FUNC_VAR  : natural := 1; -- number of input ports of a HW IP
+   constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
+   constant c_COUNTERS     : natural := 3; -- number of iterators
+   -- ===========================================
+   -- = Iterators run from Inner to Outer loop  =
+   -- ===========================================
+   constant c_CNTR_QUANT   : natural := 11;
+   constant c_CNTR_STEPS   : t_counter_step  := ( 0=>1, 1=>1, 2=>1, others=>1 );
+   constant c_CNTR_WIDTHS  : t_counter_width := ( 0=>3, 1=>11, 2=>10, others=>10 );
+   constant c_STAGES       : natural := 1; -- number of pipeline stages or delay
+   constant c_IP_RESET     : natural := 1; -- active level of the HW IP reset signal
+   constant c_WRAP         : boolean := WRAP; -- Operation mode: Single_Shot (false) or Continuous (true)
+   constant c_EXT_PAR      : natural := 0; -- number of external parameters
+   constant c_INT_PAR      : natural := 0; -- number of internal parameters
+   constant c_N_PAR        : natural := 0; -- no parameters are used
+   constant c_PAR_BITWIDTH : natural := PAR_WIDTH; -- aggregate bitwidth of the parameter vector
+   constant c_PAR_VECTOR   : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
+       (0,0,0,0), (0,0,0,0)    -- two dummy elements
+   );
+   --
+   -- ====================================
+   -- =     Components declaration       =
+   -- ====================================
+   component bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_10 is
+      generic (
+         N_IN_PORTS    : natural := 1;
+         WRAP          : boolean := true;
+         N_CNTRS       : natural := 1; 
+         QUANT         : natural := 32;
+         PAR_BITWIDTH  : natural :=1;
+         CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+         CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+      );
+      port (
+         RST           : in  std_logic;
+         CLK           : in  std_logic;
+         REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1  downto 0); 
+         READ_EN       : out std_logic_vector(c_IN_FUNC_VAR-1  downto 0);
+         READ_ST       : in  std_logic_vector(c_IN_FUNC_VAR-1  downto 0);
+         HALT          : in  std_logic;
+         FIRE          : out std_logic;
+         DONE          : out std_logic;
+         STOP          : out std_logic;
+         CONTROL       : out std_logic_vector(N_IN_PORTS-1 downto 0);
+         OBTAIN        : out std_logic_vector(N_IN_PORTS-1 downto 0);
+         RELEASE       : out std_logic_vector(N_IN_PORTS-1 downto 0)
+      );
+   end component;
+
+   component READ_MUX is
+      generic (
+         N_PORTS    : natural := 1;
+         PORT_WIDTH : natural := 32  
+      );
+      port(
+         IN_PORTS   : in  std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
+         EXISTS     : in  std_logic_vector(N_PORTS-1 downto 0);
+         READS      : out std_logic_vector(N_PORTS-1 downto 0);
+         SOFS       : in  std_logic_vector(N_PORTS-1 downto 0);
+
+         OUT_PORT   : out std_logic_vector(PORT_WIDTH-1 downto 0);
+         EXIST      : out std_logic;
+         READ       : in  std_logic;
+         SOF        : in  std_logic;
+		CLK        : in std_logic;
+
+         READ_EN    : in  std_logic;
+         READ_ST    : out std_logic;
+         CONTROL    : in  std_logic_vector(N_PORTS-1 downto 0);
+         OBTAIN     : in  std_logic_vector(N_PORTS-1 downto 0);
+         RELEASE    : in  std_logic_vector(N_PORTS-1 downto 0)
+      );
+   end component;
+
+   component bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_10 is
+      generic ( 
+         N_OUT_PORTS   : natural := 1;
+         WRAP          : boolean := true;
+         N_CNTRS       : natural := 1; 
+         QUANT         : natural := 32;
+         PAR_BITWIDTH  : natural :=1;
+         CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+         CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+      );
+      port (
+         RST           : in  std_logic;
+         CLK           : in  std_logic;
+         WRITE_EN      : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+         WRITE_ST      : in  std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+         HALT          : in  std_logic;
+         FIRE          : out std_logic;
+         DONE          : out std_logic;
+         STOP          : out std_logic;
+         CONTROL       : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+      );
+   end component;
+
+   component WRITE_DEMUX is
+      generic (
+         N_PORTS : natural := 1
+      );
+      port(
+         WRITES   : out std_logic_vector(N_PORTS-1 downto 0);
+         WRITE    : in  std_logic;
+
+         FULLS    : in  std_logic_vector(N_PORTS-1 downto 0);
+         FULL     : out std_logic;
+
+         WRITE_EN : in  std_logic;
+         WRITE_ST : out std_logic;
+         CONTROL  : in  std_logic_vector(N_PORTS-1 downto 0)
+      );
+   end component;
+
+
+   component bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_10 is
+      generic (
+         N_INPORTS  : natural := 1;
+         N_OUTPORTS : natural := 1;
+         IP_RESET   : natural := 1;
+         QUANT      : natural := 32;
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1;
+         CNTR_QUANT : natural := 32;
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST        : in  std_logic;
+         CLK        : in  std_logic;
+
+         -- Iterators
+         REG_CNTRS_RD : in  std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
+         -- Func. Input parameters
+         IN_PORT_0 : in  std_logic_vector(7 downto 0); -- tmp1
+         READ       : out std_logic_vector(N_INPORTS-1 downto 0);
+         EXIST      : in  std_logic_vector(N_INPORTS-1 downto 0);
+         -- Func. Output parameters
+         OUT_PORT_0 : out std_logic_vector(7 downto 0); -- tmp0
+         WRITE      : out std_logic_vector(N_OUTPORTS-1 downto 0);
+         FULL       : in  std_logic_vector(N_OUTPORTS-1 downto 0);
+         --
+         STOP_RD    : in  std_logic;
+         STOP_WR    : in  std_logic;
+         ERROR      : out std_logic
+      );
+   end component;
+
+   component INTERNAL_PARAMETERS is 
+      generic (
+         PAR_BITWIDTH : natural:=1;
+         PAR_VECTOR   : t_par_vector;
+         N_PAR        : natural:=0;
+         START_IN_RUN  : boolean := FALSE
+      );
+      port (  
+         RST        : in  std_logic;
+         CLK        : in  std_logic;
+
+         HALT_RD    : out std_logic;
+         HALT_WR    : out std_logic;
+         SOF_RD     : in  std_logic;
+         SOF_WR     : in  std_logic;
+         LOAD_PARAM : out std_logic;
+
+         par_one_in_Rd    : out std_logic;
+         par_one_in_Din   : in std_logic_vector(32-1 downto 0);
+         par_one_in_Exist : in std_logic;
+         par_one_in_CLK   : out std_logic;
+         par_one_in_CTRL  : in std_logic;
+
+         PARAMETERS_RD : out std_logic_vector(32-1 downto 0);
+         PARAMETERS_WR : out std_logic_vector(32-1 downto 0)
+      );
+   end component;
+
+   --
+   -- ====================================
+   -- =       Signals declaration        =
+   -- ====================================
+   -- 
+   -- HW Node Input Ports
+   signal sl_IN_PORTS_0   : std_logic_vector(2*8-1 downto 0); -- tmp1
+   signal sl_EXISTS       : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_READS        : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_CTRLS        : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_control_rd   : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_obtain_rd    : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_release_rd   : std_logic_vector(c_IN_PORTS-1 downto 0);
+   -- 
+   -- Func. Input parameters
+   signal sl_in_port_0    : std_logic_vector(7 downto 0); -- tmp1
+   signal sl_exist        : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read         : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read_en      : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read_st      : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   -- 
+   signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
+   -- 
+   -- HW Node Output Ports
+   signal sl_WRITES       : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_FULLS        : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_control_wr   : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_lortnoc_wr   : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   -- 
+   -- Func. Output parameters
+   signal sl_out_port_0   : std_logic_vector(7 downto 0); -- tmp0
+   signal sl_full         : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write        : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write_en     : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write_st     : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   -- 
+   -- 
+   signal sl_halt             : std_logic;
+   signal sl_halted           : std_logic;
+   signal sl_halt_wr          : std_logic;
+   signal sl_halt_rd          : std_logic;
+   signal sl_param_halt_wr    : std_logic;
+   signal sl_param_halt_rd    : std_logic;
+   signal sl_done_wr          : std_logic;
+   signal sl_done_rd          : std_logic;
+   signal sl_stop_wr          : std_logic;
+   signal sl_stop_rd          : std_logic;
+   signal sl_fire_wr          : std_logic;
+   signal sl_fire_rd          : std_logic;
+   signal sl_sof_wr           : std_logic;
+   signal sl_sof_rd           : std_logic;
+   signal sl_error            : std_logic;
+   signal sl_load_param       : std_logic;
+
+   --  
+   -- Parameter related signals 
+   signal sl_param_fifo_full     : std_logic;
+   signal sl_sync_num            : std_logic_vector(9 downto 0);
+
+   signal sl_RST : std_logic;
+
+begin 
+
+   sl_RST <= RST when RESET_HIGH=1 else not RST;
+      ND_10IP_11_CLK   <= CLK;
+      ND_10IP_12_CLK   <= CLK;
+      ND_10OP_1_CLK  <= CLK;
+      ND_10OP_1_d1_CLK  <= CLK;
+      ND_10OP_1_d2_CLK  <= CLK;
+
+   --
+   -- ==========================================================
+   -- =       HWN Input related modules                        =
+   -- ==========================================================
+   -- Func. Input param. "tmp1"
+   RD_MUX_0 : READ_MUX
+   generic map (
+      N_PORTS    => 2,
+      PORT_WIDTH => 8
+   )
+   port map (
+      IN_PORTS   => sl_IN_PORTS_0,
+      EXISTS     => sl_EXISTS(1 downto 0),
+      READS      => sl_READS(1 downto 0),
+      SOFS       => sl_CTRLS(1 downto 0),
+
+      OUT_PORT   => sl_in_port_0,
+      EXIST      => sl_exist(0),
+      READ       => sl_read(0),
+      SOF        => sl_sof_rd,
+      CLK        => CLK,
+
+      READ_EN    => sl_read_en(0),
+      READ_ST    => sl_read_st(0),
+      CONTROL    => sl_control_rd(1 downto 0),
+      OBTAIN     => sl_obtain_rd(1 downto 0),
+      RELEASE    => sl_release_rd(1 downto 0)
+   );
+
+   ND_10IP_11_Rd   <= sl_READS(0);
+   ND_10IP_12_Rd   <= sl_READS(1);
+
+   sl_IN_PORTS_0 <= ND_10IP_12_Din & ND_10IP_11_Din;
+
+   sl_EXISTS      <= ND_10IP_12_Exist & ND_10IP_11_Exist ;
+   sl_CTRLS       <= ND_10IP_12_CTRL & ND_10IP_11_CTRL ;
+
+   EVAL_RD : bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_10
+   generic map ( 
+      N_IN_PORTS    => c_IN_PORTS,
+      WRAP          => c_WRAP,
+      N_CNTRS       => c_COUNTERS,
+      QUANT         => c_CNTR_QUANT,
+      PAR_BITWIDTH  => c_PAR_BITWIDTH,
+      CNTR_STEP     => c_CNTR_STEPS,
+      CNTR_WIDTH    => c_CNTR_WIDTHS
+   )
+   port map(
+      RST           => sl_RST,
+      CLK           => CLK,
+      REG_CNTRS     => sl_REG_CNTRS_RD,
+      READ_EN       => sl_read_en,
+      READ_ST       => sl_read_st,
+      HALT          => sl_halt_rd,
+      FIRE          => sl_fire_rd,
+      DONE          => sl_done_rd,
+      STOP          => sl_stop_rd,
+      CONTROL       => sl_control_rd,
+      OBTAIN        => sl_obtain_rd,
+      RELEASE       => sl_release_rd
+   );
+
+   --
+   -- ==========================================================
+   -- =       HWN Output related modules                       =
+   -- ==========================================================
+   -- 
+   -- Func. Output param. "tmp0"
+   DEMUX_0 : WRITE_DEMUX
+   generic map (
+      N_PORTS => 3
+   )
+   port map (
+      WRITES   => sl_WRITES(2 downto 0),
+      FULLS    => sl_FULLS(2 downto 0),
+      CONTROL  => sl_lortnoc_wr(2 downto 0),
+      WRITE    => sl_write(0),
+      FULL     => sl_full(0),
+      WRITE_EN => sl_write_en(0),
+      WRITE_ST => sl_write_st(0)
+   );
+   --
+   ND_10OP_1_Dout <= sl_out_port_0;  -- Func. Output param. "tmp0"
+   ND_10OP_1_CTRL <= sl_sof_wr ;
+   ND_10OP_1_Wr   <= sl_WRITES(0);
+   sl_FULLS(0) <= ND_10OP_1_Full;
+   sl_lortnoc_wr(0) <= sl_control_wr(0);
+   --
+   ND_10OP_1_d1_Dout <= sl_out_port_0;  -- Func. Output param. "tmp0"
+   ND_10OP_1_d1_CTRL <= sl_sof_wr ;
+   ND_10OP_1_d1_Wr   <= sl_WRITES(1);
+   sl_FULLS(1) <= ND_10OP_1_d1_Full;
+   sl_lortnoc_wr(1) <= sl_control_wr(1);
+   --
+   ND_10OP_1_d2_Dout <= sl_out_port_0;  -- Func. Output param. "tmp0"
+   ND_10OP_1_d2_CTRL <= sl_sof_wr ;
+   ND_10OP_1_d2_Wr   <= sl_WRITES(2);
+   sl_FULLS(2) <= ND_10OP_1_d2_Full;
+   sl_lortnoc_wr(2) <= sl_control_wr(2);
+   --
+   --
+   EVAL_WR : bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_10
+   generic map ( 
+      N_OUT_PORTS   => c_OUT_PORTS,
+      WRAP          => c_WRAP,
+      N_CNTRS       => c_COUNTERS,
+      QUANT         => c_CNTR_QUANT,
+      PAR_BITWIDTH  => c_PAR_BITWIDTH,
+      CNTR_STEP     => c_CNTR_STEPS,
+      CNTR_WIDTH    => c_CNTR_WIDTHS
+   )
+   port map (
+      RST           => sl_RST,
+      CLK           => CLK,
+      WRITE_EN      => sl_write_en,
+      WRITE_ST      => sl_write_st,
+      HALT          => sl_halt_wr,
+      FIRE          => sl_fire_wr,
+      DONE          => sl_done_wr,
+      STOP          => sl_stop_wr,
+      CONTROL       => sl_control_wr
+   );
+
+   --
+   -- ==========================================================
+   -- =       HWN Execution Unit                               =
+   -- ==========================================================
+   EX : bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_10
+   generic map (
+      N_INPORTS  => c_IN_FUNC_VAR,
+      N_OUTPORTS => c_OUT_FUNC_VAR, 
+      IP_RESET   => c_IP_RESET,
+      QUANT      => QUANT,
+      STIM_DIR   => STIM_DIR,
+      c_STAGES   => c_STAGES,
+      N_CNTRS    => c_COUNTERS,
+      CNTR_QUANT => c_CNTR_QUANT,
+      CNTR_WIDTH => c_CNTR_WIDTHS
+   )
+   port map (
+      RST        => sl_RST,
+      CLK        => CLK,
+      -- Iterators
+      REG_CNTRS_RD => sl_REG_CNTRS_RD,
+      -- Func. Input parameters
+      IN_PORT_0    => sl_in_port_0,
+      READ       => sl_read,
+      EXIST      => sl_exist,
+      -- Func. Output parameters
+      OUT_PORT_0   => sl_out_port_0,
+      WRITE      => sl_write,
+      FULL       => sl_full,
+      --
+      STOP_WR    => sl_stop_wr,
+      STOP_RD    => sl_stop_rd,
+      ERROR      => sl_error
+   );
+
+   -- ==========================================================
+   -- =       PARAMETERIZATION                                 =
+   -- ==========================================================
+   -- no parameters
+   sl_halt_rd <= '0';
+   sl_halt_wr <= '0';
+--   sl_halted  <= sl_sof_rd;
+   STOP <= sl_done_wr;
+   ERROR <= sl_error;
+   BLOCK_RD <= not (  (  sl_READS(0) or   sl_READS(1)  ) );
+
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_10/src/vhdl/bunny_static_split2rtl_hwn_nd_10_eval_logic_rd.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_10/src/vhdl/bunny_static_split2rtl_hwn_nd_10_eval_logic_rd.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1cbe7470d57499303c26af8e2bd0d77ec1e886c4
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_10/src/vhdl/bunny_static_split2rtl_hwn_nd_10_eval_logic_rd.vhd
@@ -0,0 +1,320 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_10 is
+   generic (
+      N_IN_PORTS    : natural := 1;
+      WRAP          : boolean := true;
+      N_CNTRS       : natural := 1; 
+      QUANT         : natural := 32;
+      PAR_BITWIDTH  : natural  :=1;
+      CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+      CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST           : in  std_logic;
+      CLK           : in  std_logic;
+      REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+      READ_EN       : out std_logic_vector(0 downto 0);
+      READ_ST       : in  std_logic_vector(0 downto 0);
+      HALT          : in  std_logic;
+      FIRE          : out std_logic;
+      DONE          : out std_logic;
+      STOP          : out std_logic;
+      CONTROL       : out std_logic_vector(N_IN_PORTS-1 downto 0);
+      OBTAIN        : out std_logic_vector(N_IN_PORTS-1 downto 0);
+      RELEASE       : out std_logic_vector(N_IN_PORTS-1 downto 0)
+   );
+end bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_10;
+
+architecture RTL of bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_10 is
+   -- 
+   component counter is 
+      generic( 
+         C_STEP    : natural := 10; 
+         C_WIDTH   : natural := 10 
+      ); 
+      port ( 
+         RST       : in  std_logic; 
+         CLK       : in  std_logic; 
+         ENABLE    : in  std_logic; 
+         LOAD      : in  std_logic; 
+         LOWER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         UPPER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         ITERATOR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         REG_CNTR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         DONE      : out std_logic 
+      ); 
+   end component; 
+   -- 
+   component it_mod is 
+   generic( 
+      C_MOD     : natural := 10; 
+      C_WIDTH   : natural := 10; 
+      C_INIT    : natural :=  1; 
+      C_STEP    : natural :=  1  
+   ); 
+   port ( 
+      RST       : in  std_logic; 
+      CLK       : in  std_logic; 
+      LOAD      : in  std_logic; 
+      ENABLE    : in  std_logic; 
+      MODULE    : out std_logic_vector(C_WIDTH-1 downto 0) 
+   ); 
+   end component; 
+   -- 
+   --  
+   -- Parameter related signals 
+   -- 
+   -- Iterator (counter) related signals 
+   signal sl_low_i, sl_high_i : integer;
+   signal sl_low_j, sl_high_j : integer;
+   signal sl_low_color, sl_high_color : integer;
+   signal sl_loop_i, sl_loop_i_rg : integer;
+   signal sl_loop_j, sl_loop_j_rg : integer;
+   signal sl_loop_color, sl_loop_color_rg : integer;
+   signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   -- 
+   signal sl_cntr_en  : std_logic_vector(N_CNTRS   downto 0); 
+   signal sl_done     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_done_all : std_logic; 
+   signal sl_load     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_stop     : std_logic; 
+   signal sl_fire     : std_logic; 
+   signal sl_sof      : std_logic; 
+   signal sl_eof      : std_logic; 
+   signal sl_count    : std_logic; 
+
+   -- alias signals 
+   alias update_i : std_logic is sl_cntr_en(2);
+   alias update_j : std_logic is sl_cntr_en(1);
+   alias update_color : std_logic is sl_cntr_en(0);
+   alias load_i : std_logic is sl_load(2);
+   alias load_j : std_logic is sl_load(1);
+   alias load_color : std_logic is sl_load(0);
+
+   -- Trigger signals 
+   signal sl_trigger_i : std_logic;
+   signal sl_trigger_j : std_logic;
+   signal sl_trigger_color : std_logic;
+
+   -- Special Control signal
+   signal sl_CONTROL       : std_logic_vector(N_IN_PORTS-1 downto 0);
+   signal sl_no_request    : std_logic;
+   -- 
+   -- Multirate related signals
+   signal sl_bla_en   : std_logic_vector(0 downto 0); 
+   signal sl_mr_en    : std_logic_vector(0 downto 0); 
+   signal sl_mr_done  : std_logic_vector(0 downto 0); 
+   signal sl_mr_lock  : std_logic_vector(0 downto 0); 
+   signal sl_enables  : std_logic_vector(0 downto 0); 
+   signal sl_enable   : std_logic; 
+   signal ENABLE      : std_logic; 
+   -- Function input parameter "in_0", multirate=1 
+   constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+
+   signal e0, e1 : boolean;
+
+   signal sl_obtain0  : std_logic;
+   signal sl_release0 : std_logic;
+   signal sl_obtain1  : std_logic;
+   signal sl_release1 : std_logic;
+
+   -- define control variables 
+
+   type state_type is (s_idle, s_halt, s_count, s_release);
+   signal state : state_type;
+   signal halt_cnt : integer;
+   signal sl_halt : std_logic;
+
+   signal sl_cnt_rst : std_logic;
+   signal cnt_rst : std_logic;
+
+begin
+
+   -- =============================================
+   -- =             MOD Functions                  
+   -- =============================================
+   -- END of MOD definitions 
+   -- =============================================
+   -- =             Parameter Functions            
+   -- =============================================
+   sl_cnt_rst <= '0';
+   sl_halt <= HALT;
+
+   -- END of Parameter definitions 
+   sl_loop_i    <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(2)+2*QUANT-1 downto 2*QUANT)));
+   sl_loop_i_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(2)+2*QUANT-1 downto 2*QUANT)));
+   sl_loop_j    <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_j_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_color    <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+   sl_loop_color_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+   -- Const bounds for-loops 
+   sl_low_i  <= 0;
+   sl_high_i <= 359;
+   sl_low_j  <= 0;
+   sl_high_j <= 639;
+   sl_low_color  <= 0;
+   sl_high_color <= 2;
+
+
+   load_i <= '0';
+   load_j <= '0';
+   load_color <= '0';
+
+   sl_lower_bnd(3*QUANT-1 downto 2*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
+   sl_lower_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
+   sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_color,QUANT));
+
+   sl_upper_bnd(3*QUANT-1 downto 2*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
+   sl_upper_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
+   sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_color,QUANT));
+   -- Special definitions 
+
+   -- Entity and control variables
+   -- Release matrix expressions
+   e0 <= -sl_loop_j_rg + 99>=0;
+   e1 <= sl_loop_j_rg-100>=0;
+
+   sl_fire <= ('1');
+
+   -- Convert FIFO Read Port ND_10IP_11 Argument in_1 : ED_11 : 0 of type IOMM
+   sl_obtain0 <= ('1');  -- set obtain/release to const value; not used
+   sl_release0 <= ('1');
+
+   sl_CONTROL(0) <= sl_fire and b2std((e0));
+   OBTAIN(0) <= sl_obtain0;
+   RELEASE(0) <= sl_release0;
+
+   -- Convert FIFO Read Port ND_10IP_12 Argument in_2 : ED_12 : 1 of type IOMM
+   sl_obtain1 <= ('1');  -- set obtain/release to const value; not used
+   sl_release1 <= ('1');
+
+   sl_CONTROL(1) <= sl_fire and b2std((e1));
+   OBTAIN(1) <= sl_obtain1;
+   RELEASE(1) <= sl_release1;
+
+   FIRE <= sl_fire;
+
+   cnt_rst <= sl_cnt_rst or RST;
+
+   -- 
+   -- =============================================
+   -- =             Multirate                      
+   -- =============================================
+   -- Function input parameter "in_0", multirate=1 
+   CNTR_MR0 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(0),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_0,
+         UPPER_BND => sl_mr_ubnd_0,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(0)
+      );
+   -- READ_EN indicates if READ_MUX can read data
+   sl_bla_en   <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');  
+   READ_EN     <= (others=>'0') when (HALT='1') else sl_bla_en;  
+   sl_mr_en   <= READ_ST; 
+   sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en); 
+   sl_enable  <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce 
+   ENABLE     <=  sl_enable or (not sl_fire);
+   -- 
+   LOCK_PRCS: process(CLK) 
+   begin 
+       if rising_edge(CLK) then 
+           if( RST = '1' ) then 
+               sl_mr_lock <= (others=>'0'); 
+           else  
+               if (ENABLE='1') then 
+                   sl_mr_lock <= (others=>'0'); 
+               else 
+                   for i in 0 to 0 loop 
+                       if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then 
+                           sl_mr_lock(i) <= '1'; 
+                       end if; 
+                   end loop; 
+               end if; 
+           end if; 
+       end if; 
+   end process; 
+   -- END of Multirate definitions 
+   -- 
+   -- =============================================
+   -- =             Iterators                      
+   -- =============================================
+   GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
+   	CNTR_RD : counter
+   	generic map ( 
+   		C_STEP    => CNTR_STEP(i),
+   		C_WIDTH   => CNTR_WIDTH(i)
+   	)
+  	 port map (
+   		CLK       => CLK,
+   		RST       => cnt_rst,
+   		ENABLE    => sl_cntr_en(i),
+			LOAD      => sl_load(i),
+   		LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		ITERATOR  => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		REG_CNTR  => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		DONE      => sl_done(i)
+   	);
+   end generate;
+   --
+   DONE_PRCS: process(CLK)
+   begin
+   	if rising_edge(CLK) then
+          if( RST = '1' ) then
+   		    sl_stop     <= '0';
+   		    sl_done_all <= '0';
+   		    sl_sof      <= '1';
+   	    else 
+   		    if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+   			    sl_stop <= '1';
+   		    elsif (WRAP=true) then
+   			    sl_stop <= '0';
+   		    end if;
+   		    if (sl_stop='0') then
+   			    sl_done_all <= sl_cntr_en(N_CNTRS);
+   		    end if;
+   		    if (ENABLE='1') then
+   			    sl_sof <= sl_eof;
+   		    end if;
+   	    end if;
+   	end if;
+   end process;
+   --
+   sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+   CONTROL <= sl_CONTROL;
+   --
+   REG_CNTRS <= sl_reg_cntrs; 
+   DONE <= sl_done_all;     -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+   STOP <= sl_stop;         -- '1' = The couter stoped after the end of the itteration space. 
+   --
+   sl_count      <=  '0' when (sl_stop='1') else
+                     '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
+   sl_cntr_en(0) <=  sl_count; -- makes the EVAL_LOGIC count
+   --
+   sl_cntr_en(N_CNTRS  downto 1) <= sl_cntr_en(N_CNTRS-1  downto 0) and sl_done(N_CNTRS-1  downto 0);
+   sl_eof <= sl_cntr_en(N_CNTRS);   -- End-of-frame
+   --
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_10/src/vhdl/bunny_static_split2rtl_hwn_nd_10_eval_logic_wr.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_10/src/vhdl/bunny_static_split2rtl_hwn_nd_10_eval_logic_wr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..52f10719ec5d0661bce52013e166004bfa0b2bfb
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_10/src/vhdl/bunny_static_split2rtl_hwn_nd_10_eval_logic_wr.vhd
@@ -0,0 +1,307 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_10 is
+   generic ( 
+      N_OUT_PORTS   : natural := 1;
+      WRAP          : boolean := true;
+      N_CNTRS       : natural := 1;
+      QUANT         : natural := 32;
+      PAR_BITWIDTH  : natural :=1;
+      CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+      CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST           : in  std_logic;
+      CLK           : in  std_logic;
+      WRITE_EN      : out std_logic_vector(0 downto 0);
+      WRITE_ST      : in  std_logic_vector(0 downto 0);
+      HALT          : in  std_logic;
+      FIRE          : out std_logic;
+      DONE          : out std_logic;
+      STOP          : out std_logic;
+      CONTROL       : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+   );
+end bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_10;
+
+architecture RTL of bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_10 is	
+   -- 
+   component counter is 
+      generic( 
+         C_STEP    : natural := 10; 
+         C_WIDTH   : natural := 10 
+      ); 
+      port ( 
+         RST       : in  std_logic; 
+         CLK       : in  std_logic; 
+         ENABLE    : in  std_logic; 
+         LOAD      : in  std_logic; 
+         LOWER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         UPPER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         ITERATOR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         REG_CNTR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         DONE      : out std_logic 
+      ); 
+   end component; 
+   -- 
+   component it_mod is 
+   generic( 
+      C_MOD     : natural := 10; 
+      C_WIDTH   : natural := 10; 
+      C_INIT    : natural :=  1; 
+      C_STEP    : natural :=  1  
+   ); 
+   port ( 
+      RST       : in  std_logic; 
+      CLK       : in  std_logic; 
+      LOAD      : in  std_logic; 
+      ENABLE    : in  std_logic; 
+      MODULE    : out std_logic_vector(C_WIDTH-1 downto 0) 
+   ); 
+   end component; 
+   -- 
+   -- Multirate related signals
+   signal sl_bla_en   : std_logic_vector(0 downto 0); 
+   signal sl_mr_en    : std_logic_vector(0 downto 0); 
+   signal sl_mr_done  : std_logic_vector(0 downto 0); 
+   signal sl_mr_lock  : std_logic_vector(0 downto 0); 
+   signal sl_enables  : std_logic_vector(0 downto 0); 
+   signal sl_enable   : std_logic; 
+   signal ENABLE      : std_logic; 
+   -- Function output parameter "out_0", multirate=1 
+   constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   --  
+   -- Parameter related signals 
+   --  
+   -- Iterator (counter) related signals 
+   signal sl_low_i, sl_high_i : integer; 
+   signal sl_low_j, sl_high_j : integer; 
+   signal sl_low_color, sl_high_color : integer; 
+   signal sl_loop_i, sl_loop_i_rg : integer;
+   signal sl_loop_j, sl_loop_j_rg : integer;
+   signal sl_loop_color, sl_loop_color_rg : integer;
+   signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   -- 
+   signal sl_cntr_en  : std_logic_vector(N_CNTRS   downto 0); 
+   signal sl_done     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_done_all : std_logic; 
+   signal sl_load     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_stop     : std_logic; 
+   signal sl_fire     : std_logic; 
+   signal sl_eof      : std_logic; 
+   signal sl_sof      : std_logic; 
+   signal sl_count    : std_logic; 
+   -- 
+   -- Special Control signal
+   signal sl_CONTROL       : std_logic_vector(N_OUT_PORTS-1 downto 0);
+   signal sl_no_request    : std_logic;
+   -- 
+   -- alias signals 
+   alias update_i : std_logic is sl_cntr_en(2);
+   alias update_j : std_logic is sl_cntr_en(1);
+   alias update_color : std_logic is sl_cntr_en(0);
+   -- 
+   alias load_i : std_logic is sl_load(2);
+   alias load_j : std_logic is sl_load(1);
+   alias load_color : std_logic is sl_load(0);
+   -- Trigger signals 
+   signal sl_trigger_i : std_logic;
+   signal sl_trigger_j : std_logic;
+   signal sl_trigger_color : std_logic;
+
+   signal e0, e1, e2 : boolean;
+
+   -- define control variables 
+   -- MOD related signals 
+
+
+   type state_type is (s_idle, s_halt, s_count, s_release);
+   signal state : state_type;
+   signal halt_cnt : integer;
+   signal sl_halt : std_logic;
+
+   signal sl_cnt_rst : std_logic;
+   signal cnt_rst : std_logic;
+
+begin
+
+   -- =============================================
+   -- =             MOD Functions                  
+   -- =============================================
+   -- END of MOD definitions 
+   --  
+   -- Parameter related signal assignments 
+   sl_cnt_rst <= '0';
+   sl_halt <= HALT;
+   -- END of Parameter definitions 
+
+   sl_loop_i    <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(2)+2*QUANT-1 downto 2*QUANT)));
+   sl_loop_i_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(2)+2*QUANT-1 downto 2*QUANT)));
+   sl_loop_j    <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_j_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_color    <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+   sl_loop_color_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+   -- Const bounds for-loops 
+   sl_low_i  <= 0;
+   sl_high_i <= 359;
+   sl_low_j  <= 0;
+   sl_high_j <= 639;
+   sl_low_color  <= 0;
+   sl_high_color <= 2;
+
+
+   load_i <= '0';
+   load_j <= '0';
+   load_color <= '0';
+
+   sl_lower_bnd(3*QUANT-1 downto 2*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
+   sl_lower_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
+   sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_color,QUANT));
+
+   sl_upper_bnd(3*QUANT-1 downto 2*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
+   sl_upper_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
+   sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_color,QUANT));
+
+   -- Special definitions 
+
+   -- Entity and control variables
+   e0 <= sl_loop_color_rg=0;
+   e1 <= sl_loop_color_rg-1=0;
+   e2 <= sl_loop_color_rg-2=0;
+
+   sl_fire <= ('1');
+
+   -- Convert FIFO Write Port out_1 : ED_13
+   sl_CONTROL(0) <= sl_fire and b2std((e0));
+
+   -- Convert FIFO Write Port out_2 : ED_14
+   sl_CONTROL(1) <= sl_fire and b2std((e1));
+
+   -- Convert FIFO Write Port out_3 : ED_15
+   sl_CONTROL(2) <= sl_fire and b2std((e2));
+
+   FIRE <= sl_fire;
+
+   cnt_rst <= sl_cnt_rst or RST;
+
+   -- 
+   -- =============================================
+   -- =             Multirate                      
+   -- =============================================
+   -- Function output parameter "out_0", multirate=1 
+   CNTR_MR0 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(0),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_0,
+         UPPER_BND => sl_mr_ubnd_0,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(0)
+      );
+   -- 
+   -- WRITE_EN indicates if date can be written to WRITE_MUX
+   sl_bla_en      <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
+   WRITE_EN    <=  (others=>'0') when (HALT='1') else sl_bla_en;
+   -- 
+   sl_mr_en    <= (not sl_mr_lock) and WRITE_ST; 
+   sl_enables  <= sl_mr_lock or (sl_mr_done and sl_mr_en); 
+   sl_enable   <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0';  -- and_reduce 
+   ENABLE      <= sl_enable or (not sl_fire);
+   -- 
+   LOCK_PRCS: process(CLK) 
+   begin 
+       if rising_edge(CLK) then 
+           if( RST = '1' ) then 
+               sl_mr_lock <= (others=>'0'); 
+           else  
+               if (ENABLE='1') then 
+                   sl_mr_lock <= (others=>'0'); 
+               else 
+                   for i in 0 to 0 loop 
+                       if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then 
+                           sl_mr_lock(i) <= '1'; 
+                       end if; 
+                   end loop; 
+               end if; 
+           end if; 
+       end if; 
+   end process; 
+   -- END of Multirate definitions 
+   -- 
+   -- =============================================
+   -- =             Iterators                      
+   -- =============================================
+   GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
+   	CNTR_WR : counter
+   	generic map ( 
+   		C_STEP    => CNTR_STEP(i),
+   		C_WIDTH   => CNTR_WIDTH(i)
+   	)
+  	 port map (
+   		CLK       => CLK,
+   		RST       => cnt_rst,
+   		ENABLE    => sl_cntr_en(i),
+   		LOAD      => sl_load(i),
+   		LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		ITERATOR  => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		REG_CNTR  => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		DONE      => sl_done(i)
+   	);
+   end generate;
+   --
+   DONE_PRCS: process(CLK)
+   begin
+   	if rising_edge(CLK) then
+   	    if( RST = '1' ) then
+   		    sl_stop     <= '0';
+   		    sl_done_all <= '0';
+   		    sl_sof      <= '1';
+   	    else 
+   		    if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+   			    sl_stop <= '1';
+   		    elsif (WRAP=true) then
+   			    sl_stop <= '0';
+   		    end if;
+   		    if (sl_stop='0') then
+   			    sl_done_all <= sl_cntr_en(N_CNTRS);
+   		    end if;
+   		    if (ENABLE='1') then
+   			    sl_sof <= sl_eof;
+   		    end if;
+   	    end if;
+   	end if;
+   end process;
+   --
+   sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+   CONTROL <= sl_CONTROL;
+   --
+   DONE <= sl_done_all;     -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+   STOP <= sl_stop;         -- '1' = The couter stoped after the end of the itteration space. 
+   --
+   sl_count      <=  '0' when (sl_stop='1') else
+   			'1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
+   sl_cntr_en(0) <=  sl_count; -- makes the EVAL_LOGIC count
+   --
+   sl_cntr_en(N_CNTRS  downto 1) <= sl_cntr_en(N_CNTRS-1  downto 0) and sl_done(N_CNTRS-1  downto 0);
+   sl_eof <= sl_cntr_en(N_CNTRS);      -- End-of-frame (combinatorial; beter not use it outside)
+   --
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_10/src/vhdl/bunny_static_split2rtl_hwn_nd_10_execution_unit.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_10/src/vhdl/bunny_static_split2rtl_hwn_nd_10_execution_unit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e068fa34e66a7b2e40d88b5ac05ed2848413c97e
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_10/src/vhdl/bunny_static_split2rtl_hwn_nd_10_execution_unit.vhd
@@ -0,0 +1,113 @@
+-- Execute Unit automatically generated by KpnMapper
+-- Function "compaan_outlinedproc4"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_bunny_static_split2rtl_functions_1_lib;
+use compaandesign_com_bunny_static_split2rtl_functions_1_lib.all;
+
+entity bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_10 is
+   generic (
+      N_INPORTS  : natural := 1;
+      N_OUTPORTS : natural := 1;
+      IP_RESET   : natural := 1; 
+      STIM_DIR   : string  := "bla";
+      QUANT      : natural := 32;
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1; 
+      CNTR_QUANT : natural := 32; 
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+   );
+   port (
+      RST        : in  std_logic;
+      CLK        : in  std_logic;
+      -- Funtion Input parameters
+      IN_PORT_0    : in  std_logic_vector(7 downto 0);  -- Param. "tmp1"
+      READ       : out std_logic_vector(N_INPORTS-1 downto 0);
+      EXIST      : in  std_logic_vector(N_INPORTS-1 downto 0);
+      -- Iterators
+      REG_CNTRS_RD : in  std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
+      -- Funtion Output parameters
+      OUT_PORT_0   : out std_logic_vector(7 downto 0);  -- Param. "tmp0"
+      WRITE      : out std_logic_vector(N_OUTPORTS-1 downto 0);
+      FULL       : in  std_logic_vector(N_OUTPORTS-1 downto 0);
+      STOP_RD    : in  std_logic;
+      STOP_WR    : in  std_logic;
+      ERROR      : out std_logic
+   );
+end bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_10 ;
+
+-- Laura implementation
+architecture Laura of bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_10 is
+
+   component compaan_outlinedproc4 is
+      generic (
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1; 
+         CNTR_QUANT : natural := 32; 
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST   : in std_logic;
+         CLK   : in std_logic;
+         -- Inputs 
+         ip_tmp1  : in  std_logic_vector(7 downto 0);  
+         -- Iterators 
+         it_color : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+         it_j : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+         it_i : in  std_logic_vector(CNTR_WIDTH(2)-1 downto 0);
+         EXIST : in  std_logic_vector(0 downto 0);
+         READF : out std_logic_vector(0 downto 0);
+         -- Outputs 
+         op_tmp0 : out std_logic_vector(7 downto 0);
+         FULL  : in  std_logic_vector(0 downto 0);
+         WRITEF: out std_logic_vector(0 downto 0);
+         --
+         STOP_RD : in  std_logic;
+         STOP_WR : in  std_logic;
+         ERROR   : out std_logic
+      );
+   end component;
+
+   signal sl_RST : std_logic;
+
+begin
+
+   sl_RST <= RST when IP_RESET=1 else not RST;
+
+   FUNC : compaan_outlinedproc4
+   generic map (
+         STIM_DIR      => STIM_DIR,
+         c_STAGES      => c_STAGES,
+         N_CNTRS       => N_CNTRS,
+         CNTR_QUANT    => CNTR_QUANT,
+         CNTR_WIDTH    => CNTR_WIDTH
+   )
+   port map (
+      RST   => sl_RST,
+      CLK   => CLK,
+      -- Inputs 
+      ip_tmp1 => IN_PORT_0,
+      -- Iterators 
+      it_color => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
+      it_j => REG_CNTRS_RD(1*CNTR_QUANT+CNTR_WIDTH(1)-1 downto 1*CNTR_QUANT),
+      it_i => REG_CNTRS_RD(2*CNTR_QUANT+CNTR_WIDTH(2)-1 downto 2*CNTR_QUANT),
+      EXIST => EXIST,
+      READF => READ,
+      -- Outputs 
+      op_tmp0 => OUT_PORT_0,
+      FULL  => FULL,
+      WRITEF=> WRITE,
+      -- 
+      STOP_RD => STOP_RD,
+      STOP_WR => STOP_WR,
+      ERROR   => ERROR
+   );
+
+end Laura;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_12/hdllib.cfg b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_12/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..5d1dd96ec7cbc227f1b718e85a4d15f2762b52c4
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_12/hdllib.cfg
@@ -0,0 +1,18 @@
+hdl_lib_name = compaandesign_com_bunny_static_split2rtl_hwn_nd_12_1
+hdl_library_clause_name = compaandesign_com_bunny_static_split2rtl_hwn_nd_12_1_lib
+hdl_lib_uses_synth = compaandesign_com_bunny_static_split2rtl_functions_1 compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1 compaandesign_com_common_extern_connector_1 
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+	src/vhdl/bunny_static_split2rtl_hwn_nd_12_execution_unit.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_12_eval_logic_rd.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_12_eval_logic_wr.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_12.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_12/src/vhdl/bunny_static_split2rtl_hwn_nd_12.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_12/src/vhdl/bunny_static_split2rtl_hwn_nd_12.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..39a2551a87647a38a15e62bfd672f6aebb65f51d
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_12/src/vhdl/bunny_static_split2rtl_hwn_nd_12.vhd
@@ -0,0 +1,600 @@
+-- HWN Entity File automatically generated by KpnMapper (writeHdlHWNodeFile)
+-- Top level file for a Hardware Accelerator
+-- Function "serialize4t8to32"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+library compaandesign_com_common_extern_connector_1_lib;
+use compaandesign_com_common_extern_connector_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_12 is
+   generic (
+      STIM_DIR   : string  := "bla";
+      RESET_HIGH : natural := 1;
+      PAR_WIDTH  : natural := 16;
+      QUANT      : natural := 32;
+      WRAP       : boolean := true
+   );
+   port (
+
+      -- Dataflow input interfaces
+      -- ED_13 : in_0
+      ND_12IP_13_Rd    : out std_logic;
+      ND_12IP_13_Din   : in  std_logic_vector(7 downto 0);
+      ND_12IP_13_Exist : in  std_logic; 
+      ND_12IP_13_CLK   : out std_logic;
+      ND_12IP_13_CTRL  : in  std_logic;
+
+      -- ED_14 : in_1
+      ND_12IP_14_Rd    : out std_logic;
+      ND_12IP_14_Din   : in  std_logic_vector(7 downto 0);
+      ND_12IP_14_Exist : in  std_logic; 
+      ND_12IP_14_CLK   : out std_logic;
+      ND_12IP_14_CTRL  : in  std_logic;
+
+      -- ED_15 : in_2
+      ND_12IP_15_Rd    : out std_logic;
+      ND_12IP_15_Din   : in  std_logic_vector(7 downto 0);
+      ND_12IP_15_Exist : in  std_logic; 
+      ND_12IP_15_CLK   : out std_logic;
+      ND_12IP_15_CTRL  : in  std_logic;
+
+      -- ED_16 : in_3
+      ND_12IP_16_Rd    : out std_logic;
+      ND_12IP_16_Din   : in  std_logic_vector(7 downto 0);
+      ND_12IP_16_Exist : in  std_logic; 
+      ND_12IP_16_CLK   : out std_logic;
+      ND_12IP_16_CTRL  : in  std_logic;
+
+      -- Dataflow Control Input interfaces
+      -- Dataflow output interfaces
+      -- ED_17 : out_0
+      ND_12OP_1_Wr   : out std_logic;
+      ND_12OP_1_Dout : out std_logic_vector(31 downto 0);
+      ND_12OP_1_Full : in  std_logic;
+      ND_12OP_1_CLK  : out std_logic;
+      ND_12OP_1_CTRL : out std_logic;
+
+      -- ED_18 : out_0
+      ND_12OP_1_d1_Wr   : out std_logic;
+      ND_12OP_1_d1_Dout : out std_logic_vector(31 downto 0);
+      ND_12OP_1_d1_Full : in  std_logic;
+      ND_12OP_1_d1_CLK  : out std_logic;
+      ND_12OP_1_d1_CTRL : out std_logic;
+
+      PARAM_DT : in  std_logic_vector(PAR_WIDTH+10-1 downto 0);
+      PARAM_LD : in  std_logic;
+
+      RST      : in  std_logic;
+      CLK      : in  std_logic;
+      STOP     : out std_logic;
+      ERROR    : out std_logic;
+      BLOCK_RD : out std_logic
+   );
+end bunny_static_split2rtl_hwn_nd_12;
+
+architecture RTL of bunny_static_split2rtl_hwn_nd_12 is
+   --
+   -- ====================================
+   -- =     Constants declaration        =
+   -- ====================================
+   -- Setting the parameters of the HW Node
+   constant c_IN_PORTS     : natural := 4; -- number of input ports of a HW node
+   constant c_OUT_PORTS    : natural := 2; -- number of output ports of a HW node
+   constant c_IN_FUNC_VAR  : natural := 4; -- number of input ports of a HW IP
+   constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
+   constant c_COUNTERS     : natural := 2; -- number of iterators
+   -- ===========================================
+   -- = Iterators run from Inner to Outer loop  =
+   -- ===========================================
+   constant c_CNTR_QUANT   : natural := 11;
+   constant c_CNTR_STEPS   : t_counter_step  := ( 0=>1, 1=>1, others=>1 );
+   constant c_CNTR_WIDTHS  : t_counter_width := ( 0=>11, 1=>10, others=>10 );
+   constant c_STAGES       : natural := 1; -- number of pipeline stages or delay
+   constant c_IP_RESET     : natural := 1; -- active level of the HW IP reset signal
+   constant c_WRAP         : boolean := WRAP; -- Operation mode: Single_Shot (false) or Continuous (true)
+   constant c_EXT_PAR      : natural := 0; -- number of external parameters
+   constant c_INT_PAR      : natural := 0; -- number of internal parameters
+   constant c_N_PAR        : natural := 0; -- no parameters are used
+   constant c_PAR_BITWIDTH : natural := PAR_WIDTH; -- aggregate bitwidth of the parameter vector
+   constant c_PAR_VECTOR   : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
+       (0,0,0,0), (0,0,0,0)    -- two dummy elements
+   );
+   --
+   -- ====================================
+   -- =     Components declaration       =
+   -- ====================================
+   component bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_12 is
+      generic (
+         N_IN_PORTS    : natural := 1;
+         WRAP          : boolean := true;
+         N_CNTRS       : natural := 1; 
+         QUANT         : natural := 32;
+         PAR_BITWIDTH  : natural :=1;
+         CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+         CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+      );
+      port (
+         RST           : in  std_logic;
+         CLK           : in  std_logic;
+         REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1  downto 0); 
+         READ_EN       : out std_logic_vector(c_IN_FUNC_VAR-1  downto 0);
+         READ_ST       : in  std_logic_vector(c_IN_FUNC_VAR-1  downto 0);
+         HALT          : in  std_logic;
+         FIRE          : out std_logic;
+         DONE          : out std_logic;
+         STOP          : out std_logic;
+         CONTROL       : out std_logic_vector(N_IN_PORTS-1 downto 0);
+         OBTAIN        : out std_logic_vector(N_IN_PORTS-1 downto 0);
+         RELEASE       : out std_logic_vector(N_IN_PORTS-1 downto 0)
+      );
+   end component;
+
+   component READ_MUX is
+      generic (
+         N_PORTS    : natural := 1;
+         PORT_WIDTH : natural := 32  
+      );
+      port(
+         IN_PORTS   : in  std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
+         EXISTS     : in  std_logic_vector(N_PORTS-1 downto 0);
+         READS      : out std_logic_vector(N_PORTS-1 downto 0);
+         SOFS       : in  std_logic_vector(N_PORTS-1 downto 0);
+
+         OUT_PORT   : out std_logic_vector(PORT_WIDTH-1 downto 0);
+         EXIST      : out std_logic;
+         READ       : in  std_logic;
+         SOF        : in  std_logic;
+		CLK        : in std_logic;
+
+         READ_EN    : in  std_logic;
+         READ_ST    : out std_logic;
+         CONTROL    : in  std_logic_vector(N_PORTS-1 downto 0);
+         OBTAIN     : in  std_logic_vector(N_PORTS-1 downto 0);
+         RELEASE    : in  std_logic_vector(N_PORTS-1 downto 0)
+      );
+   end component;
+
+   component bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_12 is
+      generic ( 
+         N_OUT_PORTS   : natural := 1;
+         WRAP          : boolean := true;
+         N_CNTRS       : natural := 1; 
+         QUANT         : natural := 32;
+         PAR_BITWIDTH  : natural :=1;
+         CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+         CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+      );
+      port (
+         RST           : in  std_logic;
+         CLK           : in  std_logic;
+         WRITE_EN      : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+         WRITE_ST      : in  std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+         HALT          : in  std_logic;
+         FIRE          : out std_logic;
+         DONE          : out std_logic;
+         STOP          : out std_logic;
+         CONTROL       : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+      );
+   end component;
+
+   component WRITE_DEMUX is
+      generic (
+         N_PORTS : natural := 1
+      );
+      port(
+         WRITES   : out std_logic_vector(N_PORTS-1 downto 0);
+         WRITE    : in  std_logic;
+
+         FULLS    : in  std_logic_vector(N_PORTS-1 downto 0);
+         FULL     : out std_logic;
+
+         WRITE_EN : in  std_logic;
+         WRITE_ST : out std_logic;
+         CONTROL  : in  std_logic_vector(N_PORTS-1 downto 0)
+      );
+   end component;
+
+
+   component bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_12 is
+      generic (
+         N_INPORTS  : natural := 1;
+         N_OUTPORTS : natural := 1;
+         IP_RESET   : natural := 1;
+         QUANT      : natural := 32;
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1;
+         CNTR_QUANT : natural := 32;
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST        : in  std_logic;
+         CLK        : in  std_logic;
+
+         -- Iterators
+         REG_CNTRS_RD : in  std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
+         -- Func. Input parameters
+         IN_PORT_0 : in  std_logic_vector(7 downto 0); -- in0
+         IN_PORT_1 : in  std_logic_vector(7 downto 0); -- in1
+         IN_PORT_2 : in  std_logic_vector(7 downto 0); -- in2
+         IN_PORT_3 : in  std_logic_vector(7 downto 0); -- in3
+         READ       : out std_logic_vector(N_INPORTS-1 downto 0);
+         EXIST      : in  std_logic_vector(N_INPORTS-1 downto 0);
+         -- Func. Output parameters
+         OUT_PORT_0 : out std_logic_vector(31 downto 0); -- result
+         WRITE      : out std_logic_vector(N_OUTPORTS-1 downto 0);
+         FULL       : in  std_logic_vector(N_OUTPORTS-1 downto 0);
+         --
+         STOP_RD    : in  std_logic;
+         STOP_WR    : in  std_logic;
+         ERROR      : out std_logic
+      );
+   end component;
+
+   component INTERNAL_PARAMETERS is 
+      generic (
+         PAR_BITWIDTH : natural:=1;
+         PAR_VECTOR   : t_par_vector;
+         N_PAR        : natural:=0;
+         START_IN_RUN  : boolean := FALSE
+      );
+      port (  
+         RST        : in  std_logic;
+         CLK        : in  std_logic;
+
+         HALT_RD    : out std_logic;
+         HALT_WR    : out std_logic;
+         SOF_RD     : in  std_logic;
+         SOF_WR     : in  std_logic;
+         LOAD_PARAM : out std_logic;
+
+         par_one_in_Rd    : out std_logic;
+         par_one_in_Din   : in std_logic_vector(32-1 downto 0);
+         par_one_in_Exist : in std_logic;
+         par_one_in_CLK   : out std_logic;
+         par_one_in_CTRL  : in std_logic;
+
+         PARAMETERS_RD : out std_logic_vector(32-1 downto 0);
+         PARAMETERS_WR : out std_logic_vector(32-1 downto 0)
+      );
+   end component;
+
+   --
+   -- ====================================
+   -- =       Signals declaration        =
+   -- ====================================
+   -- 
+   -- HW Node Input Ports
+   signal sl_IN_PORTS_0   : std_logic_vector(1*8-1 downto 0); -- in0
+   signal sl_IN_PORTS_1   : std_logic_vector(1*8-1 downto 0); -- in1
+   signal sl_IN_PORTS_2   : std_logic_vector(1*8-1 downto 0); -- in2
+   signal sl_IN_PORTS_3   : std_logic_vector(1*8-1 downto 0); -- in3
+   signal sl_EXISTS       : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_READS        : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_CTRLS        : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_control_rd   : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_obtain_rd    : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_release_rd   : std_logic_vector(c_IN_PORTS-1 downto 0);
+   -- 
+   -- Func. Input parameters
+   signal sl_in_port_0    : std_logic_vector(7 downto 0); -- in0
+   signal sl_in_port_1    : std_logic_vector(7 downto 0); -- in1
+   signal sl_in_port_2    : std_logic_vector(7 downto 0); -- in2
+   signal sl_in_port_3    : std_logic_vector(7 downto 0); -- in3
+   signal sl_exist        : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read         : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read_en      : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read_st      : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   -- 
+   signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
+   -- 
+   -- HW Node Output Ports
+   signal sl_WRITES       : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_FULLS        : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_control_wr   : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_lortnoc_wr   : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   -- 
+   -- Func. Output parameters
+   signal sl_out_port_0   : std_logic_vector(31 downto 0); -- result
+   signal sl_full         : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write        : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write_en     : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write_st     : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   -- 
+   -- 
+   signal sl_halt             : std_logic;
+   signal sl_halted           : std_logic;
+   signal sl_halt_wr          : std_logic;
+   signal sl_halt_rd          : std_logic;
+   signal sl_param_halt_wr    : std_logic;
+   signal sl_param_halt_rd    : std_logic;
+   signal sl_done_wr          : std_logic;
+   signal sl_done_rd          : std_logic;
+   signal sl_stop_wr          : std_logic;
+   signal sl_stop_rd          : std_logic;
+   signal sl_fire_wr          : std_logic;
+   signal sl_fire_rd          : std_logic;
+   signal sl_sof_wr           : std_logic;
+   signal sl_sof_rd           : std_logic;
+   signal sl_error            : std_logic;
+   signal sl_load_param       : std_logic;
+
+   --  
+   -- Parameter related signals 
+   signal sl_param_fifo_full     : std_logic;
+   signal sl_sync_num            : std_logic_vector(9 downto 0);
+
+   signal sl_RST : std_logic;
+
+begin 
+
+   sl_RST <= RST when RESET_HIGH=1 else not RST;
+      ND_12IP_13_CLK   <= CLK;
+      ND_12IP_14_CLK   <= CLK;
+      ND_12IP_15_CLK   <= CLK;
+      ND_12IP_16_CLK   <= CLK;
+      ND_12OP_1_CLK  <= CLK;
+      ND_12OP_1_d1_CLK  <= CLK;
+
+   --
+   -- ==========================================================
+   -- =       HWN Input related modules                        =
+   -- ==========================================================
+   -- Func. Input param. "in0"
+   RD_MUX_0 : READ_MUX
+   generic map (
+      N_PORTS    => 1,
+      PORT_WIDTH => 8
+   )
+   port map (
+      IN_PORTS   => sl_IN_PORTS_0,
+      EXISTS     => sl_EXISTS(0 downto 0),
+      READS      => sl_READS(0 downto 0),
+      SOFS       => sl_CTRLS(0 downto 0),
+
+      OUT_PORT   => sl_in_port_0,
+      EXIST      => sl_exist(0),
+      READ       => sl_read(0),
+      SOF        => sl_sof_rd,
+      CLK        => CLK,
+
+      READ_EN    => sl_read_en(0),
+      READ_ST    => sl_read_st(0),
+      CONTROL    => sl_control_rd(0 downto 0),
+      OBTAIN     => sl_obtain_rd(0 downto 0),
+      RELEASE    => sl_release_rd(0 downto 0)
+   );
+
+   ND_12IP_13_Rd   <= sl_READS(0);
+
+   sl_IN_PORTS_0 <= ND_12IP_13_Din;
+
+   -- Func. Input param. "in1"
+   RD_MUX_1 : READ_MUX
+   generic map (
+      N_PORTS    => 1,
+      PORT_WIDTH => 8
+   )
+   port map (
+      IN_PORTS   => sl_IN_PORTS_1,
+      EXISTS     => sl_EXISTS(1 downto 1),
+      READS      => sl_READS(1 downto 1),
+      SOFS       => sl_CTRLS(1 downto 1),
+
+      OUT_PORT   => sl_in_port_1,
+      EXIST      => sl_exist(1),
+      READ       => sl_read(1),
+      SOF        => sl_sof_rd,
+      CLK        => CLK,
+
+      READ_EN    => sl_read_en(1),
+      READ_ST    => sl_read_st(1),
+      CONTROL    => sl_control_rd(1 downto 1),
+      OBTAIN     => sl_obtain_rd(1 downto 1),
+      RELEASE    => sl_release_rd(1 downto 1)
+   );
+
+   ND_12IP_14_Rd   <= sl_READS(1);
+
+   sl_IN_PORTS_1 <= ND_12IP_14_Din;
+
+   -- Func. Input param. "in2"
+   RD_MUX_2 : READ_MUX
+   generic map (
+      N_PORTS    => 1,
+      PORT_WIDTH => 8
+   )
+   port map (
+      IN_PORTS   => sl_IN_PORTS_2,
+      EXISTS     => sl_EXISTS(2 downto 2),
+      READS      => sl_READS(2 downto 2),
+      SOFS       => sl_CTRLS(2 downto 2),
+
+      OUT_PORT   => sl_in_port_2,
+      EXIST      => sl_exist(2),
+      READ       => sl_read(2),
+      SOF        => sl_sof_rd,
+      CLK        => CLK,
+
+      READ_EN    => sl_read_en(2),
+      READ_ST    => sl_read_st(2),
+      CONTROL    => sl_control_rd(2 downto 2),
+      OBTAIN     => sl_obtain_rd(2 downto 2),
+      RELEASE    => sl_release_rd(2 downto 2)
+   );
+
+   ND_12IP_15_Rd   <= sl_READS(2);
+
+   sl_IN_PORTS_2 <= ND_12IP_15_Din;
+
+   -- Func. Input param. "in3"
+   RD_MUX_3 : READ_MUX
+   generic map (
+      N_PORTS    => 1,
+      PORT_WIDTH => 8
+   )
+   port map (
+      IN_PORTS   => sl_IN_PORTS_3,
+      EXISTS     => sl_EXISTS(3 downto 3),
+      READS      => sl_READS(3 downto 3),
+      SOFS       => sl_CTRLS(3 downto 3),
+
+      OUT_PORT   => sl_in_port_3,
+      EXIST      => sl_exist(3),
+      READ       => sl_read(3),
+      SOF        => sl_sof_rd,
+      CLK        => CLK,
+
+      READ_EN    => sl_read_en(3),
+      READ_ST    => sl_read_st(3),
+      CONTROL    => sl_control_rd(3 downto 3),
+      OBTAIN     => sl_obtain_rd(3 downto 3),
+      RELEASE    => sl_release_rd(3 downto 3)
+   );
+
+   ND_12IP_16_Rd   <= sl_READS(3);
+
+   sl_IN_PORTS_3 <= ND_12IP_16_Din;
+
+   sl_EXISTS      <= ND_12IP_16_Exist & ND_12IP_15_Exist & ND_12IP_14_Exist & ND_12IP_13_Exist ;
+   sl_CTRLS       <= ND_12IP_16_CTRL & ND_12IP_15_CTRL & ND_12IP_14_CTRL & ND_12IP_13_CTRL ;
+
+   EVAL_RD : bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_12
+   generic map ( 
+      N_IN_PORTS    => c_IN_PORTS,
+      WRAP          => c_WRAP,
+      N_CNTRS       => c_COUNTERS,
+      QUANT         => c_CNTR_QUANT,
+      PAR_BITWIDTH  => c_PAR_BITWIDTH,
+      CNTR_STEP     => c_CNTR_STEPS,
+      CNTR_WIDTH    => c_CNTR_WIDTHS
+   )
+   port map(
+      RST           => sl_RST,
+      CLK           => CLK,
+      REG_CNTRS     => sl_REG_CNTRS_RD,
+      READ_EN       => sl_read_en,
+      READ_ST       => sl_read_st,
+      HALT          => sl_halt_rd,
+      FIRE          => sl_fire_rd,
+      DONE          => sl_done_rd,
+      STOP          => sl_stop_rd,
+      CONTROL       => sl_control_rd,
+      OBTAIN        => sl_obtain_rd,
+      RELEASE       => sl_release_rd
+   );
+
+   --
+   -- ==========================================================
+   -- =       HWN Output related modules                       =
+   -- ==========================================================
+   -- 
+   -- Func. Output param. "result"
+   DEMUX_0 : WRITE_DEMUX
+   generic map (
+      N_PORTS => 2
+   )
+   port map (
+      WRITES   => sl_WRITES(1 downto 0),
+      FULLS    => sl_FULLS(1 downto 0),
+      CONTROL  => sl_lortnoc_wr(1 downto 0),
+      WRITE    => sl_write(0),
+      FULL     => sl_full(0),
+      WRITE_EN => sl_write_en(0),
+      WRITE_ST => sl_write_st(0)
+   );
+   --
+   ND_12OP_1_Dout <= sl_out_port_0;  -- Func. Output param. "result"
+   ND_12OP_1_CTRL <= sl_sof_wr ;
+   ND_12OP_1_Wr   <= sl_WRITES(0);
+   sl_FULLS(0) <= ND_12OP_1_Full;
+   sl_lortnoc_wr(0) <= sl_control_wr(0);
+   --
+   ND_12OP_1_d1_Dout <= sl_out_port_0;  -- Func. Output param. "result"
+   ND_12OP_1_d1_CTRL <= sl_sof_wr ;
+   ND_12OP_1_d1_Wr   <= sl_WRITES(1);
+   sl_FULLS(1) <= ND_12OP_1_d1_Full;
+   sl_lortnoc_wr(1) <= sl_control_wr(1);
+   --
+   --
+   EVAL_WR : bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_12
+   generic map ( 
+      N_OUT_PORTS   => c_OUT_PORTS,
+      WRAP          => c_WRAP,
+      N_CNTRS       => c_COUNTERS,
+      QUANT         => c_CNTR_QUANT,
+      PAR_BITWIDTH  => c_PAR_BITWIDTH,
+      CNTR_STEP     => c_CNTR_STEPS,
+      CNTR_WIDTH    => c_CNTR_WIDTHS
+   )
+   port map (
+      RST           => sl_RST,
+      CLK           => CLK,
+      WRITE_EN      => sl_write_en,
+      WRITE_ST      => sl_write_st,
+      HALT          => sl_halt_wr,
+      FIRE          => sl_fire_wr,
+      DONE          => sl_done_wr,
+      STOP          => sl_stop_wr,
+      CONTROL       => sl_control_wr
+   );
+
+   --
+   -- ==========================================================
+   -- =       HWN Execution Unit                               =
+   -- ==========================================================
+   EX : bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_12
+   generic map (
+      N_INPORTS  => c_IN_FUNC_VAR,
+      N_OUTPORTS => c_OUT_FUNC_VAR, 
+      IP_RESET   => c_IP_RESET,
+      QUANT      => QUANT,
+      STIM_DIR   => STIM_DIR,
+      c_STAGES   => c_STAGES,
+      N_CNTRS    => c_COUNTERS,
+      CNTR_QUANT => c_CNTR_QUANT,
+      CNTR_WIDTH => c_CNTR_WIDTHS
+   )
+   port map (
+      RST        => sl_RST,
+      CLK        => CLK,
+      -- Iterators
+      REG_CNTRS_RD => sl_REG_CNTRS_RD,
+      -- Func. Input parameters
+      IN_PORT_0    => sl_in_port_0,
+      IN_PORT_1    => sl_in_port_1,
+      IN_PORT_2    => sl_in_port_2,
+      IN_PORT_3    => sl_in_port_3,
+      READ       => sl_read,
+      EXIST      => sl_exist,
+      -- Func. Output parameters
+      OUT_PORT_0   => sl_out_port_0,
+      WRITE      => sl_write,
+      FULL       => sl_full,
+      --
+      STOP_WR    => sl_stop_wr,
+      STOP_RD    => sl_stop_rd,
+      ERROR      => sl_error
+   );
+
+   -- ==========================================================
+   -- =       PARAMETERIZATION                                 =
+   -- ==========================================================
+   -- no parameters
+   sl_halt_rd <= '0';
+   sl_halt_wr <= '0';
+--   sl_halted  <= sl_sof_rd;
+   STOP <= sl_done_wr;
+   ERROR <= sl_error;
+   BLOCK_RD <= not (  (  sl_READS(0)  )and  (  sl_READS(1)  )and  (  sl_READS(2)  )and  (  sl_READS(3)  ) );
+
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_12/src/vhdl/bunny_static_split2rtl_hwn_nd_12_eval_logic_rd.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_12/src/vhdl/bunny_static_split2rtl_hwn_nd_12_eval_logic_rd.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f814daa429443b5232473f866144f0022d24d357
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_12/src/vhdl/bunny_static_split2rtl_hwn_nd_12_eval_logic_rd.vhd
@@ -0,0 +1,406 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_12 is
+   generic (
+      N_IN_PORTS    : natural := 1;
+      WRAP          : boolean := true;
+      N_CNTRS       : natural := 1; 
+      QUANT         : natural := 32;
+      PAR_BITWIDTH  : natural  :=1;
+      CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+      CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST           : in  std_logic;
+      CLK           : in  std_logic;
+      REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+      READ_EN       : out std_logic_vector(3 downto 0);
+      READ_ST       : in  std_logic_vector(3 downto 0);
+      HALT          : in  std_logic;
+      FIRE          : out std_logic;
+      DONE          : out std_logic;
+      STOP          : out std_logic;
+      CONTROL       : out std_logic_vector(N_IN_PORTS-1 downto 0);
+      OBTAIN        : out std_logic_vector(N_IN_PORTS-1 downto 0);
+      RELEASE       : out std_logic_vector(N_IN_PORTS-1 downto 0)
+   );
+end bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_12;
+
+architecture RTL of bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_12 is
+   -- 
+   component counter is 
+      generic( 
+         C_STEP    : natural := 10; 
+         C_WIDTH   : natural := 10 
+      ); 
+      port ( 
+         RST       : in  std_logic; 
+         CLK       : in  std_logic; 
+         ENABLE    : in  std_logic; 
+         LOAD      : in  std_logic; 
+         LOWER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         UPPER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         ITERATOR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         REG_CNTR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         DONE      : out std_logic 
+      ); 
+   end component; 
+   -- 
+   component it_mod is 
+   generic( 
+      C_MOD     : natural := 10; 
+      C_WIDTH   : natural := 10; 
+      C_INIT    : natural :=  1; 
+      C_STEP    : natural :=  1  
+   ); 
+   port ( 
+      RST       : in  std_logic; 
+      CLK       : in  std_logic; 
+      LOAD      : in  std_logic; 
+      ENABLE    : in  std_logic; 
+      MODULE    : out std_logic_vector(C_WIDTH-1 downto 0) 
+   ); 
+   end component; 
+   -- 
+   --  
+   -- Parameter related signals 
+   -- 
+   -- Iterator (counter) related signals 
+   signal sl_low_i, sl_high_i : integer;
+   signal sl_low_j, sl_high_j : integer;
+   signal sl_loop_i, sl_loop_i_rg : integer;
+   signal sl_loop_j, sl_loop_j_rg : integer;
+   signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   -- 
+   signal sl_cntr_en  : std_logic_vector(N_CNTRS   downto 0); 
+   signal sl_done     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_done_all : std_logic; 
+   signal sl_load     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_stop     : std_logic; 
+   signal sl_fire     : std_logic; 
+   signal sl_sof      : std_logic; 
+   signal sl_eof      : std_logic; 
+   signal sl_count    : std_logic; 
+
+   -- alias signals 
+   alias update_i : std_logic is sl_cntr_en(1);
+   alias update_j : std_logic is sl_cntr_en(0);
+   alias load_i : std_logic is sl_load(1);
+   alias load_j : std_logic is sl_load(0);
+
+   -- Trigger signals 
+   signal sl_trigger_i : std_logic;
+   signal sl_trigger_j : std_logic;
+
+   -- Special Control signal
+   signal sl_CONTROL       : std_logic_vector(N_IN_PORTS-1 downto 0);
+   signal sl_no_request    : std_logic;
+   -- 
+   -- Multirate related signals
+   signal sl_bla_en   : std_logic_vector(3 downto 0); 
+   signal sl_mr_en    : std_logic_vector(3 downto 0); 
+   signal sl_mr_done  : std_logic_vector(3 downto 0); 
+   signal sl_mr_lock  : std_logic_vector(3 downto 0); 
+   signal sl_enables  : std_logic_vector(3 downto 0); 
+   signal sl_enable   : std_logic; 
+   signal ENABLE      : std_logic; 
+   -- Function input parameter "in_0", multirate=1 
+   constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   -- Function input parameter "in_1", multirate=1 
+   constant sl_mr_lbnd_1 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_1 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   -- Function input parameter "in_2", multirate=1 
+   constant sl_mr_lbnd_2 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_2 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   -- Function input parameter "in_3", multirate=1 
+   constant sl_mr_lbnd_3 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_3 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+
+
+   signal sl_obtain0  : std_logic;
+   signal sl_release0 : std_logic;
+   signal sl_obtain1  : std_logic;
+   signal sl_release1 : std_logic;
+   signal sl_obtain2  : std_logic;
+   signal sl_release2 : std_logic;
+   signal sl_obtain3  : std_logic;
+   signal sl_release3 : std_logic;
+
+   -- define control variables 
+   signal div25 : integer;
+   signal mod12 : integer;
+
+   type state_type is (s_idle, s_halt, s_count, s_release);
+   signal state : state_type;
+   signal halt_cnt : integer;
+   signal sl_halt : std_logic;
+
+   signal sl_cnt_rst : std_logic;
+   signal cnt_rst : std_logic;
+   signal j0_mod_2 : std_logic_vector(1-1 downto 0);
+
+begin
+
+   -- =============================================
+   -- =             MOD Functions                  
+   -- =============================================
+   -- MOD function: j % 2 == 0
+   INST_mod12 : it_mod
+   generic map(
+      C_MOD     => 2,
+      C_WIDTH   => 1,
+      C_INIT    => 0,
+      C_STEP    => 1
+   )
+   port map(
+      RST       => RST,
+      CLK       => CLK,
+      LOAD      => sl_done(0),
+      ENABLE    => sl_cntr_en(0),
+      MODULE    => j0_mod_2
+   );
+   mod12 <= TO_INTEGER(UNSIGNED(j0_mod_2));
+   -- 
+   -- END of MOD definitions 
+   -- =============================================
+   -- =             Parameter Functions            
+   -- =============================================
+   sl_cnt_rst <= '0';
+   sl_halt <= HALT;
+
+   -- END of Parameter definitions 
+   sl_loop_i    <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_i_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_j    <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+   sl_loop_j_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+   -- Const bounds for-loops 
+   sl_low_i  <= 0;
+   sl_high_i <= 359;
+   sl_low_j  <= 0;
+   sl_high_j <= 639;
+
+
+   load_i <= '0';
+   load_j <= '0';
+
+   sl_lower_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
+   sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
+
+   sl_upper_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
+   sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
+   -- Special definitions 
+   --mod12 <= ( sl_loop_j_rg ) mod 2;
+
+   -- Entity and control variables
+   -- Release matrix expressions
+
+   sl_fire <= ('1');
+
+   -- Convert FIFO Read Port ND_12IP_13 Argument in_1 : ED_13 : 0 of type IOMM
+   sl_obtain0 <= ('1');  -- set obtain/release to const value; not used
+   sl_release0 <= ('1');
+
+   sl_CONTROL(0) <= sl_fire and ('1');
+   OBTAIN(0) <= sl_obtain0;
+   RELEASE(0) <= sl_release0;
+
+   -- Convert FIFO Read Port ND_12IP_14 Argument in_2 : ED_14 : 1 of type IOMM
+   sl_obtain1 <= ('1');  -- set obtain/release to const value; not used
+   sl_release1 <= ('1');
+
+   sl_CONTROL(1) <= sl_fire and ('1');
+   OBTAIN(1) <= sl_obtain1;
+   RELEASE(1) <= sl_release1;
+
+   -- Convert FIFO Read Port ND_12IP_15 Argument in_3 : ED_15 : 2 of type IOMM
+   sl_obtain2 <= ('1');  -- set obtain/release to const value; not used
+   sl_release2 <= ('1');
+
+   sl_CONTROL(2) <= sl_fire and ('1');
+   OBTAIN(2) <= sl_obtain2;
+   RELEASE(2) <= sl_release2;
+
+   -- Convert FIFO Read Port ND_12IP_16 Argument in_4 : ED_16 : 3 of type IOMM
+   sl_obtain3 <= ('1');  -- set obtain/release to const value; not used
+   sl_release3 <= ('1');
+
+   sl_CONTROL(3) <= sl_fire and ('1');
+   OBTAIN(3) <= sl_obtain3;
+   RELEASE(3) <= sl_release3;
+
+   FIRE <= sl_fire;
+
+   cnt_rst <= sl_cnt_rst or RST;
+
+   -- 
+   -- =============================================
+   -- =             Multirate                      
+   -- =============================================
+   -- Function input parameter "in_0", multirate=1 
+   CNTR_MR0 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(0),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_0,
+         UPPER_BND => sl_mr_ubnd_0,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(0)
+      );
+   -- Function input parameter "in_1", multirate=1 
+   CNTR_MR1 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(1),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_1,
+         UPPER_BND => sl_mr_ubnd_1,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(1)
+      );
+   -- Function input parameter "in_2", multirate=1 
+   CNTR_MR2 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(2),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_2,
+         UPPER_BND => sl_mr_ubnd_2,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(2)
+      );
+   -- Function input parameter "in_3", multirate=1 
+   CNTR_MR3 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(3),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_3,
+         UPPER_BND => sl_mr_ubnd_3,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(3)
+      );
+   -- READ_EN indicates if READ_MUX can read data
+   sl_bla_en   <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');  
+   READ_EN     <= (others=>'0') when (HALT='1') else sl_bla_en;  
+   sl_mr_en   <= READ_ST; 
+   sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en); 
+   sl_enable  <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce 
+   ENABLE     <=  sl_enable or (not sl_fire);
+   -- 
+   LOCK_PRCS: process(CLK) 
+   begin 
+       if rising_edge(CLK) then 
+           if( RST = '1' ) then 
+               sl_mr_lock <= (others=>'0'); 
+           else  
+               if (ENABLE='1') then 
+                   sl_mr_lock <= (others=>'0'); 
+               else 
+                   for i in 0 to 3 loop 
+                       if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then 
+                           sl_mr_lock(i) <= '1'; 
+                       end if; 
+                   end loop; 
+               end if; 
+           end if; 
+       end if; 
+   end process; 
+   -- END of Multirate definitions 
+   -- 
+   -- =============================================
+   -- =             Iterators                      
+   -- =============================================
+   GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
+   	CNTR_RD : counter
+   	generic map ( 
+   		C_STEP    => CNTR_STEP(i),
+   		C_WIDTH   => CNTR_WIDTH(i)
+   	)
+  	 port map (
+   		CLK       => CLK,
+   		RST       => cnt_rst,
+   		ENABLE    => sl_cntr_en(i),
+			LOAD      => sl_load(i),
+   		LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		ITERATOR  => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		REG_CNTR  => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		DONE      => sl_done(i)
+   	);
+   end generate;
+   --
+   DONE_PRCS: process(CLK)
+   begin
+   	if rising_edge(CLK) then
+          if( RST = '1' ) then
+   		    sl_stop     <= '0';
+   		    sl_done_all <= '0';
+   		    sl_sof      <= '1';
+   	    else 
+   		    if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+   			    sl_stop <= '1';
+   		    elsif (WRAP=true) then
+   			    sl_stop <= '0';
+   		    end if;
+   		    if (sl_stop='0') then
+   			    sl_done_all <= sl_cntr_en(N_CNTRS);
+   		    end if;
+   		    if (ENABLE='1') then
+   			    sl_sof <= sl_eof;
+   		    end if;
+   	    end if;
+   	end if;
+   end process;
+   --
+   sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+   CONTROL <= sl_CONTROL;
+   --
+   REG_CNTRS <= sl_reg_cntrs; 
+   DONE <= sl_done_all;     -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+   STOP <= sl_stop;         -- '1' = The couter stoped after the end of the itteration space. 
+   --
+   sl_count      <=  '0' when (sl_stop='1') else
+                     '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
+   sl_cntr_en(0) <=  sl_count; -- makes the EVAL_LOGIC count
+   --
+   sl_cntr_en(N_CNTRS  downto 1) <= sl_cntr_en(N_CNTRS-1  downto 0) and sl_done(N_CNTRS-1  downto 0);
+   sl_eof <= sl_cntr_en(N_CNTRS);   -- End-of-frame
+   --
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_12/src/vhdl/bunny_static_split2rtl_hwn_nd_12_eval_logic_wr.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_12/src/vhdl/bunny_static_split2rtl_hwn_nd_12_eval_logic_wr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..607591356d82fa1ce90c6aaafe9c534aa94daf66
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_12/src/vhdl/bunny_static_split2rtl_hwn_nd_12_eval_logic_wr.vhd
@@ -0,0 +1,312 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_12 is
+   generic ( 
+      N_OUT_PORTS   : natural := 1;
+      WRAP          : boolean := true;
+      N_CNTRS       : natural := 1;
+      QUANT         : natural := 32;
+      PAR_BITWIDTH  : natural :=1;
+      CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+      CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST           : in  std_logic;
+      CLK           : in  std_logic;
+      WRITE_EN      : out std_logic_vector(0 downto 0);
+      WRITE_ST      : in  std_logic_vector(0 downto 0);
+      HALT          : in  std_logic;
+      FIRE          : out std_logic;
+      DONE          : out std_logic;
+      STOP          : out std_logic;
+      CONTROL       : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+   );
+end bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_12;
+
+architecture RTL of bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_12 is	
+   -- 
+   component counter is 
+      generic( 
+         C_STEP    : natural := 10; 
+         C_WIDTH   : natural := 10 
+      ); 
+      port ( 
+         RST       : in  std_logic; 
+         CLK       : in  std_logic; 
+         ENABLE    : in  std_logic; 
+         LOAD      : in  std_logic; 
+         LOWER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         UPPER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         ITERATOR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         REG_CNTR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         DONE      : out std_logic 
+      ); 
+   end component; 
+   -- 
+   component it_mod is 
+   generic( 
+      C_MOD     : natural := 10; 
+      C_WIDTH   : natural := 10; 
+      C_INIT    : natural :=  1; 
+      C_STEP    : natural :=  1  
+   ); 
+   port ( 
+      RST       : in  std_logic; 
+      CLK       : in  std_logic; 
+      LOAD      : in  std_logic; 
+      ENABLE    : in  std_logic; 
+      MODULE    : out std_logic_vector(C_WIDTH-1 downto 0) 
+   ); 
+   end component; 
+   -- 
+   -- Multirate related signals
+   signal sl_bla_en   : std_logic_vector(0 downto 0); 
+   signal sl_mr_en    : std_logic_vector(0 downto 0); 
+   signal sl_mr_done  : std_logic_vector(0 downto 0); 
+   signal sl_mr_lock  : std_logic_vector(0 downto 0); 
+   signal sl_enables  : std_logic_vector(0 downto 0); 
+   signal sl_enable   : std_logic; 
+   signal ENABLE      : std_logic; 
+   -- Function output parameter "out_0", multirate=1 
+   constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   --  
+   -- Parameter related signals 
+   --  
+   -- Iterator (counter) related signals 
+   signal sl_low_i, sl_high_i : integer; 
+   signal sl_low_j, sl_high_j : integer; 
+   signal sl_loop_i, sl_loop_i_rg : integer;
+   signal sl_loop_j, sl_loop_j_rg : integer;
+   signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   -- 
+   signal sl_cntr_en  : std_logic_vector(N_CNTRS   downto 0); 
+   signal sl_done     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_done_all : std_logic; 
+   signal sl_load     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_stop     : std_logic; 
+   signal sl_fire     : std_logic; 
+   signal sl_eof      : std_logic; 
+   signal sl_sof      : std_logic; 
+   signal sl_count    : std_logic; 
+   -- 
+   -- Special Control signal
+   signal sl_CONTROL       : std_logic_vector(N_OUT_PORTS-1 downto 0);
+   signal sl_no_request    : std_logic;
+   -- 
+   -- alias signals 
+   alias update_i : std_logic is sl_cntr_en(1);
+   alias update_j : std_logic is sl_cntr_en(0);
+   -- 
+   alias load_i : std_logic is sl_load(1);
+   alias load_j : std_logic is sl_load(0);
+   -- Trigger signals 
+   signal sl_trigger_i : std_logic;
+   signal sl_trigger_j : std_logic;
+
+   signal e0, e1 : boolean;
+
+   -- define control variables 
+   -- MOD related signals 
+   signal div25 : integer;
+   signal mod12 : integer;
+
+
+   type state_type is (s_idle, s_halt, s_count, s_release);
+   signal state : state_type;
+   signal halt_cnt : integer;
+   signal sl_halt : std_logic;
+
+   signal sl_cnt_rst : std_logic;
+   signal cnt_rst : std_logic;
+   signal j0_mod_2 : std_logic_vector(1-1 downto 0);
+
+begin
+
+   -- =============================================
+   -- =             MOD Functions                  
+   -- =============================================
+   -- MOD function: j % 2 == 0
+   INST_mod12 : it_mod
+   generic map(
+      C_MOD     => 2,
+      C_WIDTH   => 1,
+      C_INIT    => 0,
+      C_STEP    => 1
+   )
+   port map(
+      RST       => RST,
+      CLK       => CLK,
+      LOAD      => sl_done(0),
+      ENABLE    => sl_cntr_en(0),
+      MODULE    => j0_mod_2
+   );
+   mod12 <= TO_INTEGER(UNSIGNED(j0_mod_2));
+   -- 
+   -- END of MOD definitions 
+   --  
+   -- Parameter related signal assignments 
+   sl_cnt_rst <= '0';
+   sl_halt <= HALT;
+   -- END of Parameter definitions 
+
+   sl_loop_i    <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_i_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_j    <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+   sl_loop_j_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+   -- Const bounds for-loops 
+   sl_low_i  <= 0;
+   sl_high_i <= 359;
+   sl_low_j  <= 0;
+   sl_high_j <= 639;
+
+
+   load_i <= '0';
+   load_j <= '0';
+
+   sl_lower_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
+   sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
+
+   sl_upper_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
+   sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
+
+   -- Special definitions 
+   --mod12 <= ( sl_loop_j_rg ) mod 2;
+
+   -- Entity and control variables
+   e0 <= -mod12=0;
+   e1 <= 1-mod12=0;
+
+   sl_fire <= ('1');
+
+   -- Convert FIFO Write Port out_1 : ED_17
+   sl_CONTROL(0) <= sl_fire and b2std((e0));
+
+   -- Convert FIFO Write Port out_2 : ED_18
+   sl_CONTROL(1) <= sl_fire and b2std((e1));
+
+   FIRE <= sl_fire;
+
+   cnt_rst <= sl_cnt_rst or RST;
+
+   -- 
+   -- =============================================
+   -- =             Multirate                      
+   -- =============================================
+   -- Function output parameter "out_0", multirate=1 
+   CNTR_MR0 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(0),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_0,
+         UPPER_BND => sl_mr_ubnd_0,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(0)
+      );
+   -- 
+   -- WRITE_EN indicates if date can be written to WRITE_MUX
+   sl_bla_en      <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
+   WRITE_EN    <=  (others=>'0') when (HALT='1') else sl_bla_en;
+   -- 
+   sl_mr_en    <= (not sl_mr_lock) and WRITE_ST; 
+   sl_enables  <= sl_mr_lock or (sl_mr_done and sl_mr_en); 
+   sl_enable   <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0';  -- and_reduce 
+   ENABLE      <= sl_enable or (not sl_fire);
+   -- 
+   LOCK_PRCS: process(CLK) 
+   begin 
+       if rising_edge(CLK) then 
+           if( RST = '1' ) then 
+               sl_mr_lock <= (others=>'0'); 
+           else  
+               if (ENABLE='1') then 
+                   sl_mr_lock <= (others=>'0'); 
+               else 
+                   for i in 0 to 0 loop 
+                       if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then 
+                           sl_mr_lock(i) <= '1'; 
+                       end if; 
+                   end loop; 
+               end if; 
+           end if; 
+       end if; 
+   end process; 
+   -- END of Multirate definitions 
+   -- 
+   -- =============================================
+   -- =             Iterators                      
+   -- =============================================
+   GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
+   	CNTR_WR : counter
+   	generic map ( 
+   		C_STEP    => CNTR_STEP(i),
+   		C_WIDTH   => CNTR_WIDTH(i)
+   	)
+  	 port map (
+   		CLK       => CLK,
+   		RST       => cnt_rst,
+   		ENABLE    => sl_cntr_en(i),
+   		LOAD      => sl_load(i),
+   		LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		ITERATOR  => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		REG_CNTR  => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		DONE      => sl_done(i)
+   	);
+   end generate;
+   --
+   DONE_PRCS: process(CLK)
+   begin
+   	if rising_edge(CLK) then
+   	    if( RST = '1' ) then
+   		    sl_stop     <= '0';
+   		    sl_done_all <= '0';
+   		    sl_sof      <= '1';
+   	    else 
+   		    if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+   			    sl_stop <= '1';
+   		    elsif (WRAP=true) then
+   			    sl_stop <= '0';
+   		    end if;
+   		    if (sl_stop='0') then
+   			    sl_done_all <= sl_cntr_en(N_CNTRS);
+   		    end if;
+   		    if (ENABLE='1') then
+   			    sl_sof <= sl_eof;
+   		    end if;
+   	    end if;
+   	end if;
+   end process;
+   --
+   sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+   CONTROL <= sl_CONTROL;
+   --
+   DONE <= sl_done_all;     -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+   STOP <= sl_stop;         -- '1' = The couter stoped after the end of the itteration space. 
+   --
+   sl_count      <=  '0' when (sl_stop='1') else
+   			'1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
+   sl_cntr_en(0) <=  sl_count; -- makes the EVAL_LOGIC count
+   --
+   sl_cntr_en(N_CNTRS  downto 1) <= sl_cntr_en(N_CNTRS-1  downto 0) and sl_done(N_CNTRS-1  downto 0);
+   sl_eof <= sl_cntr_en(N_CNTRS);      -- End-of-frame (combinatorial; beter not use it outside)
+   --
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_12/src/vhdl/bunny_static_split2rtl_hwn_nd_12_execution_unit.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_12/src/vhdl/bunny_static_split2rtl_hwn_nd_12_execution_unit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7fe5b437c2ee65d07bdec125f3966dad1e23c245
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_12/src/vhdl/bunny_static_split2rtl_hwn_nd_12_execution_unit.vhd
@@ -0,0 +1,120 @@
+-- Execute Unit automatically generated by KpnMapper
+-- Function "serialize4t8to32"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_bunny_static_split2rtl_functions_1_lib;
+use compaandesign_com_bunny_static_split2rtl_functions_1_lib.all;
+
+entity bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_12 is
+   generic (
+      N_INPORTS  : natural := 1;
+      N_OUTPORTS : natural := 1;
+      IP_RESET   : natural := 1; 
+      STIM_DIR   : string  := "bla";
+      QUANT      : natural := 32;
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1; 
+      CNTR_QUANT : natural := 32; 
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+   );
+   port (
+      RST        : in  std_logic;
+      CLK        : in  std_logic;
+      -- Funtion Input parameters
+      IN_PORT_0    : in  std_logic_vector(7 downto 0);  -- Param. "in0"
+      IN_PORT_1    : in  std_logic_vector(7 downto 0);  -- Param. "in1"
+      IN_PORT_2    : in  std_logic_vector(7 downto 0);  -- Param. "in2"
+      IN_PORT_3    : in  std_logic_vector(7 downto 0);  -- Param. "in3"
+      READ       : out std_logic_vector(N_INPORTS-1 downto 0);
+      EXIST      : in  std_logic_vector(N_INPORTS-1 downto 0);
+      -- Iterators
+      REG_CNTRS_RD : in  std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
+      -- Funtion Output parameters
+      OUT_PORT_0   : out std_logic_vector(31 downto 0);  -- Param. "result"
+      WRITE      : out std_logic_vector(N_OUTPORTS-1 downto 0);
+      FULL       : in  std_logic_vector(N_OUTPORTS-1 downto 0);
+      STOP_RD    : in  std_logic;
+      STOP_WR    : in  std_logic;
+      ERROR      : out std_logic
+   );
+end bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_12 ;
+
+-- Laura implementation
+architecture Laura of bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_12 is
+
+   component serialize4t8to32 is
+      generic (
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1; 
+         CNTR_QUANT : natural := 32; 
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST   : in std_logic;
+         CLK   : in std_logic;
+         -- Inputs 
+         ip_in0  : in  std_logic_vector(7 downto 0);  
+         ip_in1  : in  std_logic_vector(7 downto 0);  
+         ip_in2  : in  std_logic_vector(7 downto 0);  
+         ip_in3  : in  std_logic_vector(7 downto 0);  
+         -- Iterators 
+         it_j : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+         it_i : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+         EXIST : in  std_logic_vector(3 downto 0);
+         READF : out std_logic_vector(3 downto 0);
+         -- Outputs 
+         op_result : out std_logic_vector(31 downto 0);
+         FULL  : in  std_logic_vector(0 downto 0);
+         WRITEF: out std_logic_vector(0 downto 0);
+         --
+         STOP_RD : in  std_logic;
+         STOP_WR : in  std_logic;
+         ERROR   : out std_logic
+      );
+   end component;
+
+   signal sl_RST : std_logic;
+
+begin
+
+   sl_RST <= RST when IP_RESET=1 else not RST;
+
+   FUNC : serialize4t8to32
+   generic map (
+         STIM_DIR      => STIM_DIR,
+         c_STAGES      => c_STAGES,
+         N_CNTRS       => N_CNTRS,
+         CNTR_QUANT    => CNTR_QUANT,
+         CNTR_WIDTH    => CNTR_WIDTH
+   )
+   port map (
+      RST   => sl_RST,
+      CLK   => CLK,
+      -- Inputs 
+      ip_in0 => IN_PORT_0,
+      ip_in1 => IN_PORT_1,
+      ip_in2 => IN_PORT_2,
+      ip_in3 => IN_PORT_3,
+      -- Iterators 
+      it_j => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
+      it_i => REG_CNTRS_RD(1*CNTR_QUANT+CNTR_WIDTH(1)-1 downto 1*CNTR_QUANT),
+      EXIST => EXIST,
+      READF => READ,
+      -- Outputs 
+      op_result => OUT_PORT_0,
+      FULL  => FULL,
+      WRITEF=> WRITE,
+      -- 
+      STOP_RD => STOP_RD,
+      STOP_WR => STOP_WR,
+      ERROR   => ERROR
+   );
+
+end Laura;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_13/hdllib.cfg b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_13/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..5019801ef657fe76c1618f02a67aba643554788e
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_13/hdllib.cfg
@@ -0,0 +1,18 @@
+hdl_lib_name = compaandesign_com_bunny_static_split2rtl_hwn_nd_13_1
+hdl_library_clause_name = compaandesign_com_bunny_static_split2rtl_hwn_nd_13_1_lib
+hdl_lib_uses_synth = compaandesign_com_bunny_static_split2rtl_functions_1 compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1 compaandesign_com_common_extern_connector_1 
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+	src/vhdl/bunny_static_split2rtl_hwn_nd_13_execution_unit.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_13_eval_logic_rd.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_13_eval_logic_wr.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_13.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_13/src/vhdl/bunny_static_split2rtl_hwn_nd_13.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_13/src/vhdl/bunny_static_split2rtl_hwn_nd_13.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1623163ce7da3dc8b72cffc724d855468294e3a2
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_13/src/vhdl/bunny_static_split2rtl_hwn_nd_13.vhd
@@ -0,0 +1,504 @@
+-- HWN Entity File automatically generated by KpnMapper (writeHdlHWNodeFile)
+-- Top level file for a Hardware Accelerator
+-- Function "merge2t32to64"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+library compaandesign_com_common_extern_connector_1_lib;
+use compaandesign_com_common_extern_connector_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_13 is
+   generic (
+      STIM_DIR   : string  := "bla";
+      RESET_HIGH : natural := 1;
+      PAR_WIDTH  : natural := 16;
+      QUANT      : natural := 32;
+      WRAP       : boolean := true
+   );
+   port (
+
+      -- Dataflow input interfaces
+      -- ED_17 : in_0
+      ND_13IP_17_Rd    : out std_logic;
+      ND_13IP_17_Din   : in  std_logic_vector(31 downto 0);
+      ND_13IP_17_Exist : in  std_logic; 
+      ND_13IP_17_CLK   : out std_logic;
+      ND_13IP_17_CTRL  : in  std_logic;
+
+      -- ED_18 : in_1
+      ND_13IP_18_Rd    : out std_logic;
+      ND_13IP_18_Din   : in  std_logic_vector(31 downto 0);
+      ND_13IP_18_Exist : in  std_logic; 
+      ND_13IP_18_CLK   : out std_logic;
+      ND_13IP_18_CTRL  : in  std_logic;
+
+      -- Dataflow Control Input interfaces
+      -- Dataflow output interfaces
+      -- ED_19_20 : out_0
+      ND_13OP_1_d1_ND_13OP_1_Wr   : out std_logic;
+      ND_13OP_1_d1_ND_13OP_1_Dout : out std_logic_vector(63 downto 0);
+      ND_13OP_1_d1_ND_13OP_1_Full : in  std_logic;
+      ND_13OP_1_d1_ND_13OP_1_CLK  : out std_logic;
+      ND_13OP_1_d1_ND_13OP_1_CTRL : out std_logic;
+
+      PARAM_DT : in  std_logic_vector(PAR_WIDTH+10-1 downto 0);
+      PARAM_LD : in  std_logic;
+
+      RST      : in  std_logic;
+      CLK      : in  std_logic;
+      STOP     : out std_logic;
+      ERROR    : out std_logic;
+      BLOCK_RD : out std_logic
+   );
+end bunny_static_split2rtl_hwn_nd_13;
+
+architecture RTL of bunny_static_split2rtl_hwn_nd_13 is
+   --
+   -- ====================================
+   -- =     Constants declaration        =
+   -- ====================================
+   -- Setting the parameters of the HW Node
+   constant c_IN_PORTS     : natural := 2; -- number of input ports of a HW node
+   constant c_OUT_PORTS    : natural := 1; -- number of output ports of a HW node
+   constant c_IN_FUNC_VAR  : natural := 2; -- number of input ports of a HW IP
+   constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
+   constant c_COUNTERS     : natural := 2; -- number of iterators
+   -- ===========================================
+   -- = Iterators run from Inner to Outer loop  =
+   -- ===========================================
+   constant c_CNTR_QUANT   : natural := 10;
+   constant c_CNTR_STEPS   : t_counter_step  := ( 0=>1, 1=>1, others=>1 );
+   constant c_CNTR_WIDTHS  : t_counter_width := ( 0=>10, 1=>10, others=>10 );
+   constant c_STAGES       : natural := 1; -- number of pipeline stages or delay
+   constant c_IP_RESET     : natural := 1; -- active level of the HW IP reset signal
+   constant c_WRAP         : boolean := WRAP; -- Operation mode: Single_Shot (false) or Continuous (true)
+   constant c_EXT_PAR      : natural := 0; -- number of external parameters
+   constant c_INT_PAR      : natural := 0; -- number of internal parameters
+   constant c_N_PAR        : natural := 0; -- no parameters are used
+   constant c_PAR_BITWIDTH : natural := PAR_WIDTH; -- aggregate bitwidth of the parameter vector
+   constant c_PAR_VECTOR   : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
+       (0,0,0,0), (0,0,0,0)    -- two dummy elements
+   );
+   --
+   -- ====================================
+   -- =     Components declaration       =
+   -- ====================================
+   component bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_13 is
+      generic (
+         N_IN_PORTS    : natural := 1;
+         WRAP          : boolean := true;
+         N_CNTRS       : natural := 1; 
+         QUANT         : natural := 32;
+         PAR_BITWIDTH  : natural :=1;
+         CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+         CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+      );
+      port (
+         RST           : in  std_logic;
+         CLK           : in  std_logic;
+         REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1  downto 0); 
+         READ_EN       : out std_logic_vector(c_IN_FUNC_VAR-1  downto 0);
+         READ_ST       : in  std_logic_vector(c_IN_FUNC_VAR-1  downto 0);
+         HALT          : in  std_logic;
+         FIRE          : out std_logic;
+         DONE          : out std_logic;
+         STOP          : out std_logic;
+         CONTROL       : out std_logic_vector(N_IN_PORTS-1 downto 0);
+         OBTAIN        : out std_logic_vector(N_IN_PORTS-1 downto 0);
+         RELEASE       : out std_logic_vector(N_IN_PORTS-1 downto 0)
+      );
+   end component;
+
+   component READ_MUX is
+      generic (
+         N_PORTS    : natural := 1;
+         PORT_WIDTH : natural := 32  
+      );
+      port(
+         IN_PORTS   : in  std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
+         EXISTS     : in  std_logic_vector(N_PORTS-1 downto 0);
+         READS      : out std_logic_vector(N_PORTS-1 downto 0);
+         SOFS       : in  std_logic_vector(N_PORTS-1 downto 0);
+
+         OUT_PORT   : out std_logic_vector(PORT_WIDTH-1 downto 0);
+         EXIST      : out std_logic;
+         READ       : in  std_logic;
+         SOF        : in  std_logic;
+		CLK        : in std_logic;
+
+         READ_EN    : in  std_logic;
+         READ_ST    : out std_logic;
+         CONTROL    : in  std_logic_vector(N_PORTS-1 downto 0);
+         OBTAIN     : in  std_logic_vector(N_PORTS-1 downto 0);
+         RELEASE    : in  std_logic_vector(N_PORTS-1 downto 0)
+      );
+   end component;
+
+   component bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_13 is
+      generic ( 
+         N_OUT_PORTS   : natural := 1;
+         WRAP          : boolean := true;
+         N_CNTRS       : natural := 1; 
+         QUANT         : natural := 32;
+         PAR_BITWIDTH  : natural :=1;
+         CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+         CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+      );
+      port (
+         RST           : in  std_logic;
+         CLK           : in  std_logic;
+         WRITE_EN      : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+         WRITE_ST      : in  std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+         HALT          : in  std_logic;
+         FIRE          : out std_logic;
+         DONE          : out std_logic;
+         STOP          : out std_logic;
+         CONTROL       : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+      );
+   end component;
+
+   component WRITE_DEMUX is
+      generic (
+         N_PORTS : natural := 1
+      );
+      port(
+         WRITES   : out std_logic_vector(N_PORTS-1 downto 0);
+         WRITE    : in  std_logic;
+
+         FULLS    : in  std_logic_vector(N_PORTS-1 downto 0);
+         FULL     : out std_logic;
+
+         WRITE_EN : in  std_logic;
+         WRITE_ST : out std_logic;
+         CONTROL  : in  std_logic_vector(N_PORTS-1 downto 0)
+      );
+   end component;
+
+
+   component bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_13 is
+      generic (
+         N_INPORTS  : natural := 1;
+         N_OUTPORTS : natural := 1;
+         IP_RESET   : natural := 1;
+         QUANT      : natural := 32;
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1;
+         CNTR_QUANT : natural := 32;
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST        : in  std_logic;
+         CLK        : in  std_logic;
+
+         -- Iterators
+         REG_CNTRS_RD : in  std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
+         -- Func. Input parameters
+         IN_PORT_0 : in  std_logic_vector(31 downto 0); -- in0
+         IN_PORT_1 : in  std_logic_vector(31 downto 0); -- in1
+         READ       : out std_logic_vector(N_INPORTS-1 downto 0);
+         EXIST      : in  std_logic_vector(N_INPORTS-1 downto 0);
+         -- Func. Output parameters
+         OUT_PORT_0 : out std_logic_vector(63 downto 0); -- result
+         WRITE      : out std_logic_vector(N_OUTPORTS-1 downto 0);
+         FULL       : in  std_logic_vector(N_OUTPORTS-1 downto 0);
+         --
+         STOP_RD    : in  std_logic;
+         STOP_WR    : in  std_logic;
+         ERROR      : out std_logic
+      );
+   end component;
+
+   component INTERNAL_PARAMETERS is 
+      generic (
+         PAR_BITWIDTH : natural:=1;
+         PAR_VECTOR   : t_par_vector;
+         N_PAR        : natural:=0;
+         START_IN_RUN  : boolean := FALSE
+      );
+      port (  
+         RST        : in  std_logic;
+         CLK        : in  std_logic;
+
+         HALT_RD    : out std_logic;
+         HALT_WR    : out std_logic;
+         SOF_RD     : in  std_logic;
+         SOF_WR     : in  std_logic;
+         LOAD_PARAM : out std_logic;
+
+         par_one_in_Rd    : out std_logic;
+         par_one_in_Din   : in std_logic_vector(32-1 downto 0);
+         par_one_in_Exist : in std_logic;
+         par_one_in_CLK   : out std_logic;
+         par_one_in_CTRL  : in std_logic;
+
+         PARAMETERS_RD : out std_logic_vector(32-1 downto 0);
+         PARAMETERS_WR : out std_logic_vector(32-1 downto 0)
+      );
+   end component;
+
+   --
+   -- ====================================
+   -- =       Signals declaration        =
+   -- ====================================
+   -- 
+   -- HW Node Input Ports
+   signal sl_IN_PORTS_0   : std_logic_vector(1*32-1 downto 0); -- in0
+   signal sl_IN_PORTS_1   : std_logic_vector(1*32-1 downto 0); -- in1
+   signal sl_EXISTS       : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_READS        : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_CTRLS        : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_control_rd   : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_obtain_rd    : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_release_rd   : std_logic_vector(c_IN_PORTS-1 downto 0);
+   -- 
+   -- Func. Input parameters
+   signal sl_in_port_0    : std_logic_vector(31 downto 0); -- in0
+   signal sl_in_port_1    : std_logic_vector(31 downto 0); -- in1
+   signal sl_exist        : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read         : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read_en      : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read_st      : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   -- 
+   signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
+   -- 
+   -- HW Node Output Ports
+   signal sl_WRITES       : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_FULLS        : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_control_wr   : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_lortnoc_wr   : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   -- 
+   -- Func. Output parameters
+   signal sl_out_port_0   : std_logic_vector(63 downto 0); -- result
+   signal sl_full         : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write        : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write_en     : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write_st     : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   -- 
+   -- 
+   signal sl_halt             : std_logic;
+   signal sl_halted           : std_logic;
+   signal sl_halt_wr          : std_logic;
+   signal sl_halt_rd          : std_logic;
+   signal sl_param_halt_wr    : std_logic;
+   signal sl_param_halt_rd    : std_logic;
+   signal sl_done_wr          : std_logic;
+   signal sl_done_rd          : std_logic;
+   signal sl_stop_wr          : std_logic;
+   signal sl_stop_rd          : std_logic;
+   signal sl_fire_wr          : std_logic;
+   signal sl_fire_rd          : std_logic;
+   signal sl_sof_wr           : std_logic;
+   signal sl_sof_rd           : std_logic;
+   signal sl_error            : std_logic;
+   signal sl_load_param       : std_logic;
+
+   --  
+   -- Parameter related signals 
+   signal sl_param_fifo_full     : std_logic;
+   signal sl_sync_num            : std_logic_vector(9 downto 0);
+
+   signal sl_RST : std_logic;
+
+begin 
+
+   sl_RST <= RST when RESET_HIGH=1 else not RST;
+      ND_13IP_17_CLK   <= CLK;
+      ND_13IP_18_CLK   <= CLK;
+      ND_13OP_1_d1_ND_13OP_1_CLK  <= CLK;
+
+   --
+   -- ==========================================================
+   -- =       HWN Input related modules                        =
+   -- ==========================================================
+   -- Func. Input param. "in0"
+   RD_MUX_0 : READ_MUX
+   generic map (
+      N_PORTS    => 1,
+      PORT_WIDTH => 32
+   )
+   port map (
+      IN_PORTS   => sl_IN_PORTS_0,
+      EXISTS     => sl_EXISTS(0 downto 0),
+      READS      => sl_READS(0 downto 0),
+      SOFS       => sl_CTRLS(0 downto 0),
+
+      OUT_PORT   => sl_in_port_0,
+      EXIST      => sl_exist(0),
+      READ       => sl_read(0),
+      SOF        => sl_sof_rd,
+      CLK        => CLK,
+
+      READ_EN    => sl_read_en(0),
+      READ_ST    => sl_read_st(0),
+      CONTROL    => sl_control_rd(0 downto 0),
+      OBTAIN     => sl_obtain_rd(0 downto 0),
+      RELEASE    => sl_release_rd(0 downto 0)
+   );
+
+   ND_13IP_17_Rd   <= sl_READS(0);
+
+   sl_IN_PORTS_0 <= ND_13IP_17_Din;
+
+   -- Func. Input param. "in1"
+   RD_MUX_1 : READ_MUX
+   generic map (
+      N_PORTS    => 1,
+      PORT_WIDTH => 32
+   )
+   port map (
+      IN_PORTS   => sl_IN_PORTS_1,
+      EXISTS     => sl_EXISTS(1 downto 1),
+      READS      => sl_READS(1 downto 1),
+      SOFS       => sl_CTRLS(1 downto 1),
+
+      OUT_PORT   => sl_in_port_1,
+      EXIST      => sl_exist(1),
+      READ       => sl_read(1),
+      SOF        => sl_sof_rd,
+      CLK        => CLK,
+
+      READ_EN    => sl_read_en(1),
+      READ_ST    => sl_read_st(1),
+      CONTROL    => sl_control_rd(1 downto 1),
+      OBTAIN     => sl_obtain_rd(1 downto 1),
+      RELEASE    => sl_release_rd(1 downto 1)
+   );
+
+   ND_13IP_18_Rd   <= sl_READS(1);
+
+   sl_IN_PORTS_1 <= ND_13IP_18_Din;
+
+   sl_EXISTS      <= ND_13IP_18_Exist & ND_13IP_17_Exist ;
+   sl_CTRLS       <= ND_13IP_18_CTRL & ND_13IP_17_CTRL ;
+
+   EVAL_RD : bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_13
+   generic map ( 
+      N_IN_PORTS    => c_IN_PORTS,
+      WRAP          => c_WRAP,
+      N_CNTRS       => c_COUNTERS,
+      QUANT         => c_CNTR_QUANT,
+      PAR_BITWIDTH  => c_PAR_BITWIDTH,
+      CNTR_STEP     => c_CNTR_STEPS,
+      CNTR_WIDTH    => c_CNTR_WIDTHS
+   )
+   port map(
+      RST           => sl_RST,
+      CLK           => CLK,
+      REG_CNTRS     => sl_REG_CNTRS_RD,
+      READ_EN       => sl_read_en,
+      READ_ST       => sl_read_st,
+      HALT          => sl_halt_rd,
+      FIRE          => sl_fire_rd,
+      DONE          => sl_done_rd,
+      STOP          => sl_stop_rd,
+      CONTROL       => sl_control_rd,
+      OBTAIN        => sl_obtain_rd,
+      RELEASE       => sl_release_rd
+   );
+
+   --
+   -- ==========================================================
+   -- =       HWN Output related modules                       =
+   -- ==========================================================
+   -- 
+   -- Func. Output param. "result"
+   DEMUX_0 : WRITE_DEMUX
+   generic map (
+      N_PORTS => 1
+   )
+   port map (
+      WRITES   => sl_WRITES(0 downto 0),
+      FULLS    => sl_FULLS(0 downto 0),
+      CONTROL  => sl_lortnoc_wr(0 downto 0),
+      WRITE    => sl_write(0),
+      FULL     => sl_full(0),
+      WRITE_EN => sl_write_en(0),
+      WRITE_ST => sl_write_st(0)
+   );
+   --
+   ND_13OP_1_d1_ND_13OP_1_Dout <= sl_out_port_0;  -- Func. Output param. "result"
+   ND_13OP_1_d1_ND_13OP_1_CTRL <= sl_sof_wr ;
+   ND_13OP_1_d1_ND_13OP_1_Wr   <= sl_WRITES(0);
+   sl_FULLS(0) <= ND_13OP_1_d1_ND_13OP_1_Full;
+   sl_lortnoc_wr(0) <= sl_control_wr(0);
+   --
+   --
+   EVAL_WR : bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_13
+   generic map ( 
+      N_OUT_PORTS   => c_OUT_PORTS,
+      WRAP          => c_WRAP,
+      N_CNTRS       => c_COUNTERS,
+      QUANT         => c_CNTR_QUANT,
+      PAR_BITWIDTH  => c_PAR_BITWIDTH,
+      CNTR_STEP     => c_CNTR_STEPS,
+      CNTR_WIDTH    => c_CNTR_WIDTHS
+   )
+   port map (
+      RST           => sl_RST,
+      CLK           => CLK,
+      WRITE_EN      => sl_write_en,
+      WRITE_ST      => sl_write_st,
+      HALT          => sl_halt_wr,
+      FIRE          => sl_fire_wr,
+      DONE          => sl_done_wr,
+      STOP          => sl_stop_wr,
+      CONTROL       => sl_control_wr
+   );
+
+   --
+   -- ==========================================================
+   -- =       HWN Execution Unit                               =
+   -- ==========================================================
+   EX : bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_13
+   generic map (
+      N_INPORTS  => c_IN_FUNC_VAR,
+      N_OUTPORTS => c_OUT_FUNC_VAR, 
+      IP_RESET   => c_IP_RESET,
+      QUANT      => QUANT,
+      STIM_DIR   => STIM_DIR,
+      c_STAGES   => c_STAGES,
+      N_CNTRS    => c_COUNTERS,
+      CNTR_QUANT => c_CNTR_QUANT,
+      CNTR_WIDTH => c_CNTR_WIDTHS
+   )
+   port map (
+      RST        => sl_RST,
+      CLK        => CLK,
+      -- Iterators
+      REG_CNTRS_RD => sl_REG_CNTRS_RD,
+      -- Func. Input parameters
+      IN_PORT_0    => sl_in_port_0,
+      IN_PORT_1    => sl_in_port_1,
+      READ       => sl_read,
+      EXIST      => sl_exist,
+      -- Func. Output parameters
+      OUT_PORT_0   => sl_out_port_0,
+      WRITE      => sl_write,
+      FULL       => sl_full,
+      --
+      STOP_WR    => sl_stop_wr,
+      STOP_RD    => sl_stop_rd,
+      ERROR      => sl_error
+   );
+
+   -- ==========================================================
+   -- =       PARAMETERIZATION                                 =
+   -- ==========================================================
+   -- no parameters
+   sl_halt_rd <= '0';
+   sl_halt_wr <= '0';
+--   sl_halted  <= sl_sof_rd;
+   STOP <= sl_done_wr;
+   ERROR <= sl_error;
+   BLOCK_RD <= not (  (  sl_READS(0)  )and  (  sl_READS(1)  ) );
+
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_13/src/vhdl/bunny_static_split2rtl_hwn_nd_13_eval_logic_rd.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_13/src/vhdl/bunny_static_split2rtl_hwn_nd_13_eval_logic_rd.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e647dbe5159756829e551352fcb266f7e6113225
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_13/src/vhdl/bunny_static_split2rtl_hwn_nd_13_eval_logic_rd.vhd
@@ -0,0 +1,325 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_13 is
+   generic (
+      N_IN_PORTS    : natural := 1;
+      WRAP          : boolean := true;
+      N_CNTRS       : natural := 1; 
+      QUANT         : natural := 32;
+      PAR_BITWIDTH  : natural  :=1;
+      CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+      CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST           : in  std_logic;
+      CLK           : in  std_logic;
+      REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+      READ_EN       : out std_logic_vector(1 downto 0);
+      READ_ST       : in  std_logic_vector(1 downto 0);
+      HALT          : in  std_logic;
+      FIRE          : out std_logic;
+      DONE          : out std_logic;
+      STOP          : out std_logic;
+      CONTROL       : out std_logic_vector(N_IN_PORTS-1 downto 0);
+      OBTAIN        : out std_logic_vector(N_IN_PORTS-1 downto 0);
+      RELEASE       : out std_logic_vector(N_IN_PORTS-1 downto 0)
+   );
+end bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_13;
+
+architecture RTL of bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_13 is
+   -- 
+   component counter is 
+      generic( 
+         C_STEP    : natural := 10; 
+         C_WIDTH   : natural := 10 
+      ); 
+      port ( 
+         RST       : in  std_logic; 
+         CLK       : in  std_logic; 
+         ENABLE    : in  std_logic; 
+         LOAD      : in  std_logic; 
+         LOWER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         UPPER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         ITERATOR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         REG_CNTR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         DONE      : out std_logic 
+      ); 
+   end component; 
+   -- 
+   component it_mod is 
+   generic( 
+      C_MOD     : natural := 10; 
+      C_WIDTH   : natural := 10; 
+      C_INIT    : natural :=  1; 
+      C_STEP    : natural :=  1  
+   ); 
+   port ( 
+      RST       : in  std_logic; 
+      CLK       : in  std_logic; 
+      LOAD      : in  std_logic; 
+      ENABLE    : in  std_logic; 
+      MODULE    : out std_logic_vector(C_WIDTH-1 downto 0) 
+   ); 
+   end component; 
+   -- 
+   --  
+   -- Parameter related signals 
+   -- 
+   -- Iterator (counter) related signals 
+   signal sl_low_i, sl_high_i : integer;
+   signal sl_low_j, sl_high_j : integer;
+   signal sl_loop_i, sl_loop_i_rg : integer;
+   signal sl_loop_j, sl_loop_j_rg : integer;
+   signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   -- 
+   signal sl_cntr_en  : std_logic_vector(N_CNTRS   downto 0); 
+   signal sl_done     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_done_all : std_logic; 
+   signal sl_load     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_stop     : std_logic; 
+   signal sl_fire     : std_logic; 
+   signal sl_sof      : std_logic; 
+   signal sl_eof      : std_logic; 
+   signal sl_count    : std_logic; 
+
+   -- alias signals 
+   alias update_i : std_logic is sl_cntr_en(1);
+   alias update_j : std_logic is sl_cntr_en(0);
+   alias load_i : std_logic is sl_load(1);
+   alias load_j : std_logic is sl_load(0);
+
+   -- Trigger signals 
+   signal sl_trigger_i : std_logic;
+   signal sl_trigger_j : std_logic;
+
+   -- Special Control signal
+   signal sl_CONTROL       : std_logic_vector(N_IN_PORTS-1 downto 0);
+   signal sl_no_request    : std_logic;
+   -- 
+   -- Multirate related signals
+   signal sl_bla_en   : std_logic_vector(1 downto 0); 
+   signal sl_mr_en    : std_logic_vector(1 downto 0); 
+   signal sl_mr_done  : std_logic_vector(1 downto 0); 
+   signal sl_mr_lock  : std_logic_vector(1 downto 0); 
+   signal sl_enables  : std_logic_vector(1 downto 0); 
+   signal sl_enable   : std_logic; 
+   signal ENABLE      : std_logic; 
+   -- Function input parameter "in_0", multirate=1 
+   constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   -- Function input parameter "in_1", multirate=1 
+   constant sl_mr_lbnd_1 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_1 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+
+
+   signal sl_obtain0  : std_logic;
+   signal sl_release0 : std_logic;
+   signal sl_obtain1  : std_logic;
+   signal sl_release1 : std_logic;
+
+   -- define control variables 
+
+   type state_type is (s_idle, s_halt, s_count, s_release);
+   signal state : state_type;
+   signal halt_cnt : integer;
+   signal sl_halt : std_logic;
+
+   signal sl_cnt_rst : std_logic;
+   signal cnt_rst : std_logic;
+
+begin
+
+   -- =============================================
+   -- =             MOD Functions                  
+   -- =============================================
+   -- END of MOD definitions 
+   -- =============================================
+   -- =             Parameter Functions            
+   -- =============================================
+   sl_cnt_rst <= '0';
+   sl_halt <= HALT;
+
+   -- END of Parameter definitions 
+   sl_loop_i    <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_i_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_j    <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+   sl_loop_j_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+   -- Const bounds for-loops 
+   sl_low_i  <= 0;
+   sl_high_i <= 359;
+   sl_low_j  <= 0;
+   sl_high_j <= 319;
+
+
+   load_i <= '0';
+   load_j <= '0';
+
+   sl_lower_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
+   sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
+
+   sl_upper_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
+   sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
+   -- Special definitions 
+
+   -- Entity and control variables
+   -- Release matrix expressions
+
+   sl_fire <= ('1');
+
+   -- Convert FIFO Read Port ND_13IP_17 Argument in_1 : ED_17 : 0 of type IOMM
+   sl_obtain0 <= ('1');  -- set obtain/release to const value; not used
+   sl_release0 <= ('1');
+
+   sl_CONTROL(0) <= sl_fire and ('1');
+   OBTAIN(0) <= sl_obtain0;
+   RELEASE(0) <= sl_release0;
+
+   -- Convert FIFO Read Port ND_13IP_18 Argument in_2 : ED_18 : 1 of type IOMM
+   sl_obtain1 <= ('1');  -- set obtain/release to const value; not used
+   sl_release1 <= ('1');
+
+   sl_CONTROL(1) <= sl_fire and ('1');
+   OBTAIN(1) <= sl_obtain1;
+   RELEASE(1) <= sl_release1;
+
+   FIRE <= sl_fire;
+
+   cnt_rst <= sl_cnt_rst or RST;
+
+   -- 
+   -- =============================================
+   -- =             Multirate                      
+   -- =============================================
+   -- Function input parameter "in_0", multirate=1 
+   CNTR_MR0 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(0),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_0,
+         UPPER_BND => sl_mr_ubnd_0,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(0)
+      );
+   -- Function input parameter "in_1", multirate=1 
+   CNTR_MR1 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(1),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_1,
+         UPPER_BND => sl_mr_ubnd_1,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(1)
+      );
+   -- READ_EN indicates if READ_MUX can read data
+   sl_bla_en   <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');  
+   READ_EN     <= (others=>'0') when (HALT='1') else sl_bla_en;  
+   sl_mr_en   <= READ_ST; 
+   sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en); 
+   sl_enable  <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce 
+   ENABLE     <=  sl_enable or (not sl_fire);
+   -- 
+   LOCK_PRCS: process(CLK) 
+   begin 
+       if rising_edge(CLK) then 
+           if( RST = '1' ) then 
+               sl_mr_lock <= (others=>'0'); 
+           else  
+               if (ENABLE='1') then 
+                   sl_mr_lock <= (others=>'0'); 
+               else 
+                   for i in 0 to 1 loop 
+                       if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then 
+                           sl_mr_lock(i) <= '1'; 
+                       end if; 
+                   end loop; 
+               end if; 
+           end if; 
+       end if; 
+   end process; 
+   -- END of Multirate definitions 
+   -- 
+   -- =============================================
+   -- =             Iterators                      
+   -- =============================================
+   GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
+   	CNTR_RD : counter
+   	generic map ( 
+   		C_STEP    => CNTR_STEP(i),
+   		C_WIDTH   => CNTR_WIDTH(i)
+   	)
+  	 port map (
+   		CLK       => CLK,
+   		RST       => cnt_rst,
+   		ENABLE    => sl_cntr_en(i),
+			LOAD      => sl_load(i),
+   		LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		ITERATOR  => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		REG_CNTR  => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		DONE      => sl_done(i)
+   	);
+   end generate;
+   --
+   DONE_PRCS: process(CLK)
+   begin
+   	if rising_edge(CLK) then
+          if( RST = '1' ) then
+   		    sl_stop     <= '0';
+   		    sl_done_all <= '0';
+   		    sl_sof      <= '1';
+   	    else 
+   		    if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+   			    sl_stop <= '1';
+   		    elsif (WRAP=true) then
+   			    sl_stop <= '0';
+   		    end if;
+   		    if (sl_stop='0') then
+   			    sl_done_all <= sl_cntr_en(N_CNTRS);
+   		    end if;
+   		    if (ENABLE='1') then
+   			    sl_sof <= sl_eof;
+   		    end if;
+   	    end if;
+   	end if;
+   end process;
+   --
+   sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+   CONTROL <= sl_CONTROL;
+   --
+   REG_CNTRS <= sl_reg_cntrs; 
+   DONE <= sl_done_all;     -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+   STOP <= sl_stop;         -- '1' = The couter stoped after the end of the itteration space. 
+   --
+   sl_count      <=  '0' when (sl_stop='1') else
+                     '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
+   sl_cntr_en(0) <=  sl_count; -- makes the EVAL_LOGIC count
+   --
+   sl_cntr_en(N_CNTRS  downto 1) <= sl_cntr_en(N_CNTRS-1  downto 0) and sl_done(N_CNTRS-1  downto 0);
+   sl_eof <= sl_cntr_en(N_CNTRS);   -- End-of-frame
+   --
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_13/src/vhdl/bunny_static_split2rtl_hwn_nd_13_eval_logic_wr.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_13/src/vhdl/bunny_static_split2rtl_hwn_nd_13_eval_logic_wr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5ec6dd4d138b1498c7b90f6493ac0047d020dcfc
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_13/src/vhdl/bunny_static_split2rtl_hwn_nd_13_eval_logic_wr.vhd
@@ -0,0 +1,285 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_13 is
+   generic ( 
+      N_OUT_PORTS   : natural := 1;
+      WRAP          : boolean := true;
+      N_CNTRS       : natural := 1;
+      QUANT         : natural := 32;
+      PAR_BITWIDTH  : natural :=1;
+      CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+      CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST           : in  std_logic;
+      CLK           : in  std_logic;
+      WRITE_EN      : out std_logic_vector(0 downto 0);
+      WRITE_ST      : in  std_logic_vector(0 downto 0);
+      HALT          : in  std_logic;
+      FIRE          : out std_logic;
+      DONE          : out std_logic;
+      STOP          : out std_logic;
+      CONTROL       : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+   );
+end bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_13;
+
+architecture RTL of bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_13 is	
+   -- 
+   component counter is 
+      generic( 
+         C_STEP    : natural := 10; 
+         C_WIDTH   : natural := 10 
+      ); 
+      port ( 
+         RST       : in  std_logic; 
+         CLK       : in  std_logic; 
+         ENABLE    : in  std_logic; 
+         LOAD      : in  std_logic; 
+         LOWER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         UPPER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         ITERATOR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         REG_CNTR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         DONE      : out std_logic 
+      ); 
+   end component; 
+   -- 
+   component it_mod is 
+   generic( 
+      C_MOD     : natural := 10; 
+      C_WIDTH   : natural := 10; 
+      C_INIT    : natural :=  1; 
+      C_STEP    : natural :=  1  
+   ); 
+   port ( 
+      RST       : in  std_logic; 
+      CLK       : in  std_logic; 
+      LOAD      : in  std_logic; 
+      ENABLE    : in  std_logic; 
+      MODULE    : out std_logic_vector(C_WIDTH-1 downto 0) 
+   ); 
+   end component; 
+   -- 
+   -- Multirate related signals
+   signal sl_bla_en   : std_logic_vector(0 downto 0); 
+   signal sl_mr_en    : std_logic_vector(0 downto 0); 
+   signal sl_mr_done  : std_logic_vector(0 downto 0); 
+   signal sl_mr_lock  : std_logic_vector(0 downto 0); 
+   signal sl_enables  : std_logic_vector(0 downto 0); 
+   signal sl_enable   : std_logic; 
+   signal ENABLE      : std_logic; 
+   -- Function output parameter "out_0", multirate=1 
+   constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   --  
+   -- Parameter related signals 
+   --  
+   -- Iterator (counter) related signals 
+   signal sl_low_i, sl_high_i : integer; 
+   signal sl_low_j, sl_high_j : integer; 
+   signal sl_loop_i, sl_loop_i_rg : integer;
+   signal sl_loop_j, sl_loop_j_rg : integer;
+   signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   -- 
+   signal sl_cntr_en  : std_logic_vector(N_CNTRS   downto 0); 
+   signal sl_done     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_done_all : std_logic; 
+   signal sl_load     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_stop     : std_logic; 
+   signal sl_fire     : std_logic; 
+   signal sl_eof      : std_logic; 
+   signal sl_sof      : std_logic; 
+   signal sl_count    : std_logic; 
+   -- 
+   -- Special Control signal
+   signal sl_CONTROL       : std_logic_vector(N_OUT_PORTS-1 downto 0);
+   signal sl_no_request    : std_logic;
+   -- 
+   -- alias signals 
+   alias update_i : std_logic is sl_cntr_en(1);
+   alias update_j : std_logic is sl_cntr_en(0);
+   -- 
+   alias load_i : std_logic is sl_load(1);
+   alias load_j : std_logic is sl_load(0);
+   -- Trigger signals 
+   signal sl_trigger_i : std_logic;
+   signal sl_trigger_j : std_logic;
+
+
+   -- define control variables 
+   -- MOD related signals 
+
+
+   type state_type is (s_idle, s_halt, s_count, s_release);
+   signal state : state_type;
+   signal halt_cnt : integer;
+   signal sl_halt : std_logic;
+
+   signal sl_cnt_rst : std_logic;
+   signal cnt_rst : std_logic;
+
+begin
+
+   -- =============================================
+   -- =             MOD Functions                  
+   -- =============================================
+   -- END of MOD definitions 
+   --  
+   -- Parameter related signal assignments 
+   sl_cnt_rst <= '0';
+   sl_halt <= HALT;
+   -- END of Parameter definitions 
+
+   sl_loop_i    <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_i_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_j    <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+   sl_loop_j_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+   -- Const bounds for-loops 
+   sl_low_i  <= 0;
+   sl_high_i <= 359;
+   sl_low_j  <= 0;
+   sl_high_j <= 319;
+
+
+   load_i <= '0';
+   load_j <= '0';
+
+   sl_lower_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
+   sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
+
+   sl_upper_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
+   sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
+
+   -- Special definitions 
+
+   -- Entity and control variables
+
+   sl_fire <= ('1');
+
+   -- Convert FIFO Write Port out_1 : ED_19_20
+   sl_CONTROL(0) <= sl_fire and ('1');
+
+   FIRE <= sl_fire;
+
+   cnt_rst <= sl_cnt_rst or RST;
+
+   -- 
+   -- =============================================
+   -- =             Multirate                      
+   -- =============================================
+   -- Function output parameter "out_0", multirate=1 
+   CNTR_MR0 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(0),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_0,
+         UPPER_BND => sl_mr_ubnd_0,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(0)
+      );
+   -- 
+   -- WRITE_EN indicates if date can be written to WRITE_MUX
+   sl_bla_en      <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
+   WRITE_EN    <=  (others=>'0') when (HALT='1') else sl_bla_en;
+   -- 
+   sl_mr_en    <= (not sl_mr_lock) and WRITE_ST; 
+   sl_enables  <= sl_mr_lock or (sl_mr_done and sl_mr_en); 
+   sl_enable   <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0';  -- and_reduce 
+   ENABLE      <= sl_enable or (not sl_fire);
+   -- 
+   LOCK_PRCS: process(CLK) 
+   begin 
+       if rising_edge(CLK) then 
+           if( RST = '1' ) then 
+               sl_mr_lock <= (others=>'0'); 
+           else  
+               if (ENABLE='1') then 
+                   sl_mr_lock <= (others=>'0'); 
+               else 
+                   for i in 0 to 0 loop 
+                       if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then 
+                           sl_mr_lock(i) <= '1'; 
+                       end if; 
+                   end loop; 
+               end if; 
+           end if; 
+       end if; 
+   end process; 
+   -- END of Multirate definitions 
+   -- 
+   -- =============================================
+   -- =             Iterators                      
+   -- =============================================
+   GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
+   	CNTR_WR : counter
+   	generic map ( 
+   		C_STEP    => CNTR_STEP(i),
+   		C_WIDTH   => CNTR_WIDTH(i)
+   	)
+  	 port map (
+   		CLK       => CLK,
+   		RST       => cnt_rst,
+   		ENABLE    => sl_cntr_en(i),
+   		LOAD      => sl_load(i),
+   		LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		ITERATOR  => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		REG_CNTR  => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		DONE      => sl_done(i)
+   	);
+   end generate;
+   --
+   DONE_PRCS: process(CLK)
+   begin
+   	if rising_edge(CLK) then
+   	    if( RST = '1' ) then
+   		    sl_stop     <= '0';
+   		    sl_done_all <= '0';
+   		    sl_sof      <= '1';
+   	    else 
+   		    if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+   			    sl_stop <= '1';
+   		    elsif (WRAP=true) then
+   			    sl_stop <= '0';
+   		    end if;
+   		    if (sl_stop='0') then
+   			    sl_done_all <= sl_cntr_en(N_CNTRS);
+   		    end if;
+   		    if (ENABLE='1') then
+   			    sl_sof <= sl_eof;
+   		    end if;
+   	    end if;
+   	end if;
+   end process;
+   --
+   sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+   CONTROL <= sl_CONTROL;
+   --
+   DONE <= sl_done_all;     -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+   STOP <= sl_stop;         -- '1' = The couter stoped after the end of the itteration space. 
+   --
+   sl_count      <=  '0' when (sl_stop='1') else
+   			'1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
+   sl_cntr_en(0) <=  sl_count; -- makes the EVAL_LOGIC count
+   --
+   sl_cntr_en(N_CNTRS  downto 1) <= sl_cntr_en(N_CNTRS-1  downto 0) and sl_done(N_CNTRS-1  downto 0);
+   sl_eof <= sl_cntr_en(N_CNTRS);      -- End-of-frame (combinatorial; beter not use it outside)
+   --
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_13/src/vhdl/bunny_static_split2rtl_hwn_nd_13_execution_unit.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_13/src/vhdl/bunny_static_split2rtl_hwn_nd_13_execution_unit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b4bc2486ea7cce8fd389fdf52e0a09cef18e45c1
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_13/src/vhdl/bunny_static_split2rtl_hwn_nd_13_execution_unit.vhd
@@ -0,0 +1,114 @@
+-- Execute Unit automatically generated by KpnMapper
+-- Function "merge2t32to64"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_bunny_static_split2rtl_functions_1_lib;
+use compaandesign_com_bunny_static_split2rtl_functions_1_lib.all;
+
+entity bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_13 is
+   generic (
+      N_INPORTS  : natural := 1;
+      N_OUTPORTS : natural := 1;
+      IP_RESET   : natural := 1; 
+      STIM_DIR   : string  := "bla";
+      QUANT      : natural := 32;
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1; 
+      CNTR_QUANT : natural := 32; 
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+   );
+   port (
+      RST        : in  std_logic;
+      CLK        : in  std_logic;
+      -- Funtion Input parameters
+      IN_PORT_0    : in  std_logic_vector(31 downto 0);  -- Param. "in0"
+      IN_PORT_1    : in  std_logic_vector(31 downto 0);  -- Param. "in1"
+      READ       : out std_logic_vector(N_INPORTS-1 downto 0);
+      EXIST      : in  std_logic_vector(N_INPORTS-1 downto 0);
+      -- Iterators
+      REG_CNTRS_RD : in  std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
+      -- Funtion Output parameters
+      OUT_PORT_0   : out std_logic_vector(63 downto 0);  -- Param. "result"
+      WRITE      : out std_logic_vector(N_OUTPORTS-1 downto 0);
+      FULL       : in  std_logic_vector(N_OUTPORTS-1 downto 0);
+      STOP_RD    : in  std_logic;
+      STOP_WR    : in  std_logic;
+      ERROR      : out std_logic
+   );
+end bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_13 ;
+
+-- Laura implementation
+architecture Laura of bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_13 is
+
+   component merge2t32to64 is
+      generic (
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1; 
+         CNTR_QUANT : natural := 32; 
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST   : in std_logic;
+         CLK   : in std_logic;
+         -- Inputs 
+         ip_in0  : in  std_logic_vector(31 downto 0);  
+         ip_in1  : in  std_logic_vector(31 downto 0);  
+         -- Iterators 
+         it_j : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+         it_i : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+         EXIST : in  std_logic_vector(1 downto 0);
+         READF : out std_logic_vector(1 downto 0);
+         -- Outputs 
+         op_result : out std_logic_vector(63 downto 0);
+         FULL  : in  std_logic_vector(0 downto 0);
+         WRITEF: out std_logic_vector(0 downto 0);
+         --
+         STOP_RD : in  std_logic;
+         STOP_WR : in  std_logic;
+         ERROR   : out std_logic
+      );
+   end component;
+
+   signal sl_RST : std_logic;
+
+begin
+
+   sl_RST <= RST when IP_RESET=1 else not RST;
+
+   FUNC : merge2t32to64
+   generic map (
+         STIM_DIR      => STIM_DIR,
+         c_STAGES      => c_STAGES,
+         N_CNTRS       => N_CNTRS,
+         CNTR_QUANT    => CNTR_QUANT,
+         CNTR_WIDTH    => CNTR_WIDTH
+   )
+   port map (
+      RST   => sl_RST,
+      CLK   => CLK,
+      -- Inputs 
+      ip_in0 => IN_PORT_0,
+      ip_in1 => IN_PORT_1,
+      -- Iterators 
+      it_j => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
+      it_i => REG_CNTRS_RD(1*CNTR_QUANT+CNTR_WIDTH(1)-1 downto 1*CNTR_QUANT),
+      EXIST => EXIST,
+      READF => READ,
+      -- Outputs 
+      op_result => OUT_PORT_0,
+      FULL  => FULL,
+      WRITEF=> WRITE,
+      -- 
+      STOP_RD => STOP_RD,
+      STOP_WR => STOP_WR,
+      ERROR   => ERROR
+   );
+
+end Laura;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_14/hdllib.cfg b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_14/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..934aa3520bc9a5f9fc151e0ea25ac381eb1583cf
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_14/hdllib.cfg
@@ -0,0 +1,18 @@
+hdl_lib_name = compaandesign_com_bunny_static_split2rtl_hwn_nd_14_1
+hdl_library_clause_name = compaandesign_com_bunny_static_split2rtl_hwn_nd_14_1_lib
+hdl_lib_uses_synth = compaandesign_com_bunny_static_split2rtl_functions_1 compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1 compaandesign_com_common_extern_connector_1 
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+	src/vhdl/bunny_static_split2rtl_hwn_nd_14_execution_unit.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_14_eval_logic_rd.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_14_eval_logic_wr.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_14.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_14/src/vhdl/bunny_static_split2rtl_hwn_nd_14.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_14/src/vhdl/bunny_static_split2rtl_hwn_nd_14.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ae55e2696556951c9b43e52ae9b905707d258c97
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_14/src/vhdl/bunny_static_split2rtl_hwn_nd_14.vhd
@@ -0,0 +1,471 @@
+-- HWN Entity File automatically generated by KpnMapper (writeHdlHWNodeFile)
+-- Top level file for a Hardware Accelerator
+-- Function "compaan_outlinedproc6"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+library compaandesign_com_common_extern_connector_1_lib;
+use compaandesign_com_common_extern_connector_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_14 is
+   generic (
+      STIM_DIR   : string  := "bla";
+      RESET_HIGH : natural := 1;
+      PAR_WIDTH  : natural := 16;
+      QUANT      : natural := 32;
+      WRAP       : boolean := true
+   );
+   port (
+
+      -- Dataflow input interfaces
+      -- ED_19_20 : in_0
+      ND_14IP_20_ND_14IP_19_Rd    : out std_logic;
+      ND_14IP_20_ND_14IP_19_Din   : in  std_logic_vector(63 downto 0);
+      ND_14IP_20_ND_14IP_19_Exist : in  std_logic; 
+      ND_14IP_20_ND_14IP_19_CLK   : out std_logic;
+      ND_14IP_20_ND_14IP_19_CTRL  : in  std_logic;
+
+      -- ED_21 : in_0
+      ND_14IP_21_Rd    : out std_logic;
+      ND_14IP_21_Din   : in  std_logic_vector(63 downto 0);
+      ND_14IP_21_Exist : in  std_logic; 
+      ND_14IP_21_CLK   : out std_logic;
+      ND_14IP_21_CTRL  : in  std_logic;
+
+      -- Dataflow Control Input interfaces
+      -- Dataflow output interfaces
+      data_out_Wr   : out std_logic;
+      data_out_Dout : out std_logic_vector(63 downto 0);
+      data_out_Full : in  std_logic;
+      data_out_CLK  : out std_logic;
+      data_out_CTRL : out std_logic;
+
+      PARAM_DT : in  std_logic_vector(PAR_WIDTH+10-1 downto 0);
+      PARAM_LD : in  std_logic;
+
+      RST      : in  std_logic;
+      CLK      : in  std_logic;
+      STOP     : out std_logic;
+      ERROR    : out std_logic;
+      BLOCK_RD : out std_logic
+   );
+end bunny_static_split2rtl_hwn_nd_14;
+
+architecture RTL of bunny_static_split2rtl_hwn_nd_14 is
+   --
+   -- ====================================
+   -- =     Constants declaration        =
+   -- ====================================
+   -- Setting the parameters of the HW Node
+   constant c_IN_PORTS     : natural := 2; -- number of input ports of a HW node
+   constant c_OUT_PORTS    : natural := 1; -- number of output ports of a HW node
+   constant c_IN_FUNC_VAR  : natural := 1; -- number of input ports of a HW IP
+   constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
+   constant c_COUNTERS     : natural := 1; -- number of iterators
+   -- ===========================================
+   -- = Iterators run from Inner to Outer loop  =
+   -- ===========================================
+   constant c_CNTR_QUANT   : natural := 18;
+   constant c_CNTR_STEPS   : t_counter_step  := ( 0=>1, others=>1 );
+   constant c_CNTR_WIDTHS  : t_counter_width := ( 0=>18, others=>10 );
+   constant c_STAGES       : natural := 1; -- number of pipeline stages or delay
+   constant c_IP_RESET     : natural := 1; -- active level of the HW IP reset signal
+   constant c_WRAP         : boolean := WRAP; -- Operation mode: Single_Shot (false) or Continuous (true)
+   constant c_EXT_PAR      : natural := 0; -- number of external parameters
+   constant c_INT_PAR      : natural := 0; -- number of internal parameters
+   constant c_N_PAR        : natural := 0; -- no parameters are used
+   constant c_PAR_BITWIDTH : natural := PAR_WIDTH; -- aggregate bitwidth of the parameter vector
+   constant c_PAR_VECTOR   : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
+       (0,0,0,0), (0,0,0,0)    -- two dummy elements
+   );
+   --
+   -- ====================================
+   -- =     Components declaration       =
+   -- ====================================
+   component bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_14 is
+      generic (
+         N_IN_PORTS    : natural := 1;
+         WRAP          : boolean := true;
+         N_CNTRS       : natural := 1; 
+         QUANT         : natural := 32;
+         PAR_BITWIDTH  : natural :=1;
+         CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+         CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+      );
+      port (
+         RST           : in  std_logic;
+         CLK           : in  std_logic;
+         REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1  downto 0); 
+         READ_EN       : out std_logic_vector(c_IN_FUNC_VAR-1  downto 0);
+         READ_ST       : in  std_logic_vector(c_IN_FUNC_VAR-1  downto 0);
+         HALT          : in  std_logic;
+         FIRE          : out std_logic;
+         DONE          : out std_logic;
+         STOP          : out std_logic;
+         CONTROL       : out std_logic_vector(N_IN_PORTS-1 downto 0);
+         OBTAIN        : out std_logic_vector(N_IN_PORTS-1 downto 0);
+         RELEASE       : out std_logic_vector(N_IN_PORTS-1 downto 0)
+      );
+   end component;
+
+   component READ_MUX is
+      generic (
+         N_PORTS    : natural := 1;
+         PORT_WIDTH : natural := 32  
+      );
+      port(
+         IN_PORTS   : in  std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
+         EXISTS     : in  std_logic_vector(N_PORTS-1 downto 0);
+         READS      : out std_logic_vector(N_PORTS-1 downto 0);
+         SOFS       : in  std_logic_vector(N_PORTS-1 downto 0);
+
+         OUT_PORT   : out std_logic_vector(PORT_WIDTH-1 downto 0);
+         EXIST      : out std_logic;
+         READ       : in  std_logic;
+         SOF        : in  std_logic;
+		CLK        : in std_logic;
+
+         READ_EN    : in  std_logic;
+         READ_ST    : out std_logic;
+         CONTROL    : in  std_logic_vector(N_PORTS-1 downto 0);
+         OBTAIN     : in  std_logic_vector(N_PORTS-1 downto 0);
+         RELEASE    : in  std_logic_vector(N_PORTS-1 downto 0)
+      );
+   end component;
+
+   component bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_14 is
+      generic ( 
+         N_OUT_PORTS   : natural := 1;
+         WRAP          : boolean := true;
+         N_CNTRS       : natural := 1; 
+         QUANT         : natural := 32;
+         PAR_BITWIDTH  : natural :=1;
+         CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+         CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+      );
+      port (
+         RST           : in  std_logic;
+         CLK           : in  std_logic;
+         WRITE_EN      : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+         WRITE_ST      : in  std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+         HALT          : in  std_logic;
+         FIRE          : out std_logic;
+         DONE          : out std_logic;
+         STOP          : out std_logic;
+         CONTROL       : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+      );
+   end component;
+
+   component WRITE_DEMUX is
+      generic (
+         N_PORTS : natural := 1
+      );
+      port(
+         WRITES   : out std_logic_vector(N_PORTS-1 downto 0);
+         WRITE    : in  std_logic;
+
+         FULLS    : in  std_logic_vector(N_PORTS-1 downto 0);
+         FULL     : out std_logic;
+
+         WRITE_EN : in  std_logic;
+         WRITE_ST : out std_logic;
+         CONTROL  : in  std_logic_vector(N_PORTS-1 downto 0)
+      );
+   end component;
+
+
+   component bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_14 is
+      generic (
+         N_INPORTS  : natural := 1;
+         N_OUTPORTS : natural := 1;
+         IP_RESET   : natural := 1;
+         QUANT      : natural := 32;
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1;
+         CNTR_QUANT : natural := 32;
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST        : in  std_logic;
+         CLK        : in  std_logic;
+
+         -- Iterators
+         REG_CNTRS_RD : in  std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
+         -- Func. Input parameters
+         IN_PORT_0 : in  std_logic_vector(63 downto 0); -- tmp1
+         READ       : out std_logic_vector(N_INPORTS-1 downto 0);
+         EXIST      : in  std_logic_vector(N_INPORTS-1 downto 0);
+         -- Func. Output parameters
+         OUT_PORT_0 : out std_logic_vector(63 downto 0); -- tmp0
+         WRITE      : out std_logic_vector(N_OUTPORTS-1 downto 0);
+         FULL       : in  std_logic_vector(N_OUTPORTS-1 downto 0);
+         --
+         STOP_RD    : in  std_logic;
+         STOP_WR    : in  std_logic;
+         ERROR      : out std_logic
+      );
+   end component;
+
+   component INTERNAL_PARAMETERS is 
+      generic (
+         PAR_BITWIDTH : natural:=1;
+         PAR_VECTOR   : t_par_vector;
+         N_PAR        : natural:=0;
+         START_IN_RUN  : boolean := FALSE
+      );
+      port (  
+         RST        : in  std_logic;
+         CLK        : in  std_logic;
+
+         HALT_RD    : out std_logic;
+         HALT_WR    : out std_logic;
+         SOF_RD     : in  std_logic;
+         SOF_WR     : in  std_logic;
+         LOAD_PARAM : out std_logic;
+
+         par_one_in_Rd    : out std_logic;
+         par_one_in_Din   : in std_logic_vector(32-1 downto 0);
+         par_one_in_Exist : in std_logic;
+         par_one_in_CLK   : out std_logic;
+         par_one_in_CTRL  : in std_logic;
+
+         PARAMETERS_RD : out std_logic_vector(32-1 downto 0);
+         PARAMETERS_WR : out std_logic_vector(32-1 downto 0)
+      );
+   end component;
+
+   --
+   -- ====================================
+   -- =       Signals declaration        =
+   -- ====================================
+   -- 
+   -- HW Node Input Ports
+   signal sl_IN_PORTS_0   : std_logic_vector(2*64-1 downto 0); -- tmp1
+   signal sl_EXISTS       : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_READS        : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_CTRLS        : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_control_rd   : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_obtain_rd    : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_release_rd   : std_logic_vector(c_IN_PORTS-1 downto 0);
+   -- 
+   -- Func. Input parameters
+   signal sl_in_port_0    : std_logic_vector(63 downto 0); -- tmp1
+   signal sl_exist        : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read         : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read_en      : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read_st      : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   -- 
+   signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
+   -- 
+   -- HW Node Output Ports
+   signal sl_WRITES       : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_FULLS        : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_control_wr   : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_lortnoc_wr   : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   -- 
+   -- Func. Output parameters
+   signal sl_out_port_0   : std_logic_vector(63 downto 0); -- tmp0
+   signal sl_full         : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write        : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write_en     : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write_st     : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   -- 
+   -- 
+   signal sl_halt             : std_logic;
+   signal sl_halted           : std_logic;
+   signal sl_halt_wr          : std_logic;
+   signal sl_halt_rd          : std_logic;
+   signal sl_param_halt_wr    : std_logic;
+   signal sl_param_halt_rd    : std_logic;
+   signal sl_done_wr          : std_logic;
+   signal sl_done_rd          : std_logic;
+   signal sl_stop_wr          : std_logic;
+   signal sl_stop_rd          : std_logic;
+   signal sl_fire_wr          : std_logic;
+   signal sl_fire_rd          : std_logic;
+   signal sl_sof_wr           : std_logic;
+   signal sl_sof_rd           : std_logic;
+   signal sl_error            : std_logic;
+   signal sl_load_param       : std_logic;
+
+   --  
+   -- Parameter related signals 
+   signal sl_param_fifo_full     : std_logic;
+   signal sl_sync_num            : std_logic_vector(9 downto 0);
+
+   signal sl_RST : std_logic;
+
+begin 
+
+   sl_RST <= RST when RESET_HIGH=1 else not RST;
+      ND_14IP_20_ND_14IP_19_CLK   <= CLK;
+      ND_14IP_21_CLK   <= CLK;
+      data_out_CLK  <= CLK;
+
+   --
+   -- ==========================================================
+   -- =       HWN Input related modules                        =
+   -- ==========================================================
+   -- Func. Input param. "tmp1"
+   RD_MUX_0 : READ_MUX
+   generic map (
+      N_PORTS    => 2,
+      PORT_WIDTH => 64
+   )
+   port map (
+      IN_PORTS   => sl_IN_PORTS_0,
+      EXISTS     => sl_EXISTS(1 downto 0),
+      READS      => sl_READS(1 downto 0),
+      SOFS       => sl_CTRLS(1 downto 0),
+
+      OUT_PORT   => sl_in_port_0,
+      EXIST      => sl_exist(0),
+      READ       => sl_read(0),
+      SOF        => sl_sof_rd,
+      CLK        => CLK,
+
+      READ_EN    => sl_read_en(0),
+      READ_ST    => sl_read_st(0),
+      CONTROL    => sl_control_rd(1 downto 0),
+      OBTAIN     => sl_obtain_rd(1 downto 0),
+      RELEASE    => sl_release_rd(1 downto 0)
+   );
+
+   ND_14IP_20_ND_14IP_19_Rd   <= sl_READS(0);
+   ND_14IP_21_Rd   <= sl_READS(1);
+
+   sl_IN_PORTS_0 <= ND_14IP_21_Din & ND_14IP_20_ND_14IP_19_Din;
+
+   sl_EXISTS      <= ND_14IP_21_Exist & ND_14IP_20_ND_14IP_19_Exist ;
+   sl_CTRLS       <= ND_14IP_21_CTRL & ND_14IP_20_ND_14IP_19_CTRL ;
+
+   EVAL_RD : bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_14
+   generic map ( 
+      N_IN_PORTS    => c_IN_PORTS,
+      WRAP          => c_WRAP,
+      N_CNTRS       => c_COUNTERS,
+      QUANT         => c_CNTR_QUANT,
+      PAR_BITWIDTH  => c_PAR_BITWIDTH,
+      CNTR_STEP     => c_CNTR_STEPS,
+      CNTR_WIDTH    => c_CNTR_WIDTHS
+   )
+   port map(
+      RST           => sl_RST,
+      CLK           => CLK,
+      REG_CNTRS     => sl_REG_CNTRS_RD,
+      READ_EN       => sl_read_en,
+      READ_ST       => sl_read_st,
+      HALT          => sl_halt_rd,
+      FIRE          => sl_fire_rd,
+      DONE          => sl_done_rd,
+      STOP          => sl_stop_rd,
+      CONTROL       => sl_control_rd,
+      OBTAIN        => sl_obtain_rd,
+      RELEASE       => sl_release_rd
+   );
+
+   --
+   -- ==========================================================
+   -- =       HWN Output related modules                       =
+   -- ==========================================================
+   -- 
+   -- Func. Output param. "tmp0"
+   DEMUX_0 : WRITE_DEMUX
+   generic map (
+      N_PORTS => 1
+   )
+   port map (
+      WRITES   => sl_WRITES(0 downto 0),
+      FULLS    => sl_FULLS(0 downto 0),
+      CONTROL  => sl_lortnoc_wr(0 downto 0),
+      WRITE    => sl_write(0),
+      FULL     => sl_full(0),
+      WRITE_EN => sl_write_en(0),
+      WRITE_ST => sl_write_st(0)
+   );
+   --
+   data_out_Dout <= sl_out_port_0;  -- Func. Output param. "tmp0"
+   data_out_CTRL <= sl_sof_wr ;
+   data_out_Wr   <= sl_WRITES(0);
+   sl_FULLS(0) <= data_out_Full;
+   sl_lortnoc_wr(0) <= sl_control_wr(0);
+   --
+   --
+   EVAL_WR : bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_14
+   generic map ( 
+      N_OUT_PORTS   => c_OUT_PORTS,
+      WRAP          => c_WRAP,
+      N_CNTRS       => c_COUNTERS,
+      QUANT         => c_CNTR_QUANT,
+      PAR_BITWIDTH  => c_PAR_BITWIDTH,
+      CNTR_STEP     => c_CNTR_STEPS,
+      CNTR_WIDTH    => c_CNTR_WIDTHS
+   )
+   port map (
+      RST           => sl_RST,
+      CLK           => CLK,
+      WRITE_EN      => sl_write_en,
+      WRITE_ST      => sl_write_st,
+      HALT          => sl_halt_wr,
+      FIRE          => sl_fire_wr,
+      DONE          => sl_done_wr,
+      STOP          => sl_stop_wr,
+      CONTROL       => sl_control_wr
+   );
+
+   --
+   -- ==========================================================
+   -- =       HWN Execution Unit                               =
+   -- ==========================================================
+   EX : bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_14
+   generic map (
+      N_INPORTS  => c_IN_FUNC_VAR,
+      N_OUTPORTS => c_OUT_FUNC_VAR, 
+      IP_RESET   => c_IP_RESET,
+      QUANT      => QUANT,
+      STIM_DIR   => STIM_DIR,
+      c_STAGES   => c_STAGES,
+      N_CNTRS    => c_COUNTERS,
+      CNTR_QUANT => c_CNTR_QUANT,
+      CNTR_WIDTH => c_CNTR_WIDTHS
+   )
+   port map (
+      RST        => sl_RST,
+      CLK        => CLK,
+      -- Iterators
+      REG_CNTRS_RD => sl_REG_CNTRS_RD,
+      -- Func. Input parameters
+      IN_PORT_0    => sl_in_port_0,
+      READ       => sl_read,
+      EXIST      => sl_exist,
+      -- Func. Output parameters
+      OUT_PORT_0   => sl_out_port_0,
+      WRITE      => sl_write,
+      FULL       => sl_full,
+      --
+      STOP_WR    => sl_stop_wr,
+      STOP_RD    => sl_stop_rd,
+      ERROR      => sl_error
+   );
+
+   -- ==========================================================
+   -- =       PARAMETERIZATION                                 =
+   -- ==========================================================
+   -- no parameters
+   sl_halt_rd <= '0';
+   sl_halt_wr <= '0';
+--   sl_halted  <= sl_sof_rd;
+   STOP <= sl_done_wr;
+   ERROR <= sl_error;
+   BLOCK_RD <= not (  (  sl_READS(0) or   sl_READS(1)  ) );
+
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_14/src/vhdl/bunny_static_split2rtl_hwn_nd_14_eval_logic_rd.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_14/src/vhdl/bunny_static_split2rtl_hwn_nd_14_eval_logic_rd.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..017817844b469e2f991e36aaca7b452baabe41b5
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_14/src/vhdl/bunny_static_split2rtl_hwn_nd_14_eval_logic_rd.vhd
@@ -0,0 +1,317 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_14 is
+   generic (
+      N_IN_PORTS    : natural := 1;
+      WRAP          : boolean := true;
+      N_CNTRS       : natural := 1; 
+      QUANT         : natural := 32;
+      PAR_BITWIDTH  : natural  :=1;
+      CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+      CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST           : in  std_logic;
+      CLK           : in  std_logic;
+      REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+      READ_EN       : out std_logic_vector(0 downto 0);
+      READ_ST       : in  std_logic_vector(0 downto 0);
+      HALT          : in  std_logic;
+      FIRE          : out std_logic;
+      DONE          : out std_logic;
+      STOP          : out std_logic;
+      CONTROL       : out std_logic_vector(N_IN_PORTS-1 downto 0);
+      OBTAIN        : out std_logic_vector(N_IN_PORTS-1 downto 0);
+      RELEASE       : out std_logic_vector(N_IN_PORTS-1 downto 0)
+   );
+end bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_14;
+
+architecture RTL of bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_14 is
+   -- 
+   component counter is 
+      generic( 
+         C_STEP    : natural := 10; 
+         C_WIDTH   : natural := 10 
+      ); 
+      port ( 
+         RST       : in  std_logic; 
+         CLK       : in  std_logic; 
+         ENABLE    : in  std_logic; 
+         LOAD      : in  std_logic; 
+         LOWER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         UPPER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         ITERATOR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         REG_CNTR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         DONE      : out std_logic 
+      ); 
+   end component; 
+   -- 
+   component it_mod is 
+   generic( 
+      C_MOD     : natural := 10; 
+      C_WIDTH   : natural := 10; 
+      C_INIT    : natural :=  1; 
+      C_STEP    : natural :=  1  
+   ); 
+   port ( 
+      RST       : in  std_logic; 
+      CLK       : in  std_logic; 
+      LOAD      : in  std_logic; 
+      ENABLE    : in  std_logic; 
+      MODULE    : out std_logic_vector(C_WIDTH-1 downto 0) 
+   ); 
+   end component; 
+   -- 
+   --  
+   -- Parameter related signals 
+   -- 
+   -- Iterator (counter) related signals 
+   signal sl_low_x, sl_high_x : integer;
+   signal sl_loop_x, sl_loop_x_rg : integer;
+   signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   -- 
+   signal sl_cntr_en  : std_logic_vector(N_CNTRS   downto 0); 
+   signal sl_done     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_done_all : std_logic; 
+   signal sl_load     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_stop     : std_logic; 
+   signal sl_fire     : std_logic; 
+   signal sl_sof      : std_logic; 
+   signal sl_eof      : std_logic; 
+   signal sl_count    : std_logic; 
+
+   -- alias signals 
+   alias update_x : std_logic is sl_cntr_en(0);
+   alias load_x : std_logic is sl_load(0);
+
+   -- Trigger signals 
+   signal sl_trigger_x : std_logic;
+
+   -- Special Control signal
+   signal sl_CONTROL       : std_logic_vector(N_IN_PORTS-1 downto 0);
+   signal sl_no_request    : std_logic;
+   -- 
+   -- Multirate related signals
+   signal sl_bla_en   : std_logic_vector(0 downto 0); 
+   signal sl_mr_en    : std_logic_vector(0 downto 0); 
+   signal sl_mr_done  : std_logic_vector(0 downto 0); 
+   signal sl_mr_lock  : std_logic_vector(0 downto 0); 
+   signal sl_enables  : std_logic_vector(0 downto 0); 
+   signal sl_enable   : std_logic; 
+   signal ENABLE      : std_logic; 
+   -- Function input parameter "in_0", multirate=1 
+   constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+
+   signal e0, e1 : boolean;
+
+   signal sl_obtain0  : std_logic;
+   signal sl_release0 : std_logic;
+   signal sl_obtain1  : std_logic;
+   signal sl_release1 : std_logic;
+
+   -- define control variables 
+   signal div3 : integer;
+   signal mod15 : integer;
+
+   type state_type is (s_idle, s_halt, s_count, s_release);
+   signal state : state_type;
+   signal halt_cnt : integer;
+   signal sl_halt : std_logic;
+
+   signal sl_cnt_rst : std_logic;
+   signal cnt_rst : std_logic;
+   signal x0_mod_320 : std_logic_vector(9-1 downto 0);
+
+begin
+
+   -- =============================================
+   -- =             MOD Functions                  
+   -- =============================================
+   -- MOD function: x % 320 == 0
+   INST_mod15 : it_mod
+   generic map(
+      C_MOD     => 320,
+      C_WIDTH   => 9,
+      C_INIT    => 0,
+      C_STEP    => 1
+   )
+   port map(
+      RST       => RST,
+      CLK       => CLK,
+      LOAD      => sl_done(0),
+      ENABLE    => sl_cntr_en(0),
+      MODULE    => x0_mod_320
+   );
+   mod15 <= TO_INTEGER(UNSIGNED(x0_mod_320));
+   -- 
+   -- END of MOD definitions 
+   -- =============================================
+   -- =             Parameter Functions            
+   -- =============================================
+   sl_cnt_rst <= '0';
+   sl_halt <= HALT;
+
+   -- END of Parameter definitions 
+   sl_loop_x    <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+   sl_loop_x_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+   -- Const bounds for-loops 
+   sl_low_x  <= 0;
+   sl_high_x <= 116167;
+
+
+   load_x <= '0';
+
+   sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_x,QUANT));
+
+   sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_x,QUANT));
+   -- Special definitions 
+   --mod15 <=  1; -- ERROR not implementated: mod(sl_loop_x_rg, 320);;
+
+   -- Entity and control variables
+   -- Release matrix expressions
+   e0 <= -sl_loop_x_rg + 115199>=0;
+   e1 <= sl_loop_x_rg-115200>=0;
+
+   sl_fire <= ('1');
+
+   -- Convert FIFO Read Port ND_14IP_20_ND_14IP_19 Argument in_1 : ED_19_20 : 0 of type IOMM
+   sl_obtain0 <= ('1');  -- set obtain/release to const value; not used
+   sl_release0 <= ('1');
+
+   sl_CONTROL(0) <= sl_fire and b2std((e0));
+   OBTAIN(0) <= sl_obtain0;
+   RELEASE(0) <= sl_release0;
+
+   -- Convert FIFO Read Port ND_14IP_21 Argument in_2 : ED_21 : 1 of type IOMM
+   sl_obtain1 <= ('1');  -- set obtain/release to const value; not used
+   sl_release1 <= ('1');
+
+   sl_CONTROL(1) <= sl_fire and b2std((e1));
+   OBTAIN(1) <= sl_obtain1;
+   RELEASE(1) <= sl_release1;
+
+   FIRE <= sl_fire;
+
+   cnt_rst <= sl_cnt_rst or RST;
+
+   -- 
+   -- =============================================
+   -- =             Multirate                      
+   -- =============================================
+   -- Function input parameter "in_0", multirate=1 
+   CNTR_MR0 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(0),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_0,
+         UPPER_BND => sl_mr_ubnd_0,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(0)
+      );
+   -- READ_EN indicates if READ_MUX can read data
+   sl_bla_en   <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');  
+   READ_EN     <= (others=>'0') when (HALT='1') else sl_bla_en;  
+   sl_mr_en   <= READ_ST; 
+   sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en); 
+   sl_enable  <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce 
+   ENABLE     <=  sl_enable or (not sl_fire);
+   -- 
+   LOCK_PRCS: process(CLK) 
+   begin 
+       if rising_edge(CLK) then 
+           if( RST = '1' ) then 
+               sl_mr_lock <= (others=>'0'); 
+           else  
+               if (ENABLE='1') then 
+                   sl_mr_lock <= (others=>'0'); 
+               else 
+                   for i in 0 to 0 loop 
+                       if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then 
+                           sl_mr_lock(i) <= '1'; 
+                       end if; 
+                   end loop; 
+               end if; 
+           end if; 
+       end if; 
+   end process; 
+   -- END of Multirate definitions 
+   -- 
+   -- =============================================
+   -- =             Iterators                      
+   -- =============================================
+   GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
+   	CNTR_RD : counter
+   	generic map ( 
+   		C_STEP    => CNTR_STEP(i),
+   		C_WIDTH   => CNTR_WIDTH(i)
+   	)
+  	 port map (
+   		CLK       => CLK,
+   		RST       => cnt_rst,
+   		ENABLE    => sl_cntr_en(i),
+			LOAD      => sl_load(i),
+   		LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		ITERATOR  => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		REG_CNTR  => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		DONE      => sl_done(i)
+   	);
+   end generate;
+   --
+   DONE_PRCS: process(CLK)
+   begin
+   	if rising_edge(CLK) then
+          if( RST = '1' ) then
+   		    sl_stop     <= '0';
+   		    sl_done_all <= '0';
+   		    sl_sof      <= '1';
+   	    else 
+   		    if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+   			    sl_stop <= '1';
+   		    elsif (WRAP=true) then
+   			    sl_stop <= '0';
+   		    end if;
+   		    if (sl_stop='0') then
+   			    sl_done_all <= sl_cntr_en(N_CNTRS);
+   		    end if;
+   		    if (ENABLE='1') then
+   			    sl_sof <= sl_eof;
+   		    end if;
+   	    end if;
+   	end if;
+   end process;
+   --
+   sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+   CONTROL <= sl_CONTROL;
+   --
+   REG_CNTRS <= sl_reg_cntrs; 
+   DONE <= sl_done_all;     -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+   STOP <= sl_stop;         -- '1' = The couter stoped after the end of the itteration space. 
+   --
+   sl_count      <=  '0' when (sl_stop='1') else
+                     '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
+   sl_cntr_en(0) <=  sl_count; -- makes the EVAL_LOGIC count
+   --
+   sl_cntr_en(N_CNTRS  downto 1) <= sl_cntr_en(N_CNTRS-1  downto 0) and sl_done(N_CNTRS-1  downto 0);
+   sl_eof <= sl_cntr_en(N_CNTRS);   -- End-of-frame
+   --
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_14/src/vhdl/bunny_static_split2rtl_hwn_nd_14_eval_logic_wr.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_14/src/vhdl/bunny_static_split2rtl_hwn_nd_14_eval_logic_wr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5c6f461639a17e4e40954bbaa37d9622b148edbc
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_14/src/vhdl/bunny_static_split2rtl_hwn_nd_14_eval_logic_wr.vhd
@@ -0,0 +1,297 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_14 is
+   generic ( 
+      N_OUT_PORTS   : natural := 1;
+      WRAP          : boolean := true;
+      N_CNTRS       : natural := 1;
+      QUANT         : natural := 32;
+      PAR_BITWIDTH  : natural :=1;
+      CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+      CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST           : in  std_logic;
+      CLK           : in  std_logic;
+      WRITE_EN      : out std_logic_vector(0 downto 0);
+      WRITE_ST      : in  std_logic_vector(0 downto 0);
+      HALT          : in  std_logic;
+      FIRE          : out std_logic;
+      DONE          : out std_logic;
+      STOP          : out std_logic;
+      CONTROL       : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+   );
+end bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_14;
+
+architecture RTL of bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_14 is	
+   -- 
+   component counter is 
+      generic( 
+         C_STEP    : natural := 10; 
+         C_WIDTH   : natural := 10 
+      ); 
+      port ( 
+         RST       : in  std_logic; 
+         CLK       : in  std_logic; 
+         ENABLE    : in  std_logic; 
+         LOAD      : in  std_logic; 
+         LOWER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         UPPER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         ITERATOR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         REG_CNTR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         DONE      : out std_logic 
+      ); 
+   end component; 
+   -- 
+   component it_mod is 
+   generic( 
+      C_MOD     : natural := 10; 
+      C_WIDTH   : natural := 10; 
+      C_INIT    : natural :=  1; 
+      C_STEP    : natural :=  1  
+   ); 
+   port ( 
+      RST       : in  std_logic; 
+      CLK       : in  std_logic; 
+      LOAD      : in  std_logic; 
+      ENABLE    : in  std_logic; 
+      MODULE    : out std_logic_vector(C_WIDTH-1 downto 0) 
+   ); 
+   end component; 
+   -- 
+   -- Multirate related signals
+   signal sl_bla_en   : std_logic_vector(0 downto 0); 
+   signal sl_mr_en    : std_logic_vector(0 downto 0); 
+   signal sl_mr_done  : std_logic_vector(0 downto 0); 
+   signal sl_mr_lock  : std_logic_vector(0 downto 0); 
+   signal sl_enables  : std_logic_vector(0 downto 0); 
+   signal sl_enable   : std_logic; 
+   signal ENABLE      : std_logic; 
+   -- Function output parameter "data_out[x]", multirate=1 
+   constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   --  
+   -- Parameter related signals 
+   --  
+   -- Iterator (counter) related signals 
+   signal sl_low_x, sl_high_x : integer; 
+   signal sl_loop_x, sl_loop_x_rg : integer;
+   signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   -- 
+   signal sl_cntr_en  : std_logic_vector(N_CNTRS   downto 0); 
+   signal sl_done     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_done_all : std_logic; 
+   signal sl_load     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_stop     : std_logic; 
+   signal sl_fire     : std_logic; 
+   signal sl_eof      : std_logic; 
+   signal sl_sof      : std_logic; 
+   signal sl_count    : std_logic; 
+   -- 
+   -- Special Control signal
+   signal sl_CONTROL       : std_logic_vector(N_OUT_PORTS-1 downto 0);
+   signal sl_no_request    : std_logic;
+   -- 
+   -- alias signals 
+   alias update_x : std_logic is sl_cntr_en(0);
+   -- 
+   alias load_x : std_logic is sl_load(0);
+   -- Trigger signals 
+   signal sl_trigger_x : std_logic;
+
+   signal e0, e1 : boolean;
+
+   -- define control variables 
+   -- MOD related signals 
+   signal div3 : integer;
+   signal mod15 : integer;
+
+
+   type state_type is (s_idle, s_halt, s_count, s_release);
+   signal state : state_type;
+   signal halt_cnt : integer;
+   signal sl_halt : std_logic;
+
+   signal sl_cnt_rst : std_logic;
+   signal cnt_rst : std_logic;
+   signal x0_mod_320 : std_logic_vector(9-1 downto 0);
+
+begin
+
+   -- =============================================
+   -- =             MOD Functions                  
+   -- =============================================
+   -- MOD function: x % 320 == 0
+   INST_mod15 : it_mod
+   generic map(
+      C_MOD     => 320,
+      C_WIDTH   => 9,
+      C_INIT    => 0,
+      C_STEP    => 1
+   )
+   port map(
+      RST       => RST,
+      CLK       => CLK,
+      LOAD      => sl_done(0),
+      ENABLE    => sl_cntr_en(0),
+      MODULE    => x0_mod_320
+   );
+   mod15 <= TO_INTEGER(UNSIGNED(x0_mod_320));
+   -- 
+   -- END of MOD definitions 
+   --  
+   -- Parameter related signal assignments 
+   sl_cnt_rst <= '0';
+   sl_halt <= HALT;
+   -- END of Parameter definitions 
+
+   sl_loop_x    <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+   sl_loop_x_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+   -- Const bounds for-loops 
+   sl_low_x  <= 0;
+   sl_high_x <= 116167;
+
+
+   load_x <= '0';
+
+   sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_x,QUANT));
+
+   sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_x,QUANT));
+
+   -- Special definitions 
+   --mod15 <=  1; -- ERROR not implementated: mod(sl_loop_x_rg, 320);;
+
+   -- Entity and control variables
+   e0 <= sl_loop_x_rg>=0;
+   e1 <= -sl_loop_x_rg + 116167>=0;
+
+   sl_fire <= ('1');
+
+   -- Convert FIFO Write Port out_1 : EXTERNAL
+   sl_CONTROL(0) <= sl_fire and b2std((e0 and e1));
+
+   FIRE <= sl_fire;
+
+   cnt_rst <= sl_cnt_rst or RST;
+
+   -- 
+   -- =============================================
+   -- =             Multirate                      
+   -- =============================================
+   -- Function output parameter "data_out[x]", multirate=1 
+   CNTR_MR0 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(0),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_0,
+         UPPER_BND => sl_mr_ubnd_0,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(0)
+      );
+   -- 
+   -- WRITE_EN indicates if date can be written to WRITE_MUX
+   sl_bla_en      <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
+   WRITE_EN    <=  (others=>'0') when (HALT='1') else sl_bla_en;
+   -- 
+   sl_mr_en    <= (not sl_mr_lock) and WRITE_ST; 
+   sl_enables  <= sl_mr_lock or (sl_mr_done and sl_mr_en); 
+   sl_enable   <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0';  -- and_reduce 
+   ENABLE      <= sl_enable or (not sl_fire);
+   -- 
+   LOCK_PRCS: process(CLK) 
+   begin 
+       if rising_edge(CLK) then 
+           if( RST = '1' ) then 
+               sl_mr_lock <= (others=>'0'); 
+           else  
+               if (ENABLE='1') then 
+                   sl_mr_lock <= (others=>'0'); 
+               else 
+                   for i in 0 to 0 loop 
+                       if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then 
+                           sl_mr_lock(i) <= '1'; 
+                       end if; 
+                   end loop; 
+               end if; 
+           end if; 
+       end if; 
+   end process; 
+   -- END of Multirate definitions 
+   -- 
+   -- =============================================
+   -- =             Iterators                      
+   -- =============================================
+   GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
+   	CNTR_WR : counter
+   	generic map ( 
+   		C_STEP    => CNTR_STEP(i),
+   		C_WIDTH   => CNTR_WIDTH(i)
+   	)
+  	 port map (
+   		CLK       => CLK,
+   		RST       => cnt_rst,
+   		ENABLE    => sl_cntr_en(i),
+   		LOAD      => sl_load(i),
+   		LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		ITERATOR  => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		REG_CNTR  => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		DONE      => sl_done(i)
+   	);
+   end generate;
+   --
+   DONE_PRCS: process(CLK)
+   begin
+   	if rising_edge(CLK) then
+   	    if( RST = '1' ) then
+   		    sl_stop     <= '0';
+   		    sl_done_all <= '0';
+   		    sl_sof      <= '1';
+   	    else 
+   		    if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+   			    sl_stop <= '1';
+   		    elsif (WRAP=true) then
+   			    sl_stop <= '0';
+   		    end if;
+   		    if (sl_stop='0') then
+   			    sl_done_all <= sl_cntr_en(N_CNTRS);
+   		    end if;
+   		    if (ENABLE='1') then
+   			    sl_sof <= sl_eof;
+   		    end if;
+   	    end if;
+   	end if;
+   end process;
+   --
+   sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+   CONTROL <= sl_CONTROL;
+   --
+   DONE <= sl_done_all;     -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+   STOP <= sl_stop;         -- '1' = The couter stoped after the end of the itteration space. 
+   --
+   sl_count      <=  '0' when (sl_stop='1') else
+   			'1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
+   sl_cntr_en(0) <=  sl_count; -- makes the EVAL_LOGIC count
+   --
+   sl_cntr_en(N_CNTRS  downto 1) <= sl_cntr_en(N_CNTRS-1  downto 0) and sl_done(N_CNTRS-1  downto 0);
+   sl_eof <= sl_cntr_en(N_CNTRS);      -- End-of-frame (combinatorial; beter not use it outside)
+   --
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_14/src/vhdl/bunny_static_split2rtl_hwn_nd_14_execution_unit.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_14/src/vhdl/bunny_static_split2rtl_hwn_nd_14_execution_unit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f7a816dc33605839f43683112c45d40a842c6b83
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_14/src/vhdl/bunny_static_split2rtl_hwn_nd_14_execution_unit.vhd
@@ -0,0 +1,109 @@
+-- Execute Unit automatically generated by KpnMapper
+-- Function "compaan_outlinedproc6"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_bunny_static_split2rtl_functions_1_lib;
+use compaandesign_com_bunny_static_split2rtl_functions_1_lib.all;
+
+entity bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_14 is
+   generic (
+      N_INPORTS  : natural := 1;
+      N_OUTPORTS : natural := 1;
+      IP_RESET   : natural := 1; 
+      STIM_DIR   : string  := "bla";
+      QUANT      : natural := 32;
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1; 
+      CNTR_QUANT : natural := 32; 
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+   );
+   port (
+      RST        : in  std_logic;
+      CLK        : in  std_logic;
+      -- Funtion Input parameters
+      IN_PORT_0    : in  std_logic_vector(63 downto 0);  -- Param. "tmp1"
+      READ       : out std_logic_vector(N_INPORTS-1 downto 0);
+      EXIST      : in  std_logic_vector(N_INPORTS-1 downto 0);
+      -- Iterators
+      REG_CNTRS_RD : in  std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
+      -- Funtion Output parameters
+      OUT_PORT_0   : out std_logic_vector(63 downto 0);  -- Param. "tmp0"
+      WRITE      : out std_logic_vector(N_OUTPORTS-1 downto 0);
+      FULL       : in  std_logic_vector(N_OUTPORTS-1 downto 0);
+      STOP_RD    : in  std_logic;
+      STOP_WR    : in  std_logic;
+      ERROR      : out std_logic
+   );
+end bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_14 ;
+
+-- Laura implementation
+architecture Laura of bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_14 is
+
+   component compaan_outlinedproc6 is
+      generic (
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1; 
+         CNTR_QUANT : natural := 32; 
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST   : in std_logic;
+         CLK   : in std_logic;
+         -- Inputs 
+         ip_tmp1  : in  std_logic_vector(63 downto 0);  
+         -- Iterators 
+         it_x : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+         EXIST : in  std_logic_vector(0 downto 0);
+         READF : out std_logic_vector(0 downto 0);
+         -- Outputs 
+         op_tmp0 : out std_logic_vector(63 downto 0);
+         FULL  : in  std_logic_vector(0 downto 0);
+         WRITEF: out std_logic_vector(0 downto 0);
+         --
+         STOP_RD : in  std_logic;
+         STOP_WR : in  std_logic;
+         ERROR   : out std_logic
+      );
+   end component;
+
+   signal sl_RST : std_logic;
+
+begin
+
+   sl_RST <= RST when IP_RESET=1 else not RST;
+
+   FUNC : compaan_outlinedproc6
+   generic map (
+         STIM_DIR      => STIM_DIR,
+         c_STAGES      => c_STAGES,
+         N_CNTRS       => N_CNTRS,
+         CNTR_QUANT    => CNTR_QUANT,
+         CNTR_WIDTH    => CNTR_WIDTH
+   )
+   port map (
+      RST   => sl_RST,
+      CLK   => CLK,
+      -- Inputs 
+      ip_tmp1 => IN_PORT_0,
+      -- Iterators 
+      it_x => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
+      EXIST => EXIST,
+      READF => READ,
+      -- Outputs 
+      op_tmp0 => OUT_PORT_0,
+      FULL  => FULL,
+      WRITEF=> WRITE,
+      -- 
+      STOP_RD => STOP_RD,
+      STOP_WR => STOP_WR,
+      ERROR   => ERROR
+   );
+
+end Laura;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_2/hdllib.cfg b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_2/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..7d1c01355fe270a39090d6d4ec5e6be3c8b06203
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_2/hdllib.cfg
@@ -0,0 +1,18 @@
+hdl_lib_name = compaandesign_com_bunny_static_split2rtl_hwn_nd_2_1
+hdl_library_clause_name = compaandesign_com_bunny_static_split2rtl_hwn_nd_2_1_lib
+hdl_lib_uses_synth = compaandesign_com_bunny_static_split2rtl_functions_1 compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1 compaandesign_com_common_extern_connector_1 
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+	src/vhdl/bunny_static_split2rtl_hwn_nd_2_execution_unit.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_2_eval_logic_rd.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_2_eval_logic_wr.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_2.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_2/src/vhdl/bunny_static_split2rtl_hwn_nd_2.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_2/src/vhdl/bunny_static_split2rtl_hwn_nd_2.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..fcfe4aa7d212346f17c5e907119d86d588bee599
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_2/src/vhdl/bunny_static_split2rtl_hwn_nd_2.vhd
@@ -0,0 +1,476 @@
+-- HWN Entity File automatically generated by KpnMapper (writeHdlHWNodeFile)
+-- Top level file for a Hardware Accelerator
+-- Function "compaan_outlinedproc0"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+library compaandesign_com_common_extern_connector_1_lib;
+use compaandesign_com_common_extern_connector_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_2 is
+   generic (
+      STIM_DIR   : string  := "bla";
+      RESET_HIGH : natural := 1;
+      PAR_WIDTH  : natural := 16;
+      QUANT      : natural := 32;
+      WRAP       : boolean := true
+   );
+   port (
+
+      -- Dataflow input interfaces
+      data_in_Rd    : out std_logic;
+      data_in_Din   : in  std_logic_vector(63 downto 0);
+      data_in_Exist : in  std_logic; 
+      data_in_CLK   : out std_logic;
+      data_in_CTRL  : in  std_logic;
+
+      -- Dataflow Control Input interfaces
+      -- Dataflow output interfaces
+      -- ED_1 : out_0
+      ND_2OP_1_Wr   : out std_logic;
+      ND_2OP_1_Dout : out std_logic_vector(63 downto 0);
+      ND_2OP_1_Full : in  std_logic;
+      ND_2OP_1_CLK  : out std_logic;
+      ND_2OP_1_CTRL : out std_logic;
+
+      -- ED_2 : out_0
+      ND_2OP_1_d1_Wr   : out std_logic;
+      ND_2OP_1_d1_Dout : out std_logic_vector(63 downto 0);
+      ND_2OP_1_d1_Full : in  std_logic;
+      ND_2OP_1_d1_CLK  : out std_logic;
+      ND_2OP_1_d1_CTRL : out std_logic;
+
+      PARAM_DT : in  std_logic_vector(PAR_WIDTH+10-1 downto 0);
+      PARAM_LD : in  std_logic;
+
+      RST      : in  std_logic;
+      CLK      : in  std_logic;
+      STOP     : out std_logic;
+      ERROR    : out std_logic;
+      BLOCK_RD : out std_logic
+   );
+end bunny_static_split2rtl_hwn_nd_2;
+
+architecture RTL of bunny_static_split2rtl_hwn_nd_2 is
+   --
+   -- ====================================
+   -- =     Constants declaration        =
+   -- ====================================
+   -- Setting the parameters of the HW Node
+   constant c_IN_PORTS     : natural := 1; -- number of input ports of a HW node
+   constant c_OUT_PORTS    : natural := 2; -- number of output ports of a HW node
+   constant c_IN_FUNC_VAR  : natural := 1; -- number of input ports of a HW IP
+   constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
+   constant c_COUNTERS     : natural := 1; -- number of iterators
+   -- ===========================================
+   -- = Iterators run from Inner to Outer loop  =
+   -- ===========================================
+   constant c_CNTR_QUANT   : natural := 18;
+   constant c_CNTR_STEPS   : t_counter_step  := ( 0=>1, others=>1 );
+   constant c_CNTR_WIDTHS  : t_counter_width := ( 0=>18, others=>10 );
+   constant c_STAGES       : natural := 1; -- number of pipeline stages or delay
+   constant c_IP_RESET     : natural := 1; -- active level of the HW IP reset signal
+   constant c_WRAP         : boolean := WRAP; -- Operation mode: Single_Shot (false) or Continuous (true)
+   constant c_EXT_PAR      : natural := 0; -- number of external parameters
+   constant c_INT_PAR      : natural := 0; -- number of internal parameters
+   constant c_N_PAR        : natural := 0; -- no parameters are used
+   constant c_PAR_BITWIDTH : natural := PAR_WIDTH; -- aggregate bitwidth of the parameter vector
+   constant c_PAR_VECTOR   : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
+       (0,0,0,0), (0,0,0,0)    -- two dummy elements
+   );
+   --
+   -- ====================================
+   -- =     Components declaration       =
+   -- ====================================
+   component bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_2 is
+      generic (
+         N_IN_PORTS    : natural := 1;
+         WRAP          : boolean := true;
+         N_CNTRS       : natural := 1; 
+         QUANT         : natural := 32;
+         PAR_BITWIDTH  : natural :=1;
+         CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+         CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+      );
+      port (
+         RST           : in  std_logic;
+         CLK           : in  std_logic;
+         REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1  downto 0); 
+         READ_EN       : out std_logic_vector(c_IN_FUNC_VAR-1  downto 0);
+         READ_ST       : in  std_logic_vector(c_IN_FUNC_VAR-1  downto 0);
+         HALT          : in  std_logic;
+         FIRE          : out std_logic;
+         DONE          : out std_logic;
+         STOP          : out std_logic;
+         CONTROL       : out std_logic_vector(N_IN_PORTS-1 downto 0);
+         OBTAIN        : out std_logic_vector(N_IN_PORTS-1 downto 0);
+         RELEASE       : out std_logic_vector(N_IN_PORTS-1 downto 0)
+      );
+   end component;
+
+   component READ_MUX is
+      generic (
+         N_PORTS    : natural := 1;
+         PORT_WIDTH : natural := 32  
+      );
+      port(
+         IN_PORTS   : in  std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
+         EXISTS     : in  std_logic_vector(N_PORTS-1 downto 0);
+         READS      : out std_logic_vector(N_PORTS-1 downto 0);
+         SOFS       : in  std_logic_vector(N_PORTS-1 downto 0);
+
+         OUT_PORT   : out std_logic_vector(PORT_WIDTH-1 downto 0);
+         EXIST      : out std_logic;
+         READ       : in  std_logic;
+         SOF        : in  std_logic;
+		CLK        : in std_logic;
+
+         READ_EN    : in  std_logic;
+         READ_ST    : out std_logic;
+         CONTROL    : in  std_logic_vector(N_PORTS-1 downto 0);
+         OBTAIN     : in  std_logic_vector(N_PORTS-1 downto 0);
+         RELEASE    : in  std_logic_vector(N_PORTS-1 downto 0)
+      );
+   end component;
+
+   component bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_2 is
+      generic ( 
+         N_OUT_PORTS   : natural := 1;
+         WRAP          : boolean := true;
+         N_CNTRS       : natural := 1; 
+         QUANT         : natural := 32;
+         PAR_BITWIDTH  : natural :=1;
+         CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+         CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+      );
+      port (
+         RST           : in  std_logic;
+         CLK           : in  std_logic;
+         WRITE_EN      : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+         WRITE_ST      : in  std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+         HALT          : in  std_logic;
+         FIRE          : out std_logic;
+         DONE          : out std_logic;
+         STOP          : out std_logic;
+         CONTROL       : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+      );
+   end component;
+
+   component WRITE_DEMUX is
+      generic (
+         N_PORTS : natural := 1
+      );
+      port(
+         WRITES   : out std_logic_vector(N_PORTS-1 downto 0);
+         WRITE    : in  std_logic;
+
+         FULLS    : in  std_logic_vector(N_PORTS-1 downto 0);
+         FULL     : out std_logic;
+
+         WRITE_EN : in  std_logic;
+         WRITE_ST : out std_logic;
+         CONTROL  : in  std_logic_vector(N_PORTS-1 downto 0)
+      );
+   end component;
+
+
+   component bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_2 is
+      generic (
+         N_INPORTS  : natural := 1;
+         N_OUTPORTS : natural := 1;
+         IP_RESET   : natural := 1;
+         QUANT      : natural := 32;
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1;
+         CNTR_QUANT : natural := 32;
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST        : in  std_logic;
+         CLK        : in  std_logic;
+
+         -- Iterators
+         REG_CNTRS_RD : in  std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
+         -- Func. Input parameters
+         IN_PORT_0 : in  std_logic_vector(63 downto 0); -- tmp1
+         READ       : out std_logic_vector(N_INPORTS-1 downto 0);
+         EXIST      : in  std_logic_vector(N_INPORTS-1 downto 0);
+         -- Func. Output parameters
+         OUT_PORT_0 : out std_logic_vector(63 downto 0); -- tmp0
+         WRITE      : out std_logic_vector(N_OUTPORTS-1 downto 0);
+         FULL       : in  std_logic_vector(N_OUTPORTS-1 downto 0);
+         --
+         STOP_RD    : in  std_logic;
+         STOP_WR    : in  std_logic;
+         ERROR      : out std_logic
+      );
+   end component;
+
+   component INTERNAL_PARAMETERS is 
+      generic (
+         PAR_BITWIDTH : natural:=1;
+         PAR_VECTOR   : t_par_vector;
+         N_PAR        : natural:=0;
+         START_IN_RUN  : boolean := FALSE
+      );
+      port (  
+         RST        : in  std_logic;
+         CLK        : in  std_logic;
+
+         HALT_RD    : out std_logic;
+         HALT_WR    : out std_logic;
+         SOF_RD     : in  std_logic;
+         SOF_WR     : in  std_logic;
+         LOAD_PARAM : out std_logic;
+
+         par_one_in_Rd    : out std_logic;
+         par_one_in_Din   : in std_logic_vector(32-1 downto 0);
+         par_one_in_Exist : in std_logic;
+         par_one_in_CLK   : out std_logic;
+         par_one_in_CTRL  : in std_logic;
+
+         PARAMETERS_RD : out std_logic_vector(32-1 downto 0);
+         PARAMETERS_WR : out std_logic_vector(32-1 downto 0)
+      );
+   end component;
+
+   --
+   -- ====================================
+   -- =       Signals declaration        =
+   -- ====================================
+   -- 
+   -- HW Node Input Ports
+   signal sl_IN_PORTS_0   : std_logic_vector(1*64-1 downto 0); -- tmp1
+   signal sl_EXISTS       : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_READS        : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_CTRLS        : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_control_rd   : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_obtain_rd    : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_release_rd   : std_logic_vector(c_IN_PORTS-1 downto 0);
+   -- 
+   -- Func. Input parameters
+   signal sl_in_port_0    : std_logic_vector(63 downto 0); -- tmp1
+   signal sl_exist        : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read         : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read_en      : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read_st      : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   -- 
+   signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
+   -- 
+   -- HW Node Output Ports
+   signal sl_WRITES       : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_FULLS        : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_control_wr   : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_lortnoc_wr   : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   -- 
+   -- Func. Output parameters
+   signal sl_out_port_0   : std_logic_vector(63 downto 0); -- tmp0
+   signal sl_full         : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write        : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write_en     : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write_st     : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   -- 
+   -- 
+   signal sl_halt             : std_logic;
+   signal sl_halted           : std_logic;
+   signal sl_halt_wr          : std_logic;
+   signal sl_halt_rd          : std_logic;
+   signal sl_param_halt_wr    : std_logic;
+   signal sl_param_halt_rd    : std_logic;
+   signal sl_done_wr          : std_logic;
+   signal sl_done_rd          : std_logic;
+   signal sl_stop_wr          : std_logic;
+   signal sl_stop_rd          : std_logic;
+   signal sl_fire_wr          : std_logic;
+   signal sl_fire_rd          : std_logic;
+   signal sl_sof_wr           : std_logic;
+   signal sl_sof_rd           : std_logic;
+   signal sl_error            : std_logic;
+   signal sl_load_param       : std_logic;
+
+   --  
+   -- Parameter related signals 
+   signal sl_param_fifo_full     : std_logic;
+   signal sl_sync_num            : std_logic_vector(9 downto 0);
+
+   signal sl_RST : std_logic;
+
+begin 
+
+   sl_RST <= RST when RESET_HIGH=1 else not RST;
+      data_in_CLK   <= CLK;
+      ND_2OP_1_CLK  <= CLK;
+      ND_2OP_1_d1_CLK  <= CLK;
+
+   --
+   -- ==========================================================
+   -- =       HWN Input related modules                        =
+   -- ==========================================================
+   -- Func. Input param. "tmp1"
+   RD_MUX_0 : READ_MUX
+   generic map (
+      N_PORTS    => 1,
+      PORT_WIDTH => 64
+   )
+   port map (
+      IN_PORTS   => sl_IN_PORTS_0,
+      EXISTS     => sl_EXISTS(0 downto 0),
+      READS      => sl_READS(0 downto 0),
+      SOFS       => sl_CTRLS(0 downto 0),
+
+      OUT_PORT   => sl_in_port_0,
+      EXIST      => sl_exist(0),
+      READ       => sl_read(0),
+      SOF        => sl_sof_rd,
+      CLK        => CLK,
+
+      READ_EN    => sl_read_en(0),
+      READ_ST    => sl_read_st(0),
+      CONTROL    => sl_control_rd(0 downto 0),
+      OBTAIN     => sl_obtain_rd(0 downto 0),
+      RELEASE    => sl_release_rd(0 downto 0)
+   );
+
+   data_in_Rd   <= sl_READS(0);
+
+   sl_IN_PORTS_0 <= data_in_Din;
+
+   sl_EXISTS(0)   <= data_in_Exist ;
+   sl_CTRLS(0)    <= data_in_CTRL ;
+
+   EVAL_RD : bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_2
+   generic map ( 
+      N_IN_PORTS    => c_IN_PORTS,
+      WRAP          => c_WRAP,
+      N_CNTRS       => c_COUNTERS,
+      QUANT         => c_CNTR_QUANT,
+      PAR_BITWIDTH  => c_PAR_BITWIDTH,
+      CNTR_STEP     => c_CNTR_STEPS,
+      CNTR_WIDTH    => c_CNTR_WIDTHS
+   )
+   port map(
+      RST           => sl_RST,
+      CLK           => CLK,
+      REG_CNTRS     => sl_REG_CNTRS_RD,
+      READ_EN       => sl_read_en,
+      READ_ST       => sl_read_st,
+      HALT          => sl_halt_rd,
+      FIRE          => sl_fire_rd,
+      DONE          => sl_done_rd,
+      STOP          => sl_stop_rd,
+      CONTROL       => sl_control_rd,
+      OBTAIN        => sl_obtain_rd,
+      RELEASE       => sl_release_rd
+   );
+
+   --
+   -- ==========================================================
+   -- =       HWN Output related modules                       =
+   -- ==========================================================
+   -- 
+   -- Func. Output param. "tmp0"
+   DEMUX_0 : WRITE_DEMUX
+   generic map (
+      N_PORTS => 2
+   )
+   port map (
+      WRITES   => sl_WRITES(1 downto 0),
+      FULLS    => sl_FULLS(1 downto 0),
+      CONTROL  => sl_lortnoc_wr(1 downto 0),
+      WRITE    => sl_write(0),
+      FULL     => sl_full(0),
+      WRITE_EN => sl_write_en(0),
+      WRITE_ST => sl_write_st(0)
+   );
+   --
+   ND_2OP_1_Dout <= sl_out_port_0;  -- Func. Output param. "tmp0"
+   ND_2OP_1_CTRL <= sl_sof_wr ;
+   ND_2OP_1_Wr   <= sl_WRITES(0);
+   sl_FULLS(0) <= ND_2OP_1_Full;
+   sl_lortnoc_wr(0) <= sl_control_wr(0);
+   --
+   ND_2OP_1_d1_Dout <= sl_out_port_0;  -- Func. Output param. "tmp0"
+   ND_2OP_1_d1_CTRL <= sl_sof_wr ;
+   ND_2OP_1_d1_Wr   <= sl_WRITES(1);
+   sl_FULLS(1) <= ND_2OP_1_d1_Full;
+   sl_lortnoc_wr(1) <= sl_control_wr(1);
+   --
+   --
+   EVAL_WR : bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_2
+   generic map ( 
+      N_OUT_PORTS   => c_OUT_PORTS,
+      WRAP          => c_WRAP,
+      N_CNTRS       => c_COUNTERS,
+      QUANT         => c_CNTR_QUANT,
+      PAR_BITWIDTH  => c_PAR_BITWIDTH,
+      CNTR_STEP     => c_CNTR_STEPS,
+      CNTR_WIDTH    => c_CNTR_WIDTHS
+   )
+   port map (
+      RST           => sl_RST,
+      CLK           => CLK,
+      WRITE_EN      => sl_write_en,
+      WRITE_ST      => sl_write_st,
+      HALT          => sl_halt_wr,
+      FIRE          => sl_fire_wr,
+      DONE          => sl_done_wr,
+      STOP          => sl_stop_wr,
+      CONTROL       => sl_control_wr
+   );
+
+   --
+   -- ==========================================================
+   -- =       HWN Execution Unit                               =
+   -- ==========================================================
+   EX : bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_2
+   generic map (
+      N_INPORTS  => c_IN_FUNC_VAR,
+      N_OUTPORTS => c_OUT_FUNC_VAR, 
+      IP_RESET   => c_IP_RESET,
+      QUANT      => QUANT,
+      STIM_DIR   => STIM_DIR,
+      c_STAGES   => c_STAGES,
+      N_CNTRS    => c_COUNTERS,
+      CNTR_QUANT => c_CNTR_QUANT,
+      CNTR_WIDTH => c_CNTR_WIDTHS
+   )
+   port map (
+      RST        => sl_RST,
+      CLK        => CLK,
+      -- Iterators
+      REG_CNTRS_RD => sl_REG_CNTRS_RD,
+      -- Func. Input parameters
+      IN_PORT_0    => sl_in_port_0,
+      READ       => sl_read,
+      EXIST      => sl_exist,
+      -- Func. Output parameters
+      OUT_PORT_0   => sl_out_port_0,
+      WRITE      => sl_write,
+      FULL       => sl_full,
+      --
+      STOP_WR    => sl_stop_wr,
+      STOP_RD    => sl_stop_rd,
+      ERROR      => sl_error
+   );
+
+   -- ==========================================================
+   -- =       PARAMETERIZATION                                 =
+   -- ==========================================================
+   -- no parameters
+   sl_halt_rd <= '0';
+   sl_halt_wr <= '0';
+--   sl_halted  <= sl_sof_rd;
+   STOP <= sl_done_wr;
+   ERROR <= sl_error;
+   BLOCK_RD <= not (  (  sl_READS(0)  ) );
+
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_2/src/vhdl/bunny_static_split2rtl_hwn_nd_2_eval_logic_rd.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_2/src/vhdl/bunny_static_split2rtl_hwn_nd_2_eval_logic_rd.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d9246d3fd4e8af012bb00806f3c30e1e6382a75c
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_2/src/vhdl/bunny_static_split2rtl_hwn_nd_2_eval_logic_rd.vhd
@@ -0,0 +1,286 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_2 is
+   generic (
+      N_IN_PORTS    : natural := 1;
+      WRAP          : boolean := true;
+      N_CNTRS       : natural := 1; 
+      QUANT         : natural := 32;
+      PAR_BITWIDTH  : natural  :=1;
+      CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+      CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST           : in  std_logic;
+      CLK           : in  std_logic;
+      REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+      READ_EN       : out std_logic_vector(0 downto 0);
+      READ_ST       : in  std_logic_vector(0 downto 0);
+      HALT          : in  std_logic;
+      FIRE          : out std_logic;
+      DONE          : out std_logic;
+      STOP          : out std_logic;
+      CONTROL       : out std_logic_vector(N_IN_PORTS-1 downto 0);
+      OBTAIN        : out std_logic_vector(N_IN_PORTS-1 downto 0);
+      RELEASE       : out std_logic_vector(N_IN_PORTS-1 downto 0)
+   );
+end bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_2;
+
+architecture RTL of bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_2 is
+   -- 
+   component counter is 
+      generic( 
+         C_STEP    : natural := 10; 
+         C_WIDTH   : natural := 10 
+      ); 
+      port ( 
+         RST       : in  std_logic; 
+         CLK       : in  std_logic; 
+         ENABLE    : in  std_logic; 
+         LOAD      : in  std_logic; 
+         LOWER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         UPPER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         ITERATOR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         REG_CNTR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         DONE      : out std_logic 
+      ); 
+   end component; 
+   -- 
+   component it_mod is 
+   generic( 
+      C_MOD     : natural := 10; 
+      C_WIDTH   : natural := 10; 
+      C_INIT    : natural :=  1; 
+      C_STEP    : natural :=  1  
+   ); 
+   port ( 
+      RST       : in  std_logic; 
+      CLK       : in  std_logic; 
+      LOAD      : in  std_logic; 
+      ENABLE    : in  std_logic; 
+      MODULE    : out std_logic_vector(C_WIDTH-1 downto 0) 
+   ); 
+   end component; 
+   -- 
+   --  
+   -- Parameter related signals 
+   -- 
+   -- Iterator (counter) related signals 
+   signal sl_low_i, sl_high_i : integer;
+   signal sl_loop_i, sl_loop_i_rg : integer;
+   signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   -- 
+   signal sl_cntr_en  : std_logic_vector(N_CNTRS   downto 0); 
+   signal sl_done     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_done_all : std_logic; 
+   signal sl_load     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_stop     : std_logic; 
+   signal sl_fire     : std_logic; 
+   signal sl_sof      : std_logic; 
+   signal sl_eof      : std_logic; 
+   signal sl_count    : std_logic; 
+
+   -- alias signals 
+   alias update_i : std_logic is sl_cntr_en(0);
+   alias load_i : std_logic is sl_load(0);
+
+   -- Trigger signals 
+   signal sl_trigger_i : std_logic;
+
+   -- Special Control signal
+   signal sl_CONTROL       : std_logic_vector(N_IN_PORTS-1 downto 0);
+   signal sl_no_request    : std_logic;
+   -- 
+   -- Multirate related signals
+   signal sl_bla_en   : std_logic_vector(0 downto 0); 
+   signal sl_mr_en    : std_logic_vector(0 downto 0); 
+   signal sl_mr_done  : std_logic_vector(0 downto 0); 
+   signal sl_mr_lock  : std_logic_vector(0 downto 0); 
+   signal sl_enables  : std_logic_vector(0 downto 0); 
+   signal sl_enable   : std_logic; 
+   signal ENABLE      : std_logic; 
+   -- Function input parameter "data_in[i]", multirate=1 
+   constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+
+   signal e0, e1 : boolean;
+
+   signal sl_obtain0  : std_logic;
+   signal sl_release0 : std_logic;
+
+   -- define control variables 
+
+   type state_type is (s_idle, s_halt, s_count, s_release);
+   signal state : state_type;
+   signal halt_cnt : integer;
+   signal sl_halt : std_logic;
+
+   signal sl_cnt_rst : std_logic;
+   signal cnt_rst : std_logic;
+
+begin
+
+   -- =============================================
+   -- =             MOD Functions                  
+   -- =============================================
+   -- END of MOD definitions 
+   -- =============================================
+   -- =             Parameter Functions            
+   -- =============================================
+   sl_cnt_rst <= '0';
+   sl_halt <= HALT;
+
+   -- END of Parameter definitions 
+   sl_loop_i    <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+   sl_loop_i_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+   -- Const bounds for-loops 
+   sl_low_i  <= 0;
+   sl_high_i <= 116167;
+
+
+   load_i <= '0';
+
+   sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
+
+   sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
+   -- Special definitions 
+
+   -- Entity and control variables
+   -- Release matrix expressions
+   e0 <= sl_loop_i_rg>=0;
+   e1 <= -sl_loop_i_rg + 116167>=0;
+
+   sl_fire <= ('1');
+
+   -- Convert FIFO Read Port in_1 : EXTERNAL
+   sl_obtain0 <= ('1');  -- set obtain/release to const value; not used
+   sl_release0 <= ('1');
+
+   sl_CONTROL(0) <= sl_fire and b2std((e0 and e1));
+   OBTAIN(0) <= sl_obtain0;
+   RELEASE(0) <= sl_release0;
+
+   FIRE <= sl_fire;
+
+   cnt_rst <= sl_cnt_rst or RST;
+
+   -- 
+   -- =============================================
+   -- =             Multirate                      
+   -- =============================================
+   -- Function input parameter "data_in[i]", multirate=1 
+   CNTR_MR0 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(0),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_0,
+         UPPER_BND => sl_mr_ubnd_0,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(0)
+      );
+   -- READ_EN indicates if READ_MUX can read data
+   sl_bla_en   <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');  
+   READ_EN     <= (others=>'0') when (HALT='1') else sl_bla_en;  
+   sl_mr_en   <= READ_ST; 
+   sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en); 
+   sl_enable  <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce 
+   ENABLE     <=  sl_enable or (not sl_fire);
+   -- 
+   LOCK_PRCS: process(CLK) 
+   begin 
+       if rising_edge(CLK) then 
+           if( RST = '1' ) then 
+               sl_mr_lock <= (others=>'0'); 
+           else  
+               if (ENABLE='1') then 
+                   sl_mr_lock <= (others=>'0'); 
+               else 
+                   for i in 0 to 0 loop 
+                       if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then 
+                           sl_mr_lock(i) <= '1'; 
+                       end if; 
+                   end loop; 
+               end if; 
+           end if; 
+       end if; 
+   end process; 
+   -- END of Multirate definitions 
+   -- 
+   -- =============================================
+   -- =             Iterators                      
+   -- =============================================
+   GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
+   	CNTR_RD : counter
+   	generic map ( 
+   		C_STEP    => CNTR_STEP(i),
+   		C_WIDTH   => CNTR_WIDTH(i)
+   	)
+  	 port map (
+   		CLK       => CLK,
+   		RST       => cnt_rst,
+   		ENABLE    => sl_cntr_en(i),
+			LOAD      => sl_load(i),
+   		LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		ITERATOR  => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		REG_CNTR  => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		DONE      => sl_done(i)
+   	);
+   end generate;
+   --
+   DONE_PRCS: process(CLK)
+   begin
+   	if rising_edge(CLK) then
+          if( RST = '1' ) then
+   		    sl_stop     <= '0';
+   		    sl_done_all <= '0';
+   		    sl_sof      <= '1';
+   	    else 
+   		    if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+   			    sl_stop <= '1';
+   		    elsif (WRAP=true) then
+   			    sl_stop <= '0';
+   		    end if;
+   		    if (sl_stop='0') then
+   			    sl_done_all <= sl_cntr_en(N_CNTRS);
+   		    end if;
+   		    if (ENABLE='1') then
+   			    sl_sof <= sl_eof;
+   		    end if;
+   	    end if;
+   	end if;
+   end process;
+   --
+   sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+   CONTROL <= sl_CONTROL;
+   --
+   REG_CNTRS <= sl_reg_cntrs; 
+   DONE <= sl_done_all;     -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+   STOP <= sl_stop;         -- '1' = The couter stoped after the end of the itteration space. 
+   --
+   sl_count      <=  '0' when (sl_stop='1') else
+                     '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
+   sl_cntr_en(0) <=  sl_count; -- makes the EVAL_LOGIC count
+   --
+   sl_cntr_en(N_CNTRS  downto 1) <= sl_cntr_en(N_CNTRS-1  downto 0) and sl_done(N_CNTRS-1  downto 0);
+   sl_eof <= sl_cntr_en(N_CNTRS);   -- End-of-frame
+   --
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_2/src/vhdl/bunny_static_split2rtl_hwn_nd_2_eval_logic_wr.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_2/src/vhdl/bunny_static_split2rtl_hwn_nd_2_eval_logic_wr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..581b4cabc8eb04d8e505245f972e5e8bb3dc53b3
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_2/src/vhdl/bunny_static_split2rtl_hwn_nd_2_eval_logic_wr.vhd
@@ -0,0 +1,279 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_2 is
+   generic ( 
+      N_OUT_PORTS   : natural := 1;
+      WRAP          : boolean := true;
+      N_CNTRS       : natural := 1;
+      QUANT         : natural := 32;
+      PAR_BITWIDTH  : natural :=1;
+      CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+      CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST           : in  std_logic;
+      CLK           : in  std_logic;
+      WRITE_EN      : out std_logic_vector(0 downto 0);
+      WRITE_ST      : in  std_logic_vector(0 downto 0);
+      HALT          : in  std_logic;
+      FIRE          : out std_logic;
+      DONE          : out std_logic;
+      STOP          : out std_logic;
+      CONTROL       : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+   );
+end bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_2;
+
+architecture RTL of bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_2 is	
+   -- 
+   component counter is 
+      generic( 
+         C_STEP    : natural := 10; 
+         C_WIDTH   : natural := 10 
+      ); 
+      port ( 
+         RST       : in  std_logic; 
+         CLK       : in  std_logic; 
+         ENABLE    : in  std_logic; 
+         LOAD      : in  std_logic; 
+         LOWER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         UPPER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         ITERATOR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         REG_CNTR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         DONE      : out std_logic 
+      ); 
+   end component; 
+   -- 
+   component it_mod is 
+   generic( 
+      C_MOD     : natural := 10; 
+      C_WIDTH   : natural := 10; 
+      C_INIT    : natural :=  1; 
+      C_STEP    : natural :=  1  
+   ); 
+   port ( 
+      RST       : in  std_logic; 
+      CLK       : in  std_logic; 
+      LOAD      : in  std_logic; 
+      ENABLE    : in  std_logic; 
+      MODULE    : out std_logic_vector(C_WIDTH-1 downto 0) 
+   ); 
+   end component; 
+   -- 
+   -- Multirate related signals
+   signal sl_bla_en   : std_logic_vector(0 downto 0); 
+   signal sl_mr_en    : std_logic_vector(0 downto 0); 
+   signal sl_mr_done  : std_logic_vector(0 downto 0); 
+   signal sl_mr_lock  : std_logic_vector(0 downto 0); 
+   signal sl_enables  : std_logic_vector(0 downto 0); 
+   signal sl_enable   : std_logic; 
+   signal ENABLE      : std_logic; 
+   -- Function output parameter "out_0", multirate=1 
+   constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   --  
+   -- Parameter related signals 
+   --  
+   -- Iterator (counter) related signals 
+   signal sl_low_i, sl_high_i : integer; 
+   signal sl_loop_i, sl_loop_i_rg : integer;
+   signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   -- 
+   signal sl_cntr_en  : std_logic_vector(N_CNTRS   downto 0); 
+   signal sl_done     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_done_all : std_logic; 
+   signal sl_load     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_stop     : std_logic; 
+   signal sl_fire     : std_logic; 
+   signal sl_eof      : std_logic; 
+   signal sl_sof      : std_logic; 
+   signal sl_count    : std_logic; 
+   -- 
+   -- Special Control signal
+   signal sl_CONTROL       : std_logic_vector(N_OUT_PORTS-1 downto 0);
+   signal sl_no_request    : std_logic;
+   -- 
+   -- alias signals 
+   alias update_i : std_logic is sl_cntr_en(0);
+   -- 
+   alias load_i : std_logic is sl_load(0);
+   -- Trigger signals 
+   signal sl_trigger_i : std_logic;
+
+   signal e0, e1 : boolean;
+
+   -- define control variables 
+   -- MOD related signals 
+
+
+   type state_type is (s_idle, s_halt, s_count, s_release);
+   signal state : state_type;
+   signal halt_cnt : integer;
+   signal sl_halt : std_logic;
+
+   signal sl_cnt_rst : std_logic;
+   signal cnt_rst : std_logic;
+
+begin
+
+   -- =============================================
+   -- =             MOD Functions                  
+   -- =============================================
+   -- END of MOD definitions 
+   --  
+   -- Parameter related signal assignments 
+   sl_cnt_rst <= '0';
+   sl_halt <= HALT;
+   -- END of Parameter definitions 
+
+   sl_loop_i    <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+   sl_loop_i_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+   -- Const bounds for-loops 
+   sl_low_i  <= 0;
+   sl_high_i <= 116167;
+
+
+   load_i <= '0';
+
+   sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
+
+   sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
+
+   -- Special definitions 
+
+   -- Entity and control variables
+   e0 <= sl_loop_i_rg=0;
+   e1 <= -sl_loop_i_rg + 115199>=0;
+
+   sl_fire <= ('1');
+
+   -- Convert FIFO Write Port out_1 : ED_1
+   sl_CONTROL(0) <= sl_fire and b2std((e0));
+
+   -- Convert FIFO Write Port out_2 : ED_2
+   sl_CONTROL(1) <= sl_fire and b2std((e1));
+
+   FIRE <= sl_fire;
+
+   cnt_rst <= sl_cnt_rst or RST;
+
+   -- 
+   -- =============================================
+   -- =             Multirate                      
+   -- =============================================
+   -- Function output parameter "out_0", multirate=1 
+   CNTR_MR0 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(0),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_0,
+         UPPER_BND => sl_mr_ubnd_0,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(0)
+      );
+   -- 
+   -- WRITE_EN indicates if date can be written to WRITE_MUX
+   sl_bla_en      <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
+   WRITE_EN    <=  (others=>'0') when (HALT='1') else sl_bla_en;
+   -- 
+   sl_mr_en    <= (not sl_mr_lock) and WRITE_ST; 
+   sl_enables  <= sl_mr_lock or (sl_mr_done and sl_mr_en); 
+   sl_enable   <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0';  -- and_reduce 
+   ENABLE      <= sl_enable or (not sl_fire);
+   -- 
+   LOCK_PRCS: process(CLK) 
+   begin 
+       if rising_edge(CLK) then 
+           if( RST = '1' ) then 
+               sl_mr_lock <= (others=>'0'); 
+           else  
+               if (ENABLE='1') then 
+                   sl_mr_lock <= (others=>'0'); 
+               else 
+                   for i in 0 to 0 loop 
+                       if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then 
+                           sl_mr_lock(i) <= '1'; 
+                       end if; 
+                   end loop; 
+               end if; 
+           end if; 
+       end if; 
+   end process; 
+   -- END of Multirate definitions 
+   -- 
+   -- =============================================
+   -- =             Iterators                      
+   -- =============================================
+   GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
+   	CNTR_WR : counter
+   	generic map ( 
+   		C_STEP    => CNTR_STEP(i),
+   		C_WIDTH   => CNTR_WIDTH(i)
+   	)
+  	 port map (
+   		CLK       => CLK,
+   		RST       => cnt_rst,
+   		ENABLE    => sl_cntr_en(i),
+   		LOAD      => sl_load(i),
+   		LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		ITERATOR  => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		REG_CNTR  => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		DONE      => sl_done(i)
+   	);
+   end generate;
+   --
+   DONE_PRCS: process(CLK)
+   begin
+   	if rising_edge(CLK) then
+   	    if( RST = '1' ) then
+   		    sl_stop     <= '0';
+   		    sl_done_all <= '0';
+   		    sl_sof      <= '1';
+   	    else 
+   		    if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+   			    sl_stop <= '1';
+   		    elsif (WRAP=true) then
+   			    sl_stop <= '0';
+   		    end if;
+   		    if (sl_stop='0') then
+   			    sl_done_all <= sl_cntr_en(N_CNTRS);
+   		    end if;
+   		    if (ENABLE='1') then
+   			    sl_sof <= sl_eof;
+   		    end if;
+   	    end if;
+   	end if;
+   end process;
+   --
+   sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+   CONTROL <= sl_CONTROL;
+   --
+   DONE <= sl_done_all;     -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+   STOP <= sl_stop;         -- '1' = The couter stoped after the end of the itteration space. 
+   --
+   sl_count      <=  '0' when (sl_stop='1') else
+   			'1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
+   sl_cntr_en(0) <=  sl_count; -- makes the EVAL_LOGIC count
+   --
+   sl_cntr_en(N_CNTRS  downto 1) <= sl_cntr_en(N_CNTRS-1  downto 0) and sl_done(N_CNTRS-1  downto 0);
+   sl_eof <= sl_cntr_en(N_CNTRS);      -- End-of-frame (combinatorial; beter not use it outside)
+   --
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_2/src/vhdl/bunny_static_split2rtl_hwn_nd_2_execution_unit.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_2/src/vhdl/bunny_static_split2rtl_hwn_nd_2_execution_unit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d2305e71d421f247f7d5db893852752dfac4ba0a
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_2/src/vhdl/bunny_static_split2rtl_hwn_nd_2_execution_unit.vhd
@@ -0,0 +1,109 @@
+-- Execute Unit automatically generated by KpnMapper
+-- Function "compaan_outlinedproc0"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_bunny_static_split2rtl_functions_1_lib;
+use compaandesign_com_bunny_static_split2rtl_functions_1_lib.all;
+
+entity bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_2 is
+   generic (
+      N_INPORTS  : natural := 1;
+      N_OUTPORTS : natural := 1;
+      IP_RESET   : natural := 1; 
+      STIM_DIR   : string  := "bla";
+      QUANT      : natural := 32;
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1; 
+      CNTR_QUANT : natural := 32; 
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+   );
+   port (
+      RST        : in  std_logic;
+      CLK        : in  std_logic;
+      -- Funtion Input parameters
+      IN_PORT_0    : in  std_logic_vector(63 downto 0);  -- Param. "tmp1"
+      READ       : out std_logic_vector(N_INPORTS-1 downto 0);
+      EXIST      : in  std_logic_vector(N_INPORTS-1 downto 0);
+      -- Iterators
+      REG_CNTRS_RD : in  std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
+      -- Funtion Output parameters
+      OUT_PORT_0   : out std_logic_vector(63 downto 0);  -- Param. "tmp0"
+      WRITE      : out std_logic_vector(N_OUTPORTS-1 downto 0);
+      FULL       : in  std_logic_vector(N_OUTPORTS-1 downto 0);
+      STOP_RD    : in  std_logic;
+      STOP_WR    : in  std_logic;
+      ERROR      : out std_logic
+   );
+end bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_2 ;
+
+-- Laura implementation
+architecture Laura of bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_2 is
+
+   component compaan_outlinedproc0 is
+      generic (
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1; 
+         CNTR_QUANT : natural := 32; 
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST   : in std_logic;
+         CLK   : in std_logic;
+         -- Inputs 
+         ip_tmp1  : in  std_logic_vector(63 downto 0);  
+         -- Iterators 
+         it_i : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+         EXIST : in  std_logic_vector(0 downto 0);
+         READF : out std_logic_vector(0 downto 0);
+         -- Outputs 
+         op_tmp0 : out std_logic_vector(63 downto 0);
+         FULL  : in  std_logic_vector(0 downto 0);
+         WRITEF: out std_logic_vector(0 downto 0);
+         --
+         STOP_RD : in  std_logic;
+         STOP_WR : in  std_logic;
+         ERROR   : out std_logic
+      );
+   end component;
+
+   signal sl_RST : std_logic;
+
+begin
+
+   sl_RST <= RST when IP_RESET=1 else not RST;
+
+   FUNC : compaan_outlinedproc0
+   generic map (
+         STIM_DIR      => STIM_DIR,
+         c_STAGES      => c_STAGES,
+         N_CNTRS       => N_CNTRS,
+         CNTR_QUANT    => CNTR_QUANT,
+         CNTR_WIDTH    => CNTR_WIDTH
+   )
+   port map (
+      RST   => sl_RST,
+      CLK   => CLK,
+      -- Inputs 
+      ip_tmp1 => IN_PORT_0,
+      -- Iterators 
+      it_i => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
+      EXIST => EXIST,
+      READF => READ,
+      -- Outputs 
+      op_tmp0 => OUT_PORT_0,
+      FULL  => FULL,
+      WRITEF=> WRITE,
+      -- 
+      STOP_RD => STOP_RD,
+      STOP_WR => STOP_WR,
+      ERROR   => ERROR
+   );
+
+end Laura;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_4/hdllib.cfg b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_4/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..a668c44e92ff3e2976be7c6898afbe5b9d0e985a
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_4/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = compaandesign_com_bunny_static_split2rtl_hwn_nd_4_1
+hdl_library_clause_name = compaandesign_com_bunny_static_split2rtl_hwn_nd_4_1_lib
+hdl_lib_uses_synth = compaandesign_com_bunny_static_split2rtl_functions_1 compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1 compaandesign_com_common_extern_connector_1 
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+	src/vhdl/bunny_static_split2rtl_hwn_nd_4_execution_unit.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_4_eval_logic_rd.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_4.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_4/src/vhdl/bunny_static_split2rtl_hwn_nd_4.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_4/src/vhdl/bunny_static_split2rtl_hwn_nd_4.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f6d017f59c54b543a89fd08e8f98589f3dd8d142
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_4/src/vhdl/bunny_static_split2rtl_hwn_nd_4.vhd
@@ -0,0 +1,355 @@
+-- HWN Entity File automatically generated by KpnMapper (writeHdlHWNodeFile)
+-- Top level file for a Hardware Accelerator
+-- Function "increaseFrameCount"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+library compaandesign_com_common_extern_connector_1_lib;
+use compaandesign_com_common_extern_connector_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_4 is
+   generic (
+      STIM_DIR   : string  := "bla";
+      RESET_HIGH : natural := 1;
+      PAR_WIDTH  : natural := 16;
+      QUANT      : natural := 32;
+      WRAP       : boolean := true
+   );
+   port (
+      --  Non Syncronized Parameters
+      rf_count     : out  std_logic_vector( 32-1 downto 0); -- output
+
+      -- Dataflow input interfaces
+      -- ED_1 : in_0
+      ND_4IP_1_Rd    : out std_logic;
+      ND_4IP_1_Din   : in  std_logic_vector(63 downto 0);
+      ND_4IP_1_Exist : in  std_logic; 
+      ND_4IP_1_CLK   : out std_logic;
+      ND_4IP_1_CTRL  : in  std_logic;
+
+      -- Dataflow Control Input interfaces
+      -- Dataflow output interfaces
+      PARAM_DT : in  std_logic_vector(PAR_WIDTH+10-1 downto 0);
+      PARAM_LD : in  std_logic;
+
+      RST      : in  std_logic;
+      CLK      : in  std_logic;
+      STOP     : out std_logic;
+      ERROR    : out std_logic;
+      BLOCK_RD : out std_logic
+   );
+end bunny_static_split2rtl_hwn_nd_4;
+
+architecture RTL of bunny_static_split2rtl_hwn_nd_4 is
+   --
+   -- ====================================
+   -- =     Constants declaration        =
+   -- ====================================
+   -- Setting the parameters of the HW Node
+   constant c_IN_PORTS     : natural := 1; -- number of input ports of a HW node
+   constant c_OUT_PORTS    : natural := 0; -- number of output ports of a HW node
+   constant c_IN_FUNC_VAR  : natural := 1; -- number of input ports of a HW IP
+   constant c_OUT_FUNC_VAR : natural := 0; -- number of output ports of a HW IP
+   constant c_COUNTERS     : natural := 1; -- number of iterators
+   -- ===========================================
+   -- = Iterators run from Inner to Outer loop  =
+   -- ===========================================
+   constant c_CNTR_QUANT   : natural := 18;
+   constant c_CNTR_STEPS   : t_counter_step  := ( 0=>1, others=>1 );
+   constant c_CNTR_WIDTHS  : t_counter_width := ( 0=>18, others=>10 );
+   constant c_STAGES       : natural := 1; -- number of pipeline stages or delay
+   constant c_IP_RESET     : natural := 1; -- active level of the HW IP reset signal
+   constant c_WRAP         : boolean := WRAP; -- Operation mode: Single_Shot (false) or Continuous (true)
+   constant c_EXT_PAR      : natural := 0; -- number of external parameters
+   constant c_INT_PAR      : natural := 0; -- number of internal parameters
+   constant c_N_PAR        : natural := 0; -- no parameters are used
+   constant c_PAR_BITWIDTH : natural := PAR_WIDTH; -- aggregate bitwidth of the parameter vector
+   constant c_PAR_VECTOR   : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
+       (0,0,0,0), (0,0,0,0)    -- two dummy elements
+   );
+   --
+   -- ====================================
+   -- =     Components declaration       =
+   -- ====================================
+   component bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_4 is
+      generic (
+         N_IN_PORTS    : natural := 1;
+         WRAP          : boolean := true;
+         N_CNTRS       : natural := 1; 
+         QUANT         : natural := 32;
+         PAR_BITWIDTH  : natural :=1;
+         CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+         CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+      );
+      port (
+         RST           : in  std_logic;
+         CLK           : in  std_logic;
+         REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1  downto 0); 
+         READ_EN       : out std_logic_vector(c_IN_FUNC_VAR-1  downto 0);
+         READ_ST       : in  std_logic_vector(c_IN_FUNC_VAR-1  downto 0);
+         HALT          : in  std_logic;
+         FIRE          : out std_logic;
+         DONE          : out std_logic;
+         STOP          : out std_logic;
+         CONTROL       : out std_logic_vector(N_IN_PORTS-1 downto 0);
+         OBTAIN        : out std_logic_vector(N_IN_PORTS-1 downto 0);
+         RELEASE       : out std_logic_vector(N_IN_PORTS-1 downto 0)
+      );
+   end component;
+
+   component READ_MUX is
+      generic (
+         N_PORTS    : natural := 1;
+         PORT_WIDTH : natural := 32  
+      );
+      port(
+         IN_PORTS   : in  std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
+         EXISTS     : in  std_logic_vector(N_PORTS-1 downto 0);
+         READS      : out std_logic_vector(N_PORTS-1 downto 0);
+         SOFS       : in  std_logic_vector(N_PORTS-1 downto 0);
+
+         OUT_PORT   : out std_logic_vector(PORT_WIDTH-1 downto 0);
+         EXIST      : out std_logic;
+         READ       : in  std_logic;
+         SOF        : in  std_logic;
+		CLK        : in std_logic;
+
+         READ_EN    : in  std_logic;
+         READ_ST    : out std_logic;
+         CONTROL    : in  std_logic_vector(N_PORTS-1 downto 0);
+         OBTAIN     : in  std_logic_vector(N_PORTS-1 downto 0);
+         RELEASE    : in  std_logic_vector(N_PORTS-1 downto 0)
+      );
+   end component;
+
+
+   component bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_4 is
+      generic (
+         N_INPORTS  : natural := 1;
+         IP_RESET   : natural := 1;
+         QUANT      : natural := 32;
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1;
+         CNTR_QUANT : natural := 32;
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST        : in  std_logic;
+         CLK        : in  std_logic;
+
+      --  Non Syncronized Parameters
+      rf_count     : out std_logic_vector( 32-1 downto 0); -- output
+         -- Iterators
+         REG_CNTRS_RD : in  std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
+         -- Func. Input parameters
+         IN_PORT_0 : in  std_logic_vector(63 downto 0); -- pixel
+         READ       : out std_logic_vector(N_INPORTS-1 downto 0);
+         EXIST      : in  std_logic_vector(N_INPORTS-1 downto 0);
+         --
+         STOP_RD    : in  std_logic;
+         STOP_WR    : in  std_logic;
+         ERROR      : out std_logic
+      );
+   end component;
+
+   component INTERNAL_PARAMETERS is 
+      generic (
+         PAR_BITWIDTH : natural:=1;
+         PAR_VECTOR   : t_par_vector;
+         N_PAR        : natural:=0;
+         START_IN_RUN  : boolean := FALSE
+      );
+      port (  
+         RST        : in  std_logic;
+         CLK        : in  std_logic;
+
+         HALT_RD    : out std_logic;
+         HALT_WR    : out std_logic;
+         SOF_RD     : in  std_logic;
+         SOF_WR     : in  std_logic;
+         LOAD_PARAM : out std_logic;
+
+         par_one_in_Rd    : out std_logic;
+         par_one_in_Din   : in std_logic_vector(32-1 downto 0);
+         par_one_in_Exist : in std_logic;
+         par_one_in_CLK   : out std_logic;
+         par_one_in_CTRL  : in std_logic;
+
+         PARAMETERS_RD : out std_logic_vector(32-1 downto 0);
+         PARAMETERS_WR : out std_logic_vector(32-1 downto 0)
+      );
+   end component;
+
+   --
+   -- ====================================
+   -- =       Signals declaration        =
+   -- ====================================
+   -- 
+   -- HW Node Input Ports
+   signal sl_IN_PORTS_0   : std_logic_vector(1*64-1 downto 0); -- pixel
+   signal sl_EXISTS       : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_READS        : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_CTRLS        : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_control_rd   : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_obtain_rd    : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_release_rd   : std_logic_vector(c_IN_PORTS-1 downto 0);
+   -- 
+   -- Func. Input parameters
+   signal sl_in_port_0    : std_logic_vector(63 downto 0); -- pixel
+   signal sl_exist        : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read         : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read_en      : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read_st      : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   -- 
+   signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
+   -- 
+   signal sl_halt             : std_logic;
+   signal sl_halted           : std_logic;
+   signal sl_halt_wr          : std_logic;
+   signal sl_halt_rd          : std_logic;
+   signal sl_param_halt_wr    : std_logic;
+   signal sl_param_halt_rd    : std_logic;
+   signal sl_done_wr          : std_logic;
+   signal sl_done_rd          : std_logic;
+   signal sl_stop_wr          : std_logic;
+   signal sl_stop_rd          : std_logic;
+   signal sl_fire_wr          : std_logic;
+   signal sl_fire_rd          : std_logic;
+   signal sl_sof_wr           : std_logic;
+   signal sl_sof_rd           : std_logic;
+   signal sl_error            : std_logic;
+   signal sl_load_param       : std_logic;
+
+   --  
+   -- Parameter related signals 
+   signal sl_param_fifo_full     : std_logic;
+   signal sl_sync_num            : std_logic_vector(9 downto 0);
+
+   signal sl_RST : std_logic;
+
+begin 
+
+   sl_RST <= RST when RESET_HIGH=1 else not RST;
+      ND_4IP_1_CLK   <= CLK;
+
+   --
+   -- ==========================================================
+   -- =       HWN Input related modules                        =
+   -- ==========================================================
+   -- Func. Input param. "pixel"
+   RD_MUX_0 : READ_MUX
+   generic map (
+      N_PORTS    => 1,
+      PORT_WIDTH => 64
+   )
+   port map (
+      IN_PORTS   => sl_IN_PORTS_0,
+      EXISTS     => sl_EXISTS(0 downto 0),
+      READS      => sl_READS(0 downto 0),
+      SOFS       => sl_CTRLS(0 downto 0),
+
+      OUT_PORT   => sl_in_port_0,
+      EXIST      => sl_exist(0),
+      READ       => sl_read(0),
+      SOF        => sl_sof_rd,
+      CLK        => CLK,
+
+      READ_EN    => sl_read_en(0),
+      READ_ST    => sl_read_st(0),
+      CONTROL    => sl_control_rd(0 downto 0),
+      OBTAIN     => sl_obtain_rd(0 downto 0),
+      RELEASE    => sl_release_rd(0 downto 0)
+   );
+
+   ND_4IP_1_Rd   <= sl_READS(0);
+
+   sl_IN_PORTS_0 <= ND_4IP_1_Din;
+
+   sl_EXISTS(0)   <= ND_4IP_1_Exist ;
+   sl_CTRLS(0)    <= ND_4IP_1_CTRL ;
+
+   EVAL_RD : bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_4
+   generic map ( 
+      N_IN_PORTS    => c_IN_PORTS,
+      WRAP          => c_WRAP,
+      N_CNTRS       => c_COUNTERS,
+      QUANT         => c_CNTR_QUANT,
+      PAR_BITWIDTH  => c_PAR_BITWIDTH,
+      CNTR_STEP     => c_CNTR_STEPS,
+      CNTR_WIDTH    => c_CNTR_WIDTHS
+   )
+   port map(
+      RST           => sl_RST,
+      CLK           => CLK,
+      REG_CNTRS     => sl_REG_CNTRS_RD,
+      READ_EN       => sl_read_en,
+      READ_ST       => sl_read_st,
+      HALT          => sl_halt_rd,
+      FIRE          => sl_fire_rd,
+      DONE          => sl_done_rd,
+      STOP          => sl_stop_rd,
+      CONTROL       => sl_control_rd,
+      OBTAIN        => sl_obtain_rd,
+      RELEASE       => sl_release_rd
+   );
+
+   --
+   -- ==========================================================
+   -- =       HWN Output related modules                       =
+   -- ==========================================================
+   -- A Sink HWN
+   sl_done_wr <= '1';
+   sl_stop_wr <= sl_halt_wr;
+   --
+   -- ==========================================================
+   -- =       HWN Execution Unit                               =
+   -- ==========================================================
+   EX : bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_4
+   generic map (
+      N_INPORTS  => c_IN_FUNC_VAR,
+      IP_RESET   => c_IP_RESET,
+      QUANT      => QUANT,
+      STIM_DIR   => STIM_DIR,
+      c_STAGES   => c_STAGES,
+      N_CNTRS    => c_COUNTERS,
+      CNTR_QUANT => c_CNTR_QUANT,
+      CNTR_WIDTH => c_CNTR_WIDTHS
+   )
+   port map (
+      RST        => sl_RST,
+      CLK        => CLK,
+      -- RegFile
+      rf_count     => rf_count,
+      -- Iterators
+      REG_CNTRS_RD => sl_REG_CNTRS_RD,
+      -- Func. Input parameters
+      IN_PORT_0    => sl_in_port_0,
+      READ       => sl_read,
+      EXIST      => sl_exist,
+      --
+      STOP_WR    => sl_stop_wr,
+      STOP_RD    => sl_stop_rd,
+      ERROR      => sl_error
+   );
+
+   -- ==========================================================
+   -- =       PARAMETERIZATION                                 =
+   -- ==========================================================
+   -- no parameters
+   sl_halt_rd <= '0';
+   sl_halt_wr <= '0';
+--   sl_halted  <= sl_sof_rd;
+   STOP <= sl_done_rd;
+   ERROR <= sl_error;
+   BLOCK_RD <= not (  (  sl_READS(0)  ) );
+
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_4/src/vhdl/bunny_static_split2rtl_hwn_nd_4_eval_logic_rd.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_4/src/vhdl/bunny_static_split2rtl_hwn_nd_4_eval_logic_rd.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..14814c747687acb44c8a7e307015a4768ee70180
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_4/src/vhdl/bunny_static_split2rtl_hwn_nd_4_eval_logic_rd.vhd
@@ -0,0 +1,283 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_4 is
+   generic (
+      N_IN_PORTS    : natural := 1;
+      WRAP          : boolean := true;
+      N_CNTRS       : natural := 1; 
+      QUANT         : natural := 32;
+      PAR_BITWIDTH  : natural  :=1;
+      CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+      CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST           : in  std_logic;
+      CLK           : in  std_logic;
+      REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+      READ_EN       : out std_logic_vector(0 downto 0);
+      READ_ST       : in  std_logic_vector(0 downto 0);
+      HALT          : in  std_logic;
+      FIRE          : out std_logic;
+      DONE          : out std_logic;
+      STOP          : out std_logic;
+      CONTROL       : out std_logic_vector(N_IN_PORTS-1 downto 0);
+      OBTAIN        : out std_logic_vector(N_IN_PORTS-1 downto 0);
+      RELEASE       : out std_logic_vector(N_IN_PORTS-1 downto 0)
+   );
+end bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_4;
+
+architecture RTL of bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_4 is
+   -- 
+   component counter is 
+      generic( 
+         C_STEP    : natural := 10; 
+         C_WIDTH   : natural := 10 
+      ); 
+      port ( 
+         RST       : in  std_logic; 
+         CLK       : in  std_logic; 
+         ENABLE    : in  std_logic; 
+         LOAD      : in  std_logic; 
+         LOWER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         UPPER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         ITERATOR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         REG_CNTR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         DONE      : out std_logic 
+      ); 
+   end component; 
+   -- 
+   component it_mod is 
+   generic( 
+      C_MOD     : natural := 10; 
+      C_WIDTH   : natural := 10; 
+      C_INIT    : natural :=  1; 
+      C_STEP    : natural :=  1  
+   ); 
+   port ( 
+      RST       : in  std_logic; 
+      CLK       : in  std_logic; 
+      LOAD      : in  std_logic; 
+      ENABLE    : in  std_logic; 
+      MODULE    : out std_logic_vector(C_WIDTH-1 downto 0) 
+   ); 
+   end component; 
+   -- 
+   --  
+   -- Parameter related signals 
+   -- 
+   -- Iterator (counter) related signals 
+   signal sl_low_i, sl_high_i : integer;
+   signal sl_loop_i, sl_loop_i_rg : integer;
+   signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   -- 
+   signal sl_cntr_en  : std_logic_vector(N_CNTRS   downto 0); 
+   signal sl_done     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_done_all : std_logic; 
+   signal sl_load     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_stop     : std_logic; 
+   signal sl_fire     : std_logic; 
+   signal sl_sof      : std_logic; 
+   signal sl_eof      : std_logic; 
+   signal sl_count    : std_logic; 
+
+   -- alias signals 
+   alias update_i : std_logic is sl_cntr_en(0);
+   alias load_i : std_logic is sl_load(0);
+
+   -- Trigger signals 
+   signal sl_trigger_i : std_logic;
+
+   -- Special Control signal
+   signal sl_CONTROL       : std_logic_vector(N_IN_PORTS-1 downto 0);
+   signal sl_no_request    : std_logic;
+   -- 
+   -- Multirate related signals
+   signal sl_bla_en   : std_logic_vector(0 downto 0); 
+   signal sl_mr_en    : std_logic_vector(0 downto 0); 
+   signal sl_mr_done  : std_logic_vector(0 downto 0); 
+   signal sl_mr_lock  : std_logic_vector(0 downto 0); 
+   signal sl_enables  : std_logic_vector(0 downto 0); 
+   signal sl_enable   : std_logic; 
+   signal ENABLE      : std_logic; 
+   -- Function input parameter "in_0", multirate=1 
+   constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+
+
+   signal sl_obtain0  : std_logic;
+   signal sl_release0 : std_logic;
+
+   -- define control variables 
+
+   type state_type is (s_idle, s_halt, s_count, s_release);
+   signal state : state_type;
+   signal halt_cnt : integer;
+   signal sl_halt : std_logic;
+
+   signal sl_cnt_rst : std_logic;
+   signal cnt_rst : std_logic;
+
+begin
+
+   -- =============================================
+   -- =             MOD Functions                  
+   -- =============================================
+   -- END of MOD definitions 
+   -- =============================================
+   -- =             Parameter Functions            
+   -- =============================================
+   sl_cnt_rst <= '0';
+   sl_halt <= HALT;
+
+   -- END of Parameter definitions 
+   sl_loop_i    <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+   sl_loop_i_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+   -- Const bounds for-loops 
+   sl_low_i  <= 0;
+   sl_high_i <= 0;
+
+
+   load_i <= '0';
+
+   sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
+
+   sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
+   -- Special definitions 
+
+   -- Entity and control variables
+   -- Release matrix expressions
+
+   sl_fire <= ('1');
+
+   -- Convert FIFO Read Port ND_4IP_1 Argument in_1 : ED_1 : 0 of type IOMM
+   sl_obtain0 <= ('1');  -- set obtain/release to const value; not used
+   sl_release0 <= ('1');
+
+   sl_CONTROL(0) <= sl_fire and ('1');
+   OBTAIN(0) <= sl_obtain0;
+   RELEASE(0) <= sl_release0;
+
+   FIRE <= sl_fire;
+
+   cnt_rst <= sl_cnt_rst or RST;
+
+   -- 
+   -- =============================================
+   -- =             Multirate                      
+   -- =============================================
+   -- Function input parameter "in_0", multirate=1 
+   CNTR_MR0 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(0),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_0,
+         UPPER_BND => sl_mr_ubnd_0,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(0)
+      );
+   -- READ_EN indicates if READ_MUX can read data
+   sl_bla_en   <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');  
+   READ_EN     <= (others=>'0') when (HALT='1') else sl_bla_en;  
+   sl_mr_en   <= READ_ST; 
+   sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en); 
+   sl_enable  <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce 
+   ENABLE     <=  sl_enable or (not sl_fire);
+   -- 
+   LOCK_PRCS: process(CLK) 
+   begin 
+       if rising_edge(CLK) then 
+           if( RST = '1' ) then 
+               sl_mr_lock <= (others=>'0'); 
+           else  
+               if (ENABLE='1') then 
+                   sl_mr_lock <= (others=>'0'); 
+               else 
+                   for i in 0 to 0 loop 
+                       if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then 
+                           sl_mr_lock(i) <= '1'; 
+                       end if; 
+                   end loop; 
+               end if; 
+           end if; 
+       end if; 
+   end process; 
+   -- END of Multirate definitions 
+   -- 
+   -- =============================================
+   -- =             Iterators                      
+   -- =============================================
+   GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
+   	CNTR_RD : counter
+   	generic map ( 
+   		C_STEP    => CNTR_STEP(i),
+   		C_WIDTH   => CNTR_WIDTH(i)
+   	)
+  	 port map (
+   		CLK       => CLK,
+   		RST       => cnt_rst,
+   		ENABLE    => sl_cntr_en(i),
+			LOAD      => sl_load(i),
+   		LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		ITERATOR  => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		REG_CNTR  => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		DONE      => sl_done(i)
+   	);
+   end generate;
+   --
+   DONE_PRCS: process(CLK)
+   begin
+   	if rising_edge(CLK) then
+          if( RST = '1' ) then
+   		    sl_stop     <= '0';
+   		    sl_done_all <= '0';
+   		    sl_sof      <= '1';
+   	    else 
+   		    if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+   			    sl_stop <= '1';
+   		    elsif (WRAP=true) then
+   			    sl_stop <= '0';
+   		    end if;
+   		    if (sl_stop='0') then
+   			    sl_done_all <= sl_cntr_en(N_CNTRS);
+   		    end if;
+   		    if (ENABLE='1') then
+   			    sl_sof <= sl_eof;
+   		    end if;
+   	    end if;
+   	end if;
+   end process;
+   --
+   sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+   CONTROL <= sl_CONTROL;
+   --
+   REG_CNTRS <= sl_reg_cntrs; 
+   DONE <= sl_done_all;     -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+   STOP <= sl_stop;         -- '1' = The couter stoped after the end of the itteration space. 
+   --
+   sl_count      <=  '0' when (sl_stop='1') else
+                     '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
+   sl_cntr_en(0) <=  sl_count; -- makes the EVAL_LOGIC count
+   --
+   sl_cntr_en(N_CNTRS  downto 1) <= sl_cntr_en(N_CNTRS-1  downto 0) and sl_done(N_CNTRS-1  downto 0);
+   sl_eof <= sl_cntr_en(N_CNTRS);   -- End-of-frame
+   --
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_4/src/vhdl/bunny_static_split2rtl_hwn_nd_4_execution_unit.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_4/src/vhdl/bunny_static_split2rtl_hwn_nd_4_execution_unit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b2f61d39d922a9f1998663b8e051e80c9bdfc5d9
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_4/src/vhdl/bunny_static_split2rtl_hwn_nd_4_execution_unit.vhd
@@ -0,0 +1,104 @@
+-- Execute Unit automatically generated by KpnMapper
+-- Function "increaseFrameCount"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_bunny_static_split2rtl_functions_1_lib;
+use compaandesign_com_bunny_static_split2rtl_functions_1_lib.all;
+
+entity bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_4 is
+   generic (
+      N_INPORTS  : natural := 1;
+      IP_RESET   : natural := 1; 
+      STIM_DIR   : string  := "bla";
+      QUANT      : natural := 32;
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1; 
+      CNTR_QUANT : natural := 32; 
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+   );
+   port (
+      RST        : in  std_logic;
+      CLK        : in  std_logic;
+      --  Non Syncronized Parameters
+      rf_count     : out std_logic_vector( 32-1 downto 0); -- output
+      -- Funtion Input parameters
+      IN_PORT_0    : in  std_logic_vector(63 downto 0);  -- Param. "pixel"
+      READ       : out std_logic_vector(N_INPORTS-1 downto 0);
+      EXIST      : in  std_logic_vector(N_INPORTS-1 downto 0);
+      -- Iterators
+      REG_CNTRS_RD : in  std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
+      STOP_RD    : in  std_logic;
+      STOP_WR    : in  std_logic;
+      ERROR      : out std_logic
+   );
+end bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_4 ;
+
+-- Laura implementation
+architecture Laura of bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_4 is
+
+   component increaseFrameCount is
+      generic (
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1; 
+         CNTR_QUANT : natural := 32; 
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST   : in std_logic;
+         CLK   : in std_logic;
+      -- Non Syncronized Parameters
+      rf_count     : out  std_logic_vector( 32-1 downto 0); -- output
+         -- Inputs 
+         ip_pixel  : in  std_logic_vector(63 downto 0);  
+         -- Iterators 
+         it_i : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+         EXIST : in  std_logic_vector(0 downto 0);
+         READF : out std_logic_vector(0 downto 0);
+         -- Outputs 
+         --
+         STOP_RD : in  std_logic;
+         STOP_WR : in  std_logic;
+         ERROR   : out std_logic
+      );
+   end component;
+
+   signal sl_RST : std_logic;
+
+begin
+
+   sl_RST <= RST when IP_RESET=1 else not RST;
+
+   FUNC : increaseFrameCount
+   generic map (
+         STIM_DIR      => STIM_DIR,
+         c_STAGES      => c_STAGES,
+         N_CNTRS       => N_CNTRS,
+         CNTR_QUANT    => CNTR_QUANT,
+         CNTR_WIDTH    => CNTR_WIDTH
+   )
+   port map (
+      RST   => sl_RST,
+      CLK   => CLK,
+      --  Non Syncronized Parameters
+      rf_count     => rf_count,
+      -- Inputs 
+      ip_pixel => IN_PORT_0,
+      -- Iterators 
+      it_i => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
+      EXIST => EXIST,
+      READF => READ,
+      -- Outputs 
+      -- 
+      STOP_RD => STOP_RD,
+      STOP_WR => STOP_WR,
+      ERROR   => ERROR
+   );
+
+end Laura;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_5/hdllib.cfg b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_5/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..a206f7e5ac25cacb30f832dfdd14d4afca12a688
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_5/hdllib.cfg
@@ -0,0 +1,18 @@
+hdl_lib_name = compaandesign_com_bunny_static_split2rtl_hwn_nd_5_1
+hdl_library_clause_name = compaandesign_com_bunny_static_split2rtl_hwn_nd_5_1_lib
+hdl_lib_uses_synth = compaandesign_com_bunny_static_split2rtl_functions_1 compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1 compaandesign_com_common_extern_connector_1 
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+	src/vhdl/bunny_static_split2rtl_hwn_nd_5_execution_unit.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_5_eval_logic_rd.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_5_eval_logic_wr.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_5.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_5/src/vhdl/bunny_static_split2rtl_hwn_nd_5.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_5/src/vhdl/bunny_static_split2rtl_hwn_nd_5.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2906be2b7319cad3a8ed2c35fe2559c78afc14b4
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_5/src/vhdl/bunny_static_split2rtl_hwn_nd_5.vhd
@@ -0,0 +1,496 @@
+-- HWN Entity File automatically generated by KpnMapper (writeHdlHWNodeFile)
+-- Top level file for a Hardware Accelerator
+-- Function "split64to2t32"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+library compaandesign_com_common_extern_connector_1_lib;
+use compaandesign_com_common_extern_connector_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_5 is
+   generic (
+      STIM_DIR   : string  := "bla";
+      RESET_HIGH : natural := 1;
+      PAR_WIDTH  : natural := 16;
+      QUANT      : natural := 32;
+      WRAP       : boolean := true
+   );
+   port (
+
+      -- Dataflow input interfaces
+      -- ED_2 : in_0
+      ND_5IP_2_Rd    : out std_logic;
+      ND_5IP_2_Din   : in  std_logic_vector(63 downto 0);
+      ND_5IP_2_Exist : in  std_logic; 
+      ND_5IP_2_CLK   : out std_logic;
+      ND_5IP_2_CTRL  : in  std_logic;
+
+      -- Dataflow Control Input interfaces
+      -- Dataflow output interfaces
+      -- ED_3 : out_0
+      ND_5OP_1_Wr   : out std_logic;
+      ND_5OP_1_Dout : out std_logic_vector(31 downto 0);
+      ND_5OP_1_Full : in  std_logic;
+      ND_5OP_1_CLK  : out std_logic;
+      ND_5OP_1_CTRL : out std_logic;
+
+      -- ED_4_5 : out_1
+      ND_5OP_2_d1_ND_5OP_2_Wr   : out std_logic;
+      ND_5OP_2_d1_ND_5OP_2_Dout : out std_logic_vector(31 downto 0);
+      ND_5OP_2_d1_ND_5OP_2_Full : in  std_logic;
+      ND_5OP_2_d1_ND_5OP_2_CLK  : out std_logic;
+      ND_5OP_2_d1_ND_5OP_2_CTRL : out std_logic;
+
+      PARAM_DT : in  std_logic_vector(PAR_WIDTH+10-1 downto 0);
+      PARAM_LD : in  std_logic;
+
+      RST      : in  std_logic;
+      CLK      : in  std_logic;
+      STOP     : out std_logic;
+      ERROR    : out std_logic;
+      BLOCK_RD : out std_logic
+   );
+end bunny_static_split2rtl_hwn_nd_5;
+
+architecture RTL of bunny_static_split2rtl_hwn_nd_5 is
+   --
+   -- ====================================
+   -- =     Constants declaration        =
+   -- ====================================
+   -- Setting the parameters of the HW Node
+   constant c_IN_PORTS     : natural := 1; -- number of input ports of a HW node
+   constant c_OUT_PORTS    : natural := 2; -- number of output ports of a HW node
+   constant c_IN_FUNC_VAR  : natural := 1; -- number of input ports of a HW IP
+   constant c_OUT_FUNC_VAR : natural := 2; -- number of output ports of a HW IP
+   constant c_COUNTERS     : natural := 2; -- number of iterators
+   -- ===========================================
+   -- = Iterators run from Inner to Outer loop  =
+   -- ===========================================
+   constant c_CNTR_QUANT   : natural := 10;
+   constant c_CNTR_STEPS   : t_counter_step  := ( 0=>1, 1=>1, others=>1 );
+   constant c_CNTR_WIDTHS  : t_counter_width := ( 0=>10, 1=>10, others=>10 );
+   constant c_STAGES       : natural := 1; -- number of pipeline stages or delay
+   constant c_IP_RESET     : natural := 1; -- active level of the HW IP reset signal
+   constant c_WRAP         : boolean := WRAP; -- Operation mode: Single_Shot (false) or Continuous (true)
+   constant c_EXT_PAR      : natural := 0; -- number of external parameters
+   constant c_INT_PAR      : natural := 0; -- number of internal parameters
+   constant c_N_PAR        : natural := 0; -- no parameters are used
+   constant c_PAR_BITWIDTH : natural := PAR_WIDTH; -- aggregate bitwidth of the parameter vector
+   constant c_PAR_VECTOR   : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
+       (0,0,0,0), (0,0,0,0)    -- two dummy elements
+   );
+   --
+   -- ====================================
+   -- =     Components declaration       =
+   -- ====================================
+   component bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_5 is
+      generic (
+         N_IN_PORTS    : natural := 1;
+         WRAP          : boolean := true;
+         N_CNTRS       : natural := 1; 
+         QUANT         : natural := 32;
+         PAR_BITWIDTH  : natural :=1;
+         CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+         CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+      );
+      port (
+         RST           : in  std_logic;
+         CLK           : in  std_logic;
+         REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1  downto 0); 
+         READ_EN       : out std_logic_vector(c_IN_FUNC_VAR-1  downto 0);
+         READ_ST       : in  std_logic_vector(c_IN_FUNC_VAR-1  downto 0);
+         HALT          : in  std_logic;
+         FIRE          : out std_logic;
+         DONE          : out std_logic;
+         STOP          : out std_logic;
+         CONTROL       : out std_logic_vector(N_IN_PORTS-1 downto 0);
+         OBTAIN        : out std_logic_vector(N_IN_PORTS-1 downto 0);
+         RELEASE       : out std_logic_vector(N_IN_PORTS-1 downto 0)
+      );
+   end component;
+
+   component READ_MUX is
+      generic (
+         N_PORTS    : natural := 1;
+         PORT_WIDTH : natural := 32  
+      );
+      port(
+         IN_PORTS   : in  std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
+         EXISTS     : in  std_logic_vector(N_PORTS-1 downto 0);
+         READS      : out std_logic_vector(N_PORTS-1 downto 0);
+         SOFS       : in  std_logic_vector(N_PORTS-1 downto 0);
+
+         OUT_PORT   : out std_logic_vector(PORT_WIDTH-1 downto 0);
+         EXIST      : out std_logic;
+         READ       : in  std_logic;
+         SOF        : in  std_logic;
+		CLK        : in std_logic;
+
+         READ_EN    : in  std_logic;
+         READ_ST    : out std_logic;
+         CONTROL    : in  std_logic_vector(N_PORTS-1 downto 0);
+         OBTAIN     : in  std_logic_vector(N_PORTS-1 downto 0);
+         RELEASE    : in  std_logic_vector(N_PORTS-1 downto 0)
+      );
+   end component;
+
+   component bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_5 is
+      generic ( 
+         N_OUT_PORTS   : natural := 1;
+         WRAP          : boolean := true;
+         N_CNTRS       : natural := 1; 
+         QUANT         : natural := 32;
+         PAR_BITWIDTH  : natural :=1;
+         CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+         CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+      );
+      port (
+         RST           : in  std_logic;
+         CLK           : in  std_logic;
+         WRITE_EN      : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+         WRITE_ST      : in  std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+         HALT          : in  std_logic;
+         FIRE          : out std_logic;
+         DONE          : out std_logic;
+         STOP          : out std_logic;
+         CONTROL       : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+      );
+   end component;
+
+   component WRITE_DEMUX is
+      generic (
+         N_PORTS : natural := 1
+      );
+      port(
+         WRITES   : out std_logic_vector(N_PORTS-1 downto 0);
+         WRITE    : in  std_logic;
+
+         FULLS    : in  std_logic_vector(N_PORTS-1 downto 0);
+         FULL     : out std_logic;
+
+         WRITE_EN : in  std_logic;
+         WRITE_ST : out std_logic;
+         CONTROL  : in  std_logic_vector(N_PORTS-1 downto 0)
+      );
+   end component;
+
+
+   component bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_5 is
+      generic (
+         N_INPORTS  : natural := 1;
+         N_OUTPORTS : natural := 1;
+         IP_RESET   : natural := 1;
+         QUANT      : natural := 32;
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1;
+         CNTR_QUANT : natural := 32;
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST        : in  std_logic;
+         CLK        : in  std_logic;
+
+         -- Iterators
+         REG_CNTRS_RD : in  std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
+         -- Func. Input parameters
+         IN_PORT_0 : in  std_logic_vector(63 downto 0); -- stimin
+         READ       : out std_logic_vector(N_INPORTS-1 downto 0);
+         EXIST      : in  std_logic_vector(N_INPORTS-1 downto 0);
+         -- Func. Output parameters
+         OUT_PORT_0 : out std_logic_vector(31 downto 0); -- out0
+         OUT_PORT_1 : out std_logic_vector(31 downto 0); -- out1
+         WRITE      : out std_logic_vector(N_OUTPORTS-1 downto 0);
+         FULL       : in  std_logic_vector(N_OUTPORTS-1 downto 0);
+         --
+         STOP_RD    : in  std_logic;
+         STOP_WR    : in  std_logic;
+         ERROR      : out std_logic
+      );
+   end component;
+
+   component INTERNAL_PARAMETERS is 
+      generic (
+         PAR_BITWIDTH : natural:=1;
+         PAR_VECTOR   : t_par_vector;
+         N_PAR        : natural:=0;
+         START_IN_RUN  : boolean := FALSE
+      );
+      port (  
+         RST        : in  std_logic;
+         CLK        : in  std_logic;
+
+         HALT_RD    : out std_logic;
+         HALT_WR    : out std_logic;
+         SOF_RD     : in  std_logic;
+         SOF_WR     : in  std_logic;
+         LOAD_PARAM : out std_logic;
+
+         par_one_in_Rd    : out std_logic;
+         par_one_in_Din   : in std_logic_vector(32-1 downto 0);
+         par_one_in_Exist : in std_logic;
+         par_one_in_CLK   : out std_logic;
+         par_one_in_CTRL  : in std_logic;
+
+         PARAMETERS_RD : out std_logic_vector(32-1 downto 0);
+         PARAMETERS_WR : out std_logic_vector(32-1 downto 0)
+      );
+   end component;
+
+   --
+   -- ====================================
+   -- =       Signals declaration        =
+   -- ====================================
+   -- 
+   -- HW Node Input Ports
+   signal sl_IN_PORTS_0   : std_logic_vector(1*64-1 downto 0); -- stimin
+   signal sl_EXISTS       : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_READS        : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_CTRLS        : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_control_rd   : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_obtain_rd    : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_release_rd   : std_logic_vector(c_IN_PORTS-1 downto 0);
+   -- 
+   -- Func. Input parameters
+   signal sl_in_port_0    : std_logic_vector(63 downto 0); -- stimin
+   signal sl_exist        : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read         : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read_en      : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read_st      : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   -- 
+   signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
+   -- 
+   -- HW Node Output Ports
+   signal sl_WRITES       : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_FULLS        : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_control_wr   : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_lortnoc_wr   : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   -- 
+   -- Func. Output parameters
+   signal sl_out_port_0   : std_logic_vector(31 downto 0); -- out0
+   signal sl_out_port_1   : std_logic_vector(31 downto 0); -- out1
+   signal sl_full         : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write        : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write_en     : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write_st     : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   -- 
+   -- 
+   signal sl_halt             : std_logic;
+   signal sl_halted           : std_logic;
+   signal sl_halt_wr          : std_logic;
+   signal sl_halt_rd          : std_logic;
+   signal sl_param_halt_wr    : std_logic;
+   signal sl_param_halt_rd    : std_logic;
+   signal sl_done_wr          : std_logic;
+   signal sl_done_rd          : std_logic;
+   signal sl_stop_wr          : std_logic;
+   signal sl_stop_rd          : std_logic;
+   signal sl_fire_wr          : std_logic;
+   signal sl_fire_rd          : std_logic;
+   signal sl_sof_wr           : std_logic;
+   signal sl_sof_rd           : std_logic;
+   signal sl_error            : std_logic;
+   signal sl_load_param       : std_logic;
+
+   --  
+   -- Parameter related signals 
+   signal sl_param_fifo_full     : std_logic;
+   signal sl_sync_num            : std_logic_vector(9 downto 0);
+
+   signal sl_RST : std_logic;
+
+begin 
+
+   sl_RST <= RST when RESET_HIGH=1 else not RST;
+      ND_5IP_2_CLK   <= CLK;
+      ND_5OP_1_CLK  <= CLK;
+      ND_5OP_2_d1_ND_5OP_2_CLK  <= CLK;
+
+   --
+   -- ==========================================================
+   -- =       HWN Input related modules                        =
+   -- ==========================================================
+   -- Func. Input param. "stimin"
+   RD_MUX_0 : READ_MUX
+   generic map (
+      N_PORTS    => 1,
+      PORT_WIDTH => 64
+   )
+   port map (
+      IN_PORTS   => sl_IN_PORTS_0,
+      EXISTS     => sl_EXISTS(0 downto 0),
+      READS      => sl_READS(0 downto 0),
+      SOFS       => sl_CTRLS(0 downto 0),
+
+      OUT_PORT   => sl_in_port_0,
+      EXIST      => sl_exist(0),
+      READ       => sl_read(0),
+      SOF        => sl_sof_rd,
+      CLK        => CLK,
+
+      READ_EN    => sl_read_en(0),
+      READ_ST    => sl_read_st(0),
+      CONTROL    => sl_control_rd(0 downto 0),
+      OBTAIN     => sl_obtain_rd(0 downto 0),
+      RELEASE    => sl_release_rd(0 downto 0)
+   );
+
+   ND_5IP_2_Rd   <= sl_READS(0);
+
+   sl_IN_PORTS_0 <= ND_5IP_2_Din;
+
+   sl_EXISTS(0)   <= ND_5IP_2_Exist ;
+   sl_CTRLS(0)    <= ND_5IP_2_CTRL ;
+
+   EVAL_RD : bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_5
+   generic map ( 
+      N_IN_PORTS    => c_IN_PORTS,
+      WRAP          => c_WRAP,
+      N_CNTRS       => c_COUNTERS,
+      QUANT         => c_CNTR_QUANT,
+      PAR_BITWIDTH  => c_PAR_BITWIDTH,
+      CNTR_STEP     => c_CNTR_STEPS,
+      CNTR_WIDTH    => c_CNTR_WIDTHS
+   )
+   port map(
+      RST           => sl_RST,
+      CLK           => CLK,
+      REG_CNTRS     => sl_REG_CNTRS_RD,
+      READ_EN       => sl_read_en,
+      READ_ST       => sl_read_st,
+      HALT          => sl_halt_rd,
+      FIRE          => sl_fire_rd,
+      DONE          => sl_done_rd,
+      STOP          => sl_stop_rd,
+      CONTROL       => sl_control_rd,
+      OBTAIN        => sl_obtain_rd,
+      RELEASE       => sl_release_rd
+   );
+
+   --
+   -- ==========================================================
+   -- =       HWN Output related modules                       =
+   -- ==========================================================
+   -- 
+   -- Func. Output param. "out0"
+   DEMUX_0 : WRITE_DEMUX
+   generic map (
+      N_PORTS => 1
+   )
+   port map (
+      WRITES   => sl_WRITES(0 downto 0),
+      FULLS    => sl_FULLS(0 downto 0),
+      CONTROL  => sl_lortnoc_wr(0 downto 0),
+      WRITE    => sl_write(0),
+      FULL     => sl_full(0),
+      WRITE_EN => sl_write_en(0),
+      WRITE_ST => sl_write_st(0)
+   );
+   --
+   ND_5OP_1_Dout <= sl_out_port_0;  -- Func. Output param. "out0"
+   ND_5OP_1_CTRL <= sl_sof_wr ;
+   ND_5OP_1_Wr   <= sl_WRITES(0);
+   sl_FULLS(0) <= ND_5OP_1_Full;
+   sl_lortnoc_wr(0) <= sl_control_wr(0);
+   --
+   -- 
+   -- Func. Output param. "out1"
+   DEMUX_1 : WRITE_DEMUX
+   generic map (
+      N_PORTS => 1
+   )
+   port map (
+      WRITES   => sl_WRITES(1 downto 1),
+      FULLS    => sl_FULLS(1 downto 1),
+      CONTROL  => sl_lortnoc_wr(1 downto 1),
+      WRITE    => sl_write(1),
+      FULL     => sl_full(1),
+      WRITE_EN => sl_write_en(1),
+      WRITE_ST => sl_write_st(1)
+   );
+   --
+   ND_5OP_2_d1_ND_5OP_2_Dout <= sl_out_port_1;  -- Func. Output param. "out1"
+   ND_5OP_2_d1_ND_5OP_2_CTRL <= sl_sof_wr ;
+   ND_5OP_2_d1_ND_5OP_2_Wr   <= sl_WRITES(1);
+   sl_FULLS(1) <= ND_5OP_2_d1_ND_5OP_2_Full;
+   sl_lortnoc_wr(1) <= sl_control_wr(1);
+   --
+   --
+   EVAL_WR : bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_5
+   generic map ( 
+      N_OUT_PORTS   => c_OUT_PORTS,
+      WRAP          => c_WRAP,
+      N_CNTRS       => c_COUNTERS,
+      QUANT         => c_CNTR_QUANT,
+      PAR_BITWIDTH  => c_PAR_BITWIDTH,
+      CNTR_STEP     => c_CNTR_STEPS,
+      CNTR_WIDTH    => c_CNTR_WIDTHS
+   )
+   port map (
+      RST           => sl_RST,
+      CLK           => CLK,
+      WRITE_EN      => sl_write_en,
+      WRITE_ST      => sl_write_st,
+      HALT          => sl_halt_wr,
+      FIRE          => sl_fire_wr,
+      DONE          => sl_done_wr,
+      STOP          => sl_stop_wr,
+      CONTROL       => sl_control_wr
+   );
+
+   --
+   -- ==========================================================
+   -- =       HWN Execution Unit                               =
+   -- ==========================================================
+   EX : bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_5
+   generic map (
+      N_INPORTS  => c_IN_FUNC_VAR,
+      N_OUTPORTS => c_OUT_FUNC_VAR, 
+      IP_RESET   => c_IP_RESET,
+      QUANT      => QUANT,
+      STIM_DIR   => STIM_DIR,
+      c_STAGES   => c_STAGES,
+      N_CNTRS    => c_COUNTERS,
+      CNTR_QUANT => c_CNTR_QUANT,
+      CNTR_WIDTH => c_CNTR_WIDTHS
+   )
+   port map (
+      RST        => sl_RST,
+      CLK        => CLK,
+      -- Iterators
+      REG_CNTRS_RD => sl_REG_CNTRS_RD,
+      -- Func. Input parameters
+      IN_PORT_0    => sl_in_port_0,
+      READ       => sl_read,
+      EXIST      => sl_exist,
+      -- Func. Output parameters
+      OUT_PORT_0   => sl_out_port_0,
+      OUT_PORT_1   => sl_out_port_1,
+      WRITE      => sl_write,
+      FULL       => sl_full,
+      --
+      STOP_WR    => sl_stop_wr,
+      STOP_RD    => sl_stop_rd,
+      ERROR      => sl_error
+   );
+
+   -- ==========================================================
+   -- =       PARAMETERIZATION                                 =
+   -- ==========================================================
+   -- no parameters
+   sl_halt_rd <= '0';
+   sl_halt_wr <= '0';
+--   sl_halted  <= sl_sof_rd;
+   STOP <= sl_done_wr;
+   ERROR <= sl_error;
+   BLOCK_RD <= not (  (  sl_READS(0)  ) );
+
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_5/src/vhdl/bunny_static_split2rtl_hwn_nd_5_eval_logic_rd.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_5/src/vhdl/bunny_static_split2rtl_hwn_nd_5_eval_logic_rd.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..42aacbd190cce5c6ebe0fa8c80f92147d6647260
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_5/src/vhdl/bunny_static_split2rtl_hwn_nd_5_eval_logic_rd.vhd
@@ -0,0 +1,295 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_5 is
+   generic (
+      N_IN_PORTS    : natural := 1;
+      WRAP          : boolean := true;
+      N_CNTRS       : natural := 1; 
+      QUANT         : natural := 32;
+      PAR_BITWIDTH  : natural  :=1;
+      CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+      CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST           : in  std_logic;
+      CLK           : in  std_logic;
+      REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+      READ_EN       : out std_logic_vector(0 downto 0);
+      READ_ST       : in  std_logic_vector(0 downto 0);
+      HALT          : in  std_logic;
+      FIRE          : out std_logic;
+      DONE          : out std_logic;
+      STOP          : out std_logic;
+      CONTROL       : out std_logic_vector(N_IN_PORTS-1 downto 0);
+      OBTAIN        : out std_logic_vector(N_IN_PORTS-1 downto 0);
+      RELEASE       : out std_logic_vector(N_IN_PORTS-1 downto 0)
+   );
+end bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_5;
+
+architecture RTL of bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_5 is
+   -- 
+   component counter is 
+      generic( 
+         C_STEP    : natural := 10; 
+         C_WIDTH   : natural := 10 
+      ); 
+      port ( 
+         RST       : in  std_logic; 
+         CLK       : in  std_logic; 
+         ENABLE    : in  std_logic; 
+         LOAD      : in  std_logic; 
+         LOWER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         UPPER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         ITERATOR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         REG_CNTR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         DONE      : out std_logic 
+      ); 
+   end component; 
+   -- 
+   component it_mod is 
+   generic( 
+      C_MOD     : natural := 10; 
+      C_WIDTH   : natural := 10; 
+      C_INIT    : natural :=  1; 
+      C_STEP    : natural :=  1  
+   ); 
+   port ( 
+      RST       : in  std_logic; 
+      CLK       : in  std_logic; 
+      LOAD      : in  std_logic; 
+      ENABLE    : in  std_logic; 
+      MODULE    : out std_logic_vector(C_WIDTH-1 downto 0) 
+   ); 
+   end component; 
+   -- 
+   --  
+   -- Parameter related signals 
+   -- 
+   -- Iterator (counter) related signals 
+   signal sl_low_i, sl_high_i : integer;
+   signal sl_low_j, sl_high_j : integer;
+   signal sl_loop_i, sl_loop_i_rg : integer;
+   signal sl_loop_j, sl_loop_j_rg : integer;
+   signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   -- 
+   signal sl_cntr_en  : std_logic_vector(N_CNTRS   downto 0); 
+   signal sl_done     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_done_all : std_logic; 
+   signal sl_load     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_stop     : std_logic; 
+   signal sl_fire     : std_logic; 
+   signal sl_sof      : std_logic; 
+   signal sl_eof      : std_logic; 
+   signal sl_count    : std_logic; 
+
+   -- alias signals 
+   alias update_i : std_logic is sl_cntr_en(1);
+   alias update_j : std_logic is sl_cntr_en(0);
+   alias load_i : std_logic is sl_load(1);
+   alias load_j : std_logic is sl_load(0);
+
+   -- Trigger signals 
+   signal sl_trigger_i : std_logic;
+   signal sl_trigger_j : std_logic;
+
+   -- Special Control signal
+   signal sl_CONTROL       : std_logic_vector(N_IN_PORTS-1 downto 0);
+   signal sl_no_request    : std_logic;
+   -- 
+   -- Multirate related signals
+   signal sl_bla_en   : std_logic_vector(0 downto 0); 
+   signal sl_mr_en    : std_logic_vector(0 downto 0); 
+   signal sl_mr_done  : std_logic_vector(0 downto 0); 
+   signal sl_mr_lock  : std_logic_vector(0 downto 0); 
+   signal sl_enables  : std_logic_vector(0 downto 0); 
+   signal sl_enable   : std_logic; 
+   signal ENABLE      : std_logic; 
+   -- Function input parameter "in_0", multirate=1 
+   constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+
+
+   signal sl_obtain0  : std_logic;
+   signal sl_release0 : std_logic;
+
+   -- define control variables 
+
+   type state_type is (s_idle, s_halt, s_count, s_release);
+   signal state : state_type;
+   signal halt_cnt : integer;
+   signal sl_halt : std_logic;
+
+   signal sl_cnt_rst : std_logic;
+   signal cnt_rst : std_logic;
+
+begin
+
+   -- =============================================
+   -- =             MOD Functions                  
+   -- =============================================
+   -- END of MOD definitions 
+   -- =============================================
+   -- =             Parameter Functions            
+   -- =============================================
+   sl_cnt_rst <= '0';
+   sl_halt <= HALT;
+
+   -- END of Parameter definitions 
+   sl_loop_i    <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_i_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_j    <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+   sl_loop_j_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+   -- Const bounds for-loops 
+   sl_low_i  <= 0;
+   sl_high_i <= 359;
+   sl_low_j  <= 0;
+   sl_high_j <= 319;
+
+
+   load_i <= '0';
+   load_j <= '0';
+
+   sl_lower_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
+   sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
+
+   sl_upper_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
+   sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
+   -- Special definitions 
+
+   -- Entity and control variables
+   -- Release matrix expressions
+
+   sl_fire <= ('1');
+
+   -- Convert FIFO Read Port ND_5IP_2 Argument in_1 : ED_2 : 0 of type IOMM
+   sl_obtain0 <= ('1');  -- set obtain/release to const value; not used
+   sl_release0 <= ('1');
+
+   sl_CONTROL(0) <= sl_fire and ('1');
+   OBTAIN(0) <= sl_obtain0;
+   RELEASE(0) <= sl_release0;
+
+   FIRE <= sl_fire;
+
+   cnt_rst <= sl_cnt_rst or RST;
+
+   -- 
+   -- =============================================
+   -- =             Multirate                      
+   -- =============================================
+   -- Function input parameter "in_0", multirate=1 
+   CNTR_MR0 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(0),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_0,
+         UPPER_BND => sl_mr_ubnd_0,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(0)
+      );
+   -- READ_EN indicates if READ_MUX can read data
+   sl_bla_en   <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');  
+   READ_EN     <= (others=>'0') when (HALT='1') else sl_bla_en;  
+   sl_mr_en   <= READ_ST; 
+   sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en); 
+   sl_enable  <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce 
+   ENABLE     <=  sl_enable or (not sl_fire);
+   -- 
+   LOCK_PRCS: process(CLK) 
+   begin 
+       if rising_edge(CLK) then 
+           if( RST = '1' ) then 
+               sl_mr_lock <= (others=>'0'); 
+           else  
+               if (ENABLE='1') then 
+                   sl_mr_lock <= (others=>'0'); 
+               else 
+                   for i in 0 to 0 loop 
+                       if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then 
+                           sl_mr_lock(i) <= '1'; 
+                       end if; 
+                   end loop; 
+               end if; 
+           end if; 
+       end if; 
+   end process; 
+   -- END of Multirate definitions 
+   -- 
+   -- =============================================
+   -- =             Iterators                      
+   -- =============================================
+   GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
+   	CNTR_RD : counter
+   	generic map ( 
+   		C_STEP    => CNTR_STEP(i),
+   		C_WIDTH   => CNTR_WIDTH(i)
+   	)
+  	 port map (
+   		CLK       => CLK,
+   		RST       => cnt_rst,
+   		ENABLE    => sl_cntr_en(i),
+			LOAD      => sl_load(i),
+   		LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		ITERATOR  => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		REG_CNTR  => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		DONE      => sl_done(i)
+   	);
+   end generate;
+   --
+   DONE_PRCS: process(CLK)
+   begin
+   	if rising_edge(CLK) then
+          if( RST = '1' ) then
+   		    sl_stop     <= '0';
+   		    sl_done_all <= '0';
+   		    sl_sof      <= '1';
+   	    else 
+   		    if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+   			    sl_stop <= '1';
+   		    elsif (WRAP=true) then
+   			    sl_stop <= '0';
+   		    end if;
+   		    if (sl_stop='0') then
+   			    sl_done_all <= sl_cntr_en(N_CNTRS);
+   		    end if;
+   		    if (ENABLE='1') then
+   			    sl_sof <= sl_eof;
+   		    end if;
+   	    end if;
+   	end if;
+   end process;
+   --
+   sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+   CONTROL <= sl_CONTROL;
+   --
+   REG_CNTRS <= sl_reg_cntrs; 
+   DONE <= sl_done_all;     -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+   STOP <= sl_stop;         -- '1' = The couter stoped after the end of the itteration space. 
+   --
+   sl_count      <=  '0' when (sl_stop='1') else
+                     '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
+   sl_cntr_en(0) <=  sl_count; -- makes the EVAL_LOGIC count
+   --
+   sl_cntr_en(N_CNTRS  downto 1) <= sl_cntr_en(N_CNTRS-1  downto 0) and sl_done(N_CNTRS-1  downto 0);
+   sl_eof <= sl_cntr_en(N_CNTRS);   -- End-of-frame
+   --
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_5/src/vhdl/bunny_static_split2rtl_hwn_nd_5_eval_logic_wr.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_5/src/vhdl/bunny_static_split2rtl_hwn_nd_5_eval_logic_wr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..00a8630580da53de20141c3c7f5c5d9a72f21a33
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_5/src/vhdl/bunny_static_split2rtl_hwn_nd_5_eval_logic_wr.vhd
@@ -0,0 +1,308 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_5 is
+   generic ( 
+      N_OUT_PORTS   : natural := 1;
+      WRAP          : boolean := true;
+      N_CNTRS       : natural := 1;
+      QUANT         : natural := 32;
+      PAR_BITWIDTH  : natural :=1;
+      CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+      CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST           : in  std_logic;
+      CLK           : in  std_logic;
+      WRITE_EN      : out std_logic_vector(1 downto 0);
+      WRITE_ST      : in  std_logic_vector(1 downto 0);
+      HALT          : in  std_logic;
+      FIRE          : out std_logic;
+      DONE          : out std_logic;
+      STOP          : out std_logic;
+      CONTROL       : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+   );
+end bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_5;
+
+architecture RTL of bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_5 is	
+   -- 
+   component counter is 
+      generic( 
+         C_STEP    : natural := 10; 
+         C_WIDTH   : natural := 10 
+      ); 
+      port ( 
+         RST       : in  std_logic; 
+         CLK       : in  std_logic; 
+         ENABLE    : in  std_logic; 
+         LOAD      : in  std_logic; 
+         LOWER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         UPPER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         ITERATOR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         REG_CNTR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         DONE      : out std_logic 
+      ); 
+   end component; 
+   -- 
+   component it_mod is 
+   generic( 
+      C_MOD     : natural := 10; 
+      C_WIDTH   : natural := 10; 
+      C_INIT    : natural :=  1; 
+      C_STEP    : natural :=  1  
+   ); 
+   port ( 
+      RST       : in  std_logic; 
+      CLK       : in  std_logic; 
+      LOAD      : in  std_logic; 
+      ENABLE    : in  std_logic; 
+      MODULE    : out std_logic_vector(C_WIDTH-1 downto 0) 
+   ); 
+   end component; 
+   -- 
+   -- Multirate related signals
+   signal sl_bla_en   : std_logic_vector(1 downto 0); 
+   signal sl_mr_en    : std_logic_vector(1 downto 0); 
+   signal sl_mr_done  : std_logic_vector(1 downto 0); 
+   signal sl_mr_lock  : std_logic_vector(1 downto 0); 
+   signal sl_enables  : std_logic_vector(1 downto 0); 
+   signal sl_enable   : std_logic; 
+   signal ENABLE      : std_logic; 
+   -- Function output parameter "out_0", multirate=1 
+   constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   -- Function output parameter "out_1", multirate=1 
+   constant sl_mr_lbnd_1 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_1 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   --  
+   -- Parameter related signals 
+   --  
+   -- Iterator (counter) related signals 
+   signal sl_low_i, sl_high_i : integer; 
+   signal sl_low_j, sl_high_j : integer; 
+   signal sl_loop_i, sl_loop_i_rg : integer;
+   signal sl_loop_j, sl_loop_j_rg : integer;
+   signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   -- 
+   signal sl_cntr_en  : std_logic_vector(N_CNTRS   downto 0); 
+   signal sl_done     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_done_all : std_logic; 
+   signal sl_load     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_stop     : std_logic; 
+   signal sl_fire     : std_logic; 
+   signal sl_eof      : std_logic; 
+   signal sl_sof      : std_logic; 
+   signal sl_count    : std_logic; 
+   -- 
+   -- Special Control signal
+   signal sl_CONTROL       : std_logic_vector(N_OUT_PORTS-1 downto 0);
+   signal sl_no_request    : std_logic;
+   -- 
+   -- alias signals 
+   alias update_i : std_logic is sl_cntr_en(1);
+   alias update_j : std_logic is sl_cntr_en(0);
+   -- 
+   alias load_i : std_logic is sl_load(1);
+   alias load_j : std_logic is sl_load(0);
+   -- Trigger signals 
+   signal sl_trigger_i : std_logic;
+   signal sl_trigger_j : std_logic;
+
+
+   -- define control variables 
+   -- MOD related signals 
+
+
+   type state_type is (s_idle, s_halt, s_count, s_release);
+   signal state : state_type;
+   signal halt_cnt : integer;
+   signal sl_halt : std_logic;
+
+   signal sl_cnt_rst : std_logic;
+   signal cnt_rst : std_logic;
+
+begin
+
+   -- =============================================
+   -- =             MOD Functions                  
+   -- =============================================
+   -- END of MOD definitions 
+   --  
+   -- Parameter related signal assignments 
+   sl_cnt_rst <= '0';
+   sl_halt <= HALT;
+   -- END of Parameter definitions 
+
+   sl_loop_i    <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_i_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_j    <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+   sl_loop_j_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+   -- Const bounds for-loops 
+   sl_low_i  <= 0;
+   sl_high_i <= 359;
+   sl_low_j  <= 0;
+   sl_high_j <= 319;
+
+
+   load_i <= '0';
+   load_j <= '0';
+
+   sl_lower_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
+   sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
+
+   sl_upper_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
+   sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
+
+   -- Special definitions 
+
+   -- Entity and control variables
+
+   sl_fire <= ('1');
+
+   -- Convert FIFO Write Port out_1 : ED_3
+   sl_CONTROL(0) <= sl_fire and ('1');
+
+   -- Convert FIFO Write Port out_2 : ED_4_5
+   sl_CONTROL(1) <= sl_fire and ('1');
+
+   FIRE <= sl_fire;
+
+   cnt_rst <= sl_cnt_rst or RST;
+
+   -- 
+   -- =============================================
+   -- =             Multirate                      
+   -- =============================================
+   -- Function output parameter "out_0", multirate=1 
+   CNTR_MR0 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(0),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_0,
+         UPPER_BND => sl_mr_ubnd_0,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(0)
+      );
+   -- Function output parameter "out_1", multirate=1 
+   CNTR_MR1 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(1),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_1,
+         UPPER_BND => sl_mr_ubnd_1,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(1)
+      );
+   -- 
+   -- WRITE_EN indicates if date can be written to WRITE_MUX
+   sl_bla_en      <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
+   WRITE_EN    <=  (others=>'0') when (HALT='1') else sl_bla_en;
+   -- 
+   sl_mr_en    <= (not sl_mr_lock) and WRITE_ST; 
+   sl_enables  <= sl_mr_lock or (sl_mr_done and sl_mr_en); 
+   sl_enable   <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0';  -- and_reduce 
+   ENABLE      <= sl_enable or (not sl_fire);
+   -- 
+   LOCK_PRCS: process(CLK) 
+   begin 
+       if rising_edge(CLK) then 
+           if( RST = '1' ) then 
+               sl_mr_lock <= (others=>'0'); 
+           else  
+               if (ENABLE='1') then 
+                   sl_mr_lock <= (others=>'0'); 
+               else 
+                   for i in 0 to 1 loop 
+                       if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then 
+                           sl_mr_lock(i) <= '1'; 
+                       end if; 
+                   end loop; 
+               end if; 
+           end if; 
+       end if; 
+   end process; 
+   -- END of Multirate definitions 
+   -- 
+   -- =============================================
+   -- =             Iterators                      
+   -- =============================================
+   GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
+   	CNTR_WR : counter
+   	generic map ( 
+   		C_STEP    => CNTR_STEP(i),
+   		C_WIDTH   => CNTR_WIDTH(i)
+   	)
+  	 port map (
+   		CLK       => CLK,
+   		RST       => cnt_rst,
+   		ENABLE    => sl_cntr_en(i),
+   		LOAD      => sl_load(i),
+   		LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		ITERATOR  => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		REG_CNTR  => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		DONE      => sl_done(i)
+   	);
+   end generate;
+   --
+   DONE_PRCS: process(CLK)
+   begin
+   	if rising_edge(CLK) then
+   	    if( RST = '1' ) then
+   		    sl_stop     <= '0';
+   		    sl_done_all <= '0';
+   		    sl_sof      <= '1';
+   	    else 
+   		    if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+   			    sl_stop <= '1';
+   		    elsif (WRAP=true) then
+   			    sl_stop <= '0';
+   		    end if;
+   		    if (sl_stop='0') then
+   			    sl_done_all <= sl_cntr_en(N_CNTRS);
+   		    end if;
+   		    if (ENABLE='1') then
+   			    sl_sof <= sl_eof;
+   		    end if;
+   	    end if;
+   	end if;
+   end process;
+   --
+   sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+   CONTROL <= sl_CONTROL;
+   --
+   DONE <= sl_done_all;     -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+   STOP <= sl_stop;         -- '1' = The couter stoped after the end of the itteration space. 
+   --
+   sl_count      <=  '0' when (sl_stop='1') else
+   			'1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
+   sl_cntr_en(0) <=  sl_count; -- makes the EVAL_LOGIC count
+   --
+   sl_cntr_en(N_CNTRS  downto 1) <= sl_cntr_en(N_CNTRS-1  downto 0) and sl_done(N_CNTRS-1  downto 0);
+   sl_eof <= sl_cntr_en(N_CNTRS);      -- End-of-frame (combinatorial; beter not use it outside)
+   --
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_5/src/vhdl/bunny_static_split2rtl_hwn_nd_5_execution_unit.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_5/src/vhdl/bunny_static_split2rtl_hwn_nd_5_execution_unit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4e6ae951dbfe6eb988edfdf19069becd36c65710
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_5/src/vhdl/bunny_static_split2rtl_hwn_nd_5_execution_unit.vhd
@@ -0,0 +1,114 @@
+-- Execute Unit automatically generated by KpnMapper
+-- Function "split64to2t32"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_bunny_static_split2rtl_functions_1_lib;
+use compaandesign_com_bunny_static_split2rtl_functions_1_lib.all;
+
+entity bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_5 is
+   generic (
+      N_INPORTS  : natural := 1;
+      N_OUTPORTS : natural := 1;
+      IP_RESET   : natural := 1; 
+      STIM_DIR   : string  := "bla";
+      QUANT      : natural := 32;
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1; 
+      CNTR_QUANT : natural := 32; 
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+   );
+   port (
+      RST        : in  std_logic;
+      CLK        : in  std_logic;
+      -- Funtion Input parameters
+      IN_PORT_0    : in  std_logic_vector(63 downto 0);  -- Param. "stimin"
+      READ       : out std_logic_vector(N_INPORTS-1 downto 0);
+      EXIST      : in  std_logic_vector(N_INPORTS-1 downto 0);
+      -- Iterators
+      REG_CNTRS_RD : in  std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
+      -- Funtion Output parameters
+      OUT_PORT_0   : out std_logic_vector(31 downto 0);  -- Param. "out0"
+      OUT_PORT_1   : out std_logic_vector(31 downto 0);  -- Param. "out1"
+      WRITE      : out std_logic_vector(N_OUTPORTS-1 downto 0);
+      FULL       : in  std_logic_vector(N_OUTPORTS-1 downto 0);
+      STOP_RD    : in  std_logic;
+      STOP_WR    : in  std_logic;
+      ERROR      : out std_logic
+   );
+end bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_5 ;
+
+-- Laura implementation
+architecture Laura of bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_5 is
+
+   component split64to2t32 is
+      generic (
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1; 
+         CNTR_QUANT : natural := 32; 
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST   : in std_logic;
+         CLK   : in std_logic;
+         -- Inputs 
+         ip_stimin  : in  std_logic_vector(63 downto 0);  
+         -- Iterators 
+         it_j : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+         it_i : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+         EXIST : in  std_logic_vector(0 downto 0);
+         READF : out std_logic_vector(0 downto 0);
+         -- Outputs 
+         op_out0 : out std_logic_vector(31 downto 0);
+         op_out1 : out std_logic_vector(31 downto 0);
+         FULL  : in  std_logic_vector(1 downto 0);
+         WRITEF: out std_logic_vector(1 downto 0);
+         --
+         STOP_RD : in  std_logic;
+         STOP_WR : in  std_logic;
+         ERROR   : out std_logic
+      );
+   end component;
+
+   signal sl_RST : std_logic;
+
+begin
+
+   sl_RST <= RST when IP_RESET=1 else not RST;
+
+   FUNC : split64to2t32
+   generic map (
+         STIM_DIR      => STIM_DIR,
+         c_STAGES      => c_STAGES,
+         N_CNTRS       => N_CNTRS,
+         CNTR_QUANT    => CNTR_QUANT,
+         CNTR_WIDTH    => CNTR_WIDTH
+   )
+   port map (
+      RST   => sl_RST,
+      CLK   => CLK,
+      -- Inputs 
+      ip_stimin => IN_PORT_0,
+      -- Iterators 
+      it_j => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
+      it_i => REG_CNTRS_RD(1*CNTR_QUANT+CNTR_WIDTH(1)-1 downto 1*CNTR_QUANT),
+      EXIST => EXIST,
+      READF => READ,
+      -- Outputs 
+      op_out0 => OUT_PORT_0,
+      op_out1 => OUT_PORT_1,
+      FULL  => FULL,
+      WRITEF=> WRITE,
+      -- 
+      STOP_RD => STOP_RD,
+      STOP_WR => STOP_WR,
+      ERROR   => ERROR
+   );
+
+end Laura;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_6/hdllib.cfg b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_6/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..7796929b6fcfa65ec501e33afb42a052c4f93a0c
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_6/hdllib.cfg
@@ -0,0 +1,18 @@
+hdl_lib_name = compaandesign_com_bunny_static_split2rtl_hwn_nd_6_1
+hdl_library_clause_name = compaandesign_com_bunny_static_split2rtl_hwn_nd_6_1_lib
+hdl_lib_uses_synth = compaandesign_com_bunny_static_split2rtl_functions_1 compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1 compaandesign_com_common_extern_connector_1 
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+	src/vhdl/bunny_static_split2rtl_hwn_nd_6_execution_unit.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_6_eval_logic_rd.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_6_eval_logic_wr.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_6.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_6/src/vhdl/bunny_static_split2rtl_hwn_nd_6.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_6/src/vhdl/bunny_static_split2rtl_hwn_nd_6.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d2ba33b53fb32b5ed3527bc836a900855752818e
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_6/src/vhdl/bunny_static_split2rtl_hwn_nd_6.vhd
@@ -0,0 +1,546 @@
+-- HWN Entity File automatically generated by KpnMapper (writeHdlHWNodeFile)
+-- Top level file for a Hardware Accelerator
+-- Function "deserialize32to4t8"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+library compaandesign_com_common_extern_connector_1_lib;
+use compaandesign_com_common_extern_connector_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_6 is
+   generic (
+      STIM_DIR   : string  := "bla";
+      RESET_HIGH : natural := 1;
+      PAR_WIDTH  : natural := 16;
+      QUANT      : natural := 32;
+      WRAP       : boolean := true
+   );
+   port (
+
+      -- Dataflow input interfaces
+      -- ED_3 : in_0
+      ND_6IP_3_Rd    : out std_logic;
+      ND_6IP_3_Din   : in  std_logic_vector(31 downto 0);
+      ND_6IP_3_Exist : in  std_logic; 
+      ND_6IP_3_CLK   : out std_logic;
+      ND_6IP_3_CTRL  : in  std_logic;
+
+      -- ED_4_5 : in_0
+      ND_6IP_5_ND_6IP_4_Rd    : out std_logic;
+      ND_6IP_5_ND_6IP_4_Din   : in  std_logic_vector(31 downto 0);
+      ND_6IP_5_ND_6IP_4_Exist : in  std_logic; 
+      ND_6IP_5_ND_6IP_4_CLK   : out std_logic;
+      ND_6IP_5_ND_6IP_4_CTRL  : in  std_logic;
+
+      -- Dataflow Control Input interfaces
+      -- Dataflow output interfaces
+      -- ED_6 : out_0
+      ND_6OP_1_Wr   : out std_logic;
+      ND_6OP_1_Dout : out std_logic_vector(7 downto 0);
+      ND_6OP_1_Full : in  std_logic;
+      ND_6OP_1_CLK  : out std_logic;
+      ND_6OP_1_CTRL : out std_logic;
+
+      -- ED_7 : out_1
+      ND_6OP_2_Wr   : out std_logic;
+      ND_6OP_2_Dout : out std_logic_vector(7 downto 0);
+      ND_6OP_2_Full : in  std_logic;
+      ND_6OP_2_CLK  : out std_logic;
+      ND_6OP_2_CTRL : out std_logic;
+
+      -- ED_8 : out_2
+      ND_6OP_3_Wr   : out std_logic;
+      ND_6OP_3_Dout : out std_logic_vector(7 downto 0);
+      ND_6OP_3_Full : in  std_logic;
+      ND_6OP_3_CLK  : out std_logic;
+      ND_6OP_3_CTRL : out std_logic;
+
+      PARAM_DT : in  std_logic_vector(PAR_WIDTH+10-1 downto 0);
+      PARAM_LD : in  std_logic;
+
+      RST      : in  std_logic;
+      CLK      : in  std_logic;
+      STOP     : out std_logic;
+      ERROR    : out std_logic;
+      BLOCK_RD : out std_logic
+   );
+end bunny_static_split2rtl_hwn_nd_6;
+
+architecture RTL of bunny_static_split2rtl_hwn_nd_6 is
+   --
+   -- ====================================
+   -- =     Constants declaration        =
+   -- ====================================
+   -- Setting the parameters of the HW Node
+   constant c_IN_PORTS     : natural := 2; -- number of input ports of a HW node
+   constant c_OUT_PORTS    : natural := 3; -- number of output ports of a HW node
+   constant c_IN_FUNC_VAR  : natural := 1; -- number of input ports of a HW IP
+   constant c_OUT_FUNC_VAR : natural := 4; -- number of output ports of a HW IP
+   constant c_COUNTERS     : natural := 2; -- number of iterators
+   -- ===========================================
+   -- = Iterators run from Inner to Outer loop  =
+   -- ===========================================
+   constant c_CNTR_QUANT   : natural := 11;
+   constant c_CNTR_STEPS   : t_counter_step  := ( 0=>1, 1=>1, others=>1 );
+   constant c_CNTR_WIDTHS  : t_counter_width := ( 0=>11, 1=>10, others=>10 );
+   constant c_STAGES       : natural := 1; -- number of pipeline stages or delay
+   constant c_IP_RESET     : natural := 1; -- active level of the HW IP reset signal
+   constant c_WRAP         : boolean := WRAP; -- Operation mode: Single_Shot (false) or Continuous (true)
+   constant c_EXT_PAR      : natural := 0; -- number of external parameters
+   constant c_INT_PAR      : natural := 0; -- number of internal parameters
+   constant c_N_PAR        : natural := 0; -- no parameters are used
+   constant c_PAR_BITWIDTH : natural := PAR_WIDTH; -- aggregate bitwidth of the parameter vector
+   constant c_PAR_VECTOR   : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
+       (0,0,0,0), (0,0,0,0)    -- two dummy elements
+   );
+   --
+   -- ====================================
+   -- =     Components declaration       =
+   -- ====================================
+   component bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_6 is
+      generic (
+         N_IN_PORTS    : natural := 1;
+         WRAP          : boolean := true;
+         N_CNTRS       : natural := 1; 
+         QUANT         : natural := 32;
+         PAR_BITWIDTH  : natural :=1;
+         CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+         CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+      );
+      port (
+         RST           : in  std_logic;
+         CLK           : in  std_logic;
+         REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1  downto 0); 
+         READ_EN       : out std_logic_vector(c_IN_FUNC_VAR-1  downto 0);
+         READ_ST       : in  std_logic_vector(c_IN_FUNC_VAR-1  downto 0);
+         HALT          : in  std_logic;
+         FIRE          : out std_logic;
+         DONE          : out std_logic;
+         STOP          : out std_logic;
+         CONTROL       : out std_logic_vector(N_IN_PORTS-1 downto 0);
+         OBTAIN        : out std_logic_vector(N_IN_PORTS-1 downto 0);
+         RELEASE       : out std_logic_vector(N_IN_PORTS-1 downto 0)
+      );
+   end component;
+
+   component READ_MUX is
+      generic (
+         N_PORTS    : natural := 1;
+         PORT_WIDTH : natural := 32  
+      );
+      port(
+         IN_PORTS   : in  std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
+         EXISTS     : in  std_logic_vector(N_PORTS-1 downto 0);
+         READS      : out std_logic_vector(N_PORTS-1 downto 0);
+         SOFS       : in  std_logic_vector(N_PORTS-1 downto 0);
+
+         OUT_PORT   : out std_logic_vector(PORT_WIDTH-1 downto 0);
+         EXIST      : out std_logic;
+         READ       : in  std_logic;
+         SOF        : in  std_logic;
+		CLK        : in std_logic;
+
+         READ_EN    : in  std_logic;
+         READ_ST    : out std_logic;
+         CONTROL    : in  std_logic_vector(N_PORTS-1 downto 0);
+         OBTAIN     : in  std_logic_vector(N_PORTS-1 downto 0);
+         RELEASE    : in  std_logic_vector(N_PORTS-1 downto 0)
+      );
+   end component;
+
+   component bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_6 is
+      generic ( 
+         N_OUT_PORTS   : natural := 1;
+         WRAP          : boolean := true;
+         N_CNTRS       : natural := 1; 
+         QUANT         : natural := 32;
+         PAR_BITWIDTH  : natural :=1;
+         CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+         CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+      );
+      port (
+         RST           : in  std_logic;
+         CLK           : in  std_logic;
+         WRITE_EN      : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+         WRITE_ST      : in  std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+         HALT          : in  std_logic;
+         FIRE          : out std_logic;
+         DONE          : out std_logic;
+         STOP          : out std_logic;
+         CONTROL       : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+      );
+   end component;
+
+   component WRITE_DEMUX is
+      generic (
+         N_PORTS : natural := 1
+      );
+      port(
+         WRITES   : out std_logic_vector(N_PORTS-1 downto 0);
+         WRITE    : in  std_logic;
+
+         FULLS    : in  std_logic_vector(N_PORTS-1 downto 0);
+         FULL     : out std_logic;
+
+         WRITE_EN : in  std_logic;
+         WRITE_ST : out std_logic;
+         CONTROL  : in  std_logic_vector(N_PORTS-1 downto 0)
+      );
+   end component;
+
+
+   component bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_6 is
+      generic (
+         N_INPORTS  : natural := 1;
+         N_OUTPORTS : natural := 1;
+         IP_RESET   : natural := 1;
+         QUANT      : natural := 32;
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1;
+         CNTR_QUANT : natural := 32;
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST        : in  std_logic;
+         CLK        : in  std_logic;
+
+         -- Iterators
+         REG_CNTRS_RD : in  std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
+         -- Func. Input parameters
+         IN_PORT_0 : in  std_logic_vector(31 downto 0); -- stimin
+         READ       : out std_logic_vector(N_INPORTS-1 downto 0);
+         EXIST      : in  std_logic_vector(N_INPORTS-1 downto 0);
+         -- Func. Output parameters
+         OUT_PORT_0 : out std_logic_vector(7 downto 0); -- out0
+         OUT_PORT_1 : out std_logic_vector(7 downto 0); -- out1
+         OUT_PORT_2 : out std_logic_vector(7 downto 0); -- out2
+         OUT_PORT_3 : out std_logic_vector(7 downto 0); -- out3
+         WRITE      : out std_logic_vector(N_OUTPORTS-1 downto 0);
+         FULL       : in  std_logic_vector(N_OUTPORTS-1 downto 0);
+         --
+         STOP_RD    : in  std_logic;
+         STOP_WR    : in  std_logic;
+         ERROR      : out std_logic
+      );
+   end component;
+
+   component INTERNAL_PARAMETERS is 
+      generic (
+         PAR_BITWIDTH : natural:=1;
+         PAR_VECTOR   : t_par_vector;
+         N_PAR        : natural:=0;
+         START_IN_RUN  : boolean := FALSE
+      );
+      port (  
+         RST        : in  std_logic;
+         CLK        : in  std_logic;
+
+         HALT_RD    : out std_logic;
+         HALT_WR    : out std_logic;
+         SOF_RD     : in  std_logic;
+         SOF_WR     : in  std_logic;
+         LOAD_PARAM : out std_logic;
+
+         par_one_in_Rd    : out std_logic;
+         par_one_in_Din   : in std_logic_vector(32-1 downto 0);
+         par_one_in_Exist : in std_logic;
+         par_one_in_CLK   : out std_logic;
+         par_one_in_CTRL  : in std_logic;
+
+         PARAMETERS_RD : out std_logic_vector(32-1 downto 0);
+         PARAMETERS_WR : out std_logic_vector(32-1 downto 0)
+      );
+   end component;
+
+   --
+   -- ====================================
+   -- =       Signals declaration        =
+   -- ====================================
+   -- 
+   -- HW Node Input Ports
+   signal sl_IN_PORTS_0   : std_logic_vector(2*32-1 downto 0); -- stimin
+   signal sl_EXISTS       : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_READS        : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_CTRLS        : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_control_rd   : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_obtain_rd    : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_release_rd   : std_logic_vector(c_IN_PORTS-1 downto 0);
+   -- 
+   -- Func. Input parameters
+   signal sl_in_port_0    : std_logic_vector(31 downto 0); -- stimin
+   signal sl_exist        : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read         : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read_en      : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read_st      : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   -- 
+   signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
+   -- 
+   -- HW Node Output Ports
+   signal sl_WRITES       : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_FULLS        : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_control_wr   : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_lortnoc_wr   : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   -- 
+   -- Func. Output parameters
+   signal sl_out_port_0   : std_logic_vector(7 downto 0); -- out0
+   signal sl_out_port_1   : std_logic_vector(7 downto 0); -- out1
+   signal sl_out_port_2   : std_logic_vector(7 downto 0); -- out2
+   signal sl_out_port_3   : std_logic_vector(7 downto 0); -- out3
+   signal sl_full         : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write        : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write_en     : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write_st     : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   -- 
+   -- 
+   signal sl_halt             : std_logic;
+   signal sl_halted           : std_logic;
+   signal sl_halt_wr          : std_logic;
+   signal sl_halt_rd          : std_logic;
+   signal sl_param_halt_wr    : std_logic;
+   signal sl_param_halt_rd    : std_logic;
+   signal sl_done_wr          : std_logic;
+   signal sl_done_rd          : std_logic;
+   signal sl_stop_wr          : std_logic;
+   signal sl_stop_rd          : std_logic;
+   signal sl_fire_wr          : std_logic;
+   signal sl_fire_rd          : std_logic;
+   signal sl_sof_wr           : std_logic;
+   signal sl_sof_rd           : std_logic;
+   signal sl_error            : std_logic;
+   signal sl_load_param       : std_logic;
+
+   --  
+   -- Parameter related signals 
+   signal sl_param_fifo_full     : std_logic;
+   signal sl_sync_num            : std_logic_vector(9 downto 0);
+
+   signal sl_RST : std_logic;
+
+begin 
+
+   sl_RST <= RST when RESET_HIGH=1 else not RST;
+      ND_6IP_3_CLK   <= CLK;
+      ND_6IP_5_ND_6IP_4_CLK   <= CLK;
+      ND_6OP_1_CLK  <= CLK;
+      ND_6OP_2_CLK  <= CLK;
+      ND_6OP_3_CLK  <= CLK;
+
+   --
+   -- ==========================================================
+   -- =       HWN Input related modules                        =
+   -- ==========================================================
+   -- Func. Input param. "stimin"
+   RD_MUX_0 : READ_MUX
+   generic map (
+      N_PORTS    => 2,
+      PORT_WIDTH => 32
+   )
+   port map (
+      IN_PORTS   => sl_IN_PORTS_0,
+      EXISTS     => sl_EXISTS(1 downto 0),
+      READS      => sl_READS(1 downto 0),
+      SOFS       => sl_CTRLS(1 downto 0),
+
+      OUT_PORT   => sl_in_port_0,
+      EXIST      => sl_exist(0),
+      READ       => sl_read(0),
+      SOF        => sl_sof_rd,
+      CLK        => CLK,
+
+      READ_EN    => sl_read_en(0),
+      READ_ST    => sl_read_st(0),
+      CONTROL    => sl_control_rd(1 downto 0),
+      OBTAIN     => sl_obtain_rd(1 downto 0),
+      RELEASE    => sl_release_rd(1 downto 0)
+   );
+
+   ND_6IP_3_Rd   <= sl_READS(0);
+   ND_6IP_5_ND_6IP_4_Rd   <= sl_READS(1);
+
+   sl_IN_PORTS_0 <= ND_6IP_5_ND_6IP_4_Din & ND_6IP_3_Din;
+
+   sl_EXISTS      <= ND_6IP_5_ND_6IP_4_Exist & ND_6IP_3_Exist ;
+   sl_CTRLS       <= ND_6IP_5_ND_6IP_4_CTRL & ND_6IP_3_CTRL ;
+
+   EVAL_RD : bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_6
+   generic map ( 
+      N_IN_PORTS    => c_IN_PORTS,
+      WRAP          => c_WRAP,
+      N_CNTRS       => c_COUNTERS,
+      QUANT         => c_CNTR_QUANT,
+      PAR_BITWIDTH  => c_PAR_BITWIDTH,
+      CNTR_STEP     => c_CNTR_STEPS,
+      CNTR_WIDTH    => c_CNTR_WIDTHS
+   )
+   port map(
+      RST           => sl_RST,
+      CLK           => CLK,
+      REG_CNTRS     => sl_REG_CNTRS_RD,
+      READ_EN       => sl_read_en,
+      READ_ST       => sl_read_st,
+      HALT          => sl_halt_rd,
+      FIRE          => sl_fire_rd,
+      DONE          => sl_done_rd,
+      STOP          => sl_stop_rd,
+      CONTROL       => sl_control_rd,
+      OBTAIN        => sl_obtain_rd,
+      RELEASE       => sl_release_rd
+   );
+
+   --
+   -- ==========================================================
+   -- =       HWN Output related modules                       =
+   -- ==========================================================
+   -- 
+   -- Func. Output param. "out0"
+   DEMUX_0 : WRITE_DEMUX
+   generic map (
+      N_PORTS => 1
+   )
+   port map (
+      WRITES   => sl_WRITES(0 downto 0),
+      FULLS    => sl_FULLS(0 downto 0),
+      CONTROL  => sl_lortnoc_wr(0 downto 0),
+      WRITE    => sl_write(0),
+      FULL     => sl_full(0),
+      WRITE_EN => sl_write_en(0),
+      WRITE_ST => sl_write_st(0)
+   );
+   --
+   ND_6OP_1_Dout <= sl_out_port_0;  -- Func. Output param. "out0"
+   ND_6OP_1_CTRL <= sl_sof_wr ;
+   ND_6OP_1_Wr   <= sl_WRITES(0);
+   sl_FULLS(0) <= ND_6OP_1_Full;
+   sl_lortnoc_wr(0) <= sl_control_wr(0);
+   --
+   -- 
+   -- Func. Output param. "out1"
+   DEMUX_1 : WRITE_DEMUX
+   generic map (
+      N_PORTS => 1
+   )
+   port map (
+      WRITES   => sl_WRITES(1 downto 1),
+      FULLS    => sl_FULLS(1 downto 1),
+      CONTROL  => sl_lortnoc_wr(1 downto 1),
+      WRITE    => sl_write(1),
+      FULL     => sl_full(1),
+      WRITE_EN => sl_write_en(1),
+      WRITE_ST => sl_write_st(1)
+   );
+   --
+   ND_6OP_2_Dout <= sl_out_port_1;  -- Func. Output param. "out1"
+   ND_6OP_2_CTRL <= sl_sof_wr ;
+   ND_6OP_2_Wr   <= sl_WRITES(1);
+   sl_FULLS(1) <= ND_6OP_2_Full;
+   sl_lortnoc_wr(1) <= sl_control_wr(1);
+   --
+   -- 
+   -- Func. Output param. "out2"
+   DEMUX_2 : WRITE_DEMUX
+   generic map (
+      N_PORTS => 1
+   )
+   port map (
+      WRITES   => sl_WRITES(2 downto 2),
+      FULLS    => sl_FULLS(2 downto 2),
+      CONTROL  => sl_lortnoc_wr(2 downto 2),
+      WRITE    => sl_write(2),
+      FULL     => sl_full(2),
+      WRITE_EN => sl_write_en(2),
+      WRITE_ST => sl_write_st(2)
+   );
+   --
+   ND_6OP_3_Dout <= sl_out_port_2;  -- Func. Output param. "out2"
+   ND_6OP_3_CTRL <= sl_sof_wr ;
+   ND_6OP_3_Wr   <= sl_WRITES(2);
+   sl_FULLS(2) <= ND_6OP_3_Full;
+   sl_lortnoc_wr(2) <= sl_control_wr(2);
+   --
+   -- 
+   -- Func. Output param. "out3"
+   -- Not connected to any FIFO (hanging)
+   sl_full(3) <= '0'; 
+   sl_write_st(3) <= sl_write_en(3); 
+   --
+   EVAL_WR : bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_6
+   generic map ( 
+      N_OUT_PORTS   => c_OUT_PORTS,
+      WRAP          => c_WRAP,
+      N_CNTRS       => c_COUNTERS,
+      QUANT         => c_CNTR_QUANT,
+      PAR_BITWIDTH  => c_PAR_BITWIDTH,
+      CNTR_STEP     => c_CNTR_STEPS,
+      CNTR_WIDTH    => c_CNTR_WIDTHS
+   )
+   port map (
+      RST           => sl_RST,
+      CLK           => CLK,
+      WRITE_EN      => sl_write_en,
+      WRITE_ST      => sl_write_st,
+      HALT          => sl_halt_wr,
+      FIRE          => sl_fire_wr,
+      DONE          => sl_done_wr,
+      STOP          => sl_stop_wr,
+      CONTROL       => sl_control_wr
+   );
+
+   --
+   -- ==========================================================
+   -- =       HWN Execution Unit                               =
+   -- ==========================================================
+   EX : bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_6
+   generic map (
+      N_INPORTS  => c_IN_FUNC_VAR,
+      N_OUTPORTS => c_OUT_FUNC_VAR, 
+      IP_RESET   => c_IP_RESET,
+      QUANT      => QUANT,
+      STIM_DIR   => STIM_DIR,
+      c_STAGES   => c_STAGES,
+      N_CNTRS    => c_COUNTERS,
+      CNTR_QUANT => c_CNTR_QUANT,
+      CNTR_WIDTH => c_CNTR_WIDTHS
+   )
+   port map (
+      RST        => sl_RST,
+      CLK        => CLK,
+      -- Iterators
+      REG_CNTRS_RD => sl_REG_CNTRS_RD,
+      -- Func. Input parameters
+      IN_PORT_0    => sl_in_port_0,
+      READ       => sl_read,
+      EXIST      => sl_exist,
+      -- Func. Output parameters
+      OUT_PORT_0   => sl_out_port_0,
+      OUT_PORT_1   => sl_out_port_1,
+      OUT_PORT_2   => sl_out_port_2,
+      OUT_PORT_3   => sl_out_port_3,
+      WRITE      => sl_write,
+      FULL       => sl_full,
+      --
+      STOP_WR    => sl_stop_wr,
+      STOP_RD    => sl_stop_rd,
+      ERROR      => sl_error
+   );
+
+   -- ==========================================================
+   -- =       PARAMETERIZATION                                 =
+   -- ==========================================================
+   -- no parameters
+   sl_halt_rd <= '0';
+   sl_halt_wr <= '0';
+--   sl_halted  <= sl_sof_rd;
+   STOP <= sl_done_wr;
+   ERROR <= sl_error;
+   BLOCK_RD <= not (  (  sl_READS(0) or   sl_READS(1)  ) );
+
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_6/src/vhdl/bunny_static_split2rtl_hwn_nd_6_eval_logic_rd.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_6/src/vhdl/bunny_static_split2rtl_hwn_nd_6_eval_logic_rd.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2bce6f6b2aadd0d5677c7ac9cbfabfe2cdbe2747
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_6/src/vhdl/bunny_static_split2rtl_hwn_nd_6_eval_logic_rd.vhd
@@ -0,0 +1,351 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_6 is
+   generic (
+      N_IN_PORTS    : natural := 1;
+      WRAP          : boolean := true;
+      N_CNTRS       : natural := 1; 
+      QUANT         : natural := 32;
+      PAR_BITWIDTH  : natural  :=1;
+      CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+      CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST           : in  std_logic;
+      CLK           : in  std_logic;
+      REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+      READ_EN       : out std_logic_vector(0 downto 0);
+      READ_ST       : in  std_logic_vector(0 downto 0);
+      HALT          : in  std_logic;
+      FIRE          : out std_logic;
+      DONE          : out std_logic;
+      STOP          : out std_logic;
+      CONTROL       : out std_logic_vector(N_IN_PORTS-1 downto 0);
+      OBTAIN        : out std_logic_vector(N_IN_PORTS-1 downto 0);
+      RELEASE       : out std_logic_vector(N_IN_PORTS-1 downto 0)
+   );
+end bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_6;
+
+architecture RTL of bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_6 is
+   -- 
+   component counter is 
+      generic( 
+         C_STEP    : natural := 10; 
+         C_WIDTH   : natural := 10 
+      ); 
+      port ( 
+         RST       : in  std_logic; 
+         CLK       : in  std_logic; 
+         ENABLE    : in  std_logic; 
+         LOAD      : in  std_logic; 
+         LOWER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         UPPER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         ITERATOR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         REG_CNTR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         DONE      : out std_logic 
+      ); 
+   end component; 
+   -- 
+   component it_mod is 
+   generic( 
+      C_MOD     : natural := 10; 
+      C_WIDTH   : natural := 10; 
+      C_INIT    : natural :=  1; 
+      C_STEP    : natural :=  1  
+   ); 
+   port ( 
+      RST       : in  std_logic; 
+      CLK       : in  std_logic; 
+      LOAD      : in  std_logic; 
+      ENABLE    : in  std_logic; 
+      MODULE    : out std_logic_vector(C_WIDTH-1 downto 0) 
+   ); 
+   end component; 
+   -- 
+   --  
+   -- Parameter related signals 
+   -- 
+   -- Iterator (counter) related signals 
+   signal sl_low_i, sl_high_i : integer;
+   signal sl_low_j, sl_high_j : integer;
+   signal sl_loop_i, sl_loop_i_rg : integer;
+   signal sl_loop_j, sl_loop_j_rg : integer;
+   signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   -- 
+   signal sl_cntr_en  : std_logic_vector(N_CNTRS   downto 0); 
+   signal sl_done     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_done_all : std_logic; 
+   signal sl_load     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_stop     : std_logic; 
+   signal sl_fire     : std_logic; 
+   signal sl_sof      : std_logic; 
+   signal sl_eof      : std_logic; 
+   signal sl_count    : std_logic; 
+
+   -- alias signals 
+   alias update_i : std_logic is sl_cntr_en(1);
+   alias update_j : std_logic is sl_cntr_en(0);
+   alias load_i : std_logic is sl_load(1);
+   alias load_j : std_logic is sl_load(0);
+
+   -- Trigger signals 
+   signal sl_trigger_i : std_logic;
+   signal sl_trigger_j : std_logic;
+
+   -- Special Control signal
+   signal sl_CONTROL       : std_logic_vector(N_IN_PORTS-1 downto 0);
+   signal sl_no_request    : std_logic;
+   -- 
+   -- Multirate related signals
+   signal sl_bla_en   : std_logic_vector(0 downto 0); 
+   signal sl_mr_en    : std_logic_vector(0 downto 0); 
+   signal sl_mr_done  : std_logic_vector(0 downto 0); 
+   signal sl_mr_lock  : std_logic_vector(0 downto 0); 
+   signal sl_enables  : std_logic_vector(0 downto 0); 
+   signal sl_enable   : std_logic; 
+   signal ENABLE      : std_logic; 
+   -- Function input parameter "in_0", multirate=1 
+   constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+
+   signal e0, e1, e2 : boolean;
+
+   signal sl_obtain0  : std_logic;
+   signal sl_release0 : std_logic;
+   signal sl_obtain1  : std_logic;
+   signal sl_release1 : std_logic;
+
+   -- define control variables 
+   signal div1 : integer;
+   signal div2 : integer;
+   signal mod1 : integer;
+   signal mod3 : integer;
+
+   type state_type is (s_idle, s_halt, s_count, s_release);
+   signal state : state_type;
+   signal halt_cnt : integer;
+   signal sl_halt : std_logic;
+
+   signal sl_cnt_rst : std_logic;
+   signal cnt_rst : std_logic;
+   signal j0_mod_2 : std_logic_vector(1-1 downto 0);
+   signal j1_mod_2 : std_logic_vector(1-1 downto 0);
+
+begin
+
+   -- =============================================
+   -- =             MOD Functions                  
+   -- =============================================
+   -- MOD function: j % 2 == 0
+   INST_mod1 : it_mod
+   generic map(
+      C_MOD     => 2,
+      C_WIDTH   => 1,
+      C_INIT    => 0,
+      C_STEP    => 1
+   )
+   port map(
+      RST       => RST,
+      CLK       => CLK,
+      LOAD      => sl_done(0),
+      ENABLE    => sl_cntr_en(0),
+      MODULE    => j0_mod_2
+   );
+   mod1 <= TO_INTEGER(UNSIGNED(j0_mod_2));
+   -- 
+   -- MOD function: j+1 % 2 == 1
+   INST_mod3 : it_mod
+   generic map(
+      C_MOD     => 2,
+      C_WIDTH   => 1,
+      C_INIT    => 1,
+      C_STEP    => 1
+   )
+   port map(
+      RST       => RST,
+      CLK       => CLK,
+      LOAD      => sl_done(0),
+      ENABLE    => sl_cntr_en(0),
+      MODULE    => j1_mod_2
+   );
+   mod3 <= TO_INTEGER(UNSIGNED(j1_mod_2));
+   -- 
+   -- END of MOD definitions 
+   -- =============================================
+   -- =             Parameter Functions            
+   -- =============================================
+   sl_cnt_rst <= '0';
+   sl_halt <= HALT;
+
+   -- END of Parameter definitions 
+   sl_loop_i    <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_i_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_j    <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+   sl_loop_j_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+   -- Const bounds for-loops 
+   sl_low_i  <= 0;
+   sl_high_i <= 359;
+   sl_low_j  <= 0;
+   sl_high_j <= 639;
+
+
+   load_i <= '0';
+   load_j <= '0';
+
+   sl_lower_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
+   sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
+
+   sl_upper_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
+   sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
+   -- Special definitions 
+   --mod1 <= ( sl_loop_j_rg ) mod 2;
+   --mod3 <= ( sl_loop_j_rg + 1 ) mod 2;
+
+   -- Entity and control variables
+   -- Release matrix expressions
+   e0 <= -mod1 + 1-mod3=0;
+   e1 <= -mod1=0;
+   e2 <= 1-mod1=0;
+
+   sl_fire <= b2std(e0);
+
+   -- Convert FIFO Read Port ND_6IP_3 Argument in_1 : ED_3 : 0 of type IOMM
+   sl_obtain0 <= ('1');  -- set obtain/release to const value; not used
+   sl_release0 <= ('1');
+
+   sl_CONTROL(0) <= sl_fire and b2std((e1));
+   OBTAIN(0) <= sl_obtain0;
+   RELEASE(0) <= sl_release0;
+
+   -- Convert FIFO Read Port ND_6IP_5_ND_6IP_4 Argument in_2 : ED_4_5 : 1 of type IOMM
+   sl_obtain1 <= ('1');  -- set obtain/release to const value; not used
+   sl_release1 <= ('1');
+
+   sl_CONTROL(1) <= sl_fire and b2std((e2));
+   OBTAIN(1) <= sl_obtain1;
+   RELEASE(1) <= sl_release1;
+
+   FIRE <= sl_fire;
+
+   cnt_rst <= sl_cnt_rst or RST;
+
+   -- 
+   -- =============================================
+   -- =             Multirate                      
+   -- =============================================
+   -- Function input parameter "in_0", multirate=1 
+   CNTR_MR0 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(0),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_0,
+         UPPER_BND => sl_mr_ubnd_0,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(0)
+      );
+   -- READ_EN indicates if READ_MUX can read data
+   sl_bla_en   <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');  
+   READ_EN     <= (others=>'0') when (HALT='1') else sl_bla_en;  
+   sl_mr_en   <= READ_ST; 
+   sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en); 
+   sl_enable  <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce 
+   ENABLE     <=  sl_enable or (not sl_fire);
+   -- 
+   LOCK_PRCS: process(CLK) 
+   begin 
+       if rising_edge(CLK) then 
+           if( RST = '1' ) then 
+               sl_mr_lock <= (others=>'0'); 
+           else  
+               if (ENABLE='1') then 
+                   sl_mr_lock <= (others=>'0'); 
+               else 
+                   for i in 0 to 0 loop 
+                       if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then 
+                           sl_mr_lock(i) <= '1'; 
+                       end if; 
+                   end loop; 
+               end if; 
+           end if; 
+       end if; 
+   end process; 
+   -- END of Multirate definitions 
+   -- 
+   -- =============================================
+   -- =             Iterators                      
+   -- =============================================
+   GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
+   	CNTR_RD : counter
+   	generic map ( 
+   		C_STEP    => CNTR_STEP(i),
+   		C_WIDTH   => CNTR_WIDTH(i)
+   	)
+  	 port map (
+   		CLK       => CLK,
+   		RST       => cnt_rst,
+   		ENABLE    => sl_cntr_en(i),
+			LOAD      => sl_load(i),
+   		LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		ITERATOR  => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		REG_CNTR  => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		DONE      => sl_done(i)
+   	);
+   end generate;
+   --
+   DONE_PRCS: process(CLK)
+   begin
+   	if rising_edge(CLK) then
+          if( RST = '1' ) then
+   		    sl_stop     <= '0';
+   		    sl_done_all <= '0';
+   		    sl_sof      <= '1';
+   	    else 
+   		    if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+   			    sl_stop <= '1';
+   		    elsif (WRAP=true) then
+   			    sl_stop <= '0';
+   		    end if;
+   		    if (sl_stop='0') then
+   			    sl_done_all <= sl_cntr_en(N_CNTRS);
+   		    end if;
+   		    if (ENABLE='1') then
+   			    sl_sof <= sl_eof;
+   		    end if;
+   	    end if;
+   	end if;
+   end process;
+   --
+   sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+   CONTROL <= sl_CONTROL;
+   --
+   REG_CNTRS <= sl_reg_cntrs; 
+   DONE <= sl_done_all;     -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+   STOP <= sl_stop;         -- '1' = The couter stoped after the end of the itteration space. 
+   --
+   sl_count      <=  '0' when (sl_stop='1') else
+                     '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
+   sl_cntr_en(0) <=  sl_count; -- makes the EVAL_LOGIC count
+   --
+   sl_cntr_en(N_CNTRS  downto 1) <= sl_cntr_en(N_CNTRS-1  downto 0) and sl_done(N_CNTRS-1  downto 0);
+   sl_eof <= sl_cntr_en(N_CNTRS);   -- End-of-frame
+   --
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_6/src/vhdl/bunny_static_split2rtl_hwn_nd_6_eval_logic_wr.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_6/src/vhdl/bunny_static_split2rtl_hwn_nd_6_eval_logic_wr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c1cb91e7857afa6b13fe7378052cec709bda65d0
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_6/src/vhdl/bunny_static_split2rtl_hwn_nd_6_eval_logic_wr.vhd
@@ -0,0 +1,395 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_6 is
+   generic ( 
+      N_OUT_PORTS   : natural := 1;
+      WRAP          : boolean := true;
+      N_CNTRS       : natural := 1;
+      QUANT         : natural := 32;
+      PAR_BITWIDTH  : natural :=1;
+      CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+      CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST           : in  std_logic;
+      CLK           : in  std_logic;
+      WRITE_EN      : out std_logic_vector(3 downto 0);
+      WRITE_ST      : in  std_logic_vector(3 downto 0);
+      HALT          : in  std_logic;
+      FIRE          : out std_logic;
+      DONE          : out std_logic;
+      STOP          : out std_logic;
+      CONTROL       : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+   );
+end bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_6;
+
+architecture RTL of bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_6 is	
+   -- 
+   component counter is 
+      generic( 
+         C_STEP    : natural := 10; 
+         C_WIDTH   : natural := 10 
+      ); 
+      port ( 
+         RST       : in  std_logic; 
+         CLK       : in  std_logic; 
+         ENABLE    : in  std_logic; 
+         LOAD      : in  std_logic; 
+         LOWER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         UPPER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         ITERATOR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         REG_CNTR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         DONE      : out std_logic 
+      ); 
+   end component; 
+   -- 
+   component it_mod is 
+   generic( 
+      C_MOD     : natural := 10; 
+      C_WIDTH   : natural := 10; 
+      C_INIT    : natural :=  1; 
+      C_STEP    : natural :=  1  
+   ); 
+   port ( 
+      RST       : in  std_logic; 
+      CLK       : in  std_logic; 
+      LOAD      : in  std_logic; 
+      ENABLE    : in  std_logic; 
+      MODULE    : out std_logic_vector(C_WIDTH-1 downto 0) 
+   ); 
+   end component; 
+   -- 
+   -- Multirate related signals
+   signal sl_bla_en   : std_logic_vector(3 downto 0); 
+   signal sl_mr_en    : std_logic_vector(3 downto 0); 
+   signal sl_mr_done  : std_logic_vector(3 downto 0); 
+   signal sl_mr_lock  : std_logic_vector(3 downto 0); 
+   signal sl_enables  : std_logic_vector(3 downto 0); 
+   signal sl_enable   : std_logic; 
+   signal ENABLE      : std_logic; 
+   -- Function output parameter "out_0", multirate=1 
+   constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   -- Function output parameter "out_1", multirate=1 
+   constant sl_mr_lbnd_1 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_1 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   -- Function output parameter "out_2", multirate=1 
+   constant sl_mr_lbnd_2 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_2 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   -- Function output parameter "out_3", multirate=1 
+   constant sl_mr_lbnd_3 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_3 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   --  
+   -- Parameter related signals 
+   --  
+   -- Iterator (counter) related signals 
+   signal sl_low_i, sl_high_i : integer; 
+   signal sl_low_j, sl_high_j : integer; 
+   signal sl_loop_i, sl_loop_i_rg : integer;
+   signal sl_loop_j, sl_loop_j_rg : integer;
+   signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   -- 
+   signal sl_cntr_en  : std_logic_vector(N_CNTRS   downto 0); 
+   signal sl_done     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_done_all : std_logic; 
+   signal sl_load     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_stop     : std_logic; 
+   signal sl_fire     : std_logic; 
+   signal sl_eof      : std_logic; 
+   signal sl_sof      : std_logic; 
+   signal sl_count    : std_logic; 
+   -- 
+   -- Special Control signal
+   signal sl_CONTROL       : std_logic_vector(N_OUT_PORTS-1 downto 0);
+   signal sl_no_request    : std_logic;
+   -- 
+   -- alias signals 
+   alias update_i : std_logic is sl_cntr_en(1);
+   alias update_j : std_logic is sl_cntr_en(0);
+   -- 
+   alias load_i : std_logic is sl_load(1);
+   alias load_j : std_logic is sl_load(0);
+   -- Trigger signals 
+   signal sl_trigger_i : std_logic;
+   signal sl_trigger_j : std_logic;
+
+   signal e0 : boolean;
+
+   -- define control variables 
+   -- MOD related signals 
+   signal div1 : integer;
+   signal div2 : integer;
+   signal mod1 : integer;
+   signal mod3 : integer;
+
+
+   type state_type is (s_idle, s_halt, s_count, s_release);
+   signal state : state_type;
+   signal halt_cnt : integer;
+   signal sl_halt : std_logic;
+
+   signal sl_cnt_rst : std_logic;
+   signal cnt_rst : std_logic;
+   signal j0_mod_2 : std_logic_vector(1-1 downto 0);
+   signal j1_mod_2 : std_logic_vector(1-1 downto 0);
+
+begin
+
+   -- =============================================
+   -- =             MOD Functions                  
+   -- =============================================
+   -- MOD function: j % 2 == 0
+   INST_mod1 : it_mod
+   generic map(
+      C_MOD     => 2,
+      C_WIDTH   => 1,
+      C_INIT    => 0,
+      C_STEP    => 1
+   )
+   port map(
+      RST       => RST,
+      CLK       => CLK,
+      LOAD      => sl_done(0),
+      ENABLE    => sl_cntr_en(0),
+      MODULE    => j0_mod_2
+   );
+   mod1 <= TO_INTEGER(UNSIGNED(j0_mod_2));
+   -- 
+   -- MOD function: j+1 % 2 == 1
+   INST_mod3 : it_mod
+   generic map(
+      C_MOD     => 2,
+      C_WIDTH   => 1,
+      C_INIT    => 1,
+      C_STEP    => 1
+   )
+   port map(
+      RST       => RST,
+      CLK       => CLK,
+      LOAD      => sl_done(0),
+      ENABLE    => sl_cntr_en(0),
+      MODULE    => j1_mod_2
+   );
+   mod3 <= TO_INTEGER(UNSIGNED(j1_mod_2));
+   -- 
+   -- END of MOD definitions 
+   --  
+   -- Parameter related signal assignments 
+   sl_cnt_rst <= '0';
+   sl_halt <= HALT;
+   -- END of Parameter definitions 
+
+   sl_loop_i    <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_i_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_j    <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+   sl_loop_j_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+   -- Const bounds for-loops 
+   sl_low_i  <= 0;
+   sl_high_i <= 359;
+   sl_low_j  <= 0;
+   sl_high_j <= 639;
+
+
+   load_i <= '0';
+   load_j <= '0';
+
+   sl_lower_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
+   sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
+
+   sl_upper_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
+   sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
+
+   -- Special definitions 
+   --mod1 <= ( sl_loop_j_rg ) mod 2;
+   --mod3 <= ( sl_loop_j_rg + 1 ) mod 2;
+
+   -- Entity and control variables
+   e0 <= -mod1 + 1-mod3=0;
+
+   sl_fire <= b2std(e0);
+
+   -- Convert FIFO Write Port out_1 : ED_6
+   sl_CONTROL(0) <= sl_fire and ('1');
+
+   -- Convert FIFO Write Port out_2 : ED_7
+   sl_CONTROL(1) <= sl_fire and ('1');
+
+   -- Convert FIFO Write Port out_3 : ED_8
+   sl_CONTROL(2) <= sl_fire and ('1');
+
+   FIRE <= sl_fire;
+
+   cnt_rst <= sl_cnt_rst or RST;
+
+   -- 
+   -- =============================================
+   -- =             Multirate                      
+   -- =============================================
+   -- Function output parameter "out_0", multirate=1 
+   CNTR_MR0 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(0),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_0,
+         UPPER_BND => sl_mr_ubnd_0,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(0)
+      );
+   -- Function output parameter "out_1", multirate=1 
+   CNTR_MR1 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(1),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_1,
+         UPPER_BND => sl_mr_ubnd_1,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(1)
+      );
+   -- Function output parameter "out_2", multirate=1 
+   CNTR_MR2 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(2),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_2,
+         UPPER_BND => sl_mr_ubnd_2,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(2)
+      );
+   -- Function output parameter "out_3", multirate=1 
+   CNTR_MR3 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(3),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_3,
+         UPPER_BND => sl_mr_ubnd_3,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(3)
+      );
+   -- 
+   -- WRITE_EN indicates if date can be written to WRITE_MUX
+   sl_bla_en      <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
+   WRITE_EN    <=  (others=>'0') when (HALT='1') else sl_bla_en;
+   -- 
+   sl_mr_en    <= (not sl_mr_lock) and WRITE_ST; 
+   sl_enables  <= sl_mr_lock or (sl_mr_done and sl_mr_en); 
+   sl_enable   <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0';  -- and_reduce 
+   ENABLE      <= sl_enable or (not sl_fire);
+   -- 
+   LOCK_PRCS: process(CLK) 
+   begin 
+       if rising_edge(CLK) then 
+           if( RST = '1' ) then 
+               sl_mr_lock <= (others=>'0'); 
+           else  
+               if (ENABLE='1') then 
+                   sl_mr_lock <= (others=>'0'); 
+               else 
+                   for i in 0 to 3 loop 
+                       if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then 
+                           sl_mr_lock(i) <= '1'; 
+                       end if; 
+                   end loop; 
+               end if; 
+           end if; 
+       end if; 
+   end process; 
+   -- END of Multirate definitions 
+   -- 
+   -- =============================================
+   -- =             Iterators                      
+   -- =============================================
+   GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
+   	CNTR_WR : counter
+   	generic map ( 
+   		C_STEP    => CNTR_STEP(i),
+   		C_WIDTH   => CNTR_WIDTH(i)
+   	)
+  	 port map (
+   		CLK       => CLK,
+   		RST       => cnt_rst,
+   		ENABLE    => sl_cntr_en(i),
+   		LOAD      => sl_load(i),
+   		LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		ITERATOR  => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		REG_CNTR  => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		DONE      => sl_done(i)
+   	);
+   end generate;
+   --
+   DONE_PRCS: process(CLK)
+   begin
+   	if rising_edge(CLK) then
+   	    if( RST = '1' ) then
+   		    sl_stop     <= '0';
+   		    sl_done_all <= '0';
+   		    sl_sof      <= '1';
+   	    else 
+   		    if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+   			    sl_stop <= '1';
+   		    elsif (WRAP=true) then
+   			    sl_stop <= '0';
+   		    end if;
+   		    if (sl_stop='0') then
+   			    sl_done_all <= sl_cntr_en(N_CNTRS);
+   		    end if;
+   		    if (ENABLE='1') then
+   			    sl_sof <= sl_eof;
+   		    end if;
+   	    end if;
+   	end if;
+   end process;
+   --
+   sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+   CONTROL <= sl_CONTROL;
+   --
+   DONE <= sl_done_all;     -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+   STOP <= sl_stop;         -- '1' = The couter stoped after the end of the itteration space. 
+   --
+   sl_count      <=  '0' when (sl_stop='1') else
+   			'1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
+   sl_cntr_en(0) <=  sl_count; -- makes the EVAL_LOGIC count
+   --
+   sl_cntr_en(N_CNTRS  downto 1) <= sl_cntr_en(N_CNTRS-1  downto 0) and sl_done(N_CNTRS-1  downto 0);
+   sl_eof <= sl_cntr_en(N_CNTRS);      -- End-of-frame (combinatorial; beter not use it outside)
+   --
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_6/src/vhdl/bunny_static_split2rtl_hwn_nd_6_execution_unit.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_6/src/vhdl/bunny_static_split2rtl_hwn_nd_6_execution_unit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..448ca45d0eec9c458172ae3e5705cf12de4d6595
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_6/src/vhdl/bunny_static_split2rtl_hwn_nd_6_execution_unit.vhd
@@ -0,0 +1,120 @@
+-- Execute Unit automatically generated by KpnMapper
+-- Function "deserialize32to4t8"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_bunny_static_split2rtl_functions_1_lib;
+use compaandesign_com_bunny_static_split2rtl_functions_1_lib.all;
+
+entity bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_6 is
+   generic (
+      N_INPORTS  : natural := 1;
+      N_OUTPORTS : natural := 1;
+      IP_RESET   : natural := 1; 
+      STIM_DIR   : string  := "bla";
+      QUANT      : natural := 32;
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1; 
+      CNTR_QUANT : natural := 32; 
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+   );
+   port (
+      RST        : in  std_logic;
+      CLK        : in  std_logic;
+      -- Funtion Input parameters
+      IN_PORT_0    : in  std_logic_vector(31 downto 0);  -- Param. "stimin"
+      READ       : out std_logic_vector(N_INPORTS-1 downto 0);
+      EXIST      : in  std_logic_vector(N_INPORTS-1 downto 0);
+      -- Iterators
+      REG_CNTRS_RD : in  std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
+      -- Funtion Output parameters
+      OUT_PORT_0   : out std_logic_vector(7 downto 0);  -- Param. "out0"
+      OUT_PORT_1   : out std_logic_vector(7 downto 0);  -- Param. "out1"
+      OUT_PORT_2   : out std_logic_vector(7 downto 0);  -- Param. "out2"
+      OUT_PORT_3   : out std_logic_vector(7 downto 0);  -- Param. "out3"
+      WRITE      : out std_logic_vector(N_OUTPORTS-1 downto 0);
+      FULL       : in  std_logic_vector(N_OUTPORTS-1 downto 0);
+      STOP_RD    : in  std_logic;
+      STOP_WR    : in  std_logic;
+      ERROR      : out std_logic
+   );
+end bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_6 ;
+
+-- Laura implementation
+architecture Laura of bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_6 is
+
+   component deserialize32to4t8 is
+      generic (
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1; 
+         CNTR_QUANT : natural := 32; 
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST   : in std_logic;
+         CLK   : in std_logic;
+         -- Inputs 
+         ip_stimin  : in  std_logic_vector(31 downto 0);  
+         -- Iterators 
+         it_j : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+         it_i : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+         EXIST : in  std_logic_vector(0 downto 0);
+         READF : out std_logic_vector(0 downto 0);
+         -- Outputs 
+         op_out0 : out std_logic_vector(7 downto 0);
+         op_out1 : out std_logic_vector(7 downto 0);
+         op_out2 : out std_logic_vector(7 downto 0);
+         op_out3 : out std_logic_vector(7 downto 0);
+         FULL  : in  std_logic_vector(3 downto 0);
+         WRITEF: out std_logic_vector(3 downto 0);
+         --
+         STOP_RD : in  std_logic;
+         STOP_WR : in  std_logic;
+         ERROR   : out std_logic
+      );
+   end component;
+
+   signal sl_RST : std_logic;
+
+begin
+
+   sl_RST <= RST when IP_RESET=1 else not RST;
+
+   FUNC : deserialize32to4t8
+   generic map (
+         STIM_DIR      => STIM_DIR,
+         c_STAGES      => c_STAGES,
+         N_CNTRS       => N_CNTRS,
+         CNTR_QUANT    => CNTR_QUANT,
+         CNTR_WIDTH    => CNTR_WIDTH
+   )
+   port map (
+      RST   => sl_RST,
+      CLK   => CLK,
+      -- Inputs 
+      ip_stimin => IN_PORT_0,
+      -- Iterators 
+      it_j => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
+      it_i => REG_CNTRS_RD(1*CNTR_QUANT+CNTR_WIDTH(1)-1 downto 1*CNTR_QUANT),
+      EXIST => EXIST,
+      READF => READ,
+      -- Outputs 
+      op_out0 => OUT_PORT_0,
+      op_out1 => OUT_PORT_1,
+      op_out2 => OUT_PORT_2,
+      op_out3 => OUT_PORT_3,
+      FULL  => FULL,
+      WRITEF=> WRITE,
+      -- 
+      STOP_RD => STOP_RD,
+      STOP_WR => STOP_WR,
+      ERROR   => ERROR
+   );
+
+end Laura;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_7/hdllib.cfg b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_7/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..878c2ddfd510de08171d8a48864b4035e0c1b29c
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_7/hdllib.cfg
@@ -0,0 +1,18 @@
+hdl_lib_name = compaandesign_com_bunny_static_split2rtl_hwn_nd_7_1
+hdl_library_clause_name = compaandesign_com_bunny_static_split2rtl_hwn_nd_7_1_lib
+hdl_lib_uses_synth = compaandesign_com_bunny_static_split2rtl_functions_1 compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1 compaandesign_com_common_extern_connector_1 
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+	src/vhdl/bunny_static_split2rtl_hwn_nd_7_execution_unit.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_7_eval_logic_rd.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_7_eval_logic_wr.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_7.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_7/src/vhdl/bunny_static_split2rtl_hwn_nd_7.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_7/src/vhdl/bunny_static_split2rtl_hwn_nd_7.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1f62c2b6e3c4fc0baf756d2e4c2f2300a5fb80f3
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_7/src/vhdl/bunny_static_split2rtl_hwn_nd_7.vhd
@@ -0,0 +1,495 @@
+-- HWN Entity File automatically generated by KpnMapper (writeHdlHWNodeFile)
+-- Top level file for a Hardware Accelerator
+-- Function "compaan_outlinedproc2"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+library compaandesign_com_common_extern_connector_1_lib;
+use compaandesign_com_common_extern_connector_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_7 is
+   generic (
+      STIM_DIR   : string  := "bla";
+      RESET_HIGH : natural := 1;
+      PAR_WIDTH  : natural := 16;
+      QUANT      : natural := 32;
+      WRAP       : boolean := true
+   );
+   port (
+
+      -- Dataflow input interfaces
+      -- ED_6 : in_0
+      ND_7IP_6_Rd    : out std_logic;
+      ND_7IP_6_Din   : in  std_logic_vector(7 downto 0);
+      ND_7IP_6_Exist : in  std_logic; 
+      ND_7IP_6_CLK   : out std_logic;
+      ND_7IP_6_CTRL  : in  std_logic;
+
+      -- ED_7 : in_0
+      ND_7IP_7_Rd    : out std_logic;
+      ND_7IP_7_Din   : in  std_logic_vector(7 downto 0);
+      ND_7IP_7_Exist : in  std_logic; 
+      ND_7IP_7_CLK   : out std_logic;
+      ND_7IP_7_CTRL  : in  std_logic;
+
+      -- ED_8 : in_0
+      ND_7IP_8_Rd    : out std_logic;
+      ND_7IP_8_Din   : in  std_logic_vector(7 downto 0);
+      ND_7IP_8_Exist : in  std_logic; 
+      ND_7IP_8_CLK   : out std_logic;
+      ND_7IP_8_CTRL  : in  std_logic;
+
+      -- Dataflow Control Input interfaces
+      -- Dataflow output interfaces
+      -- ED_9 : out_0
+      ND_7OP_1_Wr   : out std_logic;
+      ND_7OP_1_Dout : out std_logic_vector(7 downto 0);
+      ND_7OP_1_Full : in  std_logic;
+      ND_7OP_1_CLK  : out std_logic;
+      ND_7OP_1_CTRL : out std_logic;
+
+      -- ED_10 : out_0
+      ND_7OP_1_d1_Wr   : out std_logic;
+      ND_7OP_1_d1_Dout : out std_logic_vector(7 downto 0);
+      ND_7OP_1_d1_Full : in  std_logic;
+      ND_7OP_1_d1_CLK  : out std_logic;
+      ND_7OP_1_d1_CTRL : out std_logic;
+
+      PARAM_DT : in  std_logic_vector(PAR_WIDTH+10-1 downto 0);
+      PARAM_LD : in  std_logic;
+
+      RST      : in  std_logic;
+      CLK      : in  std_logic;
+      STOP     : out std_logic;
+      ERROR    : out std_logic;
+      BLOCK_RD : out std_logic
+   );
+end bunny_static_split2rtl_hwn_nd_7;
+
+architecture RTL of bunny_static_split2rtl_hwn_nd_7 is
+   --
+   -- ====================================
+   -- =     Constants declaration        =
+   -- ====================================
+   -- Setting the parameters of the HW Node
+   constant c_IN_PORTS     : natural := 3; -- number of input ports of a HW node
+   constant c_OUT_PORTS    : natural := 2; -- number of output ports of a HW node
+   constant c_IN_FUNC_VAR  : natural := 1; -- number of input ports of a HW IP
+   constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
+   constant c_COUNTERS     : natural := 3; -- number of iterators
+   -- ===========================================
+   -- = Iterators run from Inner to Outer loop  =
+   -- ===========================================
+   constant c_CNTR_QUANT   : natural := 11;
+   constant c_CNTR_STEPS   : t_counter_step  := ( 0=>1, 1=>1, 2=>1, others=>1 );
+   constant c_CNTR_WIDTHS  : t_counter_width := ( 0=>3, 1=>11, 2=>10, others=>10 );
+   constant c_STAGES       : natural := 1; -- number of pipeline stages or delay
+   constant c_IP_RESET     : natural := 1; -- active level of the HW IP reset signal
+   constant c_WRAP         : boolean := WRAP; -- Operation mode: Single_Shot (false) or Continuous (true)
+   constant c_EXT_PAR      : natural := 0; -- number of external parameters
+   constant c_INT_PAR      : natural := 0; -- number of internal parameters
+   constant c_N_PAR        : natural := 0; -- no parameters are used
+   constant c_PAR_BITWIDTH : natural := PAR_WIDTH; -- aggregate bitwidth of the parameter vector
+   constant c_PAR_VECTOR   : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
+       (0,0,0,0), (0,0,0,0)    -- two dummy elements
+   );
+   --
+   -- ====================================
+   -- =     Components declaration       =
+   -- ====================================
+   component bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_7 is
+      generic (
+         N_IN_PORTS    : natural := 1;
+         WRAP          : boolean := true;
+         N_CNTRS       : natural := 1; 
+         QUANT         : natural := 32;
+         PAR_BITWIDTH  : natural :=1;
+         CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+         CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+      );
+      port (
+         RST           : in  std_logic;
+         CLK           : in  std_logic;
+         REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1  downto 0); 
+         READ_EN       : out std_logic_vector(c_IN_FUNC_VAR-1  downto 0);
+         READ_ST       : in  std_logic_vector(c_IN_FUNC_VAR-1  downto 0);
+         HALT          : in  std_logic;
+         FIRE          : out std_logic;
+         DONE          : out std_logic;
+         STOP          : out std_logic;
+         CONTROL       : out std_logic_vector(N_IN_PORTS-1 downto 0);
+         OBTAIN        : out std_logic_vector(N_IN_PORTS-1 downto 0);
+         RELEASE       : out std_logic_vector(N_IN_PORTS-1 downto 0)
+      );
+   end component;
+
+   component READ_MUX is
+      generic (
+         N_PORTS    : natural := 1;
+         PORT_WIDTH : natural := 32  
+      );
+      port(
+         IN_PORTS   : in  std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
+         EXISTS     : in  std_logic_vector(N_PORTS-1 downto 0);
+         READS      : out std_logic_vector(N_PORTS-1 downto 0);
+         SOFS       : in  std_logic_vector(N_PORTS-1 downto 0);
+
+         OUT_PORT   : out std_logic_vector(PORT_WIDTH-1 downto 0);
+         EXIST      : out std_logic;
+         READ       : in  std_logic;
+         SOF        : in  std_logic;
+		CLK        : in std_logic;
+
+         READ_EN    : in  std_logic;
+         READ_ST    : out std_logic;
+         CONTROL    : in  std_logic_vector(N_PORTS-1 downto 0);
+         OBTAIN     : in  std_logic_vector(N_PORTS-1 downto 0);
+         RELEASE    : in  std_logic_vector(N_PORTS-1 downto 0)
+      );
+   end component;
+
+   component bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_7 is
+      generic ( 
+         N_OUT_PORTS   : natural := 1;
+         WRAP          : boolean := true;
+         N_CNTRS       : natural := 1; 
+         QUANT         : natural := 32;
+         PAR_BITWIDTH  : natural :=1;
+         CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+         CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+      );
+      port (
+         RST           : in  std_logic;
+         CLK           : in  std_logic;
+         WRITE_EN      : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+         WRITE_ST      : in  std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+         HALT          : in  std_logic;
+         FIRE          : out std_logic;
+         DONE          : out std_logic;
+         STOP          : out std_logic;
+         CONTROL       : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+      );
+   end component;
+
+   component WRITE_DEMUX is
+      generic (
+         N_PORTS : natural := 1
+      );
+      port(
+         WRITES   : out std_logic_vector(N_PORTS-1 downto 0);
+         WRITE    : in  std_logic;
+
+         FULLS    : in  std_logic_vector(N_PORTS-1 downto 0);
+         FULL     : out std_logic;
+
+         WRITE_EN : in  std_logic;
+         WRITE_ST : out std_logic;
+         CONTROL  : in  std_logic_vector(N_PORTS-1 downto 0)
+      );
+   end component;
+
+
+   component bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_7 is
+      generic (
+         N_INPORTS  : natural := 1;
+         N_OUTPORTS : natural := 1;
+         IP_RESET   : natural := 1;
+         QUANT      : natural := 32;
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1;
+         CNTR_QUANT : natural := 32;
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST        : in  std_logic;
+         CLK        : in  std_logic;
+
+         -- Iterators
+         REG_CNTRS_RD : in  std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
+         -- Func. Input parameters
+         IN_PORT_0 : in  std_logic_vector(7 downto 0); -- tmp1
+         READ       : out std_logic_vector(N_INPORTS-1 downto 0);
+         EXIST      : in  std_logic_vector(N_INPORTS-1 downto 0);
+         -- Func. Output parameters
+         OUT_PORT_0 : out std_logic_vector(7 downto 0); -- tmp0
+         WRITE      : out std_logic_vector(N_OUTPORTS-1 downto 0);
+         FULL       : in  std_logic_vector(N_OUTPORTS-1 downto 0);
+         --
+         STOP_RD    : in  std_logic;
+         STOP_WR    : in  std_logic;
+         ERROR      : out std_logic
+      );
+   end component;
+
+   component INTERNAL_PARAMETERS is 
+      generic (
+         PAR_BITWIDTH : natural:=1;
+         PAR_VECTOR   : t_par_vector;
+         N_PAR        : natural:=0;
+         START_IN_RUN  : boolean := FALSE
+      );
+      port (  
+         RST        : in  std_logic;
+         CLK        : in  std_logic;
+
+         HALT_RD    : out std_logic;
+         HALT_WR    : out std_logic;
+         SOF_RD     : in  std_logic;
+         SOF_WR     : in  std_logic;
+         LOAD_PARAM : out std_logic;
+
+         par_one_in_Rd    : out std_logic;
+         par_one_in_Din   : in std_logic_vector(32-1 downto 0);
+         par_one_in_Exist : in std_logic;
+         par_one_in_CLK   : out std_logic;
+         par_one_in_CTRL  : in std_logic;
+
+         PARAMETERS_RD : out std_logic_vector(32-1 downto 0);
+         PARAMETERS_WR : out std_logic_vector(32-1 downto 0)
+      );
+   end component;
+
+   --
+   -- ====================================
+   -- =       Signals declaration        =
+   -- ====================================
+   -- 
+   -- HW Node Input Ports
+   signal sl_IN_PORTS_0   : std_logic_vector(3*8-1 downto 0); -- tmp1
+   signal sl_EXISTS       : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_READS        : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_CTRLS        : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_control_rd   : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_obtain_rd    : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_release_rd   : std_logic_vector(c_IN_PORTS-1 downto 0);
+   -- 
+   -- Func. Input parameters
+   signal sl_in_port_0    : std_logic_vector(7 downto 0); -- tmp1
+   signal sl_exist        : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read         : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read_en      : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read_st      : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   -- 
+   signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
+   -- 
+   -- HW Node Output Ports
+   signal sl_WRITES       : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_FULLS        : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_control_wr   : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_lortnoc_wr   : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   -- 
+   -- Func. Output parameters
+   signal sl_out_port_0   : std_logic_vector(7 downto 0); -- tmp0
+   signal sl_full         : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write        : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write_en     : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write_st     : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   -- 
+   -- 
+   signal sl_halt             : std_logic;
+   signal sl_halted           : std_logic;
+   signal sl_halt_wr          : std_logic;
+   signal sl_halt_rd          : std_logic;
+   signal sl_param_halt_wr    : std_logic;
+   signal sl_param_halt_rd    : std_logic;
+   signal sl_done_wr          : std_logic;
+   signal sl_done_rd          : std_logic;
+   signal sl_stop_wr          : std_logic;
+   signal sl_stop_rd          : std_logic;
+   signal sl_fire_wr          : std_logic;
+   signal sl_fire_rd          : std_logic;
+   signal sl_sof_wr           : std_logic;
+   signal sl_sof_rd           : std_logic;
+   signal sl_error            : std_logic;
+   signal sl_load_param       : std_logic;
+
+   --  
+   -- Parameter related signals 
+   signal sl_param_fifo_full     : std_logic;
+   signal sl_sync_num            : std_logic_vector(9 downto 0);
+
+   signal sl_RST : std_logic;
+
+begin 
+
+   sl_RST <= RST when RESET_HIGH=1 else not RST;
+      ND_7IP_6_CLK   <= CLK;
+      ND_7IP_7_CLK   <= CLK;
+      ND_7IP_8_CLK   <= CLK;
+      ND_7OP_1_CLK  <= CLK;
+      ND_7OP_1_d1_CLK  <= CLK;
+
+   --
+   -- ==========================================================
+   -- =       HWN Input related modules                        =
+   -- ==========================================================
+   -- Func. Input param. "tmp1"
+   RD_MUX_0 : READ_MUX
+   generic map (
+      N_PORTS    => 3,
+      PORT_WIDTH => 8
+   )
+   port map (
+      IN_PORTS   => sl_IN_PORTS_0,
+      EXISTS     => sl_EXISTS(2 downto 0),
+      READS      => sl_READS(2 downto 0),
+      SOFS       => sl_CTRLS(2 downto 0),
+
+      OUT_PORT   => sl_in_port_0,
+      EXIST      => sl_exist(0),
+      READ       => sl_read(0),
+      SOF        => sl_sof_rd,
+      CLK        => CLK,
+
+      READ_EN    => sl_read_en(0),
+      READ_ST    => sl_read_st(0),
+      CONTROL    => sl_control_rd(2 downto 0),
+      OBTAIN     => sl_obtain_rd(2 downto 0),
+      RELEASE    => sl_release_rd(2 downto 0)
+   );
+
+   ND_7IP_6_Rd   <= sl_READS(0);
+   ND_7IP_7_Rd   <= sl_READS(1);
+   ND_7IP_8_Rd   <= sl_READS(2);
+
+   sl_IN_PORTS_0 <= ND_7IP_8_Din & ND_7IP_7_Din & ND_7IP_6_Din;
+
+   sl_EXISTS      <= ND_7IP_8_Exist & ND_7IP_7_Exist & ND_7IP_6_Exist ;
+   sl_CTRLS       <= ND_7IP_8_CTRL & ND_7IP_7_CTRL & ND_7IP_6_CTRL ;
+
+   EVAL_RD : bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_7
+   generic map ( 
+      N_IN_PORTS    => c_IN_PORTS,
+      WRAP          => c_WRAP,
+      N_CNTRS       => c_COUNTERS,
+      QUANT         => c_CNTR_QUANT,
+      PAR_BITWIDTH  => c_PAR_BITWIDTH,
+      CNTR_STEP     => c_CNTR_STEPS,
+      CNTR_WIDTH    => c_CNTR_WIDTHS
+   )
+   port map(
+      RST           => sl_RST,
+      CLK           => CLK,
+      REG_CNTRS     => sl_REG_CNTRS_RD,
+      READ_EN       => sl_read_en,
+      READ_ST       => sl_read_st,
+      HALT          => sl_halt_rd,
+      FIRE          => sl_fire_rd,
+      DONE          => sl_done_rd,
+      STOP          => sl_stop_rd,
+      CONTROL       => sl_control_rd,
+      OBTAIN        => sl_obtain_rd,
+      RELEASE       => sl_release_rd
+   );
+
+   --
+   -- ==========================================================
+   -- =       HWN Output related modules                       =
+   -- ==========================================================
+   -- 
+   -- Func. Output param. "tmp0"
+   DEMUX_0 : WRITE_DEMUX
+   generic map (
+      N_PORTS => 2
+   )
+   port map (
+      WRITES   => sl_WRITES(1 downto 0),
+      FULLS    => sl_FULLS(1 downto 0),
+      CONTROL  => sl_lortnoc_wr(1 downto 0),
+      WRITE    => sl_write(0),
+      FULL     => sl_full(0),
+      WRITE_EN => sl_write_en(0),
+      WRITE_ST => sl_write_st(0)
+   );
+   --
+   ND_7OP_1_Dout <= sl_out_port_0;  -- Func. Output param. "tmp0"
+   ND_7OP_1_CTRL <= sl_sof_wr ;
+   ND_7OP_1_Wr   <= sl_WRITES(0);
+   sl_FULLS(0) <= ND_7OP_1_Full;
+   sl_lortnoc_wr(0) <= sl_control_wr(0);
+   --
+   ND_7OP_1_d1_Dout <= sl_out_port_0;  -- Func. Output param. "tmp0"
+   ND_7OP_1_d1_CTRL <= sl_sof_wr ;
+   ND_7OP_1_d1_Wr   <= sl_WRITES(1);
+   sl_FULLS(1) <= ND_7OP_1_d1_Full;
+   sl_lortnoc_wr(1) <= sl_control_wr(1);
+   --
+   --
+   EVAL_WR : bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_7
+   generic map ( 
+      N_OUT_PORTS   => c_OUT_PORTS,
+      WRAP          => c_WRAP,
+      N_CNTRS       => c_COUNTERS,
+      QUANT         => c_CNTR_QUANT,
+      PAR_BITWIDTH  => c_PAR_BITWIDTH,
+      CNTR_STEP     => c_CNTR_STEPS,
+      CNTR_WIDTH    => c_CNTR_WIDTHS
+   )
+   port map (
+      RST           => sl_RST,
+      CLK           => CLK,
+      WRITE_EN      => sl_write_en,
+      WRITE_ST      => sl_write_st,
+      HALT          => sl_halt_wr,
+      FIRE          => sl_fire_wr,
+      DONE          => sl_done_wr,
+      STOP          => sl_stop_wr,
+      CONTROL       => sl_control_wr
+   );
+
+   --
+   -- ==========================================================
+   -- =       HWN Execution Unit                               =
+   -- ==========================================================
+   EX : bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_7
+   generic map (
+      N_INPORTS  => c_IN_FUNC_VAR,
+      N_OUTPORTS => c_OUT_FUNC_VAR, 
+      IP_RESET   => c_IP_RESET,
+      QUANT      => QUANT,
+      STIM_DIR   => STIM_DIR,
+      c_STAGES   => c_STAGES,
+      N_CNTRS    => c_COUNTERS,
+      CNTR_QUANT => c_CNTR_QUANT,
+      CNTR_WIDTH => c_CNTR_WIDTHS
+   )
+   port map (
+      RST        => sl_RST,
+      CLK        => CLK,
+      -- Iterators
+      REG_CNTRS_RD => sl_REG_CNTRS_RD,
+      -- Func. Input parameters
+      IN_PORT_0    => sl_in_port_0,
+      READ       => sl_read,
+      EXIST      => sl_exist,
+      -- Func. Output parameters
+      OUT_PORT_0   => sl_out_port_0,
+      WRITE      => sl_write,
+      FULL       => sl_full,
+      --
+      STOP_WR    => sl_stop_wr,
+      STOP_RD    => sl_stop_rd,
+      ERROR      => sl_error
+   );
+
+   -- ==========================================================
+   -- =       PARAMETERIZATION                                 =
+   -- ==========================================================
+   -- no parameters
+   sl_halt_rd <= '0';
+   sl_halt_wr <= '0';
+--   sl_halted  <= sl_sof_rd;
+   STOP <= sl_done_wr;
+   ERROR <= sl_error;
+   BLOCK_RD <= not (  (  sl_READS(0) or   sl_READS(1) or   sl_READS(2)  ) );
+
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_7/src/vhdl/bunny_static_split2rtl_hwn_nd_7_eval_logic_rd.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_7/src/vhdl/bunny_static_split2rtl_hwn_nd_7_eval_logic_rd.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..efd7884d00e80f9e9a9c95ba4fdf8fbed614cbec
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_7/src/vhdl/bunny_static_split2rtl_hwn_nd_7_eval_logic_rd.vhd
@@ -0,0 +1,331 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_7 is
+   generic (
+      N_IN_PORTS    : natural := 1;
+      WRAP          : boolean := true;
+      N_CNTRS       : natural := 1; 
+      QUANT         : natural := 32;
+      PAR_BITWIDTH  : natural  :=1;
+      CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+      CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST           : in  std_logic;
+      CLK           : in  std_logic;
+      REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+      READ_EN       : out std_logic_vector(0 downto 0);
+      READ_ST       : in  std_logic_vector(0 downto 0);
+      HALT          : in  std_logic;
+      FIRE          : out std_logic;
+      DONE          : out std_logic;
+      STOP          : out std_logic;
+      CONTROL       : out std_logic_vector(N_IN_PORTS-1 downto 0);
+      OBTAIN        : out std_logic_vector(N_IN_PORTS-1 downto 0);
+      RELEASE       : out std_logic_vector(N_IN_PORTS-1 downto 0)
+   );
+end bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_7;
+
+architecture RTL of bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_7 is
+   -- 
+   component counter is 
+      generic( 
+         C_STEP    : natural := 10; 
+         C_WIDTH   : natural := 10 
+      ); 
+      port ( 
+         RST       : in  std_logic; 
+         CLK       : in  std_logic; 
+         ENABLE    : in  std_logic; 
+         LOAD      : in  std_logic; 
+         LOWER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         UPPER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         ITERATOR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         REG_CNTR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         DONE      : out std_logic 
+      ); 
+   end component; 
+   -- 
+   component it_mod is 
+   generic( 
+      C_MOD     : natural := 10; 
+      C_WIDTH   : natural := 10; 
+      C_INIT    : natural :=  1; 
+      C_STEP    : natural :=  1  
+   ); 
+   port ( 
+      RST       : in  std_logic; 
+      CLK       : in  std_logic; 
+      LOAD      : in  std_logic; 
+      ENABLE    : in  std_logic; 
+      MODULE    : out std_logic_vector(C_WIDTH-1 downto 0) 
+   ); 
+   end component; 
+   -- 
+   --  
+   -- Parameter related signals 
+   -- 
+   -- Iterator (counter) related signals 
+   signal sl_low_i, sl_high_i : integer;
+   signal sl_low_j, sl_high_j : integer;
+   signal sl_low_color, sl_high_color : integer;
+   signal sl_loop_i, sl_loop_i_rg : integer;
+   signal sl_loop_j, sl_loop_j_rg : integer;
+   signal sl_loop_color, sl_loop_color_rg : integer;
+   signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   -- 
+   signal sl_cntr_en  : std_logic_vector(N_CNTRS   downto 0); 
+   signal sl_done     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_done_all : std_logic; 
+   signal sl_load     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_stop     : std_logic; 
+   signal sl_fire     : std_logic; 
+   signal sl_sof      : std_logic; 
+   signal sl_eof      : std_logic; 
+   signal sl_count    : std_logic; 
+
+   -- alias signals 
+   alias update_i : std_logic is sl_cntr_en(2);
+   alias update_j : std_logic is sl_cntr_en(1);
+   alias update_color : std_logic is sl_cntr_en(0);
+   alias load_i : std_logic is sl_load(2);
+   alias load_j : std_logic is sl_load(1);
+   alias load_color : std_logic is sl_load(0);
+
+   -- Trigger signals 
+   signal sl_trigger_i : std_logic;
+   signal sl_trigger_j : std_logic;
+   signal sl_trigger_color : std_logic;
+
+   -- Special Control signal
+   signal sl_CONTROL       : std_logic_vector(N_IN_PORTS-1 downto 0);
+   signal sl_no_request    : std_logic;
+   -- 
+   -- Multirate related signals
+   signal sl_bla_en   : std_logic_vector(0 downto 0); 
+   signal sl_mr_en    : std_logic_vector(0 downto 0); 
+   signal sl_mr_done  : std_logic_vector(0 downto 0); 
+   signal sl_mr_lock  : std_logic_vector(0 downto 0); 
+   signal sl_enables  : std_logic_vector(0 downto 0); 
+   signal sl_enable   : std_logic; 
+   signal ENABLE      : std_logic; 
+   -- Function input parameter "in_0", multirate=1 
+   constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+
+   signal e0, e1, e2 : boolean;
+
+   signal sl_obtain0  : std_logic;
+   signal sl_release0 : std_logic;
+   signal sl_obtain1  : std_logic;
+   signal sl_release1 : std_logic;
+   signal sl_obtain2  : std_logic;
+   signal sl_release2 : std_logic;
+
+   -- define control variables 
+
+   type state_type is (s_idle, s_halt, s_count, s_release);
+   signal state : state_type;
+   signal halt_cnt : integer;
+   signal sl_halt : std_logic;
+
+   signal sl_cnt_rst : std_logic;
+   signal cnt_rst : std_logic;
+
+begin
+
+   -- =============================================
+   -- =             MOD Functions                  
+   -- =============================================
+   -- END of MOD definitions 
+   -- =============================================
+   -- =             Parameter Functions            
+   -- =============================================
+   sl_cnt_rst <= '0';
+   sl_halt <= HALT;
+
+   -- END of Parameter definitions 
+   sl_loop_i    <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(2)+2*QUANT-1 downto 2*QUANT)));
+   sl_loop_i_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(2)+2*QUANT-1 downto 2*QUANT)));
+   sl_loop_j    <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_j_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_color    <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+   sl_loop_color_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+   -- Const bounds for-loops 
+   sl_low_i  <= 0;
+   sl_high_i <= 359;
+   sl_low_j  <= 0;
+   sl_high_j <= 639;
+   sl_low_color  <= 0;
+   sl_high_color <= 2;
+
+
+   load_i <= '0';
+   load_j <= '0';
+   load_color <= '0';
+
+   sl_lower_bnd(3*QUANT-1 downto 2*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
+   sl_lower_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
+   sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_color,QUANT));
+
+   sl_upper_bnd(3*QUANT-1 downto 2*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
+   sl_upper_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
+   sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_color,QUANT));
+   -- Special definitions 
+
+   -- Entity and control variables
+   -- Release matrix expressions
+   e0 <= sl_loop_color_rg=0;
+   e1 <= sl_loop_color_rg-1=0;
+   e2 <= sl_loop_color_rg-2=0;
+
+   sl_fire <= ('1');
+
+   -- Convert FIFO Read Port ND_7IP_6 Argument in_1 : ED_6 : 0 of type IOMM
+   sl_obtain0 <= ('1');  -- set obtain/release to const value; not used
+   sl_release0 <= ('1');
+
+   sl_CONTROL(0) <= sl_fire and b2std((e0));
+   OBTAIN(0) <= sl_obtain0;
+   RELEASE(0) <= sl_release0;
+
+   -- Convert FIFO Read Port ND_7IP_7 Argument in_2 : ED_7 : 1 of type IOMM
+   sl_obtain1 <= ('1');  -- set obtain/release to const value; not used
+   sl_release1 <= ('1');
+
+   sl_CONTROL(1) <= sl_fire and b2std((e1));
+   OBTAIN(1) <= sl_obtain1;
+   RELEASE(1) <= sl_release1;
+
+   -- Convert FIFO Read Port ND_7IP_8 Argument in_3 : ED_8 : 2 of type IOMM
+   sl_obtain2 <= ('1');  -- set obtain/release to const value; not used
+   sl_release2 <= ('1');
+
+   sl_CONTROL(2) <= sl_fire and b2std((e2));
+   OBTAIN(2) <= sl_obtain2;
+   RELEASE(2) <= sl_release2;
+
+   FIRE <= sl_fire;
+
+   cnt_rst <= sl_cnt_rst or RST;
+
+   -- 
+   -- =============================================
+   -- =             Multirate                      
+   -- =============================================
+   -- Function input parameter "in_0", multirate=1 
+   CNTR_MR0 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(0),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_0,
+         UPPER_BND => sl_mr_ubnd_0,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(0)
+      );
+   -- READ_EN indicates if READ_MUX can read data
+   sl_bla_en   <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');  
+   READ_EN     <= (others=>'0') when (HALT='1') else sl_bla_en;  
+   sl_mr_en   <= READ_ST; 
+   sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en); 
+   sl_enable  <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce 
+   ENABLE     <=  sl_enable or (not sl_fire);
+   -- 
+   LOCK_PRCS: process(CLK) 
+   begin 
+       if rising_edge(CLK) then 
+           if( RST = '1' ) then 
+               sl_mr_lock <= (others=>'0'); 
+           else  
+               if (ENABLE='1') then 
+                   sl_mr_lock <= (others=>'0'); 
+               else 
+                   for i in 0 to 0 loop 
+                       if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then 
+                           sl_mr_lock(i) <= '1'; 
+                       end if; 
+                   end loop; 
+               end if; 
+           end if; 
+       end if; 
+   end process; 
+   -- END of Multirate definitions 
+   -- 
+   -- =============================================
+   -- =             Iterators                      
+   -- =============================================
+   GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
+   	CNTR_RD : counter
+   	generic map ( 
+   		C_STEP    => CNTR_STEP(i),
+   		C_WIDTH   => CNTR_WIDTH(i)
+   	)
+  	 port map (
+   		CLK       => CLK,
+   		RST       => cnt_rst,
+   		ENABLE    => sl_cntr_en(i),
+			LOAD      => sl_load(i),
+   		LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		ITERATOR  => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		REG_CNTR  => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		DONE      => sl_done(i)
+   	);
+   end generate;
+   --
+   DONE_PRCS: process(CLK)
+   begin
+   	if rising_edge(CLK) then
+          if( RST = '1' ) then
+   		    sl_stop     <= '0';
+   		    sl_done_all <= '0';
+   		    sl_sof      <= '1';
+   	    else 
+   		    if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+   			    sl_stop <= '1';
+   		    elsif (WRAP=true) then
+   			    sl_stop <= '0';
+   		    end if;
+   		    if (sl_stop='0') then
+   			    sl_done_all <= sl_cntr_en(N_CNTRS);
+   		    end if;
+   		    if (ENABLE='1') then
+   			    sl_sof <= sl_eof;
+   		    end if;
+   	    end if;
+   	end if;
+   end process;
+   --
+   sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+   CONTROL <= sl_CONTROL;
+   --
+   REG_CNTRS <= sl_reg_cntrs; 
+   DONE <= sl_done_all;     -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+   STOP <= sl_stop;         -- '1' = The couter stoped after the end of the itteration space. 
+   --
+   sl_count      <=  '0' when (sl_stop='1') else
+                     '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
+   sl_cntr_en(0) <=  sl_count; -- makes the EVAL_LOGIC count
+   --
+   sl_cntr_en(N_CNTRS  downto 1) <= sl_cntr_en(N_CNTRS-1  downto 0) and sl_done(N_CNTRS-1  downto 0);
+   sl_eof <= sl_cntr_en(N_CNTRS);   -- End-of-frame
+   --
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_7/src/vhdl/bunny_static_split2rtl_hwn_nd_7_eval_logic_wr.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_7/src/vhdl/bunny_static_split2rtl_hwn_nd_7_eval_logic_wr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..bef08d28c2ea70b627261ddf24b7b085dadd79a6
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_7/src/vhdl/bunny_static_split2rtl_hwn_nd_7_eval_logic_wr.vhd
@@ -0,0 +1,303 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_7 is
+   generic ( 
+      N_OUT_PORTS   : natural := 1;
+      WRAP          : boolean := true;
+      N_CNTRS       : natural := 1;
+      QUANT         : natural := 32;
+      PAR_BITWIDTH  : natural :=1;
+      CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+      CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST           : in  std_logic;
+      CLK           : in  std_logic;
+      WRITE_EN      : out std_logic_vector(0 downto 0);
+      WRITE_ST      : in  std_logic_vector(0 downto 0);
+      HALT          : in  std_logic;
+      FIRE          : out std_logic;
+      DONE          : out std_logic;
+      STOP          : out std_logic;
+      CONTROL       : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+   );
+end bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_7;
+
+architecture RTL of bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_7 is	
+   -- 
+   component counter is 
+      generic( 
+         C_STEP    : natural := 10; 
+         C_WIDTH   : natural := 10 
+      ); 
+      port ( 
+         RST       : in  std_logic; 
+         CLK       : in  std_logic; 
+         ENABLE    : in  std_logic; 
+         LOAD      : in  std_logic; 
+         LOWER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         UPPER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         ITERATOR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         REG_CNTR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         DONE      : out std_logic 
+      ); 
+   end component; 
+   -- 
+   component it_mod is 
+   generic( 
+      C_MOD     : natural := 10; 
+      C_WIDTH   : natural := 10; 
+      C_INIT    : natural :=  1; 
+      C_STEP    : natural :=  1  
+   ); 
+   port ( 
+      RST       : in  std_logic; 
+      CLK       : in  std_logic; 
+      LOAD      : in  std_logic; 
+      ENABLE    : in  std_logic; 
+      MODULE    : out std_logic_vector(C_WIDTH-1 downto 0) 
+   ); 
+   end component; 
+   -- 
+   -- Multirate related signals
+   signal sl_bla_en   : std_logic_vector(0 downto 0); 
+   signal sl_mr_en    : std_logic_vector(0 downto 0); 
+   signal sl_mr_done  : std_logic_vector(0 downto 0); 
+   signal sl_mr_lock  : std_logic_vector(0 downto 0); 
+   signal sl_enables  : std_logic_vector(0 downto 0); 
+   signal sl_enable   : std_logic; 
+   signal ENABLE      : std_logic; 
+   -- Function output parameter "out_0", multirate=1 
+   constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   --  
+   -- Parameter related signals 
+   --  
+   -- Iterator (counter) related signals 
+   signal sl_low_i, sl_high_i : integer; 
+   signal sl_low_j, sl_high_j : integer; 
+   signal sl_low_color, sl_high_color : integer; 
+   signal sl_loop_i, sl_loop_i_rg : integer;
+   signal sl_loop_j, sl_loop_j_rg : integer;
+   signal sl_loop_color, sl_loop_color_rg : integer;
+   signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   -- 
+   signal sl_cntr_en  : std_logic_vector(N_CNTRS   downto 0); 
+   signal sl_done     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_done_all : std_logic; 
+   signal sl_load     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_stop     : std_logic; 
+   signal sl_fire     : std_logic; 
+   signal sl_eof      : std_logic; 
+   signal sl_sof      : std_logic; 
+   signal sl_count    : std_logic; 
+   -- 
+   -- Special Control signal
+   signal sl_CONTROL       : std_logic_vector(N_OUT_PORTS-1 downto 0);
+   signal sl_no_request    : std_logic;
+   -- 
+   -- alias signals 
+   alias update_i : std_logic is sl_cntr_en(2);
+   alias update_j : std_logic is sl_cntr_en(1);
+   alias update_color : std_logic is sl_cntr_en(0);
+   -- 
+   alias load_i : std_logic is sl_load(2);
+   alias load_j : std_logic is sl_load(1);
+   alias load_color : std_logic is sl_load(0);
+   -- Trigger signals 
+   signal sl_trigger_i : std_logic;
+   signal sl_trigger_j : std_logic;
+   signal sl_trigger_color : std_logic;
+
+   signal e0, e1 : boolean;
+
+   -- define control variables 
+   -- MOD related signals 
+
+
+   type state_type is (s_idle, s_halt, s_count, s_release);
+   signal state : state_type;
+   signal halt_cnt : integer;
+   signal sl_halt : std_logic;
+
+   signal sl_cnt_rst : std_logic;
+   signal cnt_rst : std_logic;
+
+begin
+
+   -- =============================================
+   -- =             MOD Functions                  
+   -- =============================================
+   -- END of MOD definitions 
+   --  
+   -- Parameter related signal assignments 
+   sl_cnt_rst <= '0';
+   sl_halt <= HALT;
+   -- END of Parameter definitions 
+
+   sl_loop_i    <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(2)+2*QUANT-1 downto 2*QUANT)));
+   sl_loop_i_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(2)+2*QUANT-1 downto 2*QUANT)));
+   sl_loop_j    <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_j_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_color    <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+   sl_loop_color_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+   -- Const bounds for-loops 
+   sl_low_i  <= 0;
+   sl_high_i <= 359;
+   sl_low_j  <= 0;
+   sl_high_j <= 639;
+   sl_low_color  <= 0;
+   sl_high_color <= 2;
+
+
+   load_i <= '0';
+   load_j <= '0';
+   load_color <= '0';
+
+   sl_lower_bnd(3*QUANT-1 downto 2*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
+   sl_lower_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
+   sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_color,QUANT));
+
+   sl_upper_bnd(3*QUANT-1 downto 2*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
+   sl_upper_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
+   sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_color,QUANT));
+
+   -- Special definitions 
+
+   -- Entity and control variables
+   e0 <= -sl_loop_j_rg + 99>=0;
+   e1 <= sl_loop_j_rg-100>=0;
+
+   sl_fire <= ('1');
+
+   -- Convert FIFO Write Port out_1 : ED_9
+   sl_CONTROL(0) <= sl_fire and b2std((e0));
+
+   -- Convert FIFO Write Port out_2 : ED_10
+   sl_CONTROL(1) <= sl_fire and b2std((e1));
+
+   FIRE <= sl_fire;
+
+   cnt_rst <= sl_cnt_rst or RST;
+
+   -- 
+   -- =============================================
+   -- =             Multirate                      
+   -- =============================================
+   -- Function output parameter "out_0", multirate=1 
+   CNTR_MR0 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(0),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_0,
+         UPPER_BND => sl_mr_ubnd_0,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(0)
+      );
+   -- 
+   -- WRITE_EN indicates if date can be written to WRITE_MUX
+   sl_bla_en      <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
+   WRITE_EN    <=  (others=>'0') when (HALT='1') else sl_bla_en;
+   -- 
+   sl_mr_en    <= (not sl_mr_lock) and WRITE_ST; 
+   sl_enables  <= sl_mr_lock or (sl_mr_done and sl_mr_en); 
+   sl_enable   <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0';  -- and_reduce 
+   ENABLE      <= sl_enable or (not sl_fire);
+   -- 
+   LOCK_PRCS: process(CLK) 
+   begin 
+       if rising_edge(CLK) then 
+           if( RST = '1' ) then 
+               sl_mr_lock <= (others=>'0'); 
+           else  
+               if (ENABLE='1') then 
+                   sl_mr_lock <= (others=>'0'); 
+               else 
+                   for i in 0 to 0 loop 
+                       if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then 
+                           sl_mr_lock(i) <= '1'; 
+                       end if; 
+                   end loop; 
+               end if; 
+           end if; 
+       end if; 
+   end process; 
+   -- END of Multirate definitions 
+   -- 
+   -- =============================================
+   -- =             Iterators                      
+   -- =============================================
+   GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
+   	CNTR_WR : counter
+   	generic map ( 
+   		C_STEP    => CNTR_STEP(i),
+   		C_WIDTH   => CNTR_WIDTH(i)
+   	)
+  	 port map (
+   		CLK       => CLK,
+   		RST       => cnt_rst,
+   		ENABLE    => sl_cntr_en(i),
+   		LOAD      => sl_load(i),
+   		LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		ITERATOR  => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		REG_CNTR  => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		DONE      => sl_done(i)
+   	);
+   end generate;
+   --
+   DONE_PRCS: process(CLK)
+   begin
+   	if rising_edge(CLK) then
+   	    if( RST = '1' ) then
+   		    sl_stop     <= '0';
+   		    sl_done_all <= '0';
+   		    sl_sof      <= '1';
+   	    else 
+   		    if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+   			    sl_stop <= '1';
+   		    elsif (WRAP=true) then
+   			    sl_stop <= '0';
+   		    end if;
+   		    if (sl_stop='0') then
+   			    sl_done_all <= sl_cntr_en(N_CNTRS);
+   		    end if;
+   		    if (ENABLE='1') then
+   			    sl_sof <= sl_eof;
+   		    end if;
+   	    end if;
+   	end if;
+   end process;
+   --
+   sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+   CONTROL <= sl_CONTROL;
+   --
+   DONE <= sl_done_all;     -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+   STOP <= sl_stop;         -- '1' = The couter stoped after the end of the itteration space. 
+   --
+   sl_count      <=  '0' when (sl_stop='1') else
+   			'1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
+   sl_cntr_en(0) <=  sl_count; -- makes the EVAL_LOGIC count
+   --
+   sl_cntr_en(N_CNTRS  downto 1) <= sl_cntr_en(N_CNTRS-1  downto 0) and sl_done(N_CNTRS-1  downto 0);
+   sl_eof <= sl_cntr_en(N_CNTRS);      -- End-of-frame (combinatorial; beter not use it outside)
+   --
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_7/src/vhdl/bunny_static_split2rtl_hwn_nd_7_execution_unit.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_7/src/vhdl/bunny_static_split2rtl_hwn_nd_7_execution_unit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c43bfcea40609409f0d2cb1ab702c7f944917239
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_7/src/vhdl/bunny_static_split2rtl_hwn_nd_7_execution_unit.vhd
@@ -0,0 +1,113 @@
+-- Execute Unit automatically generated by KpnMapper
+-- Function "compaan_outlinedproc2"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_bunny_static_split2rtl_functions_1_lib;
+use compaandesign_com_bunny_static_split2rtl_functions_1_lib.all;
+
+entity bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_7 is
+   generic (
+      N_INPORTS  : natural := 1;
+      N_OUTPORTS : natural := 1;
+      IP_RESET   : natural := 1; 
+      STIM_DIR   : string  := "bla";
+      QUANT      : natural := 32;
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1; 
+      CNTR_QUANT : natural := 32; 
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+   );
+   port (
+      RST        : in  std_logic;
+      CLK        : in  std_logic;
+      -- Funtion Input parameters
+      IN_PORT_0    : in  std_logic_vector(7 downto 0);  -- Param. "tmp1"
+      READ       : out std_logic_vector(N_INPORTS-1 downto 0);
+      EXIST      : in  std_logic_vector(N_INPORTS-1 downto 0);
+      -- Iterators
+      REG_CNTRS_RD : in  std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
+      -- Funtion Output parameters
+      OUT_PORT_0   : out std_logic_vector(7 downto 0);  -- Param. "tmp0"
+      WRITE      : out std_logic_vector(N_OUTPORTS-1 downto 0);
+      FULL       : in  std_logic_vector(N_OUTPORTS-1 downto 0);
+      STOP_RD    : in  std_logic;
+      STOP_WR    : in  std_logic;
+      ERROR      : out std_logic
+   );
+end bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_7 ;
+
+-- Laura implementation
+architecture Laura of bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_7 is
+
+   component compaan_outlinedproc2 is
+      generic (
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1; 
+         CNTR_QUANT : natural := 32; 
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST   : in std_logic;
+         CLK   : in std_logic;
+         -- Inputs 
+         ip_tmp1  : in  std_logic_vector(7 downto 0);  
+         -- Iterators 
+         it_color : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+         it_j : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+         it_i : in  std_logic_vector(CNTR_WIDTH(2)-1 downto 0);
+         EXIST : in  std_logic_vector(0 downto 0);
+         READF : out std_logic_vector(0 downto 0);
+         -- Outputs 
+         op_tmp0 : out std_logic_vector(7 downto 0);
+         FULL  : in  std_logic_vector(0 downto 0);
+         WRITEF: out std_logic_vector(0 downto 0);
+         --
+         STOP_RD : in  std_logic;
+         STOP_WR : in  std_logic;
+         ERROR   : out std_logic
+      );
+   end component;
+
+   signal sl_RST : std_logic;
+
+begin
+
+   sl_RST <= RST when IP_RESET=1 else not RST;
+
+   FUNC : compaan_outlinedproc2
+   generic map (
+         STIM_DIR      => STIM_DIR,
+         c_STAGES      => c_STAGES,
+         N_CNTRS       => N_CNTRS,
+         CNTR_QUANT    => CNTR_QUANT,
+         CNTR_WIDTH    => CNTR_WIDTH
+   )
+   port map (
+      RST   => sl_RST,
+      CLK   => CLK,
+      -- Inputs 
+      ip_tmp1 => IN_PORT_0,
+      -- Iterators 
+      it_color => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
+      it_j => REG_CNTRS_RD(1*CNTR_QUANT+CNTR_WIDTH(1)-1 downto 1*CNTR_QUANT),
+      it_i => REG_CNTRS_RD(2*CNTR_QUANT+CNTR_WIDTH(2)-1 downto 2*CNTR_QUANT),
+      EXIST => EXIST,
+      READF => READ,
+      -- Outputs 
+      op_tmp0 => OUT_PORT_0,
+      FULL  => FULL,
+      WRITEF=> WRITE,
+      -- 
+      STOP_RD => STOP_RD,
+      STOP_WR => STOP_WR,
+      ERROR   => ERROR
+   );
+
+end Laura;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_8/hdllib.cfg b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_8/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..7456564f30f6ea676c1568a68301ab881d7a2cee
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_8/hdllib.cfg
@@ -0,0 +1,18 @@
+hdl_lib_name = compaandesign_com_bunny_static_split2rtl_hwn_nd_8_1
+hdl_library_clause_name = compaandesign_com_bunny_static_split2rtl_hwn_nd_8_1_lib
+hdl_lib_uses_synth = compaandesign_com_bunny_static_split2rtl_functions_1 compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1 compaandesign_com_common_extern_connector_1 
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+	src/vhdl/bunny_static_split2rtl_hwn_nd_8_execution_unit.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_8_eval_logic_rd.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_8_eval_logic_wr.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_8.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_8/src/vhdl/bunny_static_split2rtl_hwn_nd_8.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_8/src/vhdl/bunny_static_split2rtl_hwn_nd_8.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e0baabbb6330f34783dfbb2950a9090c7c8c30da
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_8/src/vhdl/bunny_static_split2rtl_hwn_nd_8.vhd
@@ -0,0 +1,463 @@
+-- HWN Entity File automatically generated by KpnMapper (writeHdlHWNodeFile)
+-- Top level file for a Hardware Accelerator
+-- Function "compaan_outlinedproc3"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+library compaandesign_com_common_extern_connector_1_lib;
+use compaandesign_com_common_extern_connector_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_8 is
+   generic (
+      STIM_DIR   : string  := "bla";
+      RESET_HIGH : natural := 1;
+      PAR_WIDTH  : natural := 16;
+      QUANT      : natural := 32;
+      WRAP       : boolean := true
+   );
+   port (
+
+      -- Dataflow input interfaces
+      -- ED_9 : in_0
+      ND_8IP_9_Rd    : out std_logic;
+      ND_8IP_9_Din   : in  std_logic_vector(7 downto 0);
+      ND_8IP_9_Exist : in  std_logic; 
+      ND_8IP_9_CLK   : out std_logic;
+      ND_8IP_9_CTRL  : in  std_logic;
+
+      -- Dataflow Control Input interfaces
+      -- Dataflow output interfaces
+      -- ED_11 : out_0
+      ND_8OP_1_Wr   : out std_logic;
+      ND_8OP_1_Dout : out std_logic_vector(7 downto 0);
+      ND_8OP_1_Full : in  std_logic;
+      ND_8OP_1_CLK  : out std_logic;
+      ND_8OP_1_CTRL : out std_logic;
+
+      PARAM_DT : in  std_logic_vector(PAR_WIDTH+10-1 downto 0);
+      PARAM_LD : in  std_logic;
+
+      RST      : in  std_logic;
+      CLK      : in  std_logic;
+      STOP     : out std_logic;
+      ERROR    : out std_logic;
+      BLOCK_RD : out std_logic
+   );
+end bunny_static_split2rtl_hwn_nd_8;
+
+architecture RTL of bunny_static_split2rtl_hwn_nd_8 is
+   --
+   -- ====================================
+   -- =     Constants declaration        =
+   -- ====================================
+   -- Setting the parameters of the HW Node
+   constant c_IN_PORTS     : natural := 1; -- number of input ports of a HW node
+   constant c_OUT_PORTS    : natural := 1; -- number of output ports of a HW node
+   constant c_IN_FUNC_VAR  : natural := 1; -- number of input ports of a HW IP
+   constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
+   constant c_COUNTERS     : natural := 3; -- number of iterators
+   -- ===========================================
+   -- = Iterators run from Inner to Outer loop  =
+   -- ===========================================
+   constant c_CNTR_QUANT   : natural := 11;
+   constant c_CNTR_STEPS   : t_counter_step  := ( 0=>1, 1=>1, 2=>1, others=>1 );
+   constant c_CNTR_WIDTHS  : t_counter_width := ( 0=>3, 1=>11, 2=>10, others=>10 );
+   constant c_STAGES       : natural := 1; -- number of pipeline stages or delay
+   constant c_IP_RESET     : natural := 1; -- active level of the HW IP reset signal
+   constant c_WRAP         : boolean := WRAP; -- Operation mode: Single_Shot (false) or Continuous (true)
+   constant c_EXT_PAR      : natural := 0; -- number of external parameters
+   constant c_INT_PAR      : natural := 0; -- number of internal parameters
+   constant c_N_PAR        : natural := 0; -- no parameters are used
+   constant c_PAR_BITWIDTH : natural := PAR_WIDTH; -- aggregate bitwidth of the parameter vector
+   constant c_PAR_VECTOR   : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
+       (0,0,0,0), (0,0,0,0)    -- two dummy elements
+   );
+   --
+   -- ====================================
+   -- =     Components declaration       =
+   -- ====================================
+   component bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_8 is
+      generic (
+         N_IN_PORTS    : natural := 1;
+         WRAP          : boolean := true;
+         N_CNTRS       : natural := 1; 
+         QUANT         : natural := 32;
+         PAR_BITWIDTH  : natural :=1;
+         CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+         CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+      );
+      port (
+         RST           : in  std_logic;
+         CLK           : in  std_logic;
+         REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1  downto 0); 
+         READ_EN       : out std_logic_vector(c_IN_FUNC_VAR-1  downto 0);
+         READ_ST       : in  std_logic_vector(c_IN_FUNC_VAR-1  downto 0);
+         HALT          : in  std_logic;
+         FIRE          : out std_logic;
+         DONE          : out std_logic;
+         STOP          : out std_logic;
+         CONTROL       : out std_logic_vector(N_IN_PORTS-1 downto 0);
+         OBTAIN        : out std_logic_vector(N_IN_PORTS-1 downto 0);
+         RELEASE       : out std_logic_vector(N_IN_PORTS-1 downto 0)
+      );
+   end component;
+
+   component READ_MUX is
+      generic (
+         N_PORTS    : natural := 1;
+         PORT_WIDTH : natural := 32  
+      );
+      port(
+         IN_PORTS   : in  std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
+         EXISTS     : in  std_logic_vector(N_PORTS-1 downto 0);
+         READS      : out std_logic_vector(N_PORTS-1 downto 0);
+         SOFS       : in  std_logic_vector(N_PORTS-1 downto 0);
+
+         OUT_PORT   : out std_logic_vector(PORT_WIDTH-1 downto 0);
+         EXIST      : out std_logic;
+         READ       : in  std_logic;
+         SOF        : in  std_logic;
+		CLK        : in std_logic;
+
+         READ_EN    : in  std_logic;
+         READ_ST    : out std_logic;
+         CONTROL    : in  std_logic_vector(N_PORTS-1 downto 0);
+         OBTAIN     : in  std_logic_vector(N_PORTS-1 downto 0);
+         RELEASE    : in  std_logic_vector(N_PORTS-1 downto 0)
+      );
+   end component;
+
+   component bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_8 is
+      generic ( 
+         N_OUT_PORTS   : natural := 1;
+         WRAP          : boolean := true;
+         N_CNTRS       : natural := 1; 
+         QUANT         : natural := 32;
+         PAR_BITWIDTH  : natural :=1;
+         CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+         CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+      );
+      port (
+         RST           : in  std_logic;
+         CLK           : in  std_logic;
+         WRITE_EN      : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+         WRITE_ST      : in  std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+         HALT          : in  std_logic;
+         FIRE          : out std_logic;
+         DONE          : out std_logic;
+         STOP          : out std_logic;
+         CONTROL       : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+      );
+   end component;
+
+   component WRITE_DEMUX is
+      generic (
+         N_PORTS : natural := 1
+      );
+      port(
+         WRITES   : out std_logic_vector(N_PORTS-1 downto 0);
+         WRITE    : in  std_logic;
+
+         FULLS    : in  std_logic_vector(N_PORTS-1 downto 0);
+         FULL     : out std_logic;
+
+         WRITE_EN : in  std_logic;
+         WRITE_ST : out std_logic;
+         CONTROL  : in  std_logic_vector(N_PORTS-1 downto 0)
+      );
+   end component;
+
+
+   component bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_8 is
+      generic (
+         N_INPORTS  : natural := 1;
+         N_OUTPORTS : natural := 1;
+         IP_RESET   : natural := 1;
+         QUANT      : natural := 32;
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1;
+         CNTR_QUANT : natural := 32;
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST        : in  std_logic;
+         CLK        : in  std_logic;
+
+         -- Iterators
+         REG_CNTRS_RD : in  std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
+         -- Func. Input parameters
+         IN_PORT_0 : in  std_logic_vector(7 downto 0); -- tmp1
+         READ       : out std_logic_vector(N_INPORTS-1 downto 0);
+         EXIST      : in  std_logic_vector(N_INPORTS-1 downto 0);
+         -- Func. Output parameters
+         OUT_PORT_0 : out std_logic_vector(7 downto 0); -- tmp0
+         WRITE      : out std_logic_vector(N_OUTPORTS-1 downto 0);
+         FULL       : in  std_logic_vector(N_OUTPORTS-1 downto 0);
+         --
+         STOP_RD    : in  std_logic;
+         STOP_WR    : in  std_logic;
+         ERROR      : out std_logic
+      );
+   end component;
+
+   component INTERNAL_PARAMETERS is 
+      generic (
+         PAR_BITWIDTH : natural:=1;
+         PAR_VECTOR   : t_par_vector;
+         N_PAR        : natural:=0;
+         START_IN_RUN  : boolean := FALSE
+      );
+      port (  
+         RST        : in  std_logic;
+         CLK        : in  std_logic;
+
+         HALT_RD    : out std_logic;
+         HALT_WR    : out std_logic;
+         SOF_RD     : in  std_logic;
+         SOF_WR     : in  std_logic;
+         LOAD_PARAM : out std_logic;
+
+         par_one_in_Rd    : out std_logic;
+         par_one_in_Din   : in std_logic_vector(32-1 downto 0);
+         par_one_in_Exist : in std_logic;
+         par_one_in_CLK   : out std_logic;
+         par_one_in_CTRL  : in std_logic;
+
+         PARAMETERS_RD : out std_logic_vector(32-1 downto 0);
+         PARAMETERS_WR : out std_logic_vector(32-1 downto 0)
+      );
+   end component;
+
+   --
+   -- ====================================
+   -- =       Signals declaration        =
+   -- ====================================
+   -- 
+   -- HW Node Input Ports
+   signal sl_IN_PORTS_0   : std_logic_vector(1*8-1 downto 0); -- tmp1
+   signal sl_EXISTS       : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_READS        : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_CTRLS        : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_control_rd   : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_obtain_rd    : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_release_rd   : std_logic_vector(c_IN_PORTS-1 downto 0);
+   -- 
+   -- Func. Input parameters
+   signal sl_in_port_0    : std_logic_vector(7 downto 0); -- tmp1
+   signal sl_exist        : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read         : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read_en      : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read_st      : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   -- 
+   signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
+   -- 
+   -- HW Node Output Ports
+   signal sl_WRITES       : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_FULLS        : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_control_wr   : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_lortnoc_wr   : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   -- 
+   -- Func. Output parameters
+   signal sl_out_port_0   : std_logic_vector(7 downto 0); -- tmp0
+   signal sl_full         : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write        : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write_en     : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write_st     : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   -- 
+   -- 
+   signal sl_halt             : std_logic;
+   signal sl_halted           : std_logic;
+   signal sl_halt_wr          : std_logic;
+   signal sl_halt_rd          : std_logic;
+   signal sl_param_halt_wr    : std_logic;
+   signal sl_param_halt_rd    : std_logic;
+   signal sl_done_wr          : std_logic;
+   signal sl_done_rd          : std_logic;
+   signal sl_stop_wr          : std_logic;
+   signal sl_stop_rd          : std_logic;
+   signal sl_fire_wr          : std_logic;
+   signal sl_fire_rd          : std_logic;
+   signal sl_sof_wr           : std_logic;
+   signal sl_sof_rd           : std_logic;
+   signal sl_error            : std_logic;
+   signal sl_load_param       : std_logic;
+
+   --  
+   -- Parameter related signals 
+   signal sl_param_fifo_full     : std_logic;
+   signal sl_sync_num            : std_logic_vector(9 downto 0);
+
+   signal sl_RST : std_logic;
+
+begin 
+
+   sl_RST <= RST when RESET_HIGH=1 else not RST;
+      ND_8IP_9_CLK   <= CLK;
+      ND_8OP_1_CLK  <= CLK;
+
+   --
+   -- ==========================================================
+   -- =       HWN Input related modules                        =
+   -- ==========================================================
+   -- Func. Input param. "tmp1"
+   RD_MUX_0 : READ_MUX
+   generic map (
+      N_PORTS    => 1,
+      PORT_WIDTH => 8
+   )
+   port map (
+      IN_PORTS   => sl_IN_PORTS_0,
+      EXISTS     => sl_EXISTS(0 downto 0),
+      READS      => sl_READS(0 downto 0),
+      SOFS       => sl_CTRLS(0 downto 0),
+
+      OUT_PORT   => sl_in_port_0,
+      EXIST      => sl_exist(0),
+      READ       => sl_read(0),
+      SOF        => sl_sof_rd,
+      CLK        => CLK,
+
+      READ_EN    => sl_read_en(0),
+      READ_ST    => sl_read_st(0),
+      CONTROL    => sl_control_rd(0 downto 0),
+      OBTAIN     => sl_obtain_rd(0 downto 0),
+      RELEASE    => sl_release_rd(0 downto 0)
+   );
+
+   ND_8IP_9_Rd   <= sl_READS(0);
+
+   sl_IN_PORTS_0 <= ND_8IP_9_Din;
+
+   sl_EXISTS(0)   <= ND_8IP_9_Exist ;
+   sl_CTRLS(0)    <= ND_8IP_9_CTRL ;
+
+   EVAL_RD : bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_8
+   generic map ( 
+      N_IN_PORTS    => c_IN_PORTS,
+      WRAP          => c_WRAP,
+      N_CNTRS       => c_COUNTERS,
+      QUANT         => c_CNTR_QUANT,
+      PAR_BITWIDTH  => c_PAR_BITWIDTH,
+      CNTR_STEP     => c_CNTR_STEPS,
+      CNTR_WIDTH    => c_CNTR_WIDTHS
+   )
+   port map(
+      RST           => sl_RST,
+      CLK           => CLK,
+      REG_CNTRS     => sl_REG_CNTRS_RD,
+      READ_EN       => sl_read_en,
+      READ_ST       => sl_read_st,
+      HALT          => sl_halt_rd,
+      FIRE          => sl_fire_rd,
+      DONE          => sl_done_rd,
+      STOP          => sl_stop_rd,
+      CONTROL       => sl_control_rd,
+      OBTAIN        => sl_obtain_rd,
+      RELEASE       => sl_release_rd
+   );
+
+   --
+   -- ==========================================================
+   -- =       HWN Output related modules                       =
+   -- ==========================================================
+   -- 
+   -- Func. Output param. "tmp0"
+   DEMUX_0 : WRITE_DEMUX
+   generic map (
+      N_PORTS => 1
+   )
+   port map (
+      WRITES   => sl_WRITES(0 downto 0),
+      FULLS    => sl_FULLS(0 downto 0),
+      CONTROL  => sl_lortnoc_wr(0 downto 0),
+      WRITE    => sl_write(0),
+      FULL     => sl_full(0),
+      WRITE_EN => sl_write_en(0),
+      WRITE_ST => sl_write_st(0)
+   );
+   --
+   ND_8OP_1_Dout <= sl_out_port_0;  -- Func. Output param. "tmp0"
+   ND_8OP_1_CTRL <= sl_sof_wr ;
+   ND_8OP_1_Wr   <= sl_WRITES(0);
+   sl_FULLS(0) <= ND_8OP_1_Full;
+   sl_lortnoc_wr(0) <= sl_control_wr(0);
+   --
+   --
+   EVAL_WR : bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_8
+   generic map ( 
+      N_OUT_PORTS   => c_OUT_PORTS,
+      WRAP          => c_WRAP,
+      N_CNTRS       => c_COUNTERS,
+      QUANT         => c_CNTR_QUANT,
+      PAR_BITWIDTH  => c_PAR_BITWIDTH,
+      CNTR_STEP     => c_CNTR_STEPS,
+      CNTR_WIDTH    => c_CNTR_WIDTHS
+   )
+   port map (
+      RST           => sl_RST,
+      CLK           => CLK,
+      WRITE_EN      => sl_write_en,
+      WRITE_ST      => sl_write_st,
+      HALT          => sl_halt_wr,
+      FIRE          => sl_fire_wr,
+      DONE          => sl_done_wr,
+      STOP          => sl_stop_wr,
+      CONTROL       => sl_control_wr
+   );
+
+   --
+   -- ==========================================================
+   -- =       HWN Execution Unit                               =
+   -- ==========================================================
+   EX : bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_8
+   generic map (
+      N_INPORTS  => c_IN_FUNC_VAR,
+      N_OUTPORTS => c_OUT_FUNC_VAR, 
+      IP_RESET   => c_IP_RESET,
+      QUANT      => QUANT,
+      STIM_DIR   => STIM_DIR,
+      c_STAGES   => c_STAGES,
+      N_CNTRS    => c_COUNTERS,
+      CNTR_QUANT => c_CNTR_QUANT,
+      CNTR_WIDTH => c_CNTR_WIDTHS
+   )
+   port map (
+      RST        => sl_RST,
+      CLK        => CLK,
+      -- Iterators
+      REG_CNTRS_RD => sl_REG_CNTRS_RD,
+      -- Func. Input parameters
+      IN_PORT_0    => sl_in_port_0,
+      READ       => sl_read,
+      EXIST      => sl_exist,
+      -- Func. Output parameters
+      OUT_PORT_0   => sl_out_port_0,
+      WRITE      => sl_write,
+      FULL       => sl_full,
+      --
+      STOP_WR    => sl_stop_wr,
+      STOP_RD    => sl_stop_rd,
+      ERROR      => sl_error
+   );
+
+   -- ==========================================================
+   -- =       PARAMETERIZATION                                 =
+   -- ==========================================================
+   -- no parameters
+   sl_halt_rd <= '0';
+   sl_halt_wr <= '0';
+--   sl_halted  <= sl_sof_rd;
+   STOP <= sl_done_wr;
+   ERROR <= sl_error;
+   BLOCK_RD <= not (  (  sl_READS(0)  ) );
+
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_8/src/vhdl/bunny_static_split2rtl_hwn_nd_8_eval_logic_rd.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_8/src/vhdl/bunny_static_split2rtl_hwn_nd_8_eval_logic_rd.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..033bcb0997e9e7ce31ea6e00e00ce5821371c9b8
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_8/src/vhdl/bunny_static_split2rtl_hwn_nd_8_eval_logic_rd.vhd
@@ -0,0 +1,307 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_8 is
+   generic (
+      N_IN_PORTS    : natural := 1;
+      WRAP          : boolean := true;
+      N_CNTRS       : natural := 1; 
+      QUANT         : natural := 32;
+      PAR_BITWIDTH  : natural  :=1;
+      CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+      CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST           : in  std_logic;
+      CLK           : in  std_logic;
+      REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+      READ_EN       : out std_logic_vector(0 downto 0);
+      READ_ST       : in  std_logic_vector(0 downto 0);
+      HALT          : in  std_logic;
+      FIRE          : out std_logic;
+      DONE          : out std_logic;
+      STOP          : out std_logic;
+      CONTROL       : out std_logic_vector(N_IN_PORTS-1 downto 0);
+      OBTAIN        : out std_logic_vector(N_IN_PORTS-1 downto 0);
+      RELEASE       : out std_logic_vector(N_IN_PORTS-1 downto 0)
+   );
+end bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_8;
+
+architecture RTL of bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_8 is
+   -- 
+   component counter is 
+      generic( 
+         C_STEP    : natural := 10; 
+         C_WIDTH   : natural := 10 
+      ); 
+      port ( 
+         RST       : in  std_logic; 
+         CLK       : in  std_logic; 
+         ENABLE    : in  std_logic; 
+         LOAD      : in  std_logic; 
+         LOWER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         UPPER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         ITERATOR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         REG_CNTR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         DONE      : out std_logic 
+      ); 
+   end component; 
+   -- 
+   component it_mod is 
+   generic( 
+      C_MOD     : natural := 10; 
+      C_WIDTH   : natural := 10; 
+      C_INIT    : natural :=  1; 
+      C_STEP    : natural :=  1  
+   ); 
+   port ( 
+      RST       : in  std_logic; 
+      CLK       : in  std_logic; 
+      LOAD      : in  std_logic; 
+      ENABLE    : in  std_logic; 
+      MODULE    : out std_logic_vector(C_WIDTH-1 downto 0) 
+   ); 
+   end component; 
+   -- 
+   --  
+   -- Parameter related signals 
+   -- 
+   -- Iterator (counter) related signals 
+   signal sl_low_i, sl_high_i : integer;
+   signal sl_low_j, sl_high_j : integer;
+   signal sl_low_color, sl_high_color : integer;
+   signal sl_loop_i, sl_loop_i_rg : integer;
+   signal sl_loop_j, sl_loop_j_rg : integer;
+   signal sl_loop_color, sl_loop_color_rg : integer;
+   signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   -- 
+   signal sl_cntr_en  : std_logic_vector(N_CNTRS   downto 0); 
+   signal sl_done     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_done_all : std_logic; 
+   signal sl_load     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_stop     : std_logic; 
+   signal sl_fire     : std_logic; 
+   signal sl_sof      : std_logic; 
+   signal sl_eof      : std_logic; 
+   signal sl_count    : std_logic; 
+
+   -- alias signals 
+   alias update_i : std_logic is sl_cntr_en(2);
+   alias update_j : std_logic is sl_cntr_en(1);
+   alias update_color : std_logic is sl_cntr_en(0);
+   alias load_i : std_logic is sl_load(2);
+   alias load_j : std_logic is sl_load(1);
+   alias load_color : std_logic is sl_load(0);
+
+   -- Trigger signals 
+   signal sl_trigger_i : std_logic;
+   signal sl_trigger_j : std_logic;
+   signal sl_trigger_color : std_logic;
+
+   -- Special Control signal
+   signal sl_CONTROL       : std_logic_vector(N_IN_PORTS-1 downto 0);
+   signal sl_no_request    : std_logic;
+   -- 
+   -- Multirate related signals
+   signal sl_bla_en   : std_logic_vector(0 downto 0); 
+   signal sl_mr_en    : std_logic_vector(0 downto 0); 
+   signal sl_mr_done  : std_logic_vector(0 downto 0); 
+   signal sl_mr_lock  : std_logic_vector(0 downto 0); 
+   signal sl_enables  : std_logic_vector(0 downto 0); 
+   signal sl_enable   : std_logic; 
+   signal ENABLE      : std_logic; 
+   -- Function input parameter "in_0", multirate=1 
+   constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+
+
+   signal sl_obtain0  : std_logic;
+   signal sl_release0 : std_logic;
+
+   -- define control variables 
+
+   type state_type is (s_idle, s_halt, s_count, s_release);
+   signal state : state_type;
+   signal halt_cnt : integer;
+   signal sl_halt : std_logic;
+
+   signal sl_cnt_rst : std_logic;
+   signal cnt_rst : std_logic;
+
+begin
+
+   -- =============================================
+   -- =             MOD Functions                  
+   -- =============================================
+   -- END of MOD definitions 
+   -- =============================================
+   -- =             Parameter Functions            
+   -- =============================================
+   sl_cnt_rst <= '0';
+   sl_halt <= HALT;
+
+   -- END of Parameter definitions 
+   sl_loop_i    <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(2)+2*QUANT-1 downto 2*QUANT)));
+   sl_loop_i_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(2)+2*QUANT-1 downto 2*QUANT)));
+   sl_loop_j    <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_j_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_color    <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+   sl_loop_color_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+   -- Const bounds for-loops 
+   sl_low_i  <= 0;
+   sl_high_i <= 359;
+   sl_low_j  <= 0;
+   sl_high_j <= 99;
+   sl_low_color  <= 0;
+   sl_high_color <= 2;
+
+
+   load_i <= '0';
+   load_j <= '0';
+   load_color <= '0';
+
+   sl_lower_bnd(3*QUANT-1 downto 2*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
+   sl_lower_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
+   sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_color,QUANT));
+
+   sl_upper_bnd(3*QUANT-1 downto 2*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
+   sl_upper_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
+   sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_color,QUANT));
+   -- Special definitions 
+
+   -- Entity and control variables
+   -- Release matrix expressions
+
+   sl_fire <= ('1');
+
+   -- Convert FIFO Read Port ND_8IP_9 Argument in_1 : ED_9 : 0 of type IOMM
+   sl_obtain0 <= ('1');  -- set obtain/release to const value; not used
+   sl_release0 <= ('1');
+
+   sl_CONTROL(0) <= sl_fire and ('1');
+   OBTAIN(0) <= sl_obtain0;
+   RELEASE(0) <= sl_release0;
+
+   FIRE <= sl_fire;
+
+   cnt_rst <= sl_cnt_rst or RST;
+
+   -- 
+   -- =============================================
+   -- =             Multirate                      
+   -- =============================================
+   -- Function input parameter "in_0", multirate=1 
+   CNTR_MR0 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(0),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_0,
+         UPPER_BND => sl_mr_ubnd_0,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(0)
+      );
+   -- READ_EN indicates if READ_MUX can read data
+   sl_bla_en   <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');  
+   READ_EN     <= (others=>'0') when (HALT='1') else sl_bla_en;  
+   sl_mr_en   <= READ_ST; 
+   sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en); 
+   sl_enable  <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce 
+   ENABLE     <=  sl_enable or (not sl_fire);
+   -- 
+   LOCK_PRCS: process(CLK) 
+   begin 
+       if rising_edge(CLK) then 
+           if( RST = '1' ) then 
+               sl_mr_lock <= (others=>'0'); 
+           else  
+               if (ENABLE='1') then 
+                   sl_mr_lock <= (others=>'0'); 
+               else 
+                   for i in 0 to 0 loop 
+                       if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then 
+                           sl_mr_lock(i) <= '1'; 
+                       end if; 
+                   end loop; 
+               end if; 
+           end if; 
+       end if; 
+   end process; 
+   -- END of Multirate definitions 
+   -- 
+   -- =============================================
+   -- =             Iterators                      
+   -- =============================================
+   GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
+   	CNTR_RD : counter
+   	generic map ( 
+   		C_STEP    => CNTR_STEP(i),
+   		C_WIDTH   => CNTR_WIDTH(i)
+   	)
+  	 port map (
+   		CLK       => CLK,
+   		RST       => cnt_rst,
+   		ENABLE    => sl_cntr_en(i),
+			LOAD      => sl_load(i),
+   		LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		ITERATOR  => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		REG_CNTR  => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		DONE      => sl_done(i)
+   	);
+   end generate;
+   --
+   DONE_PRCS: process(CLK)
+   begin
+   	if rising_edge(CLK) then
+          if( RST = '1' ) then
+   		    sl_stop     <= '0';
+   		    sl_done_all <= '0';
+   		    sl_sof      <= '1';
+   	    else 
+   		    if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+   			    sl_stop <= '1';
+   		    elsif (WRAP=true) then
+   			    sl_stop <= '0';
+   		    end if;
+   		    if (sl_stop='0') then
+   			    sl_done_all <= sl_cntr_en(N_CNTRS);
+   		    end if;
+   		    if (ENABLE='1') then
+   			    sl_sof <= sl_eof;
+   		    end if;
+   	    end if;
+   	end if;
+   end process;
+   --
+   sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+   CONTROL <= sl_CONTROL;
+   --
+   REG_CNTRS <= sl_reg_cntrs; 
+   DONE <= sl_done_all;     -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+   STOP <= sl_stop;         -- '1' = The couter stoped after the end of the itteration space. 
+   --
+   sl_count      <=  '0' when (sl_stop='1') else
+                     '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
+   sl_cntr_en(0) <=  sl_count; -- makes the EVAL_LOGIC count
+   --
+   sl_cntr_en(N_CNTRS  downto 1) <= sl_cntr_en(N_CNTRS-1  downto 0) and sl_done(N_CNTRS-1  downto 0);
+   sl_eof <= sl_cntr_en(N_CNTRS);   -- End-of-frame
+   --
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_8/src/vhdl/bunny_static_split2rtl_hwn_nd_8_eval_logic_wr.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_8/src/vhdl/bunny_static_split2rtl_hwn_nd_8_eval_logic_wr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a518c12824eceda58cef24acbd515a0b9565a933
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_8/src/vhdl/bunny_static_split2rtl_hwn_nd_8_eval_logic_wr.vhd
@@ -0,0 +1,297 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_8 is
+   generic ( 
+      N_OUT_PORTS   : natural := 1;
+      WRAP          : boolean := true;
+      N_CNTRS       : natural := 1;
+      QUANT         : natural := 32;
+      PAR_BITWIDTH  : natural :=1;
+      CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+      CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST           : in  std_logic;
+      CLK           : in  std_logic;
+      WRITE_EN      : out std_logic_vector(0 downto 0);
+      WRITE_ST      : in  std_logic_vector(0 downto 0);
+      HALT          : in  std_logic;
+      FIRE          : out std_logic;
+      DONE          : out std_logic;
+      STOP          : out std_logic;
+      CONTROL       : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+   );
+end bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_8;
+
+architecture RTL of bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_8 is	
+   -- 
+   component counter is 
+      generic( 
+         C_STEP    : natural := 10; 
+         C_WIDTH   : natural := 10 
+      ); 
+      port ( 
+         RST       : in  std_logic; 
+         CLK       : in  std_logic; 
+         ENABLE    : in  std_logic; 
+         LOAD      : in  std_logic; 
+         LOWER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         UPPER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         ITERATOR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         REG_CNTR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         DONE      : out std_logic 
+      ); 
+   end component; 
+   -- 
+   component it_mod is 
+   generic( 
+      C_MOD     : natural := 10; 
+      C_WIDTH   : natural := 10; 
+      C_INIT    : natural :=  1; 
+      C_STEP    : natural :=  1  
+   ); 
+   port ( 
+      RST       : in  std_logic; 
+      CLK       : in  std_logic; 
+      LOAD      : in  std_logic; 
+      ENABLE    : in  std_logic; 
+      MODULE    : out std_logic_vector(C_WIDTH-1 downto 0) 
+   ); 
+   end component; 
+   -- 
+   -- Multirate related signals
+   signal sl_bla_en   : std_logic_vector(0 downto 0); 
+   signal sl_mr_en    : std_logic_vector(0 downto 0); 
+   signal sl_mr_done  : std_logic_vector(0 downto 0); 
+   signal sl_mr_lock  : std_logic_vector(0 downto 0); 
+   signal sl_enables  : std_logic_vector(0 downto 0); 
+   signal sl_enable   : std_logic; 
+   signal ENABLE      : std_logic; 
+   -- Function output parameter "out_0", multirate=1 
+   constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   --  
+   -- Parameter related signals 
+   --  
+   -- Iterator (counter) related signals 
+   signal sl_low_i, sl_high_i : integer; 
+   signal sl_low_j, sl_high_j : integer; 
+   signal sl_low_color, sl_high_color : integer; 
+   signal sl_loop_i, sl_loop_i_rg : integer;
+   signal sl_loop_j, sl_loop_j_rg : integer;
+   signal sl_loop_color, sl_loop_color_rg : integer;
+   signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   -- 
+   signal sl_cntr_en  : std_logic_vector(N_CNTRS   downto 0); 
+   signal sl_done     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_done_all : std_logic; 
+   signal sl_load     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_stop     : std_logic; 
+   signal sl_fire     : std_logic; 
+   signal sl_eof      : std_logic; 
+   signal sl_sof      : std_logic; 
+   signal sl_count    : std_logic; 
+   -- 
+   -- Special Control signal
+   signal sl_CONTROL       : std_logic_vector(N_OUT_PORTS-1 downto 0);
+   signal sl_no_request    : std_logic;
+   -- 
+   -- alias signals 
+   alias update_i : std_logic is sl_cntr_en(2);
+   alias update_j : std_logic is sl_cntr_en(1);
+   alias update_color : std_logic is sl_cntr_en(0);
+   -- 
+   alias load_i : std_logic is sl_load(2);
+   alias load_j : std_logic is sl_load(1);
+   alias load_color : std_logic is sl_load(0);
+   -- Trigger signals 
+   signal sl_trigger_i : std_logic;
+   signal sl_trigger_j : std_logic;
+   signal sl_trigger_color : std_logic;
+
+
+   -- define control variables 
+   -- MOD related signals 
+
+
+   type state_type is (s_idle, s_halt, s_count, s_release);
+   signal state : state_type;
+   signal halt_cnt : integer;
+   signal sl_halt : std_logic;
+
+   signal sl_cnt_rst : std_logic;
+   signal cnt_rst : std_logic;
+
+begin
+
+   -- =============================================
+   -- =             MOD Functions                  
+   -- =============================================
+   -- END of MOD definitions 
+   --  
+   -- Parameter related signal assignments 
+   sl_cnt_rst <= '0';
+   sl_halt <= HALT;
+   -- END of Parameter definitions 
+
+   sl_loop_i    <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(2)+2*QUANT-1 downto 2*QUANT)));
+   sl_loop_i_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(2)+2*QUANT-1 downto 2*QUANT)));
+   sl_loop_j    <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_j_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_color    <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+   sl_loop_color_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+   -- Const bounds for-loops 
+   sl_low_i  <= 0;
+   sl_high_i <= 359;
+   sl_low_j  <= 0;
+   sl_high_j <= 99;
+   sl_low_color  <= 0;
+   sl_high_color <= 2;
+
+
+   load_i <= '0';
+   load_j <= '0';
+   load_color <= '0';
+
+   sl_lower_bnd(3*QUANT-1 downto 2*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
+   sl_lower_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
+   sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_color,QUANT));
+
+   sl_upper_bnd(3*QUANT-1 downto 2*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
+   sl_upper_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
+   sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_color,QUANT));
+
+   -- Special definitions 
+
+   -- Entity and control variables
+
+   sl_fire <= ('1');
+
+   -- Convert FIFO Write Port out_1 : ED_11
+   sl_CONTROL(0) <= sl_fire and ('1');
+
+   FIRE <= sl_fire;
+
+   cnt_rst <= sl_cnt_rst or RST;
+
+   -- 
+   -- =============================================
+   -- =             Multirate                      
+   -- =============================================
+   -- Function output parameter "out_0", multirate=1 
+   CNTR_MR0 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(0),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_0,
+         UPPER_BND => sl_mr_ubnd_0,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(0)
+      );
+   -- 
+   -- WRITE_EN indicates if date can be written to WRITE_MUX
+   sl_bla_en      <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
+   WRITE_EN    <=  (others=>'0') when (HALT='1') else sl_bla_en;
+   -- 
+   sl_mr_en    <= (not sl_mr_lock) and WRITE_ST; 
+   sl_enables  <= sl_mr_lock or (sl_mr_done and sl_mr_en); 
+   sl_enable   <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0';  -- and_reduce 
+   ENABLE      <= sl_enable or (not sl_fire);
+   -- 
+   LOCK_PRCS: process(CLK) 
+   begin 
+       if rising_edge(CLK) then 
+           if( RST = '1' ) then 
+               sl_mr_lock <= (others=>'0'); 
+           else  
+               if (ENABLE='1') then 
+                   sl_mr_lock <= (others=>'0'); 
+               else 
+                   for i in 0 to 0 loop 
+                       if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then 
+                           sl_mr_lock(i) <= '1'; 
+                       end if; 
+                   end loop; 
+               end if; 
+           end if; 
+       end if; 
+   end process; 
+   -- END of Multirate definitions 
+   -- 
+   -- =============================================
+   -- =             Iterators                      
+   -- =============================================
+   GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
+   	CNTR_WR : counter
+   	generic map ( 
+   		C_STEP    => CNTR_STEP(i),
+   		C_WIDTH   => CNTR_WIDTH(i)
+   	)
+  	 port map (
+   		CLK       => CLK,
+   		RST       => cnt_rst,
+   		ENABLE    => sl_cntr_en(i),
+   		LOAD      => sl_load(i),
+   		LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		ITERATOR  => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		REG_CNTR  => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		DONE      => sl_done(i)
+   	);
+   end generate;
+   --
+   DONE_PRCS: process(CLK)
+   begin
+   	if rising_edge(CLK) then
+   	    if( RST = '1' ) then
+   		    sl_stop     <= '0';
+   		    sl_done_all <= '0';
+   		    sl_sof      <= '1';
+   	    else 
+   		    if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+   			    sl_stop <= '1';
+   		    elsif (WRAP=true) then
+   			    sl_stop <= '0';
+   		    end if;
+   		    if (sl_stop='0') then
+   			    sl_done_all <= sl_cntr_en(N_CNTRS);
+   		    end if;
+   		    if (ENABLE='1') then
+   			    sl_sof <= sl_eof;
+   		    end if;
+   	    end if;
+   	end if;
+   end process;
+   --
+   sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+   CONTROL <= sl_CONTROL;
+   --
+   DONE <= sl_done_all;     -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+   STOP <= sl_stop;         -- '1' = The couter stoped after the end of the itteration space. 
+   --
+   sl_count      <=  '0' when (sl_stop='1') else
+   			'1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
+   sl_cntr_en(0) <=  sl_count; -- makes the EVAL_LOGIC count
+   --
+   sl_cntr_en(N_CNTRS  downto 1) <= sl_cntr_en(N_CNTRS-1  downto 0) and sl_done(N_CNTRS-1  downto 0);
+   sl_eof <= sl_cntr_en(N_CNTRS);      -- End-of-frame (combinatorial; beter not use it outside)
+   --
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_8/src/vhdl/bunny_static_split2rtl_hwn_nd_8_execution_unit.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_8/src/vhdl/bunny_static_split2rtl_hwn_nd_8_execution_unit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d3041bc3bd3ec663f90a9070dbbb54308adbb74d
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_8/src/vhdl/bunny_static_split2rtl_hwn_nd_8_execution_unit.vhd
@@ -0,0 +1,113 @@
+-- Execute Unit automatically generated by KpnMapper
+-- Function "compaan_outlinedproc3"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_bunny_static_split2rtl_functions_1_lib;
+use compaandesign_com_bunny_static_split2rtl_functions_1_lib.all;
+
+entity bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_8 is
+   generic (
+      N_INPORTS  : natural := 1;
+      N_OUTPORTS : natural := 1;
+      IP_RESET   : natural := 1; 
+      STIM_DIR   : string  := "bla";
+      QUANT      : natural := 32;
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1; 
+      CNTR_QUANT : natural := 32; 
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+   );
+   port (
+      RST        : in  std_logic;
+      CLK        : in  std_logic;
+      -- Funtion Input parameters
+      IN_PORT_0    : in  std_logic_vector(7 downto 0);  -- Param. "tmp1"
+      READ       : out std_logic_vector(N_INPORTS-1 downto 0);
+      EXIST      : in  std_logic_vector(N_INPORTS-1 downto 0);
+      -- Iterators
+      REG_CNTRS_RD : in  std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
+      -- Funtion Output parameters
+      OUT_PORT_0   : out std_logic_vector(7 downto 0);  -- Param. "tmp0"
+      WRITE      : out std_logic_vector(N_OUTPORTS-1 downto 0);
+      FULL       : in  std_logic_vector(N_OUTPORTS-1 downto 0);
+      STOP_RD    : in  std_logic;
+      STOP_WR    : in  std_logic;
+      ERROR      : out std_logic
+   );
+end bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_8 ;
+
+-- Laura implementation
+architecture Laura of bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_8 is
+
+   component compaan_outlinedproc3 is
+      generic (
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1; 
+         CNTR_QUANT : natural := 32; 
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST   : in std_logic;
+         CLK   : in std_logic;
+         -- Inputs 
+         ip_tmp1  : in  std_logic_vector(7 downto 0);  
+         -- Iterators 
+         it_color : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+         it_j : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+         it_i : in  std_logic_vector(CNTR_WIDTH(2)-1 downto 0);
+         EXIST : in  std_logic_vector(0 downto 0);
+         READF : out std_logic_vector(0 downto 0);
+         -- Outputs 
+         op_tmp0 : out std_logic_vector(7 downto 0);
+         FULL  : in  std_logic_vector(0 downto 0);
+         WRITEF: out std_logic_vector(0 downto 0);
+         --
+         STOP_RD : in  std_logic;
+         STOP_WR : in  std_logic;
+         ERROR   : out std_logic
+      );
+   end component;
+
+   signal sl_RST : std_logic;
+
+begin
+
+   sl_RST <= RST when IP_RESET=1 else not RST;
+
+   FUNC : compaan_outlinedproc3
+   generic map (
+         STIM_DIR      => STIM_DIR,
+         c_STAGES      => c_STAGES,
+         N_CNTRS       => N_CNTRS,
+         CNTR_QUANT    => CNTR_QUANT,
+         CNTR_WIDTH    => CNTR_WIDTH
+   )
+   port map (
+      RST   => sl_RST,
+      CLK   => CLK,
+      -- Inputs 
+      ip_tmp1 => IN_PORT_0,
+      -- Iterators 
+      it_color => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
+      it_j => REG_CNTRS_RD(1*CNTR_QUANT+CNTR_WIDTH(1)-1 downto 1*CNTR_QUANT),
+      it_i => REG_CNTRS_RD(2*CNTR_QUANT+CNTR_WIDTH(2)-1 downto 2*CNTR_QUANT),
+      EXIST => EXIST,
+      READF => READ,
+      -- Outputs 
+      op_tmp0 => OUT_PORT_0,
+      FULL  => FULL,
+      WRITEF=> WRITE,
+      -- 
+      STOP_RD => STOP_RD,
+      STOP_WR => STOP_WR,
+      ERROR   => ERROR
+   );
+
+end Laura;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_9/hdllib.cfg b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_9/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..52c2096f22d61c89157d6c2c07523fd74c50a235
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_9/hdllib.cfg
@@ -0,0 +1,18 @@
+hdl_lib_name = compaandesign_com_bunny_static_split2rtl_hwn_nd_9_1
+hdl_library_clause_name = compaandesign_com_bunny_static_split2rtl_hwn_nd_9_1_lib
+hdl_lib_uses_synth = compaandesign_com_bunny_static_split2rtl_functions_1 compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1 compaandesign_com_common_extern_connector_1 
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+	src/vhdl/bunny_static_split2rtl_hwn_nd_9_execution_unit.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_9_eval_logic_rd.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_9_eval_logic_wr.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_9.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_9/src/vhdl/bunny_static_split2rtl_hwn_nd_9.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_9/src/vhdl/bunny_static_split2rtl_hwn_nd_9.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e37574c78fb9ba75db2f53a0307e244259ee791a
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_9/src/vhdl/bunny_static_split2rtl_hwn_nd_9.vhd
@@ -0,0 +1,469 @@
+-- HWN Entity File automatically generated by KpnMapper (writeHdlHWNodeFile)
+-- Top level file for a Hardware Accelerator
+-- Function "invert_image"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+
+library compaandesign_com_common_extern_connector_1_lib;
+use compaandesign_com_common_extern_connector_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_9 is
+   generic (
+      STIM_DIR   : string  := "bla";
+      RESET_HIGH : natural := 1;
+      PAR_WIDTH  : natural := 16;
+      QUANT      : natural := 32;
+      WRAP       : boolean := true
+   );
+   port (
+      --  Non Syncronized Parameters
+      rf_brightness     : in   std_logic_vector( 32-1 downto 0); -- input 
+
+      -- Dataflow input interfaces
+      -- ED_10 : in_0
+      ND_9IP_10_Rd    : out std_logic;
+      ND_9IP_10_Din   : in  std_logic_vector(7 downto 0);
+      ND_9IP_10_Exist : in  std_logic; 
+      ND_9IP_10_CLK   : out std_logic;
+      ND_9IP_10_CTRL  : in  std_logic;
+
+      -- Dataflow Control Input interfaces
+      -- Dataflow output interfaces
+      -- ED_12 : out_0
+      ND_9OP_1_Wr   : out std_logic;
+      ND_9OP_1_Dout : out std_logic_vector(7 downto 0);
+      ND_9OP_1_Full : in  std_logic;
+      ND_9OP_1_CLK  : out std_logic;
+      ND_9OP_1_CTRL : out std_logic;
+
+      PARAM_DT : in  std_logic_vector(PAR_WIDTH+10-1 downto 0);
+      PARAM_LD : in  std_logic;
+
+      RST      : in  std_logic;
+      CLK      : in  std_logic;
+      STOP     : out std_logic;
+      ERROR    : out std_logic;
+      BLOCK_RD : out std_logic
+   );
+end bunny_static_split2rtl_hwn_nd_9;
+
+architecture RTL of bunny_static_split2rtl_hwn_nd_9 is
+   --
+   -- ====================================
+   -- =     Constants declaration        =
+   -- ====================================
+   -- Setting the parameters of the HW Node
+   constant c_IN_PORTS     : natural := 1; -- number of input ports of a HW node
+   constant c_OUT_PORTS    : natural := 1; -- number of output ports of a HW node
+   constant c_IN_FUNC_VAR  : natural := 1; -- number of input ports of a HW IP
+   constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
+   constant c_COUNTERS     : natural := 3; -- number of iterators
+   -- ===========================================
+   -- = Iterators run from Inner to Outer loop  =
+   -- ===========================================
+   constant c_CNTR_QUANT   : natural := 11;
+   constant c_CNTR_STEPS   : t_counter_step  := ( 0=>1, 1=>1, 2=>1, others=>1 );
+   constant c_CNTR_WIDTHS  : t_counter_width := ( 0=>3, 1=>11, 2=>10, others=>10 );
+   constant c_STAGES       : natural := 3; -- number of pipeline stages or delay
+   constant c_IP_RESET     : natural := 1; -- active level of the HW IP reset signal
+   constant c_WRAP         : boolean := WRAP; -- Operation mode: Single_Shot (false) or Continuous (true)
+   constant c_EXT_PAR      : natural := 0; -- number of external parameters
+   constant c_INT_PAR      : natural := 0; -- number of internal parameters
+   constant c_N_PAR        : natural := 0; -- no parameters are used
+   constant c_PAR_BITWIDTH : natural := PAR_WIDTH; -- aggregate bitwidth of the parameter vector
+   constant c_PAR_VECTOR   : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
+       (0,0,0,0), (0,0,0,0)    -- two dummy elements
+   );
+   --
+   -- ====================================
+   -- =     Components declaration       =
+   -- ====================================
+   component bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_9 is
+      generic (
+         N_IN_PORTS    : natural := 1;
+         WRAP          : boolean := true;
+         N_CNTRS       : natural := 1; 
+         QUANT         : natural := 32;
+         PAR_BITWIDTH  : natural :=1;
+         CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+         CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+      );
+      port (
+         RST           : in  std_logic;
+         CLK           : in  std_logic;
+         REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1  downto 0); 
+         READ_EN       : out std_logic_vector(c_IN_FUNC_VAR-1  downto 0);
+         READ_ST       : in  std_logic_vector(c_IN_FUNC_VAR-1  downto 0);
+         HALT          : in  std_logic;
+         FIRE          : out std_logic;
+         DONE          : out std_logic;
+         STOP          : out std_logic;
+         CONTROL       : out std_logic_vector(N_IN_PORTS-1 downto 0);
+         OBTAIN        : out std_logic_vector(N_IN_PORTS-1 downto 0);
+         RELEASE       : out std_logic_vector(N_IN_PORTS-1 downto 0)
+      );
+   end component;
+
+   component READ_MUX is
+      generic (
+         N_PORTS    : natural := 1;
+         PORT_WIDTH : natural := 32  
+      );
+      port(
+         IN_PORTS   : in  std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
+         EXISTS     : in  std_logic_vector(N_PORTS-1 downto 0);
+         READS      : out std_logic_vector(N_PORTS-1 downto 0);
+         SOFS       : in  std_logic_vector(N_PORTS-1 downto 0);
+
+         OUT_PORT   : out std_logic_vector(PORT_WIDTH-1 downto 0);
+         EXIST      : out std_logic;
+         READ       : in  std_logic;
+         SOF        : in  std_logic;
+		CLK        : in std_logic;
+
+         READ_EN    : in  std_logic;
+         READ_ST    : out std_logic;
+         CONTROL    : in  std_logic_vector(N_PORTS-1 downto 0);
+         OBTAIN     : in  std_logic_vector(N_PORTS-1 downto 0);
+         RELEASE    : in  std_logic_vector(N_PORTS-1 downto 0)
+      );
+   end component;
+
+   component bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_9 is
+      generic ( 
+         N_OUT_PORTS   : natural := 1;
+         WRAP          : boolean := true;
+         N_CNTRS       : natural := 1; 
+         QUANT         : natural := 32;
+         PAR_BITWIDTH  : natural :=1;
+         CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+         CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+      );
+      port (
+         RST           : in  std_logic;
+         CLK           : in  std_logic;
+         WRITE_EN      : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+         WRITE_ST      : in  std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+         HALT          : in  std_logic;
+         FIRE          : out std_logic;
+         DONE          : out std_logic;
+         STOP          : out std_logic;
+         CONTROL       : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+      );
+   end component;
+
+   component WRITE_DEMUX is
+      generic (
+         N_PORTS : natural := 1
+      );
+      port(
+         WRITES   : out std_logic_vector(N_PORTS-1 downto 0);
+         WRITE    : in  std_logic;
+
+         FULLS    : in  std_logic_vector(N_PORTS-1 downto 0);
+         FULL     : out std_logic;
+
+         WRITE_EN : in  std_logic;
+         WRITE_ST : out std_logic;
+         CONTROL  : in  std_logic_vector(N_PORTS-1 downto 0)
+      );
+   end component;
+
+
+   component bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_9 is
+      generic (
+         N_INPORTS  : natural := 1;
+         N_OUTPORTS : natural := 1;
+         IP_RESET   : natural := 1;
+         QUANT      : natural := 32;
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1;
+         CNTR_QUANT : natural := 32;
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST        : in  std_logic;
+         CLK        : in  std_logic;
+
+      --  Non Syncronized Parameters
+      rf_brightness     : in  std_logic_vector( 32-1 downto 0); -- input
+         -- Iterators
+         REG_CNTRS_RD : in  std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
+         -- Func. Input parameters
+         IN_PORT_0 : in  std_logic_vector(7 downto 0); -- x
+         READ       : out std_logic_vector(N_INPORTS-1 downto 0);
+         EXIST      : in  std_logic_vector(N_INPORTS-1 downto 0);
+         -- Func. Output parameters
+         OUT_PORT_0 : out std_logic_vector(7 downto 0); -- return_value
+         WRITE      : out std_logic_vector(N_OUTPORTS-1 downto 0);
+         FULL       : in  std_logic_vector(N_OUTPORTS-1 downto 0);
+         --
+         STOP_RD    : in  std_logic;
+         STOP_WR    : in  std_logic;
+         ERROR      : out std_logic
+      );
+   end component;
+
+   component INTERNAL_PARAMETERS is 
+      generic (
+         PAR_BITWIDTH : natural:=1;
+         PAR_VECTOR   : t_par_vector;
+         N_PAR        : natural:=0;
+         START_IN_RUN  : boolean := FALSE
+      );
+      port (  
+         RST        : in  std_logic;
+         CLK        : in  std_logic;
+
+         HALT_RD    : out std_logic;
+         HALT_WR    : out std_logic;
+         SOF_RD     : in  std_logic;
+         SOF_WR     : in  std_logic;
+         LOAD_PARAM : out std_logic;
+
+         par_one_in_Rd    : out std_logic;
+         par_one_in_Din   : in std_logic_vector(32-1 downto 0);
+         par_one_in_Exist : in std_logic;
+         par_one_in_CLK   : out std_logic;
+         par_one_in_CTRL  : in std_logic;
+
+         PARAMETERS_RD : out std_logic_vector(32-1 downto 0);
+         PARAMETERS_WR : out std_logic_vector(32-1 downto 0)
+      );
+   end component;
+
+   --
+   -- ====================================
+   -- =       Signals declaration        =
+   -- ====================================
+   -- 
+   -- HW Node Input Ports
+   signal sl_IN_PORTS_0   : std_logic_vector(1*8-1 downto 0); -- x
+   signal sl_EXISTS       : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_READS        : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_CTRLS        : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_control_rd   : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_obtain_rd    : std_logic_vector(c_IN_PORTS-1 downto 0);
+   signal sl_release_rd   : std_logic_vector(c_IN_PORTS-1 downto 0);
+   -- 
+   -- Func. Input parameters
+   signal sl_in_port_0    : std_logic_vector(7 downto 0); -- x
+   signal sl_exist        : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read         : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read_en      : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   signal sl_read_st      : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
+   -- 
+   signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
+   -- 
+   -- HW Node Output Ports
+   signal sl_WRITES       : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_FULLS        : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_control_wr   : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   signal sl_lortnoc_wr   : std_logic_vector(c_OUT_PORTS-1 downto 0);
+   -- 
+   -- Func. Output parameters
+   signal sl_out_port_0   : std_logic_vector(7 downto 0); -- return_value
+   signal sl_full         : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write        : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write_en     : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   signal sl_write_st     : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
+   -- 
+   -- 
+   signal sl_halt             : std_logic;
+   signal sl_halted           : std_logic;
+   signal sl_halt_wr          : std_logic;
+   signal sl_halt_rd          : std_logic;
+   signal sl_param_halt_wr    : std_logic;
+   signal sl_param_halt_rd    : std_logic;
+   signal sl_done_wr          : std_logic;
+   signal sl_done_rd          : std_logic;
+   signal sl_stop_wr          : std_logic;
+   signal sl_stop_rd          : std_logic;
+   signal sl_fire_wr          : std_logic;
+   signal sl_fire_rd          : std_logic;
+   signal sl_sof_wr           : std_logic;
+   signal sl_sof_rd           : std_logic;
+   signal sl_error            : std_logic;
+   signal sl_load_param       : std_logic;
+
+   --  
+   -- Parameter related signals 
+   signal sl_param_fifo_full     : std_logic;
+   signal sl_sync_num            : std_logic_vector(9 downto 0);
+
+   signal sl_RST : std_logic;
+
+begin 
+
+   sl_RST <= RST when RESET_HIGH=1 else not RST;
+      ND_9IP_10_CLK   <= CLK;
+      ND_9OP_1_CLK  <= CLK;
+
+   --
+   -- ==========================================================
+   -- =       HWN Input related modules                        =
+   -- ==========================================================
+   -- Func. Input param. "x"
+   RD_MUX_0 : READ_MUX
+   generic map (
+      N_PORTS    => 1,
+      PORT_WIDTH => 8
+   )
+   port map (
+      IN_PORTS   => sl_IN_PORTS_0,
+      EXISTS     => sl_EXISTS(0 downto 0),
+      READS      => sl_READS(0 downto 0),
+      SOFS       => sl_CTRLS(0 downto 0),
+
+      OUT_PORT   => sl_in_port_0,
+      EXIST      => sl_exist(0),
+      READ       => sl_read(0),
+      SOF        => sl_sof_rd,
+      CLK        => CLK,
+
+      READ_EN    => sl_read_en(0),
+      READ_ST    => sl_read_st(0),
+      CONTROL    => sl_control_rd(0 downto 0),
+      OBTAIN     => sl_obtain_rd(0 downto 0),
+      RELEASE    => sl_release_rd(0 downto 0)
+   );
+
+   ND_9IP_10_Rd   <= sl_READS(0);
+
+   sl_IN_PORTS_0 <= ND_9IP_10_Din;
+
+   sl_EXISTS(0)   <= ND_9IP_10_Exist ;
+   sl_CTRLS(0)    <= ND_9IP_10_CTRL ;
+
+   EVAL_RD : bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_9
+   generic map ( 
+      N_IN_PORTS    => c_IN_PORTS,
+      WRAP          => c_WRAP,
+      N_CNTRS       => c_COUNTERS,
+      QUANT         => c_CNTR_QUANT,
+      PAR_BITWIDTH  => c_PAR_BITWIDTH,
+      CNTR_STEP     => c_CNTR_STEPS,
+      CNTR_WIDTH    => c_CNTR_WIDTHS
+   )
+   port map(
+      RST           => sl_RST,
+      CLK           => CLK,
+      REG_CNTRS     => sl_REG_CNTRS_RD,
+      READ_EN       => sl_read_en,
+      READ_ST       => sl_read_st,
+      HALT          => sl_halt_rd,
+      FIRE          => sl_fire_rd,
+      DONE          => sl_done_rd,
+      STOP          => sl_stop_rd,
+      CONTROL       => sl_control_rd,
+      OBTAIN        => sl_obtain_rd,
+      RELEASE       => sl_release_rd
+   );
+
+   --
+   -- ==========================================================
+   -- =       HWN Output related modules                       =
+   -- ==========================================================
+   -- 
+   -- Func. Output param. "return_value"
+   DEMUX_0 : WRITE_DEMUX
+   generic map (
+      N_PORTS => 1
+   )
+   port map (
+      WRITES   => sl_WRITES(0 downto 0),
+      FULLS    => sl_FULLS(0 downto 0),
+      CONTROL  => sl_lortnoc_wr(0 downto 0),
+      WRITE    => sl_write(0),
+      FULL     => sl_full(0),
+      WRITE_EN => sl_write_en(0),
+      WRITE_ST => sl_write_st(0)
+   );
+   --
+   ND_9OP_1_Dout <= sl_out_port_0;  -- Func. Output param. "return_value"
+   ND_9OP_1_CTRL <= sl_sof_wr ;
+   ND_9OP_1_Wr   <= sl_WRITES(0);
+   sl_FULLS(0) <= ND_9OP_1_Full;
+   sl_lortnoc_wr(0) <= sl_control_wr(0);
+   --
+   --
+   EVAL_WR : bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_9
+   generic map ( 
+      N_OUT_PORTS   => c_OUT_PORTS,
+      WRAP          => c_WRAP,
+      N_CNTRS       => c_COUNTERS,
+      QUANT         => c_CNTR_QUANT,
+      PAR_BITWIDTH  => c_PAR_BITWIDTH,
+      CNTR_STEP     => c_CNTR_STEPS,
+      CNTR_WIDTH    => c_CNTR_WIDTHS
+   )
+   port map (
+      RST           => sl_RST,
+      CLK           => CLK,
+      WRITE_EN      => sl_write_en,
+      WRITE_ST      => sl_write_st,
+      HALT          => sl_halt_wr,
+      FIRE          => sl_fire_wr,
+      DONE          => sl_done_wr,
+      STOP          => sl_stop_wr,
+      CONTROL       => sl_control_wr
+   );
+
+   --
+   -- ==========================================================
+   -- =       HWN Execution Unit                               =
+   -- ==========================================================
+   EX : bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_9
+   generic map (
+      N_INPORTS  => c_IN_FUNC_VAR,
+      N_OUTPORTS => c_OUT_FUNC_VAR, 
+      IP_RESET   => c_IP_RESET,
+      QUANT      => QUANT,
+      STIM_DIR   => STIM_DIR,
+      c_STAGES   => c_STAGES,
+      N_CNTRS    => c_COUNTERS,
+      CNTR_QUANT => c_CNTR_QUANT,
+      CNTR_WIDTH => c_CNTR_WIDTHS
+   )
+   port map (
+      RST        => sl_RST,
+      CLK        => CLK,
+      -- RegFile
+      rf_brightness     => rf_brightness,
+      -- Iterators
+      REG_CNTRS_RD => sl_REG_CNTRS_RD,
+      -- Func. Input parameters
+      IN_PORT_0    => sl_in_port_0,
+      READ       => sl_read,
+      EXIST      => sl_exist,
+      -- Func. Output parameters
+      OUT_PORT_0   => sl_out_port_0,
+      WRITE      => sl_write,
+      FULL       => sl_full,
+      --
+      STOP_WR    => sl_stop_wr,
+      STOP_RD    => sl_stop_rd,
+      ERROR      => sl_error
+   );
+
+   -- ==========================================================
+   -- =       PARAMETERIZATION                                 =
+   -- ==========================================================
+   -- no parameters
+   sl_halt_rd <= '0';
+   sl_halt_wr <= '0';
+--   sl_halted  <= sl_sof_rd;
+   STOP <= sl_done_wr;
+   ERROR <= sl_error;
+   BLOCK_RD <= not (  (  sl_READS(0)  ) );
+
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_9/src/vhdl/bunny_static_split2rtl_hwn_nd_9_eval_logic_rd.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_9/src/vhdl/bunny_static_split2rtl_hwn_nd_9_eval_logic_rd.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..05900aec6ac39f79d9fb48549975402eee5d620a
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_9/src/vhdl/bunny_static_split2rtl_hwn_nd_9_eval_logic_rd.vhd
@@ -0,0 +1,307 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_9 is
+   generic (
+      N_IN_PORTS    : natural := 1;
+      WRAP          : boolean := true;
+      N_CNTRS       : natural := 1; 
+      QUANT         : natural := 32;
+      PAR_BITWIDTH  : natural  :=1;
+      CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+      CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST           : in  std_logic;
+      CLK           : in  std_logic;
+      REG_CNTRS     : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
+      READ_EN       : out std_logic_vector(0 downto 0);
+      READ_ST       : in  std_logic_vector(0 downto 0);
+      HALT          : in  std_logic;
+      FIRE          : out std_logic;
+      DONE          : out std_logic;
+      STOP          : out std_logic;
+      CONTROL       : out std_logic_vector(N_IN_PORTS-1 downto 0);
+      OBTAIN        : out std_logic_vector(N_IN_PORTS-1 downto 0);
+      RELEASE       : out std_logic_vector(N_IN_PORTS-1 downto 0)
+   );
+end bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_9;
+
+architecture RTL of bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_9 is
+   -- 
+   component counter is 
+      generic( 
+         C_STEP    : natural := 10; 
+         C_WIDTH   : natural := 10 
+      ); 
+      port ( 
+         RST       : in  std_logic; 
+         CLK       : in  std_logic; 
+         ENABLE    : in  std_logic; 
+         LOAD      : in  std_logic; 
+         LOWER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         UPPER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         ITERATOR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         REG_CNTR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         DONE      : out std_logic 
+      ); 
+   end component; 
+   -- 
+   component it_mod is 
+   generic( 
+      C_MOD     : natural := 10; 
+      C_WIDTH   : natural := 10; 
+      C_INIT    : natural :=  1; 
+      C_STEP    : natural :=  1  
+   ); 
+   port ( 
+      RST       : in  std_logic; 
+      CLK       : in  std_logic; 
+      LOAD      : in  std_logic; 
+      ENABLE    : in  std_logic; 
+      MODULE    : out std_logic_vector(C_WIDTH-1 downto 0) 
+   ); 
+   end component; 
+   -- 
+   --  
+   -- Parameter related signals 
+   -- 
+   -- Iterator (counter) related signals 
+   signal sl_low_i, sl_high_i : integer;
+   signal sl_low_j, sl_high_j : integer;
+   signal sl_low_color, sl_high_color : integer;
+   signal sl_loop_i, sl_loop_i_rg : integer;
+   signal sl_loop_j, sl_loop_j_rg : integer;
+   signal sl_loop_color, sl_loop_color_rg : integer;
+   signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   -- 
+   signal sl_cntr_en  : std_logic_vector(N_CNTRS   downto 0); 
+   signal sl_done     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_done_all : std_logic; 
+   signal sl_load     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_stop     : std_logic; 
+   signal sl_fire     : std_logic; 
+   signal sl_sof      : std_logic; 
+   signal sl_eof      : std_logic; 
+   signal sl_count    : std_logic; 
+
+   -- alias signals 
+   alias update_i : std_logic is sl_cntr_en(2);
+   alias update_j : std_logic is sl_cntr_en(1);
+   alias update_color : std_logic is sl_cntr_en(0);
+   alias load_i : std_logic is sl_load(2);
+   alias load_j : std_logic is sl_load(1);
+   alias load_color : std_logic is sl_load(0);
+
+   -- Trigger signals 
+   signal sl_trigger_i : std_logic;
+   signal sl_trigger_j : std_logic;
+   signal sl_trigger_color : std_logic;
+
+   -- Special Control signal
+   signal sl_CONTROL       : std_logic_vector(N_IN_PORTS-1 downto 0);
+   signal sl_no_request    : std_logic;
+   -- 
+   -- Multirate related signals
+   signal sl_bla_en   : std_logic_vector(0 downto 0); 
+   signal sl_mr_en    : std_logic_vector(0 downto 0); 
+   signal sl_mr_done  : std_logic_vector(0 downto 0); 
+   signal sl_mr_lock  : std_logic_vector(0 downto 0); 
+   signal sl_enables  : std_logic_vector(0 downto 0); 
+   signal sl_enable   : std_logic; 
+   signal ENABLE      : std_logic; 
+   -- Function input parameter "in_0", multirate=1 
+   constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+
+
+   signal sl_obtain0  : std_logic;
+   signal sl_release0 : std_logic;
+
+   -- define control variables 
+
+   type state_type is (s_idle, s_halt, s_count, s_release);
+   signal state : state_type;
+   signal halt_cnt : integer;
+   signal sl_halt : std_logic;
+
+   signal sl_cnt_rst : std_logic;
+   signal cnt_rst : std_logic;
+
+begin
+
+   -- =============================================
+   -- =             MOD Functions                  
+   -- =============================================
+   -- END of MOD definitions 
+   -- =============================================
+   -- =             Parameter Functions            
+   -- =============================================
+   sl_cnt_rst <= '0';
+   sl_halt <= HALT;
+
+   -- END of Parameter definitions 
+   sl_loop_i    <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(2)+2*QUANT-1 downto 2*QUANT)));
+   sl_loop_i_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(2)+2*QUANT-1 downto 2*QUANT)));
+   sl_loop_j    <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_j_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_color    <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+   sl_loop_color_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+   -- Const bounds for-loops 
+   sl_low_i  <= 0;
+   sl_high_i <= 359;
+   sl_low_j  <= 100;
+   sl_high_j <= 639;
+   sl_low_color  <= 0;
+   sl_high_color <= 2;
+
+
+   load_i <= '0';
+   load_j <= '0';
+   load_color <= '0';
+
+   sl_lower_bnd(3*QUANT-1 downto 2*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
+   sl_lower_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
+   sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_color,QUANT));
+
+   sl_upper_bnd(3*QUANT-1 downto 2*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
+   sl_upper_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
+   sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_color,QUANT));
+   -- Special definitions 
+
+   -- Entity and control variables
+   -- Release matrix expressions
+
+   sl_fire <= ('1');
+
+   -- Convert FIFO Read Port ND_9IP_10 Argument in_1 : ED_10 : 0 of type IOMM
+   sl_obtain0 <= ('1');  -- set obtain/release to const value; not used
+   sl_release0 <= ('1');
+
+   sl_CONTROL(0) <= sl_fire and ('1');
+   OBTAIN(0) <= sl_obtain0;
+   RELEASE(0) <= sl_release0;
+
+   FIRE <= sl_fire;
+
+   cnt_rst <= sl_cnt_rst or RST;
+
+   -- 
+   -- =============================================
+   -- =             Multirate                      
+   -- =============================================
+   -- Function input parameter "in_0", multirate=1 
+   CNTR_MR0 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(0),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_0,
+         UPPER_BND => sl_mr_ubnd_0,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(0)
+      );
+   -- READ_EN indicates if READ_MUX can read data
+   sl_bla_en   <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');  
+   READ_EN     <= (others=>'0') when (HALT='1') else sl_bla_en;  
+   sl_mr_en   <= READ_ST; 
+   sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en); 
+   sl_enable  <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce 
+   ENABLE     <=  sl_enable or (not sl_fire);
+   -- 
+   LOCK_PRCS: process(CLK) 
+   begin 
+       if rising_edge(CLK) then 
+           if( RST = '1' ) then 
+               sl_mr_lock <= (others=>'0'); 
+           else  
+               if (ENABLE='1') then 
+                   sl_mr_lock <= (others=>'0'); 
+               else 
+                   for i in 0 to 0 loop 
+                       if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then 
+                           sl_mr_lock(i) <= '1'; 
+                       end if; 
+                   end loop; 
+               end if; 
+           end if; 
+       end if; 
+   end process; 
+   -- END of Multirate definitions 
+   -- 
+   -- =============================================
+   -- =             Iterators                      
+   -- =============================================
+   GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
+   	CNTR_RD : counter
+   	generic map ( 
+   		C_STEP    => CNTR_STEP(i),
+   		C_WIDTH   => CNTR_WIDTH(i)
+   	)
+  	 port map (
+   		CLK       => CLK,
+   		RST       => cnt_rst,
+   		ENABLE    => sl_cntr_en(i),
+			LOAD      => sl_load(i),
+   		LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		ITERATOR  => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		REG_CNTR  => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		DONE      => sl_done(i)
+   	);
+   end generate;
+   --
+   DONE_PRCS: process(CLK)
+   begin
+   	if rising_edge(CLK) then
+          if( RST = '1' ) then
+   		    sl_stop     <= '0';
+   		    sl_done_all <= '0';
+   		    sl_sof      <= '1';
+   	    else 
+   		    if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+   			    sl_stop <= '1';
+   		    elsif (WRAP=true) then
+   			    sl_stop <= '0';
+   		    end if;
+   		    if (sl_stop='0') then
+   			    sl_done_all <= sl_cntr_en(N_CNTRS);
+   		    end if;
+   		    if (ENABLE='1') then
+   			    sl_sof <= sl_eof;
+   		    end if;
+   	    end if;
+   	end if;
+   end process;
+   --
+   sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+   CONTROL <= sl_CONTROL;
+   --
+   REG_CNTRS <= sl_reg_cntrs; 
+   DONE <= sl_done_all;     -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+   STOP <= sl_stop;         -- '1' = The couter stoped after the end of the itteration space. 
+   --
+   sl_count      <=  '0' when (sl_stop='1') else
+                     '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
+   sl_cntr_en(0) <=  sl_count; -- makes the EVAL_LOGIC count
+   --
+   sl_cntr_en(N_CNTRS  downto 1) <= sl_cntr_en(N_CNTRS-1  downto 0) and sl_done(N_CNTRS-1  downto 0);
+   sl_eof <= sl_cntr_en(N_CNTRS);   -- End-of-frame
+   --
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_9/src/vhdl/bunny_static_split2rtl_hwn_nd_9_eval_logic_wr.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_9/src/vhdl/bunny_static_split2rtl_hwn_nd_9_eval_logic_wr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..24bdd76428f39cc8b842cdf3cf261b91eaaf1725
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_9/src/vhdl/bunny_static_split2rtl_hwn_nd_9_eval_logic_wr.vhd
@@ -0,0 +1,297 @@
+-- File automatically generated by KpnMapper
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_hwnode_1_lib;
+use compaandesign_com_common_hwnode_1_lib.all;
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+entity bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_9 is
+   generic ( 
+      N_OUT_PORTS   : natural := 1;
+      WRAP          : boolean := true;
+      N_CNTRS       : natural := 1;
+      QUANT         : natural := 32;
+      PAR_BITWIDTH  : natural :=1;
+      CNTR_STEP     : t_counter_step  := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
+      CNTR_WIDTH    : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
+   );
+   port (
+      RST           : in  std_logic;
+      CLK           : in  std_logic;
+      WRITE_EN      : out std_logic_vector(0 downto 0);
+      WRITE_ST      : in  std_logic_vector(0 downto 0);
+      HALT          : in  std_logic;
+      FIRE          : out std_logic;
+      DONE          : out std_logic;
+      STOP          : out std_logic;
+      CONTROL       : out std_logic_vector(N_OUT_PORTS-1 downto 0)
+   );
+end bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_9;
+
+architecture RTL of bunny_static_split2rtl_EVAL_LOGIC_WR_hwn_nd_9 is	
+   -- 
+   component counter is 
+      generic( 
+         C_STEP    : natural := 10; 
+         C_WIDTH   : natural := 10 
+      ); 
+      port ( 
+         RST       : in  std_logic; 
+         CLK       : in  std_logic; 
+         ENABLE    : in  std_logic; 
+         LOAD      : in  std_logic; 
+         LOWER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         UPPER_BND : in  std_logic_vector(C_WIDTH-1 downto 0); 
+         ITERATOR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         REG_CNTR  : out std_logic_vector(C_WIDTH-1 downto 0); 
+         DONE      : out std_logic 
+      ); 
+   end component; 
+   -- 
+   component it_mod is 
+   generic( 
+      C_MOD     : natural := 10; 
+      C_WIDTH   : natural := 10; 
+      C_INIT    : natural :=  1; 
+      C_STEP    : natural :=  1  
+   ); 
+   port ( 
+      RST       : in  std_logic; 
+      CLK       : in  std_logic; 
+      LOAD      : in  std_logic; 
+      ENABLE    : in  std_logic; 
+      MODULE    : out std_logic_vector(C_WIDTH-1 downto 0) 
+   ); 
+   end component; 
+   -- 
+   -- Multirate related signals
+   signal sl_bla_en   : std_logic_vector(0 downto 0); 
+   signal sl_mr_en    : std_logic_vector(0 downto 0); 
+   signal sl_mr_done  : std_logic_vector(0 downto 0); 
+   signal sl_mr_lock  : std_logic_vector(0 downto 0); 
+   signal sl_enables  : std_logic_vector(0 downto 0); 
+   signal sl_enable   : std_logic; 
+   signal ENABLE      : std_logic; 
+   -- Function output parameter "out_0", multirate=1 
+   constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1)); 
+   --  
+   -- Parameter related signals 
+   --  
+   -- Iterator (counter) related signals 
+   signal sl_low_i, sl_high_i : integer; 
+   signal sl_low_j, sl_high_j : integer; 
+   signal sl_low_color, sl_high_color : integer; 
+   signal sl_loop_i, sl_loop_i_rg : integer;
+   signal sl_loop_j, sl_loop_j_rg : integer;
+   signal sl_loop_color, sl_loop_color_rg : integer;
+   signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0); 
+   -- 
+   signal sl_cntr_en  : std_logic_vector(N_CNTRS   downto 0); 
+   signal sl_done     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_done_all : std_logic; 
+   signal sl_load     : std_logic_vector(N_CNTRS-1 downto 0); 
+   signal sl_stop     : std_logic; 
+   signal sl_fire     : std_logic; 
+   signal sl_eof      : std_logic; 
+   signal sl_sof      : std_logic; 
+   signal sl_count    : std_logic; 
+   -- 
+   -- Special Control signal
+   signal sl_CONTROL       : std_logic_vector(N_OUT_PORTS-1 downto 0);
+   signal sl_no_request    : std_logic;
+   -- 
+   -- alias signals 
+   alias update_i : std_logic is sl_cntr_en(2);
+   alias update_j : std_logic is sl_cntr_en(1);
+   alias update_color : std_logic is sl_cntr_en(0);
+   -- 
+   alias load_i : std_logic is sl_load(2);
+   alias load_j : std_logic is sl_load(1);
+   alias load_color : std_logic is sl_load(0);
+   -- Trigger signals 
+   signal sl_trigger_i : std_logic;
+   signal sl_trigger_j : std_logic;
+   signal sl_trigger_color : std_logic;
+
+
+   -- define control variables 
+   -- MOD related signals 
+
+
+   type state_type is (s_idle, s_halt, s_count, s_release);
+   signal state : state_type;
+   signal halt_cnt : integer;
+   signal sl_halt : std_logic;
+
+   signal sl_cnt_rst : std_logic;
+   signal cnt_rst : std_logic;
+
+begin
+
+   -- =============================================
+   -- =             MOD Functions                  
+   -- =============================================
+   -- END of MOD definitions 
+   --  
+   -- Parameter related signal assignments 
+   sl_cnt_rst <= '0';
+   sl_halt <= HALT;
+   -- END of Parameter definitions 
+
+   sl_loop_i    <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(2)+2*QUANT-1 downto 2*QUANT)));
+   sl_loop_i_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(2)+2*QUANT-1 downto 2*QUANT)));
+   sl_loop_j    <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_j_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(1)+1*QUANT-1 downto 1*QUANT)));
+   sl_loop_color    <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+   sl_loop_color_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
+
+   -- Const bounds for-loops 
+   sl_low_i  <= 0;
+   sl_high_i <= 359;
+   sl_low_j  <= 100;
+   sl_high_j <= 639;
+   sl_low_color  <= 0;
+   sl_high_color <= 2;
+
+
+   load_i <= '0';
+   load_j <= '0';
+   load_color <= '0';
+
+   sl_lower_bnd(3*QUANT-1 downto 2*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
+   sl_lower_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
+   sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_color,QUANT));
+
+   sl_upper_bnd(3*QUANT-1 downto 2*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
+   sl_upper_bnd(2*QUANT-1 downto 1*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
+   sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_color,QUANT));
+
+   -- Special definitions 
+
+   -- Entity and control variables
+
+   sl_fire <= ('1');
+
+   -- Convert FIFO Write Port out_1 : ED_12
+   sl_CONTROL(0) <= sl_fire and ('1');
+
+   FIRE <= sl_fire;
+
+   cnt_rst <= sl_cnt_rst or RST;
+
+   -- 
+   -- =============================================
+   -- =             Multirate                      
+   -- =============================================
+   -- Function output parameter "out_0", multirate=1 
+   CNTR_MR0 : counter 
+      generic map ( 
+         C_STEP    => 1,
+         C_WIDTH   => 1
+      )
+      port map (
+         CLK       => CLK,
+         RST       => RST,
+         ENABLE    => sl_mr_en(0),
+         LOAD      => '0',
+         LOWER_BND => sl_mr_lbnd_0,
+         UPPER_BND => sl_mr_ubnd_0,
+         ITERATOR  => open,
+         REG_CNTR  => open,
+         DONE      => sl_mr_done(0)
+      );
+   -- 
+   -- WRITE_EN indicates if date can be written to WRITE_MUX
+   sl_bla_en      <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
+   WRITE_EN    <=  (others=>'0') when (HALT='1') else sl_bla_en;
+   -- 
+   sl_mr_en    <= (not sl_mr_lock) and WRITE_ST; 
+   sl_enables  <= sl_mr_lock or (sl_mr_done and sl_mr_en); 
+   sl_enable   <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0';  -- and_reduce 
+   ENABLE      <= sl_enable or (not sl_fire);
+   -- 
+   LOCK_PRCS: process(CLK) 
+   begin 
+       if rising_edge(CLK) then 
+           if( RST = '1' ) then 
+               sl_mr_lock <= (others=>'0'); 
+           else  
+               if (ENABLE='1') then 
+                   sl_mr_lock <= (others=>'0'); 
+               else 
+                   for i in 0 to 0 loop 
+                       if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then 
+                           sl_mr_lock(i) <= '1'; 
+                       end if; 
+                   end loop; 
+               end if; 
+           end if; 
+       end if; 
+   end process; 
+   -- END of Multirate definitions 
+   -- 
+   -- =============================================
+   -- =             Iterators                      
+   -- =============================================
+   GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
+   	CNTR_WR : counter
+   	generic map ( 
+   		C_STEP    => CNTR_STEP(i),
+   		C_WIDTH   => CNTR_WIDTH(i)
+   	)
+  	 port map (
+   		CLK       => CLK,
+   		RST       => cnt_rst,
+   		ENABLE    => sl_cntr_en(i),
+   		LOAD      => sl_load(i),
+   		LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		ITERATOR  => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		REG_CNTR  => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
+   		DONE      => sl_done(i)
+   	);
+   end generate;
+   --
+   DONE_PRCS: process(CLK)
+   begin
+   	if rising_edge(CLK) then
+   	    if( RST = '1' ) then
+   		    sl_stop     <= '0';
+   		    sl_done_all <= '0';
+   		    sl_sof      <= '1';
+   	    else 
+   		    if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
+   			    sl_stop <= '1';
+   		    elsif (WRAP=true) then
+   			    sl_stop <= '0';
+   		    end if;
+   		    if (sl_stop='0') then
+   			    sl_done_all <= sl_cntr_en(N_CNTRS);
+   		    end if;
+   		    if (ENABLE='1') then
+   			    sl_sof <= sl_eof;
+   		    end if;
+   	    end if;
+   	end if;
+   end process;
+   --
+   sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0') and sl_halt='0') else '1';
+   CONTROL <= sl_CONTROL;
+   --
+   DONE <= sl_done_all;     -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
+   STOP <= sl_stop;         -- '1' = The couter stoped after the end of the itteration space. 
+   --
+   sl_count      <=  '0' when (sl_stop='1') else
+   			'1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
+   sl_cntr_en(0) <=  sl_count; -- makes the EVAL_LOGIC count
+   --
+   sl_cntr_en(N_CNTRS  downto 1) <= sl_cntr_en(N_CNTRS-1  downto 0) and sl_done(N_CNTRS-1  downto 0);
+   sl_eof <= sl_cntr_en(N_CNTRS);      -- End-of-frame (combinatorial; beter not use it outside)
+   --
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_9/src/vhdl/bunny_static_split2rtl_hwn_nd_9_execution_unit.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_9/src/vhdl/bunny_static_split2rtl_hwn_nd_9_execution_unit.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..672e24a87044a60101b9ea64ae635d24484df384
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_9/src/vhdl/bunny_static_split2rtl_hwn_nd_9_execution_unit.vhd
@@ -0,0 +1,119 @@
+-- Execute Unit automatically generated by KpnMapper
+-- Function "invert_image"
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library compaandesign_com_common_common_1_lib;
+use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
+
+library compaandesign_com_bunny_static_split2rtl_functions_1_lib;
+use compaandesign_com_bunny_static_split2rtl_functions_1_lib.all;
+
+entity bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_9 is
+   generic (
+      N_INPORTS  : natural := 1;
+      N_OUTPORTS : natural := 1;
+      IP_RESET   : natural := 1; 
+      STIM_DIR   : string  := "bla";
+      QUANT      : natural := 32;
+      c_STAGES   : natural := 1;
+      N_CNTRS    : natural := 1; 
+      CNTR_QUANT : natural := 32; 
+      CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+   );
+   port (
+      RST        : in  std_logic;
+      CLK        : in  std_logic;
+      --  Non Syncronized Parameters
+      rf_brightness     : in  std_logic_vector( 32-1 downto 0); -- input 
+      -- Funtion Input parameters
+      IN_PORT_0    : in  std_logic_vector(7 downto 0);  -- Param. "x"
+      READ       : out std_logic_vector(N_INPORTS-1 downto 0);
+      EXIST      : in  std_logic_vector(N_INPORTS-1 downto 0);
+      -- Iterators
+      REG_CNTRS_RD : in  std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
+      -- Funtion Output parameters
+      OUT_PORT_0   : out std_logic_vector(7 downto 0);  -- Param. "return_value"
+      WRITE      : out std_logic_vector(N_OUTPORTS-1 downto 0);
+      FULL       : in  std_logic_vector(N_OUTPORTS-1 downto 0);
+      STOP_RD    : in  std_logic;
+      STOP_WR    : in  std_logic;
+      ERROR      : out std_logic
+   );
+end bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_9 ;
+
+-- Laura implementation
+architecture Laura of bunny_static_split2rtl_EXECUTION_UNIT_hwn_nd_9 is
+
+   component invert_image is
+      generic (
+         STIM_DIR   : string  := "bla";
+         c_STAGES   : natural := 1;
+         N_CNTRS    : natural := 1; 
+         CNTR_QUANT : natural := 32; 
+         CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 ) 
+      );
+      port (
+         RST   : in std_logic;
+         CLK   : in std_logic;
+      -- Non Syncronized Parameters
+      rf_brightness     : in  std_logic_vector( 32-1 downto 0); -- input
+         -- Inputs 
+         ip_x  : in  std_logic_vector(7 downto 0);  
+         -- Iterators 
+         it_color : in  std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
+         it_j : in  std_logic_vector(CNTR_WIDTH(1)-1 downto 0);
+         it_i : in  std_logic_vector(CNTR_WIDTH(2)-1 downto 0);
+         EXIST : in  std_logic_vector(0 downto 0);
+         READF : out std_logic_vector(0 downto 0);
+         -- Outputs 
+         op_return_value : out std_logic_vector(7 downto 0);
+         FULL  : in  std_logic_vector(0 downto 0);
+         WRITEF: out std_logic_vector(0 downto 0);
+         --
+         STOP_RD : in  std_logic;
+         STOP_WR : in  std_logic;
+         ERROR   : out std_logic
+      );
+   end component;
+
+   signal sl_RST : std_logic;
+
+begin
+
+   sl_RST <= RST when IP_RESET=1 else not RST;
+
+   FUNC : invert_image
+   generic map (
+         STIM_DIR      => STIM_DIR,
+         c_STAGES      => c_STAGES,
+         N_CNTRS       => N_CNTRS,
+         CNTR_QUANT    => CNTR_QUANT,
+         CNTR_WIDTH    => CNTR_WIDTH
+   )
+   port map (
+      RST   => sl_RST,
+      CLK   => CLK,
+      --  Non Syncronized Parameters
+      rf_brightness     => rf_brightness,
+      -- Inputs 
+      ip_x => IN_PORT_0,
+      -- Iterators 
+      it_color => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
+      it_j => REG_CNTRS_RD(1*CNTR_QUANT+CNTR_WIDTH(1)-1 downto 1*CNTR_QUANT),
+      it_i => REG_CNTRS_RD(2*CNTR_QUANT+CNTR_WIDTH(2)-1 downto 2*CNTR_QUANT),
+      EXIST => EXIST,
+      READF => READ,
+      -- Outputs 
+      op_return_value => OUT_PORT_0,
+      FULL  => FULL,
+      WRITEF=> WRITE,
+      -- 
+      STOP_RD => STOP_RD,
+      STOP_WR => STOP_WR,
+      ERROR   => ERROR
+   );
+
+end Laura;
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/register_rf/hdllib.cfg b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/register_rf/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..472bb6698801fc6d80010fbf6ce22cbce9d99a39
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/register_rf/hdllib.cfg
@@ -0,0 +1,15 @@
+hdl_lib_name = compaandesign_com_bunny_static_split2rtl_register_rf_1
+hdl_library_clause_name = compaandesign_com_bunny_static_split2rtl_register_rf_1_lib
+hdl_lib_uses_synth = 
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files =
+	src/vhdl/register_rf.vhd
+
+test_bench_files =
+
+modelsim_copy_files =
diff --git a/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/register_rf/src/vhdl/register_rf.vhd b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/register_rf/src/vhdl/register_rf.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9fdb09a6ff0d5ee93d4ac06009847edafdd3c4ff
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/register_rf/src/vhdl/register_rf.vhd
@@ -0,0 +1,150 @@
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity register_rf is
+ generic (
+	C_commit_rf_address   : std_logic_vector(18 downto 0) := B"0000000000000000000"; -- 0
+	C_brightness_rf_address   : std_logic_vector(18 downto 0) := B"0000000000000000100"; -- 4
+	C_count_rf_address   : std_logic_vector(18 downto 0) := B"0000000000000001000" -- 8
+ );
+
+port (
+	rst  : in std_logic;
+	clk  : in std_logic;
+	pci_clk  : in std_logic;
+	--
+	
+	-- Interface to PCIe 
+	address         : in std_logic_vector(18 downto 0);
+	read_data       : out std_logic_vector(31 downto 0);
+	read_en         : in std_logic;
+	write_en        : in std_logic;
+	write_data      : in std_logic_vector(31 downto 0);
+	--
+	-- Interface to reg commit
+	commit_rf_read_data       : in std_logic_vector(32-1 downto 0);
+	commit_rf_read_en         : out std_logic;
+	commit_rf_write_en        : out std_logic;
+	commit_rf_write_data      : out std_logic_vector(32-1 downto 0);
+	--
+ 
+	-- Interface to reg brightness
+	brightness_rf_read_data       : in std_logic_vector(32-1 downto 0);
+	brightness_rf_read_en         : out std_logic;
+	brightness_rf_write_en        : out std_logic;
+	brightness_rf_write_data      : out std_logic_vector(32-1 downto 0);
+	--
+ 
+	-- Interface to reg count
+	count_rf_read_data       : in std_logic_vector(32-1 downto 0);
+	count_rf_read_en         : out std_logic;
+	count_rf_write_en        : out std_logic;
+	count_rf_write_data      : out std_logic_vector(32-1 downto 0)
+ 
+);
+end register_rf;
+
+architecture RTL of register_rf is
+ 
+	signal sl_read_data : std_logic_vector(32-1 downto 0)   := (others=>'0');
+ 
+begin
+process (pci_clk,rst)
+	begin
+		if (rising_edge(pci_clk)) then
+			if (rst = '1') then
+				commit_rf_write_en <= '0';
+				commit_rf_read_en  <= '0';
+				commit_rf_write_data  <= (others => '0');
+			else
+
+				if ( (address(18 downto 2) = C_commit_rf_address(18 downto 2)) and write_en = '1') then
+						commit_rf_write_data <= write_data(32-1 downto 0);
+						commit_rf_write_en <= '1';
+				else
+					commit_rf_write_en <= '0';
+				end if;
+
+				if( (address(18 downto 2) = C_commit_rf_address(18 downto 2)) and read_en= '1') then
+					commit_rf_read_en <= '1';
+				else
+					commit_rf_read_en <= '0';
+				end if;
+		end if;
+	end if;
+end process;
+
+process (pci_clk,rst)
+	begin
+		if (rising_edge(pci_clk)) then
+			if (rst = '1') then
+				brightness_rf_write_en <= '0';
+				brightness_rf_read_en  <= '0';
+				brightness_rf_write_data  <= (others => '0');
+			else
+
+				if ( (address(18 downto 2) = C_brightness_rf_address(18 downto 2)) and write_en = '1') then
+						brightness_rf_write_data <= write_data(32-1 downto 0);
+						brightness_rf_write_en <= '1';
+				else
+					brightness_rf_write_en <= '0';
+				end if;
+
+				if( (address(18 downto 2) = C_brightness_rf_address(18 downto 2)) and read_en= '1') then
+					brightness_rf_read_en <= '1';
+				else
+					brightness_rf_read_en <= '0';
+				end if;
+		end if;
+	end if;
+end process;
+
+process (pci_clk,rst)
+	begin
+		if (rising_edge(pci_clk)) then
+			if (rst = '1') then
+				count_rf_write_en <= '0';
+				count_rf_read_en  <= '0';
+				count_rf_write_data  <= (others => '0');
+			else
+
+				if ( (address(18 downto 2) = C_count_rf_address(18 downto 2)) and write_en = '1') then
+						count_rf_write_data <= write_data(32-1 downto 0);
+						count_rf_write_en <= '1';
+				else
+					count_rf_write_en <= '0';
+				end if;
+
+				if( (address(18 downto 2) = C_count_rf_address(18 downto 2)) and read_en= '1') then
+					count_rf_read_en <= '1';
+				else
+					count_rf_read_en <= '0';
+				end if;
+		end if;
+	end if;
+end process;
+
+process (pci_clk,rst)
+begin
+  if (rising_edge(pci_clk)) then
+     if (rst = '1') then
+	  else
+	    case  address(18 downto 2)  is
+			when (C_commit_rf_address(18 downto 2) ) =>
+			  sl_read_data(32-1 downto 0) <=   commit_rf_read_data;
+			when (C_brightness_rf_address(18 downto 2) ) =>
+			  sl_read_data(32-1 downto 0) <=   brightness_rf_read_data;
+			when (C_count_rf_address(18 downto 2) ) =>
+			  sl_read_data(32-1 downto 0) <=   count_rf_read_data;
+			when others => 
+				sl_read_data <=   (others => '0');
+		end case;
+	 end if;
+	end if;
+end process;
+
+read_data <=sl_read_data;
+
+end RTL;
diff --git a/applications/compaan/libraries/bunny_static_split/hdllib.cfg b/applications/compaan/libraries/bunny_static_split/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..11ef5ebe4cd18698a2b0e1658b7aa846e387ae8c
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/hdllib.cfg
@@ -0,0 +1,48 @@
+hdl_lib_name = bunny_static_split
+hdl_library_clause_name = bunny_static_split_lib
+
+hdl_lib_uses_synth = compaandesign_com_bunny_static_split2rtl_register_rf_1 compaandesign_com_bunny_static_split2rtl_hwn_nd_13_1 compaandesign_com_bunny_static_split2rtl_hwn_nd_10_1 compaandesign_com_bunny_static_split2rtl_hwn_nd_9_1 compaandesign_com_bunny_static_split2rtl_hwn_nd_6_1 compaandesign_com_common_wire_connector_1 compaandesign_com_bunny_static_split2rtl_hwn_nd_12_1 compaandesign_com_bunny_static_split2rtl_hwn_nd_4_1 compaandesign_com_altera_fifo_1 compaandesign_com_bunny_static_split2rtl_hwn_nd_14_1 compaandesign_com_common_const_connector_1 compaandesign_com_bunny_static_split2rtl_hwn_nd_5_1 compaandesign_com_bunny_static_split2rtl_hwn_nd_7_1 compaandesign_com_bunny_static_split2rtl_hwn_nd_8_1 compaandesign_com_bunny_static_split2rtl_hwn_nd_2_1 
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+# Specify here all the files you want to be included in the library.
+synth_files = 
+	src/vhdl/bunny_static_split.vhd
+	src/vhdl/bunny_static_split2rtl_ed_10_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_ed_11_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_ed_12_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_ed_13_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_ed_14_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_ed_15_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_ed_16_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_ed_17_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_ed_18_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_ed_19_20_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_ed_1_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_ed_21_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_ed_2_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_ed_3_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_ed_4_5_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_ed_6_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_ed_7_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_ed_8_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_ed_9_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_10_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_11_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_12_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_13_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_14_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_2_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_3_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_4_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_5_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_6_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_7_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_8_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_hwn_nd_9_ip_wrapper.vhd
+	src/vhdl/bunny_static_split2rtl_register_rf_ip_wrapper.vhd
+
+test_bench_files =
+	src/vhdl/system_ext_TB.vhd
diff --git a/applications/compaan/libraries/bunny_static_split/modelsim_hier_timeline.tcl b/applications/compaan/libraries/bunny_static_split/modelsim_hier_timeline.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..a19e3dcbdcb72107d61cef3cfabe442f9cc04729
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/modelsim_hier_timeline.tcl
@@ -0,0 +1,13 @@
+divider add TIMELINE -color darkgreen
+wave add SUT/bunny_static_split2rtl_hwn_nd_2_ip/bunny_static_split2rtl_hwn_nd_2_ip_wrapper_ip/EX/FUNC/CTRL/execute_pipe -name compaandesign.com:bunny_static_split2rtl:hwn_nd_2:1
+wave add SUT/bunny_static_split2rtl_hwn_nd_4_ip/bunny_static_split2rtl_hwn_nd_4_ip_wrapper_ip/EX/FUNC/CTRL/execute_pipe -name compaandesign.com:bunny_static_split2rtl:hwn_nd_4:1
+wave add SUT/bunny_static_split2rtl_hwn_nd_5_ip/bunny_static_split2rtl_hwn_nd_5_ip_wrapper_ip/EX/FUNC/CTRL/execute_pipe -name compaandesign.com:bunny_static_split2rtl:hwn_nd_5:1
+wave add SUT/bunny_static_split2rtl_hwn_nd_6_ip/bunny_static_split2rtl_hwn_nd_6_ip_wrapper_ip/EX/FUNC/CTRL/execute_pipe -name compaandesign.com:bunny_static_split2rtl:hwn_nd_6:1
+wave add SUT/bunny_static_split2rtl_hwn_nd_7_ip/bunny_static_split2rtl_hwn_nd_7_ip_wrapper_ip/EX/FUNC/CTRL/execute_pipe -name compaandesign.com:bunny_static_split2rtl:hwn_nd_7:1
+wave add SUT/bunny_static_split2rtl_hwn_nd_8_ip/bunny_static_split2rtl_hwn_nd_8_ip_wrapper_ip/EX/FUNC/CTRL/execute_pipe -name compaandesign.com:bunny_static_split2rtl:hwn_nd_8:1
+wave add SUT/bunny_static_split2rtl_hwn_nd_9_ip/bunny_static_split2rtl_hwn_nd_9_ip_wrapper_ip/EX/FUNC/CTRL/execute_pipe -name compaandesign.com:bunny_static_split2rtl:hwn_nd_9:1
+wave add SUT/bunny_static_split2rtl_hwn_nd_10_ip/bunny_static_split2rtl_hwn_nd_10_ip_wrapper_ip/EX/FUNC/CTRL/execute_pipe -name compaandesign.com:bunny_static_split2rtl:hwn_nd_10:1
+wave add SUT/bunny_static_split2rtl_hwn_nd_12_ip/bunny_static_split2rtl_hwn_nd_12_ip_wrapper_ip/EX/FUNC/CTRL/execute_pipe -name compaandesign.com:bunny_static_split2rtl:hwn_nd_12:1
+wave add SUT/bunny_static_split2rtl_hwn_nd_13_ip/bunny_static_split2rtl_hwn_nd_13_ip_wrapper_ip/EX/FUNC/CTRL/execute_pipe -name compaandesign.com:bunny_static_split2rtl:hwn_nd_13:1
+wave add SUT/bunny_static_split2rtl_hwn_nd_14_ip/bunny_static_split2rtl_hwn_nd_14_ip_wrapper_ip/EX/FUNC/CTRL/execute_pipe -name compaandesign.com:bunny_static_split2rtl:hwn_nd_14:1
+divider add TIMELINE -color darkgreen
diff --git a/applications/compaan/libraries/bunny_static_split/modelsim_system.do b/applications/compaan/libraries/bunny_static_split/modelsim_system.do
new file mode 100644
index 0000000000000000000000000000000000000000..85a51bddd22b4b88d27dec57a25fece3fa0b8e95
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/modelsim_system.do
@@ -0,0 +1,505 @@
+transcript on
+
+onerror {quit -f}
+onbreak {quit -f}
+config wave -signalnamewidth 1
+
+#source vhdl-library-setup.tcl
+
+set path_to_quartus /opt/Altera/15.0/quartus
+vlib lpm
+vmap lpm lpm
+vcom -work lpm -2002 -explicit $path_to_quartus/eda/sim_lib/220pack.vhd
+vcom -work lpm -2002 -explicit $path_to_quartus/eda/sim_lib/220model.vhd
+
+vlib sgate
+vmap sgate sgate
+vcom -work sgate -2002 -explicit $path_to_quartus/eda/sim_lib/sgate_pack.vhd
+vcom -work sgate -2002 -explicit $path_to_quartus/eda/sim_lib/sgate.vhd
+
+vlib altera_mf
+vmap altera_mf altera_mf
+vcom -work altera_mf -2002 -explicit $path_to_quartus/eda/sim_lib/altera_mf_components.vhd
+vcom -work altera_mf -2002 -explicit $path_to_quartus/eda/sim_lib/altera_mf.vhd
+
+vlib altera_lnsim
+vmap altera_lnsim altera_lnsim
+vcom -work altera_lnsim -2002 -explicit $path_to_quartus/eda/sim_lib/altera_lnsim_components.vhd
+vcom -work altera_mf -2002 -explicit $path_to_quartus/eda/sim_lib/altera_mf.vhd
+
+vlib altera
+vmap altera altera
+vcom -work altera -2002 -explicit $path_to_quartus/eda/sim_lib/altera_primitives_components.vhd
+vcom -work altera -2002 -explicit $path_to_quartus/eda/sim_lib/altera_primitives.vhd
+
+vlib stratixiv
+vmap stratixiv stratixiv
+vcom -work stratixiv -2002 -explicit $path_to_quartus/eda/sim_lib/stratixiv_atoms.vhd
+vcom -work stratixiv -2002 -explicit $path_to_quartus/eda/sim_lib/stratixiv_components.vhd
+
+vlib stratixiv_hssi
+vmap stratixiv_hssi stratixiv_hssi
+vcom -work stratixiv_hssi -2002 -explicit $path_to_quartus/eda/sim_lib/stratixiv_hssi_components.vhd
+vcom -work stratixiv_hssi -2002 -explicit $path_to_quartus/eda/sim_lib/stratixiv_hssi_atoms.vhd
+
+vlib stratixiv_pcie_hip
+vmap stratixiv_pcie_hip stratixiv_pcie_hip
+vcom -work stratixiv_pcie_hip -2002 -explicit $path_to_quartus/eda/sim_lib/stratixiv_pcie_hip_components.vhd
+vcom -work stratixiv_pcie_hip -2002 -explicit $path_to_quartus/eda/sim_lib/stratixiv_pcie_hip_atoms.vhd
+
+if {[file exists work]} {
+	vdel -lib work -all
+}
+vlib work
+vmap work work
+
+if {[file exists technology_lib]} {
+	vdel -lib technology_lib -all
+}
+vlib technology_lib
+vmap work technology_lib
+
+if {[file exists common_lib]} {
+	vdel -lib common_lib -all
+}
+vlib common_lib
+vmap work common_lib
+
+if {[file exists tech_memory_lib]} {
+	vdel -lib tech_memory_lib -all
+}
+vlib tech_memory_lib
+vmap work tech_memory_lib
+
+if {[file exists ip_stratixiv_fifo_lib]} {
+	vdel -lib ip_stratixiv_fifo_lib -all
+}
+vlib ip_stratixiv_fifo_lib
+vmap work ip_stratixiv_fifo_lib
+
+if {[file exists ip_stratixiv_ram_lib]} {
+	vdel -lib ip_stratixiv_ram_lib -all
+}
+vlib ip_stratixiv_ram_lib
+vmap work ip_stratixiv_ram_lib
+
+if {[file exists ip_arria10_ram_lib]} {
+	vdel -lib ip_arria10_ram_lib -all
+}
+vlib ip_arria10_ram_lib
+vmap work ip_arria10_ram_lib
+
+if {[file exists ip_arria10_fifo_lib]} {
+	vdel -lib ip_arria10_fifo_lib -all
+}
+vlib ip_arria10_fifo_lib
+vmap work ip_arria10_fifo_lib
+
+if {[file exists ip_arria10_e3sge3_fifo_lib]} {
+	vdel -lib ip_arria10_e3sge3_fifo_lib -all
+}
+vlib ip_arria10_e3sge3_fifo_lib
+vmap work ip_arria10_e3sge3_fifo_lib
+
+if {[file exists ip_arria10_e3sge3_ram_lib]} {
+	vdel -lib ip_arria10_e3sge3_ram_lib -all
+}
+vlib ip_arria10_e3sge3_ram_lib
+vmap work ip_arria10_e3sge3_ram_lib
+
+if {[file exists tech_fifo_lib]} {
+	vdel -lib tech_fifo_lib -all
+}
+vlib tech_fifo_lib
+vmap work tech_fifo_lib
+
+if {[file exists dp_lib]} {
+	vdel -lib dp_lib -all
+}
+vlib dp_lib
+vmap work dp_lib
+
+
+set SVNROOT /home/kienhuis/svnroot/UniBoard_FP7
+set RadioHDL ${SVNROOT}/RadioHDL/trunk
+set UniBoard ${SVNROOT}/UniBoard/trunk
+
+vcom -93 -work common_lib ${UniBoard}/Firmware/modules/common/src/vhdl/common_pkg.vhd
+vcom -93 -work work ${UniBoard}/Firmware/modules/common/src/vhdl/common_pkg.vhd
+vcom -93 -work work ${RadioHDL}/libraries/base/common/src/vhdl/common_mem_pkg.vhd
+vcom -93 -work common_lib ${RadioHDL}/libraries/base/common/src/vhdl/common_mem_pkg.vhd
+vcom -93 -work work ${RadioHDL}/libraries/technology/technology_pkg.vhd
+vcom -93 -work technology_lib ${RadioHDL}/libraries/technology/technology_pkg.vhd
+vcom -93 -work work ${RadioHDL}/libraries/technology/technology_select_pkg.vhd
+vcom -93 -work technology_lib ${RadioHDL}/libraries/technology/technology_select_pkg.vhd
+
+vcom -93 -work ip_arria10_fifo_lib ${RadioHDL}/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.vhd
+
+vcom -93 -work ip_stratixiv_fifo_lib ${RadioHDL}/libraries/technology/ip_stratixiv/fifo/ip_stratixiv_fifo_dc.vhd
+vcom -93 -work ip_stratixiv_fifo_lib ${RadioHDL}/libraries/technology/ip_stratixiv/fifo/ip_stratixiv_fifo_sc.vhd
+vcom -93 -work ip_stratixiv_fifo_lib ${RadioHDL}/libraries/technology/ip_stratixiv/fifo/ip_stratixiv_fifo_dc_mixed_widths.vhd
+
+vcom -93 -work ip_arria10_e3sge3_fifo_lib ${RadioHDL}/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_dc.vhd
+vcom -93 -work ip_arria10_e3sge3_fifo_lib ${RadioHDL}/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_sc.vhd
+vcom -93 -work ip_arria10_e3sge3_fifo_lib ${RadioHDL}/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_dc_mixed_widths.vhd
+
+vcom -93 -work tech_fifo_lib ${RadioHDL}/libraries/technology/fifo/tech_fifo_component_pkg.vhd
+vcom -93 -work tech_fifo_lib ${RadioHDL}/libraries/technology/fifo/tech_fifo_dc.vhd
+vcom -93 -work tech_fifo_lib ${RadioHDL}/libraries/technology/fifo/tech_fifo_sc.vhd
+vcom -93 -work tech_fifo_lib ${RadioHDL}/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
+vcom -93 -work common_lib ${UniBoard}/Firmware/modules/common/src/vhdl/common_async.vhd
+vcom -93 -work common_lib ${UniBoard}/Firmware/modules/common/src/vhdl/common_areset.vhd
+
+vcom -93 -work dp_lib ${RadioHDL}/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
+vcom -93 -work dp_lib ${UniBoard}/Firmware/modules/dp/src/vhdl/dp_latency_increase.vhd
+vcom -93 -work dp_lib ${UniBoard}/Firmware/modules/dp/src/vhdl/dp_latency_adapter.vhd
+
+vcom -93 -work common_lib ${RadioHDL}/libraries/base/common/src/vhdl/common_fifo_sc.vhd
+vcom -93 -work common_lib ${RadioHDL}/libraries/base/common/src/vhdl/common_fifo_dc.vhd
+vcom -93 -work dp_lib ${RadioHDL}/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
+vcom -93 -work dp_lib ${RadioHDL}/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
+
+vcom -93 -work common_lib ${UniBoard}/Firmware/modules/common/src/vhdl/common_async.vhd
+vcom -93 -work common_lib ${UniBoard}/Firmware/modules/common/src/vhdl/common_pipeline.vhd
+
+vcom -93 -work ip_stratixiv_ram_lib ${RadioHDL}/libraries/technology/ip_stratixiv/ram/ip_stratixiv_ram_crw_crw.vhd
+vcom -93 -work ip_stratixiv_ram_lib ${RadioHDL}/libraries/technology/ip_stratixiv/ram/ip_stratixiv_ram_cr_cw.vhd
+
+vcom -93 -work ip_arria10_ram_lib ${RadioHDL}/libraries/technology/ip_arria10/ram/ip_arria10_simple_dual_port_ram_dual_clock.vhd
+vcom -93 -work ip_arria10_ram_lib ${RadioHDL}/libraries/technology/ip_arria10/ram/ip_arria10_true_dual_port_ram_dual_clock.vhd
+vcom -93 -work ip_arria10_ram_lib ${RadioHDL}/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd
+vcom -93 -work ip_arria10_ram_lib ${RadioHDL}/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
+
+vcom -93 -work ip_arria10_e3sge3_ram_lib ${RadioHDL}/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_simple_dual_port_ram_dual_clock.vhd
+vcom -93 -work ip_arria10_e3sge3_ram_lib ${RadioHDL}/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_true_dual_port_ram_dual_clock.vhd
+vcom -93 -work ip_arria10_e3sge3_ram_lib ${RadioHDL}/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd
+vcom -93 -work ip_arria10_e3sge3_ram_lib ${RadioHDL}/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd
+
+vcom -93 -work tech_memory_lib ${RadioHDL}/libraries/technology/memory/tech_memory_component_pkg.vhd
+vcom -93 -work tech_memory_lib ${RadioHDL}/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
+vcom -93 -work tech_memory_lib ${RadioHDL}/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
+
+vcom -93 -work common_lib ${RadioHDL}/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
+vcom -93 -work common_lib ${RadioHDL}/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
+vcom -93 -work common_lib ${RadioHDL}/libraries/base/common/src/vhdl/common_ram_r_w.vhd
+
+# -- Compaan Specific 
+if {[file exists compaandesign_com_common_common_1_lib]} {
+	vdel -lib compaandesign_com_common_common_1_lib -all
+}
+vlib compaandesign_com_common_common_1_lib
+vmap work compaandesign_com_common_common_1_lib
+
+vcom -93 -work compaandesign_com_common_common_1_lib {compaandesign_com/common/common/src/vhdl/hw_node_pkg.vhd}
+
+if {[file exists compaandesign_com_common_const_connector_1_lib]} {
+	vdel -lib compaandesign_com_common_const_connector_1_lib -all
+}
+vlib compaandesign_com_common_const_connector_1_lib
+vmap work compaandesign_com_common_const_connector_1_lib
+
+vcom -93 -work compaandesign_com_common_const_connector_1_lib {compaandesign_com/common/const_connector/src/vhdl/const_connector.vhd}
+
+if {[file exists compaandesign_com_altera_fifo_1_lib]} {
+	vdel -lib compaandesign_com_altera_fifo_1_lib -all
+}
+vlib compaandesign_com_altera_fifo_1_lib
+vmap work compaandesign_com_altera_fifo_1_lib
+
+vcom -93 -work compaandesign_com_altera_fifo_1_lib {compaandesign_com/altera/fifo/src/vhdl/fsl_v20.vhd}
+
+if {[file exists compaandesign_com_altera_memory_1_lib]} {
+	vdel -lib compaandesign_com_altera_memory_1_lib -all
+}
+vlib compaandesign_com_altera_memory_1_lib
+vmap work compaandesign_com_altera_memory_1_lib
+
+vcom -93 -work compaandesign_com_altera_memory_1_lib {compaandesign_com/altera/memory/src/vhdl/sync_bram.vhd}
+
+if {[file exists compaandesign_com_common_extern_connector_1_lib]} {
+	vdel -lib compaandesign_com_common_extern_connector_1_lib -all
+}
+vlib compaandesign_com_common_extern_connector_1_lib
+vmap work compaandesign_com_common_extern_connector_1_lib
+
+vcom -93 -work compaandesign_com_common_extern_connector_1_lib {compaandesign_com/common/extern_connector/src/vhdl/extern_connector.vhd}
+
+if {[file exists compaandesign_com_common_hwnode_1_lib]} {
+	vdel -lib compaandesign_com_common_hwnode_1_lib -all
+}
+vlib compaandesign_com_common_hwnode_1_lib
+vmap work compaandesign_com_common_hwnode_1_lib
+
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/controller.vhd}
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/counter.vhd}
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/it_mod.vhd}
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/it_mul.vhd}
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/external_parameters.vhd}
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/internal_parameters.vhd}
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/read_mux.vhd}
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/read_mmux.vhd}
+vcom -93 -work compaandesign_com_common_hwnode_1_lib {compaandesign_com/common/hwnode/src/vhdl/write_demux.vhd}
+
+if {[file exists compaandesign_com_common_wire_connector_1_lib]} {
+	vdel -lib compaandesign_com_common_wire_connector_1_lib -all
+}
+vlib compaandesign_com_common_wire_connector_1_lib
+vmap work compaandesign_com_common_wire_connector_1_lib
+
+vcom -93 -work compaandesign_com_common_wire_connector_1_lib {compaandesign_com/common/wire_connector/src/vhdl/wire_connector.vhd}
+
+if {[file exists compaandesign_com_bunny_static_split2rtl_functions_1_lib]} {
+	vdel -lib compaandesign_com_bunny_static_split2rtl_functions_1_lib -all
+}
+vlib compaandesign_com_bunny_static_split2rtl_functions_1_lib
+vmap work compaandesign_com_bunny_static_split2rtl_functions_1_lib
+
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_functions_1_lib {compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc0.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_functions_1_lib {compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc0_pipeline.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_functions_1_lib {compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/increaseFrameCount.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_functions_1_lib {compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/increaseFrameCount_pipeline.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_functions_1_lib {compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/split64to2t32.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_functions_1_lib {compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/split64to2t32_pipeline.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_functions_1_lib {compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/deserialize32to4t8.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_functions_1_lib {compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/deserialize32to4t8_pipeline.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_functions_1_lib {compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc2.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_functions_1_lib {compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc2_pipeline.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_functions_1_lib {compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc3.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_functions_1_lib {compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc3_pipeline.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_functions_1_lib {compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/invert_image.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_functions_1_lib {compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/invert_image_pipeline.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_functions_1_lib {compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc4.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_functions_1_lib {compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc4_pipeline.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_functions_1_lib {compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/serialize4t8to32.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_functions_1_lib {compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/serialize4t8to32_pipeline.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_functions_1_lib {compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/merge2t32to64.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_functions_1_lib {compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/merge2t32to64_pipeline.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_functions_1_lib {compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc6.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_functions_1_lib {compaandesign_com/bunny_static_split2rtl/functions/src/vhdl/compaan_outlinedproc6_pipeline.vhd}
+
+if {[file exists compaandesign_com_bunny_static_split2rtl_hwn_nd_2_1_lib]} {
+	vdel -lib compaandesign_com_bunny_static_split2rtl_hwn_nd_2_1_lib -all
+}
+vlib compaandesign_com_bunny_static_split2rtl_hwn_nd_2_1_lib
+vmap work compaandesign_com_bunny_static_split2rtl_hwn_nd_2_1_lib
+
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_2_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_2/src/vhdl/bunny_static_split2rtl_hwn_nd_2_execution_unit.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_2_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_2/src/vhdl/bunny_static_split2rtl_hwn_nd_2_eval_logic_rd.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_2_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_2/src/vhdl/bunny_static_split2rtl_hwn_nd_2_eval_logic_wr.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_2_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_2/src/vhdl/bunny_static_split2rtl_hwn_nd_2.vhd}
+
+if {[file exists compaandesign_com_common_const_connector_1_lib]} {
+	vdel -lib compaandesign_com_common_const_connector_1_lib -all
+}
+vlib compaandesign_com_common_const_connector_1_lib
+vmap work compaandesign_com_common_const_connector_1_lib
+
+vcom -93 -work compaandesign_com_common_const_connector_1_lib {compaandesign_com/common/const_connector/src/vhdl/const_connector.vhd}
+
+if {[file exists compaandesign_com_bunny_static_split2rtl_hwn_nd_4_1_lib]} {
+	vdel -lib compaandesign_com_bunny_static_split2rtl_hwn_nd_4_1_lib -all
+}
+vlib compaandesign_com_bunny_static_split2rtl_hwn_nd_4_1_lib
+vmap work compaandesign_com_bunny_static_split2rtl_hwn_nd_4_1_lib
+
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_4_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_4/src/vhdl/bunny_static_split2rtl_hwn_nd_4_execution_unit.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_4_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_4/src/vhdl/bunny_static_split2rtl_hwn_nd_4_eval_logic_rd.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_4_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_4/src/vhdl/bunny_static_split2rtl_hwn_nd_4.vhd}
+
+if {[file exists compaandesign_com_bunny_static_split2rtl_hwn_nd_5_1_lib]} {
+	vdel -lib compaandesign_com_bunny_static_split2rtl_hwn_nd_5_1_lib -all
+}
+vlib compaandesign_com_bunny_static_split2rtl_hwn_nd_5_1_lib
+vmap work compaandesign_com_bunny_static_split2rtl_hwn_nd_5_1_lib
+
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_5_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_5/src/vhdl/bunny_static_split2rtl_hwn_nd_5_execution_unit.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_5_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_5/src/vhdl/bunny_static_split2rtl_hwn_nd_5_eval_logic_rd.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_5_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_5/src/vhdl/bunny_static_split2rtl_hwn_nd_5_eval_logic_wr.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_5_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_5/src/vhdl/bunny_static_split2rtl_hwn_nd_5.vhd}
+
+if {[file exists compaandesign_com_bunny_static_split2rtl_hwn_nd_6_1_lib]} {
+	vdel -lib compaandesign_com_bunny_static_split2rtl_hwn_nd_6_1_lib -all
+}
+vlib compaandesign_com_bunny_static_split2rtl_hwn_nd_6_1_lib
+vmap work compaandesign_com_bunny_static_split2rtl_hwn_nd_6_1_lib
+
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_6_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_6/src/vhdl/bunny_static_split2rtl_hwn_nd_6_execution_unit.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_6_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_6/src/vhdl/bunny_static_split2rtl_hwn_nd_6_eval_logic_rd.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_6_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_6/src/vhdl/bunny_static_split2rtl_hwn_nd_6_eval_logic_wr.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_6_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_6/src/vhdl/bunny_static_split2rtl_hwn_nd_6.vhd}
+
+if {[file exists compaandesign_com_bunny_static_split2rtl_hwn_nd_7_1_lib]} {
+	vdel -lib compaandesign_com_bunny_static_split2rtl_hwn_nd_7_1_lib -all
+}
+vlib compaandesign_com_bunny_static_split2rtl_hwn_nd_7_1_lib
+vmap work compaandesign_com_bunny_static_split2rtl_hwn_nd_7_1_lib
+
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_7_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_7/src/vhdl/bunny_static_split2rtl_hwn_nd_7_execution_unit.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_7_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_7/src/vhdl/bunny_static_split2rtl_hwn_nd_7_eval_logic_rd.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_7_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_7/src/vhdl/bunny_static_split2rtl_hwn_nd_7_eval_logic_wr.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_7_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_7/src/vhdl/bunny_static_split2rtl_hwn_nd_7.vhd}
+
+if {[file exists compaandesign_com_bunny_static_split2rtl_hwn_nd_8_1_lib]} {
+	vdel -lib compaandesign_com_bunny_static_split2rtl_hwn_nd_8_1_lib -all
+}
+vlib compaandesign_com_bunny_static_split2rtl_hwn_nd_8_1_lib
+vmap work compaandesign_com_bunny_static_split2rtl_hwn_nd_8_1_lib
+
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_8_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_8/src/vhdl/bunny_static_split2rtl_hwn_nd_8_execution_unit.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_8_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_8/src/vhdl/bunny_static_split2rtl_hwn_nd_8_eval_logic_rd.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_8_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_8/src/vhdl/bunny_static_split2rtl_hwn_nd_8_eval_logic_wr.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_8_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_8/src/vhdl/bunny_static_split2rtl_hwn_nd_8.vhd}
+
+if {[file exists compaandesign_com_bunny_static_split2rtl_hwn_nd_9_1_lib]} {
+	vdel -lib compaandesign_com_bunny_static_split2rtl_hwn_nd_9_1_lib -all
+}
+vlib compaandesign_com_bunny_static_split2rtl_hwn_nd_9_1_lib
+vmap work compaandesign_com_bunny_static_split2rtl_hwn_nd_9_1_lib
+
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_9_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_9/src/vhdl/bunny_static_split2rtl_hwn_nd_9_execution_unit.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_9_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_9/src/vhdl/bunny_static_split2rtl_hwn_nd_9_eval_logic_rd.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_9_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_9/src/vhdl/bunny_static_split2rtl_hwn_nd_9_eval_logic_wr.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_9_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_9/src/vhdl/bunny_static_split2rtl_hwn_nd_9.vhd}
+
+if {[file exists compaandesign_com_bunny_static_split2rtl_hwn_nd_10_1_lib]} {
+	vdel -lib compaandesign_com_bunny_static_split2rtl_hwn_nd_10_1_lib -all
+}
+vlib compaandesign_com_bunny_static_split2rtl_hwn_nd_10_1_lib
+vmap work compaandesign_com_bunny_static_split2rtl_hwn_nd_10_1_lib
+
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_10_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_10/src/vhdl/bunny_static_split2rtl_hwn_nd_10_execution_unit.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_10_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_10/src/vhdl/bunny_static_split2rtl_hwn_nd_10_eval_logic_rd.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_10_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_10/src/vhdl/bunny_static_split2rtl_hwn_nd_10_eval_logic_wr.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_10_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_10/src/vhdl/bunny_static_split2rtl_hwn_nd_10.vhd}
+
+if {[file exists compaandesign_com_common_const_connector_1_lib]} {
+	vdel -lib compaandesign_com_common_const_connector_1_lib -all
+}
+vlib compaandesign_com_common_const_connector_1_lib
+vmap work compaandesign_com_common_const_connector_1_lib
+
+vcom -93 -work compaandesign_com_common_const_connector_1_lib {compaandesign_com/common/const_connector/src/vhdl/const_connector.vhd}
+
+if {[file exists compaandesign_com_bunny_static_split2rtl_hwn_nd_12_1_lib]} {
+	vdel -lib compaandesign_com_bunny_static_split2rtl_hwn_nd_12_1_lib -all
+}
+vlib compaandesign_com_bunny_static_split2rtl_hwn_nd_12_1_lib
+vmap work compaandesign_com_bunny_static_split2rtl_hwn_nd_12_1_lib
+
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_12_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_12/src/vhdl/bunny_static_split2rtl_hwn_nd_12_execution_unit.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_12_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_12/src/vhdl/bunny_static_split2rtl_hwn_nd_12_eval_logic_rd.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_12_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_12/src/vhdl/bunny_static_split2rtl_hwn_nd_12_eval_logic_wr.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_12_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_12/src/vhdl/bunny_static_split2rtl_hwn_nd_12.vhd}
+
+if {[file exists compaandesign_com_bunny_static_split2rtl_hwn_nd_13_1_lib]} {
+	vdel -lib compaandesign_com_bunny_static_split2rtl_hwn_nd_13_1_lib -all
+}
+vlib compaandesign_com_bunny_static_split2rtl_hwn_nd_13_1_lib
+vmap work compaandesign_com_bunny_static_split2rtl_hwn_nd_13_1_lib
+
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_13_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_13/src/vhdl/bunny_static_split2rtl_hwn_nd_13_execution_unit.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_13_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_13/src/vhdl/bunny_static_split2rtl_hwn_nd_13_eval_logic_rd.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_13_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_13/src/vhdl/bunny_static_split2rtl_hwn_nd_13_eval_logic_wr.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_13_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_13/src/vhdl/bunny_static_split2rtl_hwn_nd_13.vhd}
+
+if {[file exists compaandesign_com_bunny_static_split2rtl_hwn_nd_14_1_lib]} {
+	vdel -lib compaandesign_com_bunny_static_split2rtl_hwn_nd_14_1_lib -all
+}
+vlib compaandesign_com_bunny_static_split2rtl_hwn_nd_14_1_lib
+vmap work compaandesign_com_bunny_static_split2rtl_hwn_nd_14_1_lib
+
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_14_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_14/src/vhdl/bunny_static_split2rtl_hwn_nd_14_execution_unit.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_14_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_14/src/vhdl/bunny_static_split2rtl_hwn_nd_14_eval_logic_rd.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_14_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_14/src/vhdl/bunny_static_split2rtl_hwn_nd_14_eval_logic_wr.vhd}
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_hwn_nd_14_1_lib {compaandesign_com/bunny_static_split2rtl/hwn_nd_14/src/vhdl/bunny_static_split2rtl_hwn_nd_14.vhd}
+
+if {[file exists compaandesign_com_bunny_static_split2rtl_register_rf_1_lib]} {
+	vdel -lib compaandesign_com_bunny_static_split2rtl_register_rf_1_lib -all
+}
+vlib compaandesign_com_bunny_static_split2rtl_register_rf_1_lib
+vmap work compaandesign_com_bunny_static_split2rtl_register_rf_1_lib
+
+vcom -93 -work compaandesign_com_bunny_static_split2rtl_register_rf_1_lib {compaandesign_com/bunny_static_split2rtl/register_rf/src/vhdl/register_rf.vhd}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+if {[file exists compaandesign_com_common_wire_connector_1_lib]} {
+	vdel -lib compaandesign_com_common_wire_connector_1_lib -all
+}
+vlib compaandesign_com_common_wire_connector_1_lib
+vmap work compaandesign_com_common_wire_connector_1_lib
+
+vcom -93 -work compaandesign_com_common_wire_connector_1_lib {compaandesign_com/common/wire_connector/src/vhdl/wire_connector.vhd}
+
+if {[file exists compaandesign_com_common_wire_connector_1_lib]} {
+	vdel -lib compaandesign_com_common_wire_connector_1_lib -all
+}
+vlib compaandesign_com_common_wire_connector_1_lib
+vmap work compaandesign_com_common_wire_connector_1_lib
+
+vcom -93 -work compaandesign_com_common_wire_connector_1_lib {compaandesign_com/common/wire_connector/src/vhdl/wire_connector.vhd}
+
+
+vcom -93 -work work src/vhdl/bunny_static_split.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_ed_10_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_ed_11_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_ed_12_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_ed_13_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_ed_14_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_ed_15_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_ed_16_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_ed_17_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_ed_18_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_ed_19_20_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_ed_1_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_ed_21_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_ed_2_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_ed_3_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_ed_4_5_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_ed_6_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_ed_7_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_ed_8_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_ed_9_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_hwn_nd_10_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_hwn_nd_11_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_hwn_nd_12_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_hwn_nd_13_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_hwn_nd_14_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_hwn_nd_2_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_hwn_nd_3_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_hwn_nd_4_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_hwn_nd_5_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_hwn_nd_6_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_hwn_nd_7_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_hwn_nd_8_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_hwn_nd_9_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/bunny_static_split2rtl_register_rf_ip_wrapper.vhd
+vcom -93 -work work src/vhdl/system_ext_TB.vhd
+
+vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L stratixiv_hssi -L ip_stratixiv_ram_lib -L stratixiv_pcie_hip -L stratixiv -L common_lib -L tech_memory_lib  -L ip_stratixiv_fifo_lib -L tech_fifo_lib -L dp_lib -L technology_lib -L work   -L compaandesign_com_bunny_static_split2rtl_register_rf_1_lib -L compaandesign_com_bunny_static_split2rtl_hwn_nd_13_1_lib -L compaandesign_com_common_hwnode_1_lib -L compaandesign_com_bunny_static_split2rtl_hwn_nd_10_1_lib -L compaandesign_com_bunny_static_split2rtl_hwn_nd_9_1_lib -L compaandesign_com_bunny_static_split2rtl_hwn_nd_6_1_lib -L compaandesign_com_common_wire_connector_1_lib -L compaandesign_com_bunny_static_split2rtl_hwn_nd_12_1_lib -L compaandesign_com_bunny_static_split2rtl_hwn_nd_4_1_lib -L compaandesign_com_bunny_static_split2rtl_functions_1_lib -L compaandesign_com_bunny_static_split2rtl_hwn_nd_14_1_lib -L compaandesign_com_altera_fifo_1_lib -L compaandesign_com_common_const_connector_1_lib -L compaandesign_com_bunny_static_split2rtl_hwn_nd_5_1_lib -L compaandesign_com_bunny_static_split2rtl_hwn_nd_7_1_lib -L compaandesign_com_bunny_static_split2rtl_hwn_nd_8_1_lib -L compaandesign_com_altera_memory_1_lib -L compaandesign_com_bunny_static_split2rtl_hwn_nd_2_1_lib -L compaandesign_com_common_common_1_lib -L compaandesign_com_common_extern_connector_1_lib -voptargs="+acc" system_ext_TB
+#add wave *
+#view structure
+#view signals
+#source isim_wave.tcl
+
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+run -all
+
+quit -f
+
diff --git a/applications/compaan/libraries/bunny_static_split/run_quartus.tcl b/applications/compaan/libraries/bunny_static_split/run_quartus.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..cc65b9fef7075b7d338fe722bb4cd3851c39ba70
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/run_quartus.tcl
@@ -0,0 +1,127 @@
+# Load Quartus II Tcl Project package
+package require ::quartus::project
+
+set need_to_close_project 0
+set make_assignments 1
+
+# Check that the right project is open
+if {[is_project_open]} {
+	if {[string compare $quartus(project) "bunny_static_split"]} {
+	puts "Project bunny_static_split is not open"
+	set make_assignments 0
+}
+} else {
+	# Only open if not already open
+	if {[project_exists bunny_static_split]} {
+		project_open -revision bunny_static_split bunny_static_split
+	} else {
+		project_new -revision bunny_static_split bunny_static_split
+	}
+}
+set need_to_close_project 1
+
+# Make assignments
+if {$make_assignments} {
+	set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.0
+	set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:41:26  JANUARY 22, 2015"
+	set_global_assignment -name LAST_QUARTUS_VERSION 12.0
+	set_global_assignment -name FAMILY "Stratix V"
+	set_global_assignment -name TOP_LEVEL_ENTITY bunny_static_split
+	set_global_assignment -name DEVICE auto
+	set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+	set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/write_demux.vhd -library compaandesign_com_common_hwnode_1
+	set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/read_mux.vhd -library compaandesign_com_common_hwnode_1
+	set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/read_mmux.vhd -library compaandesign_com_common_hwnode_1
+	set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/parameters.vhd -library compaandesign_com_common_hwnode_1
+	set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/it_mul.vhd -library compaandesign_com_common_hwnode_1
+	set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/it_mod.vhd -library compaandesign_com_common_hwnode_1
+	set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/counter.vhd -library compaandesign_com_common_hwnode_1
+	set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/controller.vhd -library compaandesign_com_common_hwnode_1
+	set_global_assignment -name VHDL_FILE compaandesign_com/common/altera/1/fsl_v20.vhd -library compaandesign_com_common_fifo_1
+	set_global_assignment -name VHDL_FILE compaandesign_com/common/common/1/hw_node_pkg.vhd -library compaandesign_com_common_common_1
+
+
+	set_global_assignment -name VHDL_FILE compaandesign_com/bunny_static_split2rtl/hwn_nd_2/1/sourceCode -library compaandesign_com_bunny_static_split2rtl_hwn_nd_2_1
+
+	set_global_assignment -name VHDL_FILE compaandesign_com/common/const_connector/1/sourceCode -library compaandesign_com_common_const_connector_1
+
+	set_global_assignment -name VHDL_FILE compaandesign_com/bunny_static_split2rtl/hwn_nd_4/1/sourceCode -library compaandesign_com_bunny_static_split2rtl_hwn_nd_4_1
+
+	set_global_assignment -name VHDL_FILE compaandesign_com/bunny_static_split2rtl/hwn_nd_5/1/sourceCode -library compaandesign_com_bunny_static_split2rtl_hwn_nd_5_1
+
+	set_global_assignment -name VHDL_FILE compaandesign_com/bunny_static_split2rtl/hwn_nd_6/1/sourceCode -library compaandesign_com_bunny_static_split2rtl_hwn_nd_6_1
+
+	set_global_assignment -name VHDL_FILE compaandesign_com/bunny_static_split2rtl/hwn_nd_7/1/sourceCode -library compaandesign_com_bunny_static_split2rtl_hwn_nd_7_1
+
+	set_global_assignment -name VHDL_FILE compaandesign_com/bunny_static_split2rtl/hwn_nd_8/1/sourceCode -library compaandesign_com_bunny_static_split2rtl_hwn_nd_8_1
+
+	set_global_assignment -name VHDL_FILE compaandesign_com/bunny_static_split2rtl/hwn_nd_9/1/sourceCode -library compaandesign_com_bunny_static_split2rtl_hwn_nd_9_1
+
+	set_global_assignment -name VHDL_FILE compaandesign_com/bunny_static_split2rtl/hwn_nd_10/1/sourceCode -library compaandesign_com_bunny_static_split2rtl_hwn_nd_10_1
+
+	set_global_assignment -name VHDL_FILE compaandesign_com/common/const_connector/1/sourceCode -library compaandesign_com_common_const_connector_1
+
+	set_global_assignment -name VHDL_FILE compaandesign_com/bunny_static_split2rtl/hwn_nd_12/1/sourceCode -library compaandesign_com_bunny_static_split2rtl_hwn_nd_12_1
+
+	set_global_assignment -name VHDL_FILE compaandesign_com/bunny_static_split2rtl/hwn_nd_13/1/sourceCode -library compaandesign_com_bunny_static_split2rtl_hwn_nd_13_1
+
+	set_global_assignment -name VHDL_FILE compaandesign_com/bunny_static_split2rtl/hwn_nd_14/1/sourceCode -library compaandesign_com_bunny_static_split2rtl_hwn_nd_14_1
+
+	set_global_assignment -name VHDL_FILE compaandesign_com/bunny_static_split2rtl/register_rf/1/sourceCode -library compaandesign_com_bunny_static_split2rtl_register_rf_1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+	set_global_assignment -name VHDL_FILE compaandesign_com/common/wire_connector/1/sourceCode -library compaandesign_com_common_wire_connector_1
+
+	set_global_assignment -name VHDL_FILE compaandesign_com/common/wire_connector/1/sourceCode -library compaandesign_com_common_wire_connector_1
+# add functions of Laura node into a library
+
+	set strlist [glob compaandesign_com/bunny_static_split2rtl/functions/1/*.vhd]
+	foreach strfile $strlist {
+		set file_name $strfile
+		set_global_assignment -name VHDL_FILE $file_name -library compaandesign_com_bunny_static_split2rtl_functions_1
+	}
+
+
+# add wrapper to library work
+	set strlist [glob *.vhd]
+	foreach strfile $strlist {
+		set file_name $strfile
+		set_global_assignment -name VHDL_FILE $file_name -library work
+	}
+
+# testbench information
+set_global_assignment -name VHDL_FILE system_ext_TB.vhd -library work
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH bunny_static_split -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_NAME bunny_static_split -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME bunny_static_split -section_id bunny_static_split
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME bunny_static_split -section_id bunny_static_split
+set_global_assignment -name EDA_TEST_BENCH_FILE system_ext_TB.vhd -section_id bunny_static_split -library work
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+# Commit assignments
+export_assignments
+
+# Close project
+if {$need_to_close_project} {
+	project_close
+}
+}
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e1d0dcd37cdaf2de12a52807fd8da3446e012939
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split.vhd
@@ -0,0 +1,1962 @@
+-------------------------------------------------------------------------------
+-- TOP LEVEL 
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+entity bunny_static_split is
+  port (
+
+    data_in_Data : in std_logic_vector(63 downto 0 );
+    data_in_Control : in std_logic;
+    data_in_Read : out std_logic;
+    data_in_Exists : in std_logic;
+
+    data_out_Data : out std_logic_vector(63 downto 0 );
+    data_out_Control : out std_logic;
+    data_out_Write : out std_logic;
+    data_out_Full : in std_logic;
+
+    TEST_STOP : out std_logic_vector(13 downto 0 );
+    TEST_ERROR : out std_logic_vector(13 downto 0 );
+    TEST_FIFO_FULL : out std_logic_vector(18 downto 0 );
+    TEST_BLOCK_RD : out std_logic_vector(13 downto 0 );
+    address : in std_logic_vector(18 downto 0 );
+    read_data : out std_logic_vector(31 downto 0 );
+    read_en : in std_logic;
+    write_en : in std_logic;
+    write_data : in std_logic_vector(31 downto 0 );
+    pci_clk : in std_logic;
+
+    KPN_CLK : in std_logic;
+    KPN_RST : in std_logic
+  );
+end bunny_static_split;
+
+architecture STRUCTURE of bunny_static_split is
+
+  component bunny_static_split2rtl_hwn_nd_2_ip_wrapper is
+    port (
+		data_in_Rd : out std_logic;
+		data_in_Din : in std_logic_vector(63 downto 0);
+		data_in_Exist : in std_logic;
+		data_in_CLK : out std_logic;
+		data_in_CTRL : in std_logic;
+
+		ND_2OP_1_Wr : out std_logic;
+		ND_2OP_1_Dout : out std_logic_vector(63 downto 0);
+		ND_2OP_1_Full : in std_logic;
+		ND_2OP_1_CLK : out std_logic;
+		ND_2OP_1_CTRL : out std_logic;
+
+		ND_2OP_1_d1_Wr : out std_logic;
+		ND_2OP_1_d1_Dout : out std_logic_vector(63 downto 0);
+		ND_2OP_1_d1_Full : in std_logic;
+		ND_2OP_1_d1_CLK : out std_logic;
+		ND_2OP_1_d1_CTRL : out std_logic;
+
+		PARAM_DT : in std_logic_vector(10 downto 0);
+		PARAM_LD : in std_logic;
+		STOP : out std_logic;
+		ERROR : out std_logic;
+		BLOCK_RD : out std_logic;
+
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+	end component;
+
+  component bunny_static_split2rtl_hwn_nd_3_ip_wrapper is
+    port (
+		FSL_M_Wr : out std_logic;
+		FSL_M_Dout : out std_logic_vector(63 downto 0);
+		FSL_M_Full : in std_logic;
+		FSL_M_CLK : out std_logic;
+		FSL_M_CTRL : out std_logic;
+
+
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+	end component;
+
+  component bunny_static_split2rtl_hwn_nd_4_ip_wrapper is
+    port (
+		rf_count : out std_logic_vector(31 downto 0);
+		ND_4IP_1_Rd : out std_logic;
+		ND_4IP_1_Din : in std_logic_vector(63 downto 0);
+		ND_4IP_1_Exist : in std_logic;
+		ND_4IP_1_CLK : out std_logic;
+		ND_4IP_1_CTRL : in std_logic;
+
+		PARAM_DT : in std_logic_vector(10 downto 0);
+		PARAM_LD : in std_logic;
+		STOP : out std_logic;
+		ERROR : out std_logic;
+		BLOCK_RD : out std_logic;
+
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+	end component;
+
+  component bunny_static_split2rtl_hwn_nd_5_ip_wrapper is
+    port (
+		ND_5IP_2_Rd : out std_logic;
+		ND_5IP_2_Din : in std_logic_vector(63 downto 0);
+		ND_5IP_2_Exist : in std_logic;
+		ND_5IP_2_CLK : out std_logic;
+		ND_5IP_2_CTRL : in std_logic;
+
+		ND_5OP_1_Wr : out std_logic;
+		ND_5OP_1_Dout : out std_logic_vector(31 downto 0);
+		ND_5OP_1_Full : in std_logic;
+		ND_5OP_1_CLK : out std_logic;
+		ND_5OP_1_CTRL : out std_logic;
+
+		ND_5OP_2_d1_ND_5OP_2_Wr : out std_logic;
+		ND_5OP_2_d1_ND_5OP_2_Dout : out std_logic_vector(31 downto 0);
+		ND_5OP_2_d1_ND_5OP_2_Full : in std_logic;
+		ND_5OP_2_d1_ND_5OP_2_CLK : out std_logic;
+		ND_5OP_2_d1_ND_5OP_2_CTRL : out std_logic;
+
+		PARAM_DT : in std_logic_vector(10 downto 0);
+		PARAM_LD : in std_logic;
+		STOP : out std_logic;
+		ERROR : out std_logic;
+		BLOCK_RD : out std_logic;
+
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+	end component;
+
+  component bunny_static_split2rtl_hwn_nd_6_ip_wrapper is
+    port (
+		ND_6IP_3_Rd : out std_logic;
+		ND_6IP_3_Din : in std_logic_vector(31 downto 0);
+		ND_6IP_3_Exist : in std_logic;
+		ND_6IP_3_CLK : out std_logic;
+		ND_6IP_3_CTRL : in std_logic;
+
+		ND_6IP_5_ND_6IP_4_Rd : out std_logic;
+		ND_6IP_5_ND_6IP_4_Din : in std_logic_vector(31 downto 0);
+		ND_6IP_5_ND_6IP_4_Exist : in std_logic;
+		ND_6IP_5_ND_6IP_4_CLK : out std_logic;
+		ND_6IP_5_ND_6IP_4_CTRL : in std_logic;
+
+		ND_6OP_1_Wr : out std_logic;
+		ND_6OP_1_Dout : out std_logic_vector(7 downto 0);
+		ND_6OP_1_Full : in std_logic;
+		ND_6OP_1_CLK : out std_logic;
+		ND_6OP_1_CTRL : out std_logic;
+
+		ND_6OP_2_Wr : out std_logic;
+		ND_6OP_2_Dout : out std_logic_vector(7 downto 0);
+		ND_6OP_2_Full : in std_logic;
+		ND_6OP_2_CLK : out std_logic;
+		ND_6OP_2_CTRL : out std_logic;
+
+		ND_6OP_3_Wr : out std_logic;
+		ND_6OP_3_Dout : out std_logic_vector(7 downto 0);
+		ND_6OP_3_Full : in std_logic;
+		ND_6OP_3_CLK : out std_logic;
+		ND_6OP_3_CTRL : out std_logic;
+
+		PARAM_DT : in std_logic_vector(10 downto 0);
+		PARAM_LD : in std_logic;
+		STOP : out std_logic;
+		ERROR : out std_logic;
+		BLOCK_RD : out std_logic;
+
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+	end component;
+
+  component bunny_static_split2rtl_hwn_nd_7_ip_wrapper is
+    port (
+		ND_7IP_6_Rd : out std_logic;
+		ND_7IP_6_Din : in std_logic_vector(7 downto 0);
+		ND_7IP_6_Exist : in std_logic;
+		ND_7IP_6_CLK : out std_logic;
+		ND_7IP_6_CTRL : in std_logic;
+
+		ND_7IP_7_Rd : out std_logic;
+		ND_7IP_7_Din : in std_logic_vector(7 downto 0);
+		ND_7IP_7_Exist : in std_logic;
+		ND_7IP_7_CLK : out std_logic;
+		ND_7IP_7_CTRL : in std_logic;
+
+		ND_7IP_8_Rd : out std_logic;
+		ND_7IP_8_Din : in std_logic_vector(7 downto 0);
+		ND_7IP_8_Exist : in std_logic;
+		ND_7IP_8_CLK : out std_logic;
+		ND_7IP_8_CTRL : in std_logic;
+
+		ND_7OP_1_Wr : out std_logic;
+		ND_7OP_1_Dout : out std_logic_vector(7 downto 0);
+		ND_7OP_1_Full : in std_logic;
+		ND_7OP_1_CLK : out std_logic;
+		ND_7OP_1_CTRL : out std_logic;
+
+		ND_7OP_1_d1_Wr : out std_logic;
+		ND_7OP_1_d1_Dout : out std_logic_vector(7 downto 0);
+		ND_7OP_1_d1_Full : in std_logic;
+		ND_7OP_1_d1_CLK : out std_logic;
+		ND_7OP_1_d1_CTRL : out std_logic;
+
+		PARAM_DT : in std_logic_vector(10 downto 0);
+		PARAM_LD : in std_logic;
+		STOP : out std_logic;
+		ERROR : out std_logic;
+		BLOCK_RD : out std_logic;
+
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+	end component;
+
+  component bunny_static_split2rtl_hwn_nd_8_ip_wrapper is
+    port (
+		ND_8IP_9_Rd : out std_logic;
+		ND_8IP_9_Din : in std_logic_vector(7 downto 0);
+		ND_8IP_9_Exist : in std_logic;
+		ND_8IP_9_CLK : out std_logic;
+		ND_8IP_9_CTRL : in std_logic;
+
+		ND_8OP_1_Wr : out std_logic;
+		ND_8OP_1_Dout : out std_logic_vector(7 downto 0);
+		ND_8OP_1_Full : in std_logic;
+		ND_8OP_1_CLK : out std_logic;
+		ND_8OP_1_CTRL : out std_logic;
+
+		PARAM_DT : in std_logic_vector(10 downto 0);
+		PARAM_LD : in std_logic;
+		STOP : out std_logic;
+		ERROR : out std_logic;
+		BLOCK_RD : out std_logic;
+
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+	end component;
+
+  component bunny_static_split2rtl_hwn_nd_9_ip_wrapper is
+    port (
+		rf_brightness : in std_logic_vector(31 downto 0);
+		ND_9IP_10_Rd : out std_logic;
+		ND_9IP_10_Din : in std_logic_vector(7 downto 0);
+		ND_9IP_10_Exist : in std_logic;
+		ND_9IP_10_CLK : out std_logic;
+		ND_9IP_10_CTRL : in std_logic;
+
+		ND_9OP_1_Wr : out std_logic;
+		ND_9OP_1_Dout : out std_logic_vector(7 downto 0);
+		ND_9OP_1_Full : in std_logic;
+		ND_9OP_1_CLK : out std_logic;
+		ND_9OP_1_CTRL : out std_logic;
+
+		PARAM_DT : in std_logic_vector(10 downto 0);
+		PARAM_LD : in std_logic;
+		STOP : out std_logic;
+		ERROR : out std_logic;
+		BLOCK_RD : out std_logic;
+
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+	end component;
+
+  component bunny_static_split2rtl_hwn_nd_10_ip_wrapper is
+    port (
+		ND_10IP_11_Rd : out std_logic;
+		ND_10IP_11_Din : in std_logic_vector(7 downto 0);
+		ND_10IP_11_Exist : in std_logic;
+		ND_10IP_11_CLK : out std_logic;
+		ND_10IP_11_CTRL : in std_logic;
+
+		ND_10IP_12_Rd : out std_logic;
+		ND_10IP_12_Din : in std_logic_vector(7 downto 0);
+		ND_10IP_12_Exist : in std_logic;
+		ND_10IP_12_CLK : out std_logic;
+		ND_10IP_12_CTRL : in std_logic;
+
+		ND_10OP_1_Wr : out std_logic;
+		ND_10OP_1_Dout : out std_logic_vector(7 downto 0);
+		ND_10OP_1_Full : in std_logic;
+		ND_10OP_1_CLK : out std_logic;
+		ND_10OP_1_CTRL : out std_logic;
+
+		ND_10OP_1_d1_Wr : out std_logic;
+		ND_10OP_1_d1_Dout : out std_logic_vector(7 downto 0);
+		ND_10OP_1_d1_Full : in std_logic;
+		ND_10OP_1_d1_CLK : out std_logic;
+		ND_10OP_1_d1_CTRL : out std_logic;
+
+		ND_10OP_1_d2_Wr : out std_logic;
+		ND_10OP_1_d2_Dout : out std_logic_vector(7 downto 0);
+		ND_10OP_1_d2_Full : in std_logic;
+		ND_10OP_1_d2_CLK : out std_logic;
+		ND_10OP_1_d2_CTRL : out std_logic;
+
+		PARAM_DT : in std_logic_vector(10 downto 0);
+		PARAM_LD : in std_logic;
+		STOP : out std_logic;
+		ERROR : out std_logic;
+		BLOCK_RD : out std_logic;
+
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+	end component;
+
+  component bunny_static_split2rtl_hwn_nd_11_ip_wrapper is
+    port (
+		FSL_M_Wr : out std_logic;
+		FSL_M_Dout : out std_logic_vector(7 downto 0);
+		FSL_M_Full : in std_logic;
+		FSL_M_CLK : out std_logic;
+		FSL_M_CTRL : out std_logic;
+
+
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+	end component;
+
+  component bunny_static_split2rtl_hwn_nd_12_ip_wrapper is
+    port (
+		ND_12IP_13_Rd : out std_logic;
+		ND_12IP_13_Din : in std_logic_vector(7 downto 0);
+		ND_12IP_13_Exist : in std_logic;
+		ND_12IP_13_CLK : out std_logic;
+		ND_12IP_13_CTRL : in std_logic;
+
+		ND_12IP_14_Rd : out std_logic;
+		ND_12IP_14_Din : in std_logic_vector(7 downto 0);
+		ND_12IP_14_Exist : in std_logic;
+		ND_12IP_14_CLK : out std_logic;
+		ND_12IP_14_CTRL : in std_logic;
+
+		ND_12IP_15_Rd : out std_logic;
+		ND_12IP_15_Din : in std_logic_vector(7 downto 0);
+		ND_12IP_15_Exist : in std_logic;
+		ND_12IP_15_CLK : out std_logic;
+		ND_12IP_15_CTRL : in std_logic;
+
+		ND_12IP_16_Rd : out std_logic;
+		ND_12IP_16_Din : in std_logic_vector(7 downto 0);
+		ND_12IP_16_Exist : in std_logic;
+		ND_12IP_16_CLK : out std_logic;
+		ND_12IP_16_CTRL : in std_logic;
+
+		ND_12OP_1_Wr : out std_logic;
+		ND_12OP_1_Dout : out std_logic_vector(31 downto 0);
+		ND_12OP_1_Full : in std_logic;
+		ND_12OP_1_CLK : out std_logic;
+		ND_12OP_1_CTRL : out std_logic;
+
+		ND_12OP_1_d1_Wr : out std_logic;
+		ND_12OP_1_d1_Dout : out std_logic_vector(31 downto 0);
+		ND_12OP_1_d1_Full : in std_logic;
+		ND_12OP_1_d1_CLK : out std_logic;
+		ND_12OP_1_d1_CTRL : out std_logic;
+
+		PARAM_DT : in std_logic_vector(10 downto 0);
+		PARAM_LD : in std_logic;
+		STOP : out std_logic;
+		ERROR : out std_logic;
+		BLOCK_RD : out std_logic;
+
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+	end component;
+
+  component bunny_static_split2rtl_hwn_nd_13_ip_wrapper is
+    port (
+		ND_13IP_17_Rd : out std_logic;
+		ND_13IP_17_Din : in std_logic_vector(31 downto 0);
+		ND_13IP_17_Exist : in std_logic;
+		ND_13IP_17_CLK : out std_logic;
+		ND_13IP_17_CTRL : in std_logic;
+
+		ND_13IP_18_Rd : out std_logic;
+		ND_13IP_18_Din : in std_logic_vector(31 downto 0);
+		ND_13IP_18_Exist : in std_logic;
+		ND_13IP_18_CLK : out std_logic;
+		ND_13IP_18_CTRL : in std_logic;
+
+		ND_13OP_1_d1_ND_13OP_1_Wr : out std_logic;
+		ND_13OP_1_d1_ND_13OP_1_Dout : out std_logic_vector(63 downto 0);
+		ND_13OP_1_d1_ND_13OP_1_Full : in std_logic;
+		ND_13OP_1_d1_ND_13OP_1_CLK : out std_logic;
+		ND_13OP_1_d1_ND_13OP_1_CTRL : out std_logic;
+
+		PARAM_DT : in std_logic_vector(10 downto 0);
+		PARAM_LD : in std_logic;
+		STOP : out std_logic;
+		ERROR : out std_logic;
+		BLOCK_RD : out std_logic;
+
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+	end component;
+
+  component bunny_static_split2rtl_hwn_nd_14_ip_wrapper is
+    port (
+		ND_14IP_20_ND_14IP_19_Rd : out std_logic;
+		ND_14IP_20_ND_14IP_19_Din : in std_logic_vector(63 downto 0);
+		ND_14IP_20_ND_14IP_19_Exist : in std_logic;
+		ND_14IP_20_ND_14IP_19_CLK : out std_logic;
+		ND_14IP_20_ND_14IP_19_CTRL : in std_logic;
+
+		ND_14IP_21_Rd : out std_logic;
+		ND_14IP_21_Din : in std_logic_vector(63 downto 0);
+		ND_14IP_21_Exist : in std_logic;
+		ND_14IP_21_CLK : out std_logic;
+		ND_14IP_21_CTRL : in std_logic;
+
+		data_out_Wr : out std_logic;
+		data_out_Dout : out std_logic_vector(63 downto 0);
+		data_out_Full : in std_logic;
+		data_out_CLK : out std_logic;
+		data_out_CTRL : out std_logic;
+
+		PARAM_DT : in std_logic_vector(10 downto 0);
+		PARAM_LD : in std_logic;
+		STOP : out std_logic;
+		ERROR : out std_logic;
+		BLOCK_RD : out std_logic;
+
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+	end component;
+
+component bunny_static_split2rtl_register_rf_ip_wrapper is
+	port (
+		address : in std_logic_vector(18 downto 0);
+		read_data : out std_logic_vector(31 downto 0);
+		read_en : in std_logic;
+		write_en : in std_logic;
+		write_data : in std_logic_vector(31 downto 0);
+		pci_clk : in std_logic;
+		commit_rf_read_data : in std_logic_vector(31 downto 0);
+		commit_rf_read_en : out std_logic;
+		commit_rf_write_en : out std_logic;
+		commit_rf_write_data : out std_logic_vector(31 downto 0);
+		brightness_rf_read_data : in std_logic_vector(31 downto 0);
+		brightness_rf_read_en : out std_logic;
+		brightness_rf_write_en : out std_logic;
+		brightness_rf_write_data : out std_logic_vector(31 downto 0);
+		count_rf_read_data : in std_logic_vector(31 downto 0);
+		count_rf_read_en : out std_logic;
+		count_rf_write_en : out std_logic;
+		count_rf_write_data : out std_logic_vector(31 downto 0);
+		RST : in std_logic;
+		CLK : in std_logic
+
+	);
+end component;
+
+  component bunny_static_split2rtl_ed_1_ip_wrapper is
+    port (
+      FSL_Clk : in std_logic;
+      SYS_Rst : in std_logic;
+      FSL_Rst : out std_logic;
+      FSL_M_Clk : in std_logic;
+      FSL_M_Data : in std_logic_vector(0 to 63);
+      FSL_M_Control : in std_logic;
+      FSL_M_Write : in std_logic;
+      FSL_M_Full : out std_logic;
+      FSL_S_Clk : in std_logic;
+      FSL_S_Data : out std_logic_vector(0 to 63);
+      FSL_S_Control : out std_logic;
+      FSL_S_Read : in std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full : out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+  component bunny_static_split2rtl_ed_2_ip_wrapper is
+    port (
+      FSL_Clk : in std_logic;
+      SYS_Rst : in std_logic;
+      FSL_Rst : out std_logic;
+      FSL_M_Clk : in std_logic;
+      FSL_M_Data : in std_logic_vector(0 to 63);
+      FSL_M_Control : in std_logic;
+      FSL_M_Write : in std_logic;
+      FSL_M_Full : out std_logic;
+      FSL_S_Clk : in std_logic;
+      FSL_S_Data : out std_logic_vector(0 to 63);
+      FSL_S_Control : out std_logic;
+      FSL_S_Read : in std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full : out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+  component bunny_static_split2rtl_ed_3_ip_wrapper is
+    port (
+      FSL_Clk : in std_logic;
+      SYS_Rst : in std_logic;
+      FSL_Rst : out std_logic;
+      FSL_M_Clk : in std_logic;
+      FSL_M_Data : in std_logic_vector(0 to 31);
+      FSL_M_Control : in std_logic;
+      FSL_M_Write : in std_logic;
+      FSL_M_Full : out std_logic;
+      FSL_S_Clk : in std_logic;
+      FSL_S_Data : out std_logic_vector(0 to 31);
+      FSL_S_Control : out std_logic;
+      FSL_S_Read : in std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full : out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+  component bunny_static_split2rtl_ed_4_5_ip_wrapper is
+    port (
+      FSL_Clk : in std_logic;
+      SYS_Rst : in std_logic;
+      FSL_Rst : out std_logic;
+      FSL_M_Clk : in std_logic;
+      FSL_M_Data : in std_logic_vector(0 to 31);
+      FSL_M_Control : in std_logic;
+      FSL_M_Write : in std_logic;
+      FSL_M_Full : out std_logic;
+      FSL_S_Clk : in std_logic;
+      FSL_S_Data : out std_logic_vector(0 to 31);
+      FSL_S_Control : out std_logic;
+      FSL_S_Read : in std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full : out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+  component bunny_static_split2rtl_ed_6_ip_wrapper is
+    port (
+      FSL_Clk : in std_logic;
+      SYS_Rst : in std_logic;
+      FSL_Rst : out std_logic;
+      FSL_M_Clk : in std_logic;
+      FSL_M_Data : in std_logic_vector(0 to 7);
+      FSL_M_Control : in std_logic;
+      FSL_M_Write : in std_logic;
+      FSL_M_Full : out std_logic;
+      FSL_S_Clk : in std_logic;
+      FSL_S_Data : out std_logic_vector(0 to 7);
+      FSL_S_Control : out std_logic;
+      FSL_S_Read : in std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full : out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+  component bunny_static_split2rtl_ed_7_ip_wrapper is
+    port (
+      FSL_Clk : in std_logic;
+      SYS_Rst : in std_logic;
+      FSL_Rst : out std_logic;
+      FSL_M_Clk : in std_logic;
+      FSL_M_Data : in std_logic_vector(0 to 7);
+      FSL_M_Control : in std_logic;
+      FSL_M_Write : in std_logic;
+      FSL_M_Full : out std_logic;
+      FSL_S_Clk : in std_logic;
+      FSL_S_Data : out std_logic_vector(0 to 7);
+      FSL_S_Control : out std_logic;
+      FSL_S_Read : in std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full : out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+  component bunny_static_split2rtl_ed_8_ip_wrapper is
+    port (
+      FSL_Clk : in std_logic;
+      SYS_Rst : in std_logic;
+      FSL_Rst : out std_logic;
+      FSL_M_Clk : in std_logic;
+      FSL_M_Data : in std_logic_vector(0 to 7);
+      FSL_M_Control : in std_logic;
+      FSL_M_Write : in std_logic;
+      FSL_M_Full : out std_logic;
+      FSL_S_Clk : in std_logic;
+      FSL_S_Data : out std_logic_vector(0 to 7);
+      FSL_S_Control : out std_logic;
+      FSL_S_Read : in std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full : out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+  component bunny_static_split2rtl_ed_9_ip_wrapper is
+    port (
+      FSL_Clk : in std_logic;
+      SYS_Rst : in std_logic;
+      FSL_Rst : out std_logic;
+      FSL_M_Clk : in std_logic;
+      FSL_M_Data : in std_logic_vector(0 to 7);
+      FSL_M_Control : in std_logic;
+      FSL_M_Write : in std_logic;
+      FSL_M_Full : out std_logic;
+      FSL_S_Clk : in std_logic;
+      FSL_S_Data : out std_logic_vector(0 to 7);
+      FSL_S_Control : out std_logic;
+      FSL_S_Read : in std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full : out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+  component bunny_static_split2rtl_ed_10_ip_wrapper is
+    port (
+      FSL_Clk : in std_logic;
+      SYS_Rst : in std_logic;
+      FSL_Rst : out std_logic;
+      FSL_M_Clk : in std_logic;
+      FSL_M_Data : in std_logic_vector(0 to 7);
+      FSL_M_Control : in std_logic;
+      FSL_M_Write : in std_logic;
+      FSL_M_Full : out std_logic;
+      FSL_S_Clk : in std_logic;
+      FSL_S_Data : out std_logic_vector(0 to 7);
+      FSL_S_Control : out std_logic;
+      FSL_S_Read : in std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full : out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+  component bunny_static_split2rtl_ed_11_ip_wrapper is
+    port (
+      FSL_Clk : in std_logic;
+      SYS_Rst : in std_logic;
+      FSL_Rst : out std_logic;
+      FSL_M_Clk : in std_logic;
+      FSL_M_Data : in std_logic_vector(0 to 7);
+      FSL_M_Control : in std_logic;
+      FSL_M_Write : in std_logic;
+      FSL_M_Full : out std_logic;
+      FSL_S_Clk : in std_logic;
+      FSL_S_Data : out std_logic_vector(0 to 7);
+      FSL_S_Control : out std_logic;
+      FSL_S_Read : in std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full : out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+  component bunny_static_split2rtl_ed_12_ip_wrapper is
+    port (
+      FSL_Clk : in std_logic;
+      SYS_Rst : in std_logic;
+      FSL_Rst : out std_logic;
+      FSL_M_Clk : in std_logic;
+      FSL_M_Data : in std_logic_vector(0 to 7);
+      FSL_M_Control : in std_logic;
+      FSL_M_Write : in std_logic;
+      FSL_M_Full : out std_logic;
+      FSL_S_Clk : in std_logic;
+      FSL_S_Data : out std_logic_vector(0 to 7);
+      FSL_S_Control : out std_logic;
+      FSL_S_Read : in std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full : out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+  component bunny_static_split2rtl_ed_13_ip_wrapper is
+    port (
+      FSL_Clk : in std_logic;
+      SYS_Rst : in std_logic;
+      FSL_Rst : out std_logic;
+      FSL_M_Clk : in std_logic;
+      FSL_M_Data : in std_logic_vector(0 to 7);
+      FSL_M_Control : in std_logic;
+      FSL_M_Write : in std_logic;
+      FSL_M_Full : out std_logic;
+      FSL_S_Clk : in std_logic;
+      FSL_S_Data : out std_logic_vector(0 to 7);
+      FSL_S_Control : out std_logic;
+      FSL_S_Read : in std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full : out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+  component bunny_static_split2rtl_ed_14_ip_wrapper is
+    port (
+      FSL_Clk : in std_logic;
+      SYS_Rst : in std_logic;
+      FSL_Rst : out std_logic;
+      FSL_M_Clk : in std_logic;
+      FSL_M_Data : in std_logic_vector(0 to 7);
+      FSL_M_Control : in std_logic;
+      FSL_M_Write : in std_logic;
+      FSL_M_Full : out std_logic;
+      FSL_S_Clk : in std_logic;
+      FSL_S_Data : out std_logic_vector(0 to 7);
+      FSL_S_Control : out std_logic;
+      FSL_S_Read : in std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full : out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+  component bunny_static_split2rtl_ed_15_ip_wrapper is
+    port (
+      FSL_Clk : in std_logic;
+      SYS_Rst : in std_logic;
+      FSL_Rst : out std_logic;
+      FSL_M_Clk : in std_logic;
+      FSL_M_Data : in std_logic_vector(0 to 7);
+      FSL_M_Control : in std_logic;
+      FSL_M_Write : in std_logic;
+      FSL_M_Full : out std_logic;
+      FSL_S_Clk : in std_logic;
+      FSL_S_Data : out std_logic_vector(0 to 7);
+      FSL_S_Control : out std_logic;
+      FSL_S_Read : in std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full : out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+  component bunny_static_split2rtl_ed_17_ip_wrapper is
+    port (
+      FSL_Clk : in std_logic;
+      SYS_Rst : in std_logic;
+      FSL_Rst : out std_logic;
+      FSL_M_Clk : in std_logic;
+      FSL_M_Data : in std_logic_vector(0 to 31);
+      FSL_M_Control : in std_logic;
+      FSL_M_Write : in std_logic;
+      FSL_M_Full : out std_logic;
+      FSL_S_Clk : in std_logic;
+      FSL_S_Data : out std_logic_vector(0 to 31);
+      FSL_S_Control : out std_logic;
+      FSL_S_Read : in std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full : out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+  component bunny_static_split2rtl_ed_18_ip_wrapper is
+    port (
+      FSL_Clk : in std_logic;
+      SYS_Rst : in std_logic;
+      FSL_Rst : out std_logic;
+      FSL_M_Clk : in std_logic;
+      FSL_M_Data : in std_logic_vector(0 to 31);
+      FSL_M_Control : in std_logic;
+      FSL_M_Write : in std_logic;
+      FSL_M_Full : out std_logic;
+      FSL_S_Clk : in std_logic;
+      FSL_S_Data : out std_logic_vector(0 to 31);
+      FSL_S_Control : out std_logic;
+      FSL_S_Read : in std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full : out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+  component bunny_static_split2rtl_ed_19_20_ip_wrapper is
+    port (
+      FSL_Clk : in std_logic;
+      SYS_Rst : in std_logic;
+      FSL_Rst : out std_logic;
+      FSL_M_Clk : in std_logic;
+      FSL_M_Data : in std_logic_vector(0 to 63);
+      FSL_M_Control : in std_logic;
+      FSL_M_Write : in std_logic;
+      FSL_M_Full : out std_logic;
+      FSL_S_Clk : in std_logic;
+      FSL_S_Data : out std_logic_vector(0 to 63);
+      FSL_S_Control : out std_logic;
+      FSL_S_Read : in std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full : out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+  component bunny_static_split2rtl_ed_16_ip_wrapper is
+    port (
+      FSL_Clk : in std_logic;
+      SYS_Rst : in std_logic;
+      FSL_Rst : out std_logic;
+      FSL_M_Clk : in std_logic;
+      FSL_M_Data : in std_logic_vector(0 to 7);
+      FSL_M_Control : in std_logic;
+      FSL_M_Write : in std_logic;
+      FSL_M_Full : out std_logic;
+      FSL_S_Clk : in std_logic;
+      FSL_S_Data : out std_logic_vector(0 to 7);
+      FSL_S_Control : out std_logic;
+      FSL_S_Read : in std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full : out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+  component bunny_static_split2rtl_ed_21_ip_wrapper is
+    port (
+      FSL_Clk : in std_logic;
+      SYS_Rst : in std_logic;
+      FSL_Rst : out std_logic;
+      FSL_M_Clk : in std_logic;
+      FSL_M_Data : in std_logic_vector(0 to 63);
+      FSL_M_Control : in std_logic;
+      FSL_M_Write : in std_logic;
+      FSL_M_Full : out std_logic;
+      FSL_S_Clk : in std_logic;
+      FSL_S_Data : out std_logic_vector(0 to 63);
+      FSL_S_Control : out std_logic;
+      FSL_S_Read : in std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full : out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+  -- Internal signals
+
+	signal signal_ed_1_out_FSL_M_Control : std_logic;
+	signal signal_ed_1_out_FSL_M_Data : std_logic_vector(0 to 63);
+	signal signal_ed_1_out_FSL_M_Full : std_logic;
+	signal signal_ed_1_out_FSL_M_Write : std_logic;
+	signal signal_ed_2_out_FSL_M_Control : std_logic;
+	signal signal_ed_2_out_FSL_M_Data : std_logic_vector(0 to 63);
+	signal signal_ed_2_out_FSL_M_Full : std_logic;
+	signal signal_ed_2_out_FSL_M_Write : std_logic;
+	signal signal_ed_21_out_FSL_M_Control : std_logic;
+	signal signal_ed_21_out_FSL_M_Data : std_logic_vector(0 to 63);
+	signal signal_ed_21_out_FSL_M_Full : std_logic;
+	signal signal_ed_21_out_FSL_M_Write : std_logic;
+	signal signal_ed_1_in_FSL_S_Control : std_logic;
+	signal signal_ed_1_in_FSL_S_Data : std_logic_vector(0 to 63);
+	signal signal_ed_1_in_FSL_S_Exists : std_logic;
+	signal signal_ed_1_in_FSL_S_Read : std_logic;
+	signal signal_ed_2_in_FSL_S_Control : std_logic;
+	signal signal_ed_2_in_FSL_S_Data : std_logic_vector(0 to 63);
+	signal signal_ed_2_in_FSL_S_Exists : std_logic;
+	signal signal_ed_2_in_FSL_S_Read : std_logic;
+	signal signal_ed_3_out_FSL_M_Control : std_logic;
+	signal signal_ed_3_out_FSL_M_Data : std_logic_vector(0 to 31);
+	signal signal_ed_3_out_FSL_M_Full : std_logic;
+	signal signal_ed_3_out_FSL_M_Write : std_logic;
+	signal signal_ed_4_5_out_FSL_M_Control : std_logic;
+	signal signal_ed_4_5_out_FSL_M_Data : std_logic_vector(0 to 31);
+	signal signal_ed_4_5_out_FSL_M_Full : std_logic;
+	signal signal_ed_4_5_out_FSL_M_Write : std_logic;
+	signal signal_ed_3_in_FSL_S_Control : std_logic;
+	signal signal_ed_3_in_FSL_S_Data : std_logic_vector(0 to 31);
+	signal signal_ed_3_in_FSL_S_Exists : std_logic;
+	signal signal_ed_3_in_FSL_S_Read : std_logic;
+	signal signal_ed_4_5_in_FSL_S_Control : std_logic;
+	signal signal_ed_4_5_in_FSL_S_Data : std_logic_vector(0 to 31);
+	signal signal_ed_4_5_in_FSL_S_Exists : std_logic;
+	signal signal_ed_4_5_in_FSL_S_Read : std_logic;
+	signal signal_ed_6_out_FSL_M_Control : std_logic;
+	signal signal_ed_6_out_FSL_M_Data : std_logic_vector(0 to 7);
+	signal signal_ed_6_out_FSL_M_Full : std_logic;
+	signal signal_ed_6_out_FSL_M_Write : std_logic;
+	signal signal_ed_7_out_FSL_M_Control : std_logic;
+	signal signal_ed_7_out_FSL_M_Data : std_logic_vector(0 to 7);
+	signal signal_ed_7_out_FSL_M_Full : std_logic;
+	signal signal_ed_7_out_FSL_M_Write : std_logic;
+	signal signal_ed_8_out_FSL_M_Control : std_logic;
+	signal signal_ed_8_out_FSL_M_Data : std_logic_vector(0 to 7);
+	signal signal_ed_8_out_FSL_M_Full : std_logic;
+	signal signal_ed_8_out_FSL_M_Write : std_logic;
+	signal signal_ed_6_in_FSL_S_Control : std_logic;
+	signal signal_ed_6_in_FSL_S_Data : std_logic_vector(0 to 7);
+	signal signal_ed_6_in_FSL_S_Exists : std_logic;
+	signal signal_ed_6_in_FSL_S_Read : std_logic;
+	signal signal_ed_7_in_FSL_S_Control : std_logic;
+	signal signal_ed_7_in_FSL_S_Data : std_logic_vector(0 to 7);
+	signal signal_ed_7_in_FSL_S_Exists : std_logic;
+	signal signal_ed_7_in_FSL_S_Read : std_logic;
+	signal signal_ed_8_in_FSL_S_Control : std_logic;
+	signal signal_ed_8_in_FSL_S_Data : std_logic_vector(0 to 7);
+	signal signal_ed_8_in_FSL_S_Exists : std_logic;
+	signal signal_ed_8_in_FSL_S_Read : std_logic;
+	signal signal_ed_9_out_FSL_M_Control : std_logic;
+	signal signal_ed_9_out_FSL_M_Data : std_logic_vector(0 to 7);
+	signal signal_ed_9_out_FSL_M_Full : std_logic;
+	signal signal_ed_9_out_FSL_M_Write : std_logic;
+	signal signal_ed_10_out_FSL_M_Control : std_logic;
+	signal signal_ed_10_out_FSL_M_Data : std_logic_vector(0 to 7);
+	signal signal_ed_10_out_FSL_M_Full : std_logic;
+	signal signal_ed_10_out_FSL_M_Write : std_logic;
+	signal signal_ed_9_in_FSL_S_Control : std_logic;
+	signal signal_ed_9_in_FSL_S_Data : std_logic_vector(0 to 7);
+	signal signal_ed_9_in_FSL_S_Exists : std_logic;
+	signal signal_ed_9_in_FSL_S_Read : std_logic;
+	signal signal_ed_11_out_FSL_M_Control : std_logic;
+	signal signal_ed_11_out_FSL_M_Data : std_logic_vector(0 to 7);
+	signal signal_ed_11_out_FSL_M_Full : std_logic;
+	signal signal_ed_11_out_FSL_M_Write : std_logic;
+	signal signal_ed_10_in_FSL_S_Control : std_logic;
+	signal signal_ed_10_in_FSL_S_Data : std_logic_vector(0 to 7);
+	signal signal_ed_10_in_FSL_S_Exists : std_logic;
+	signal signal_ed_10_in_FSL_S_Read : std_logic;
+	signal signal_ed_12_out_FSL_M_Control : std_logic;
+	signal signal_ed_12_out_FSL_M_Data : std_logic_vector(0 to 7);
+	signal signal_ed_12_out_FSL_M_Full : std_logic;
+	signal signal_ed_12_out_FSL_M_Write : std_logic;
+	signal signal_ed_11_in_FSL_S_Control : std_logic;
+	signal signal_ed_11_in_FSL_S_Data : std_logic_vector(0 to 7);
+	signal signal_ed_11_in_FSL_S_Exists : std_logic;
+	signal signal_ed_11_in_FSL_S_Read : std_logic;
+	signal signal_ed_12_in_FSL_S_Control : std_logic;
+	signal signal_ed_12_in_FSL_S_Data : std_logic_vector(0 to 7);
+	signal signal_ed_12_in_FSL_S_Exists : std_logic;
+	signal signal_ed_12_in_FSL_S_Read : std_logic;
+	signal signal_ed_13_out_FSL_M_Control : std_logic;
+	signal signal_ed_13_out_FSL_M_Data : std_logic_vector(0 to 7);
+	signal signal_ed_13_out_FSL_M_Full : std_logic;
+	signal signal_ed_13_out_FSL_M_Write : std_logic;
+	signal signal_ed_14_out_FSL_M_Control : std_logic;
+	signal signal_ed_14_out_FSL_M_Data : std_logic_vector(0 to 7);
+	signal signal_ed_14_out_FSL_M_Full : std_logic;
+	signal signal_ed_14_out_FSL_M_Write : std_logic;
+	signal signal_ed_15_out_FSL_M_Control : std_logic;
+	signal signal_ed_15_out_FSL_M_Data : std_logic_vector(0 to 7);
+	signal signal_ed_15_out_FSL_M_Full : std_logic;
+	signal signal_ed_15_out_FSL_M_Write : std_logic;
+	signal signal_ed_16_out_FSL_M_Control : std_logic;
+	signal signal_ed_16_out_FSL_M_Data : std_logic_vector(0 to 7);
+	signal signal_ed_16_out_FSL_M_Full : std_logic;
+	signal signal_ed_16_out_FSL_M_Write : std_logic;
+	signal signal_ed_13_in_FSL_S_Control : std_logic;
+	signal signal_ed_13_in_FSL_S_Data : std_logic_vector(0 to 7);
+	signal signal_ed_13_in_FSL_S_Exists : std_logic;
+	signal signal_ed_13_in_FSL_S_Read : std_logic;
+	signal signal_ed_14_in_FSL_S_Control : std_logic;
+	signal signal_ed_14_in_FSL_S_Data : std_logic_vector(0 to 7);
+	signal signal_ed_14_in_FSL_S_Exists : std_logic;
+	signal signal_ed_14_in_FSL_S_Read : std_logic;
+	signal signal_ed_15_in_FSL_S_Control : std_logic;
+	signal signal_ed_15_in_FSL_S_Data : std_logic_vector(0 to 7);
+	signal signal_ed_15_in_FSL_S_Exists : std_logic;
+	signal signal_ed_15_in_FSL_S_Read : std_logic;
+	signal signal_ed_16_in_FSL_S_Control : std_logic;
+	signal signal_ed_16_in_FSL_S_Data : std_logic_vector(0 to 7);
+	signal signal_ed_16_in_FSL_S_Exists : std_logic;
+	signal signal_ed_16_in_FSL_S_Read : std_logic;
+	signal signal_ed_17_out_FSL_M_Control : std_logic;
+	signal signal_ed_17_out_FSL_M_Data : std_logic_vector(0 to 31);
+	signal signal_ed_17_out_FSL_M_Full : std_logic;
+	signal signal_ed_17_out_FSL_M_Write : std_logic;
+	signal signal_ed_18_out_FSL_M_Control : std_logic;
+	signal signal_ed_18_out_FSL_M_Data : std_logic_vector(0 to 31);
+	signal signal_ed_18_out_FSL_M_Full : std_logic;
+	signal signal_ed_18_out_FSL_M_Write : std_logic;
+	signal signal_ed_17_in_FSL_S_Control : std_logic;
+	signal signal_ed_17_in_FSL_S_Data : std_logic_vector(0 to 31);
+	signal signal_ed_17_in_FSL_S_Exists : std_logic;
+	signal signal_ed_17_in_FSL_S_Read : std_logic;
+	signal signal_ed_18_in_FSL_S_Control : std_logic;
+	signal signal_ed_18_in_FSL_S_Data : std_logic_vector(0 to 31);
+	signal signal_ed_18_in_FSL_S_Exists : std_logic;
+	signal signal_ed_18_in_FSL_S_Read : std_logic;
+	signal signal_ed_19_20_out_FSL_M_Control : std_logic;
+	signal signal_ed_19_20_out_FSL_M_Data : std_logic_vector(0 to 63);
+	signal signal_ed_19_20_out_FSL_M_Full : std_logic;
+	signal signal_ed_19_20_out_FSL_M_Write : std_logic;
+	signal signal_ed_19_20_in_FSL_S_Control : std_logic;
+	signal signal_ed_19_20_in_FSL_S_Data : std_logic_vector(0 to 63);
+	signal signal_ed_19_20_in_FSL_S_Exists : std_logic;
+	signal signal_ed_19_20_in_FSL_S_Read : std_logic;
+	signal signal_ed_21_in_FSL_S_Control : std_logic;
+	signal signal_ed_21_in_FSL_S_Data : std_logic_vector(0 to 63);
+	signal signal_ed_21_in_FSL_S_Exists : std_logic;
+	signal signal_ed_21_in_FSL_S_Read : std_logic;
+  -- Internal signals END 
+  -- Internal signals getDesignAdHocConnectionIDs 
+
+  -- AD HOC Internal signals
+
+	signal signal_hwn_nd_1_STOP : std_logic;
+	signal signal_hwn_nd_1_ERROR : std_logic;
+	signal signal_hwn_nd_1_BLOCK_RD : std_logic;
+	signal signal_hwn_nd_2_STOP : std_logic;
+	signal signal_hwn_nd_2_ERROR : std_logic;
+	signal signal_hwn_nd_2_BLOCK_RD : std_logic;
+	signal signal_hwn_nd_3_STOP : std_logic;
+	signal signal_hwn_nd_3_ERROR : std_logic;
+	signal signal_hwn_nd_3_BLOCK_RD : std_logic;
+	signal signal_hwn_nd_4_STOP : std_logic;
+	signal signal_hwn_nd_4_ERROR : std_logic;
+	signal signal_hwn_nd_4_BLOCK_RD : std_logic;
+	signal signal_hwn_nd_5_STOP : std_logic;
+	signal signal_hwn_nd_5_ERROR : std_logic;
+	signal signal_hwn_nd_5_BLOCK_RD : std_logic;
+	signal signal_hwn_nd_6_STOP : std_logic;
+	signal signal_hwn_nd_6_ERROR : std_logic;
+	signal signal_hwn_nd_6_BLOCK_RD : std_logic;
+	signal signal_hwn_nd_7_STOP : std_logic;
+	signal signal_hwn_nd_7_ERROR : std_logic;
+	signal signal_hwn_nd_7_BLOCK_RD : std_logic;
+	signal signal_hwn_nd_8_STOP : std_logic;
+	signal signal_hwn_nd_8_ERROR : std_logic;
+	signal signal_hwn_nd_8_BLOCK_RD : std_logic;
+	signal signal_hwn_nd_9_STOP : std_logic;
+	signal signal_hwn_nd_9_ERROR : std_logic;
+	signal signal_hwn_nd_9_BLOCK_RD : std_logic;
+	signal signal_hwn_nd_10_STOP : std_logic;
+	signal signal_hwn_nd_10_ERROR : std_logic;
+	signal signal_hwn_nd_10_BLOCK_RD : std_logic;
+	signal signal_hwn_nd_11_STOP : std_logic;
+	signal signal_hwn_nd_11_ERROR : std_logic;
+	signal signal_hwn_nd_11_BLOCK_RD : std_logic;
+	signal signal_hwn_nd_12_STOP : std_logic;
+	signal signal_hwn_nd_12_ERROR : std_logic;
+	signal signal_hwn_nd_12_BLOCK_RD : std_logic;
+	signal signal_hwn_nd_13_STOP : std_logic;
+	signal signal_hwn_nd_13_ERROR : std_logic;
+	signal signal_hwn_nd_13_BLOCK_RD : std_logic;
+	signal signal_hwn_nd_14_STOP : std_logic;
+	signal signal_hwn_nd_14_ERROR : std_logic;
+	signal signal_hwn_nd_14_BLOCK_RD : std_logic;
+	signal signal_ed_1_FIFO_FULL : std_logic;
+	signal signal_ed_2_FIFO_FULL : std_logic;
+	signal signal_ed_3_FIFO_FULL : std_logic;
+	signal signal_ed_4_5_FIFO_FULL : std_logic;
+	signal signal_ed_6_FIFO_FULL : std_logic;
+	signal signal_ed_7_FIFO_FULL : std_logic;
+	signal signal_ed_8_FIFO_FULL : std_logic;
+	signal signal_ed_9_FIFO_FULL : std_logic;
+	signal signal_ed_10_FIFO_FULL : std_logic;
+	signal signal_ed_11_FIFO_FULL : std_logic;
+	signal signal_ed_12_FIFO_FULL : std_logic;
+	signal signal_ed_13_FIFO_FULL : std_logic;
+	signal signal_ed_14_FIFO_FULL : std_logic;
+	signal signal_ed_15_FIFO_FULL : std_logic;
+	signal signal_ed_17_FIFO_FULL : std_logic;
+	signal signal_ed_18_FIFO_FULL : std_logic;
+	signal signal_ed_19_20_FIFO_FULL : std_logic;
+	signal signal_PARAM_DT : std_logic_vector(10 downto 0);
+	signal signal_PARAM_LD : std_logic;
+	signal signal_PARAMETERS : std_logic_vector(0 downto 0);
+	signal signal_PARAMETERS_LD : std_logic;
+	signal signal_address : std_logic_vector(18 downto 0);
+	signal signal_read_data : std_logic_vector(31 downto 0);
+	signal signal_write_data : std_logic_vector(31 downto 0);
+	signal signal_read_en : std_logic;
+	signal signal_write_en : std_logic;
+	signal signal_SHMEM_WRITE_count : std_logic_vector(31 downto 0);
+	signal signal_SHMEM_READ_count : std_logic_vector(31 downto 0);
+	signal signal_SHMEM_READ_EN_count : std_logic;
+	signal signal_SHMEM_WRITE_EN_count : std_logic;
+	signal signal_SHMEM_WRITE_brightness : std_logic_vector(31 downto 0);
+	signal signal_SHMEM_READ_brightness : std_logic_vector(31 downto 0);
+	signal signal_SHMEM_READ_EN_brightness : std_logic;
+	signal signal_SHMEM_WRITE_EN_brightness : std_logic;
+	signal signal_param_ext_pci_clk : std_logic;
+	signal signal_register_rf_pci_clk : std_logic;
+	signal signal_SYNC_NUM : std_logic_vector(9 downto 0);
+  -- Internal signals writeInternalAdHocConnections 
+
+  -- Hierarchical signals 
+
+	signal I_data_in_Control : std_logic;
+	signal I_data_in_Data : std_logic_vector(63 downto 0);
+	signal I_data_in_Exists : std_logic;
+	signal I_data_in_Read : std_logic;
+	signal I_data_out_Control : std_logic;
+	signal I_data_out_Data : std_logic_vector(63 downto 0);
+	signal I_data_out_Full : std_logic;
+	signal I_data_out_Write : std_logic;
+  -- Internal signals writeHierarchicalConnections 
+
+	-- Default signals
+
+	signal net_gnd0 : std_logic;
+	signal net_gnd16 : std_logic_vector(15 downto 0);
+
+	signal sys_clk_s : std_logic;
+	signal sys_rst_s : std_logic;
+
+
+	-- START the actual definition of a Design
+
+begin
+
+	-- Connect Clock
+
+	sys_clk_s <= KPN_CLK;
+	sys_rst_s <= KPN_RST;
+
+
+	-- Connect Hiercical Interconnections
+
+	I_data_in_Data <= data_in_Data;
+	I_data_in_Control <= data_in_Control;
+	data_in_Read <= I_data_in_Read;
+	I_data_in_Exists <= data_in_Exists;
+	data_out_Data <= I_data_out_Data;
+	data_out_Control <= I_data_out_Control;
+	data_out_Write <= I_data_out_Write;
+	I_data_out_Full <= data_out_Full;
+
+	-- AD HOC EXTERNAL CONNECTIONS 
+	TEST_STOP(0) <= signal_hwn_nd_1_STOP;
+	signal_hwn_nd_1_STOP <= '1'; -- TIED VALUE
+	TEST_ERROR(0) <= signal_hwn_nd_1_ERROR;
+	signal_hwn_nd_1_ERROR <= '0'; -- TIED VALUE
+	TEST_BLOCK_RD(0) <= signal_hwn_nd_1_BLOCK_RD;
+	TEST_STOP(1) <= signal_hwn_nd_2_STOP;
+	TEST_ERROR(1) <= signal_hwn_nd_2_ERROR;
+	TEST_BLOCK_RD(1) <= signal_hwn_nd_2_BLOCK_RD;
+	TEST_STOP(2) <= signal_hwn_nd_3_STOP;
+	TEST_ERROR(2) <= signal_hwn_nd_3_ERROR;
+	TEST_BLOCK_RD(2) <= signal_hwn_nd_3_BLOCK_RD;
+	TEST_STOP(3) <= signal_hwn_nd_4_STOP;
+	TEST_ERROR(3) <= signal_hwn_nd_4_ERROR;
+	TEST_BLOCK_RD(3) <= signal_hwn_nd_4_BLOCK_RD;
+	TEST_STOP(4) <= signal_hwn_nd_5_STOP;
+	TEST_ERROR(4) <= signal_hwn_nd_5_ERROR;
+	TEST_BLOCK_RD(4) <= signal_hwn_nd_5_BLOCK_RD;
+	TEST_STOP(5) <= signal_hwn_nd_6_STOP;
+	TEST_ERROR(5) <= signal_hwn_nd_6_ERROR;
+	TEST_BLOCK_RD(5) <= signal_hwn_nd_6_BLOCK_RD;
+	TEST_STOP(6) <= signal_hwn_nd_7_STOP;
+	TEST_ERROR(6) <= signal_hwn_nd_7_ERROR;
+	TEST_BLOCK_RD(6) <= signal_hwn_nd_7_BLOCK_RD;
+	TEST_STOP(7) <= signal_hwn_nd_8_STOP;
+	TEST_ERROR(7) <= signal_hwn_nd_8_ERROR;
+	TEST_BLOCK_RD(7) <= signal_hwn_nd_8_BLOCK_RD;
+	TEST_STOP(8) <= signal_hwn_nd_9_STOP;
+	TEST_ERROR(8) <= signal_hwn_nd_9_ERROR;
+	TEST_BLOCK_RD(8) <= signal_hwn_nd_9_BLOCK_RD;
+	TEST_STOP(9) <= signal_hwn_nd_10_STOP;
+	TEST_ERROR(9) <= signal_hwn_nd_10_ERROR;
+	TEST_BLOCK_RD(9) <= signal_hwn_nd_10_BLOCK_RD;
+	TEST_STOP(10) <= signal_hwn_nd_11_STOP;
+	TEST_ERROR(10) <= signal_hwn_nd_11_ERROR;
+	TEST_BLOCK_RD(10) <= signal_hwn_nd_11_BLOCK_RD;
+	TEST_STOP(11) <= signal_hwn_nd_12_STOP;
+	TEST_ERROR(11) <= signal_hwn_nd_12_ERROR;
+	TEST_BLOCK_RD(11) <= signal_hwn_nd_12_BLOCK_RD;
+	TEST_STOP(12) <= signal_hwn_nd_13_STOP;
+	TEST_ERROR(12) <= signal_hwn_nd_13_ERROR;
+	TEST_BLOCK_RD(12) <= signal_hwn_nd_13_BLOCK_RD;
+	TEST_STOP(13) <= signal_hwn_nd_14_STOP;
+	TEST_ERROR(13) <= signal_hwn_nd_14_ERROR;
+	TEST_BLOCK_RD(13) <= signal_hwn_nd_14_BLOCK_RD;
+	TEST_FIFO_FULL(0) <= signal_ed_1_FIFO_FULL;
+	TEST_FIFO_FULL(1) <= signal_ed_2_FIFO_FULL;
+	TEST_FIFO_FULL(2) <= signal_ed_3_FIFO_FULL;
+	TEST_FIFO_FULL(3) <= signal_ed_4_5_FIFO_FULL;
+	TEST_FIFO_FULL(4) <= signal_ed_6_FIFO_FULL;
+	TEST_FIFO_FULL(5) <= signal_ed_7_FIFO_FULL;
+	TEST_FIFO_FULL(6) <= signal_ed_8_FIFO_FULL;
+	TEST_FIFO_FULL(7) <= signal_ed_9_FIFO_FULL;
+	TEST_FIFO_FULL(8) <= signal_ed_10_FIFO_FULL;
+	TEST_FIFO_FULL(9) <= signal_ed_11_FIFO_FULL;
+	TEST_FIFO_FULL(10) <= signal_ed_12_FIFO_FULL;
+	TEST_FIFO_FULL(11) <= signal_ed_13_FIFO_FULL;
+	TEST_FIFO_FULL(12) <= signal_ed_14_FIFO_FULL;
+	TEST_FIFO_FULL(13) <= signal_ed_15_FIFO_FULL;
+	TEST_FIFO_FULL(14) <= signal_ed_17_FIFO_FULL;
+	TEST_FIFO_FULL(15) <= signal_ed_18_FIFO_FULL;
+	TEST_FIFO_FULL(16) <= signal_ed_19_20_FIFO_FULL;
+	signal_address <= address( 18 downto 0);
+	read_data( 31 downto 0) <= signal_read_data;
+	signal_write_data <= write_data( 31 downto 0);
+	signal_read_en <= read_en;
+	signal_write_en <= write_en;
+	signal_param_ext_pci_clk <= pci_clk;
+	signal_register_rf_pci_clk <= pci_clk;
+
+-- Give default signals, default values
+
+	net_gnd0 <= '0';
+	net_gnd16(15 downto 0) <= B"0000000000000000";
+
+-- Instanciate the wrappers (HWN and Edges)
+
+
+  bunny_static_split2rtl_hwn_nd_2_ip : bunny_static_split2rtl_hwn_nd_2_ip_wrapper
+	port map (
+		data_in_Rd => I_data_in_Read,
+		data_in_Din => I_data_in_Data(63 downto 0),
+		data_in_Exist => I_data_in_Exists,
+		data_in_CLK => open,
+		data_in_CTRL => I_data_in_Control,
+		ND_2OP_1_Wr => signal_ed_1_out_FSL_M_Write,
+		ND_2OP_1_Dout(63 downto 0) => signal_ed_1_out_FSL_M_Data(0 to 63),
+		ND_2OP_1_Full => signal_ed_1_out_FSL_M_Full,
+		ND_2OP_1_CLK => open,
+		ND_2OP_1_CTRL => signal_ed_1_out_FSL_M_Control,
+		ND_2OP_1_d1_Wr => signal_ed_2_out_FSL_M_Write,
+		ND_2OP_1_d1_Dout(63 downto 0) => signal_ed_2_out_FSL_M_Data(0 to 63),
+		ND_2OP_1_d1_Full => signal_ed_2_out_FSL_M_Full,
+		ND_2OP_1_d1_CLK => open,
+		ND_2OP_1_d1_CTRL => signal_ed_2_out_FSL_M_Control,
+		PARAM_DT => signal_PARAM_DT,
+		PARAM_LD => signal_PARAM_LD,
+		STOP => signal_hwn_nd_2_STOP,
+		ERROR => signal_hwn_nd_2_ERROR,
+		BLOCK_RD => signal_hwn_nd_2_BLOCK_RD,
+		RST => sys_rst_s,
+		CLK => sys_clk_s
+	);
+
+  bunny_static_split2rtl_hwn_nd_3_ip : bunny_static_split2rtl_hwn_nd_3_ip_wrapper
+	port map (
+		FSL_M_Wr => signal_ed_21_out_FSL_M_Write,
+		FSL_M_Dout(63 downto 0) => signal_ed_21_out_FSL_M_Data(0 to 63),
+		FSL_M_Full => signal_ed_21_out_FSL_M_Full,
+		FSL_M_CLK => open,
+		FSL_M_CTRL => signal_ed_21_out_FSL_M_Control,
+		RST => sys_rst_s,
+		CLK => sys_clk_s
+	);
+
+  bunny_static_split2rtl_hwn_nd_4_ip : bunny_static_split2rtl_hwn_nd_4_ip_wrapper
+	port map (
+		rf_count ( 31 downto 0 ) => signal_SHMEM_READ_count ( 31 downto 0 ),
+		ND_4IP_1_Rd => signal_ed_1_in_FSL_S_Read,
+		ND_4IP_1_Din(63 downto 0) => signal_ed_1_in_FSL_S_Data(0 to 63),
+		ND_4IP_1_Exist => signal_ed_1_in_FSL_S_Exists,
+		ND_4IP_1_CLK => open,
+		ND_4IP_1_CTRL => signal_ed_1_in_FSL_S_Control,
+		PARAM_DT => signal_PARAM_DT,
+		PARAM_LD => signal_PARAM_LD,
+		STOP => signal_hwn_nd_4_STOP,
+		ERROR => signal_hwn_nd_4_ERROR,
+		BLOCK_RD => signal_hwn_nd_4_BLOCK_RD,
+		RST => sys_rst_s,
+		CLK => sys_clk_s
+	);
+
+  bunny_static_split2rtl_hwn_nd_5_ip : bunny_static_split2rtl_hwn_nd_5_ip_wrapper
+	port map (
+		ND_5IP_2_Rd => signal_ed_2_in_FSL_S_Read,
+		ND_5IP_2_Din(63 downto 0) => signal_ed_2_in_FSL_S_Data(0 to 63),
+		ND_5IP_2_Exist => signal_ed_2_in_FSL_S_Exists,
+		ND_5IP_2_CLK => open,
+		ND_5IP_2_CTRL => signal_ed_2_in_FSL_S_Control,
+		ND_5OP_1_Wr => signal_ed_3_out_FSL_M_Write,
+		ND_5OP_1_Dout(31 downto 0) => signal_ed_3_out_FSL_M_Data(0 to 31),
+		ND_5OP_1_Full => signal_ed_3_out_FSL_M_Full,
+		ND_5OP_1_CLK => open,
+		ND_5OP_1_CTRL => signal_ed_3_out_FSL_M_Control,
+		ND_5OP_2_d1_ND_5OP_2_Wr => signal_ed_4_5_out_FSL_M_Write,
+		ND_5OP_2_d1_ND_5OP_2_Dout(31 downto 0) => signal_ed_4_5_out_FSL_M_Data(0 to 31),
+		ND_5OP_2_d1_ND_5OP_2_Full => signal_ed_4_5_out_FSL_M_Full,
+		ND_5OP_2_d1_ND_5OP_2_CLK => open,
+		ND_5OP_2_d1_ND_5OP_2_CTRL => signal_ed_4_5_out_FSL_M_Control,
+		PARAM_DT => signal_PARAM_DT,
+		PARAM_LD => signal_PARAM_LD,
+		STOP => signal_hwn_nd_5_STOP,
+		ERROR => signal_hwn_nd_5_ERROR,
+		BLOCK_RD => signal_hwn_nd_5_BLOCK_RD,
+		RST => sys_rst_s,
+		CLK => sys_clk_s
+	);
+
+  bunny_static_split2rtl_hwn_nd_6_ip : bunny_static_split2rtl_hwn_nd_6_ip_wrapper
+	port map (
+		ND_6IP_3_Rd => signal_ed_3_in_FSL_S_Read,
+		ND_6IP_3_Din(31 downto 0) => signal_ed_3_in_FSL_S_Data(0 to 31),
+		ND_6IP_3_Exist => signal_ed_3_in_FSL_S_Exists,
+		ND_6IP_3_CLK => open,
+		ND_6IP_3_CTRL => signal_ed_3_in_FSL_S_Control,
+		ND_6IP_5_ND_6IP_4_Rd => signal_ed_4_5_in_FSL_S_Read,
+		ND_6IP_5_ND_6IP_4_Din(31 downto 0) => signal_ed_4_5_in_FSL_S_Data(0 to 31),
+		ND_6IP_5_ND_6IP_4_Exist => signal_ed_4_5_in_FSL_S_Exists,
+		ND_6IP_5_ND_6IP_4_CLK => open,
+		ND_6IP_5_ND_6IP_4_CTRL => signal_ed_4_5_in_FSL_S_Control,
+		ND_6OP_1_Wr => signal_ed_6_out_FSL_M_Write,
+		ND_6OP_1_Dout(7 downto 0) => signal_ed_6_out_FSL_M_Data(0 to 7),
+		ND_6OP_1_Full => signal_ed_6_out_FSL_M_Full,
+		ND_6OP_1_CLK => open,
+		ND_6OP_1_CTRL => signal_ed_6_out_FSL_M_Control,
+		ND_6OP_2_Wr => signal_ed_7_out_FSL_M_Write,
+		ND_6OP_2_Dout(7 downto 0) => signal_ed_7_out_FSL_M_Data(0 to 7),
+		ND_6OP_2_Full => signal_ed_7_out_FSL_M_Full,
+		ND_6OP_2_CLK => open,
+		ND_6OP_2_CTRL => signal_ed_7_out_FSL_M_Control,
+		ND_6OP_3_Wr => signal_ed_8_out_FSL_M_Write,
+		ND_6OP_3_Dout(7 downto 0) => signal_ed_8_out_FSL_M_Data(0 to 7),
+		ND_6OP_3_Full => signal_ed_8_out_FSL_M_Full,
+		ND_6OP_3_CLK => open,
+		ND_6OP_3_CTRL => signal_ed_8_out_FSL_M_Control,
+		PARAM_DT => signal_PARAM_DT,
+		PARAM_LD => signal_PARAM_LD,
+		STOP => signal_hwn_nd_6_STOP,
+		ERROR => signal_hwn_nd_6_ERROR,
+		BLOCK_RD => signal_hwn_nd_6_BLOCK_RD,
+		RST => sys_rst_s,
+		CLK => sys_clk_s
+	);
+
+  bunny_static_split2rtl_hwn_nd_7_ip : bunny_static_split2rtl_hwn_nd_7_ip_wrapper
+	port map (
+		ND_7IP_6_Rd => signal_ed_6_in_FSL_S_Read,
+		ND_7IP_6_Din(7 downto 0) => signal_ed_6_in_FSL_S_Data(0 to 7),
+		ND_7IP_6_Exist => signal_ed_6_in_FSL_S_Exists,
+		ND_7IP_6_CLK => open,
+		ND_7IP_6_CTRL => signal_ed_6_in_FSL_S_Control,
+		ND_7IP_7_Rd => signal_ed_7_in_FSL_S_Read,
+		ND_7IP_7_Din(7 downto 0) => signal_ed_7_in_FSL_S_Data(0 to 7),
+		ND_7IP_7_Exist => signal_ed_7_in_FSL_S_Exists,
+		ND_7IP_7_CLK => open,
+		ND_7IP_7_CTRL => signal_ed_7_in_FSL_S_Control,
+		ND_7IP_8_Rd => signal_ed_8_in_FSL_S_Read,
+		ND_7IP_8_Din(7 downto 0) => signal_ed_8_in_FSL_S_Data(0 to 7),
+		ND_7IP_8_Exist => signal_ed_8_in_FSL_S_Exists,
+		ND_7IP_8_CLK => open,
+		ND_7IP_8_CTRL => signal_ed_8_in_FSL_S_Control,
+		ND_7OP_1_Wr => signal_ed_9_out_FSL_M_Write,
+		ND_7OP_1_Dout(7 downto 0) => signal_ed_9_out_FSL_M_Data(0 to 7),
+		ND_7OP_1_Full => signal_ed_9_out_FSL_M_Full,
+		ND_7OP_1_CLK => open,
+		ND_7OP_1_CTRL => signal_ed_9_out_FSL_M_Control,
+		ND_7OP_1_d1_Wr => signal_ed_10_out_FSL_M_Write,
+		ND_7OP_1_d1_Dout(7 downto 0) => signal_ed_10_out_FSL_M_Data(0 to 7),
+		ND_7OP_1_d1_Full => signal_ed_10_out_FSL_M_Full,
+		ND_7OP_1_d1_CLK => open,
+		ND_7OP_1_d1_CTRL => signal_ed_10_out_FSL_M_Control,
+		PARAM_DT => signal_PARAM_DT,
+		PARAM_LD => signal_PARAM_LD,
+		STOP => signal_hwn_nd_7_STOP,
+		ERROR => signal_hwn_nd_7_ERROR,
+		BLOCK_RD => signal_hwn_nd_7_BLOCK_RD,
+		RST => sys_rst_s,
+		CLK => sys_clk_s
+	);
+
+  bunny_static_split2rtl_hwn_nd_8_ip : bunny_static_split2rtl_hwn_nd_8_ip_wrapper
+	port map (
+		ND_8IP_9_Rd => signal_ed_9_in_FSL_S_Read,
+		ND_8IP_9_Din(7 downto 0) => signal_ed_9_in_FSL_S_Data(0 to 7),
+		ND_8IP_9_Exist => signal_ed_9_in_FSL_S_Exists,
+		ND_8IP_9_CLK => open,
+		ND_8IP_9_CTRL => signal_ed_9_in_FSL_S_Control,
+		ND_8OP_1_Wr => signal_ed_11_out_FSL_M_Write,
+		ND_8OP_1_Dout(7 downto 0) => signal_ed_11_out_FSL_M_Data(0 to 7),
+		ND_8OP_1_Full => signal_ed_11_out_FSL_M_Full,
+		ND_8OP_1_CLK => open,
+		ND_8OP_1_CTRL => signal_ed_11_out_FSL_M_Control,
+		PARAM_DT => signal_PARAM_DT,
+		PARAM_LD => signal_PARAM_LD,
+		STOP => signal_hwn_nd_8_STOP,
+		ERROR => signal_hwn_nd_8_ERROR,
+		BLOCK_RD => signal_hwn_nd_8_BLOCK_RD,
+		RST => sys_rst_s,
+		CLK => sys_clk_s
+	);
+
+  bunny_static_split2rtl_hwn_nd_9_ip : bunny_static_split2rtl_hwn_nd_9_ip_wrapper
+	port map (
+		rf_brightness ( 31 downto 0 ) => signal_SHMEM_WRITE_brightness ( 31 downto 0 ),
+		ND_9IP_10_Rd => signal_ed_10_in_FSL_S_Read,
+		ND_9IP_10_Din(7 downto 0) => signal_ed_10_in_FSL_S_Data(0 to 7),
+		ND_9IP_10_Exist => signal_ed_10_in_FSL_S_Exists,
+		ND_9IP_10_CLK => open,
+		ND_9IP_10_CTRL => signal_ed_10_in_FSL_S_Control,
+		ND_9OP_1_Wr => signal_ed_12_out_FSL_M_Write,
+		ND_9OP_1_Dout(7 downto 0) => signal_ed_12_out_FSL_M_Data(0 to 7),
+		ND_9OP_1_Full => signal_ed_12_out_FSL_M_Full,
+		ND_9OP_1_CLK => open,
+		ND_9OP_1_CTRL => signal_ed_12_out_FSL_M_Control,
+		PARAM_DT => signal_PARAM_DT,
+		PARAM_LD => signal_PARAM_LD,
+		STOP => signal_hwn_nd_9_STOP,
+		ERROR => signal_hwn_nd_9_ERROR,
+		BLOCK_RD => signal_hwn_nd_9_BLOCK_RD,
+		RST => sys_rst_s,
+		CLK => sys_clk_s
+	);
+
+  bunny_static_split2rtl_hwn_nd_10_ip : bunny_static_split2rtl_hwn_nd_10_ip_wrapper
+	port map (
+		ND_10IP_11_Rd => signal_ed_11_in_FSL_S_Read,
+		ND_10IP_11_Din(7 downto 0) => signal_ed_11_in_FSL_S_Data(0 to 7),
+		ND_10IP_11_Exist => signal_ed_11_in_FSL_S_Exists,
+		ND_10IP_11_CLK => open,
+		ND_10IP_11_CTRL => signal_ed_11_in_FSL_S_Control,
+		ND_10IP_12_Rd => signal_ed_12_in_FSL_S_Read,
+		ND_10IP_12_Din(7 downto 0) => signal_ed_12_in_FSL_S_Data(0 to 7),
+		ND_10IP_12_Exist => signal_ed_12_in_FSL_S_Exists,
+		ND_10IP_12_CLK => open,
+		ND_10IP_12_CTRL => signal_ed_12_in_FSL_S_Control,
+		ND_10OP_1_Wr => signal_ed_13_out_FSL_M_Write,
+		ND_10OP_1_Dout(7 downto 0) => signal_ed_13_out_FSL_M_Data(0 to 7),
+		ND_10OP_1_Full => signal_ed_13_out_FSL_M_Full,
+		ND_10OP_1_CLK => open,
+		ND_10OP_1_CTRL => signal_ed_13_out_FSL_M_Control,
+		ND_10OP_1_d1_Wr => signal_ed_14_out_FSL_M_Write,
+		ND_10OP_1_d1_Dout(7 downto 0) => signal_ed_14_out_FSL_M_Data(0 to 7),
+		ND_10OP_1_d1_Full => signal_ed_14_out_FSL_M_Full,
+		ND_10OP_1_d1_CLK => open,
+		ND_10OP_1_d1_CTRL => signal_ed_14_out_FSL_M_Control,
+		ND_10OP_1_d2_Wr => signal_ed_15_out_FSL_M_Write,
+		ND_10OP_1_d2_Dout(7 downto 0) => signal_ed_15_out_FSL_M_Data(0 to 7),
+		ND_10OP_1_d2_Full => signal_ed_15_out_FSL_M_Full,
+		ND_10OP_1_d2_CLK => open,
+		ND_10OP_1_d2_CTRL => signal_ed_15_out_FSL_M_Control,
+		PARAM_DT => signal_PARAM_DT,
+		PARAM_LD => signal_PARAM_LD,
+		STOP => signal_hwn_nd_10_STOP,
+		ERROR => signal_hwn_nd_10_ERROR,
+		BLOCK_RD => signal_hwn_nd_10_BLOCK_RD,
+		RST => sys_rst_s,
+		CLK => sys_clk_s
+	);
+
+  bunny_static_split2rtl_hwn_nd_11_ip : bunny_static_split2rtl_hwn_nd_11_ip_wrapper
+	port map (
+		FSL_M_Wr => signal_ed_16_out_FSL_M_Write,
+		FSL_M_Dout(7 downto 0) => signal_ed_16_out_FSL_M_Data(0 to 7),
+		FSL_M_Full => signal_ed_16_out_FSL_M_Full,
+		FSL_M_CLK => open,
+		FSL_M_CTRL => signal_ed_16_out_FSL_M_Control,
+		RST => sys_rst_s,
+		CLK => sys_clk_s
+	);
+
+  bunny_static_split2rtl_hwn_nd_12_ip : bunny_static_split2rtl_hwn_nd_12_ip_wrapper
+	port map (
+		ND_12IP_13_Rd => signal_ed_13_in_FSL_S_Read,
+		ND_12IP_13_Din(7 downto 0) => signal_ed_13_in_FSL_S_Data(0 to 7),
+		ND_12IP_13_Exist => signal_ed_13_in_FSL_S_Exists,
+		ND_12IP_13_CLK => open,
+		ND_12IP_13_CTRL => signal_ed_13_in_FSL_S_Control,
+		ND_12IP_14_Rd => signal_ed_14_in_FSL_S_Read,
+		ND_12IP_14_Din(7 downto 0) => signal_ed_14_in_FSL_S_Data(0 to 7),
+		ND_12IP_14_Exist => signal_ed_14_in_FSL_S_Exists,
+		ND_12IP_14_CLK => open,
+		ND_12IP_14_CTRL => signal_ed_14_in_FSL_S_Control,
+		ND_12IP_15_Rd => signal_ed_15_in_FSL_S_Read,
+		ND_12IP_15_Din(7 downto 0) => signal_ed_15_in_FSL_S_Data(0 to 7),
+		ND_12IP_15_Exist => signal_ed_15_in_FSL_S_Exists,
+		ND_12IP_15_CLK => open,
+		ND_12IP_15_CTRL => signal_ed_15_in_FSL_S_Control,
+		ND_12IP_16_Rd => signal_ed_16_in_FSL_S_Read,
+		ND_12IP_16_Din(7 downto 0) => signal_ed_16_in_FSL_S_Data(0 to 7),
+		ND_12IP_16_Exist => signal_ed_16_in_FSL_S_Exists,
+		ND_12IP_16_CLK => open,
+		ND_12IP_16_CTRL => signal_ed_16_in_FSL_S_Control,
+		ND_12OP_1_Wr => signal_ed_17_out_FSL_M_Write,
+		ND_12OP_1_Dout(31 downto 0) => signal_ed_17_out_FSL_M_Data(0 to 31),
+		ND_12OP_1_Full => signal_ed_17_out_FSL_M_Full,
+		ND_12OP_1_CLK => open,
+		ND_12OP_1_CTRL => signal_ed_17_out_FSL_M_Control,
+		ND_12OP_1_d1_Wr => signal_ed_18_out_FSL_M_Write,
+		ND_12OP_1_d1_Dout(31 downto 0) => signal_ed_18_out_FSL_M_Data(0 to 31),
+		ND_12OP_1_d1_Full => signal_ed_18_out_FSL_M_Full,
+		ND_12OP_1_d1_CLK => open,
+		ND_12OP_1_d1_CTRL => signal_ed_18_out_FSL_M_Control,
+		PARAM_DT => signal_PARAM_DT,
+		PARAM_LD => signal_PARAM_LD,
+		STOP => signal_hwn_nd_12_STOP,
+		ERROR => signal_hwn_nd_12_ERROR,
+		BLOCK_RD => signal_hwn_nd_12_BLOCK_RD,
+		RST => sys_rst_s,
+		CLK => sys_clk_s
+	);
+
+  bunny_static_split2rtl_hwn_nd_13_ip : bunny_static_split2rtl_hwn_nd_13_ip_wrapper
+	port map (
+		ND_13IP_17_Rd => signal_ed_17_in_FSL_S_Read,
+		ND_13IP_17_Din(31 downto 0) => signal_ed_17_in_FSL_S_Data(0 to 31),
+		ND_13IP_17_Exist => signal_ed_17_in_FSL_S_Exists,
+		ND_13IP_17_CLK => open,
+		ND_13IP_17_CTRL => signal_ed_17_in_FSL_S_Control,
+		ND_13IP_18_Rd => signal_ed_18_in_FSL_S_Read,
+		ND_13IP_18_Din(31 downto 0) => signal_ed_18_in_FSL_S_Data(0 to 31),
+		ND_13IP_18_Exist => signal_ed_18_in_FSL_S_Exists,
+		ND_13IP_18_CLK => open,
+		ND_13IP_18_CTRL => signal_ed_18_in_FSL_S_Control,
+		ND_13OP_1_d1_ND_13OP_1_Wr => signal_ed_19_20_out_FSL_M_Write,
+		ND_13OP_1_d1_ND_13OP_1_Dout(63 downto 0) => signal_ed_19_20_out_FSL_M_Data(0 to 63),
+		ND_13OP_1_d1_ND_13OP_1_Full => signal_ed_19_20_out_FSL_M_Full,
+		ND_13OP_1_d1_ND_13OP_1_CLK => open,
+		ND_13OP_1_d1_ND_13OP_1_CTRL => signal_ed_19_20_out_FSL_M_Control,
+		PARAM_DT => signal_PARAM_DT,
+		PARAM_LD => signal_PARAM_LD,
+		STOP => signal_hwn_nd_13_STOP,
+		ERROR => signal_hwn_nd_13_ERROR,
+		BLOCK_RD => signal_hwn_nd_13_BLOCK_RD,
+		RST => sys_rst_s,
+		CLK => sys_clk_s
+	);
+
+  bunny_static_split2rtl_hwn_nd_14_ip : bunny_static_split2rtl_hwn_nd_14_ip_wrapper
+	port map (
+		ND_14IP_20_ND_14IP_19_Rd => signal_ed_19_20_in_FSL_S_Read,
+		ND_14IP_20_ND_14IP_19_Din(63 downto 0) => signal_ed_19_20_in_FSL_S_Data(0 to 63),
+		ND_14IP_20_ND_14IP_19_Exist => signal_ed_19_20_in_FSL_S_Exists,
+		ND_14IP_20_ND_14IP_19_CLK => open,
+		ND_14IP_20_ND_14IP_19_CTRL => signal_ed_19_20_in_FSL_S_Control,
+		ND_14IP_21_Rd => signal_ed_21_in_FSL_S_Read,
+		ND_14IP_21_Din(63 downto 0) => signal_ed_21_in_FSL_S_Data(0 to 63),
+		ND_14IP_21_Exist => signal_ed_21_in_FSL_S_Exists,
+		ND_14IP_21_CLK => open,
+		ND_14IP_21_CTRL => signal_ed_21_in_FSL_S_Control,
+		data_out_Wr => I_data_out_Write,
+		data_out_Dout => I_data_out_Data(63 downto 0),
+		data_out_Full => I_data_out_Full,
+		data_out_CLK => open,
+		data_out_CTRL => I_data_out_Control,
+		PARAM_DT => signal_PARAM_DT,
+		PARAM_LD => signal_PARAM_LD,
+		STOP => signal_hwn_nd_14_STOP,
+		ERROR => signal_hwn_nd_14_ERROR,
+		BLOCK_RD => signal_hwn_nd_14_BLOCK_RD,
+		RST => sys_rst_s,
+		CLK => sys_clk_s
+	);
+
+  bunny_static_split2rtl_register_rf_ip : bunny_static_split2rtl_register_rf_ip_wrapper
+	port map (
+		address => signal_address,
+		read_data => signal_read_data,
+		read_en => signal_read_en,
+		write_en => signal_write_en,
+		write_data => signal_write_data,
+		pci_clk => signal_register_rf_pci_clk,
+		brightness_rf_read_data => signal_SHMEM_READ_brightness,
+		brightness_rf_read_en => signal_SHMEM_READ_EN_brightness,
+		brightness_rf_write_en => signal_SHMEM_WRITE_EN_brightness,
+		brightness_rf_write_data => signal_SHMEM_WRITE_brightness,
+		count_rf_read_data => signal_SHMEM_READ_count,
+		count_rf_read_en => signal_SHMEM_READ_EN_count,
+		count_rf_write_en => signal_SHMEM_WRITE_EN_count,
+		count_rf_write_data => signal_SHMEM_WRITE_count,
+		RST => sys_rst_s,
+		CLK => sys_clk_s
+	);
+
+  bunny_static_split2rtl_ed_1 : bunny_static_split2rtl_ed_1_ip_wrapper
+	port map (
+		FSL_Clk => sys_clk_s,
+		SYS_Rst => sys_rst_s,
+		FSL_Rst => open,
+		FSL_M_Clk => net_gnd0,
+		FSL_M_Data => signal_ed_1_out_FSL_M_Data,
+		FSL_M_Control => signal_ed_1_out_FSL_M_Control,
+		FSL_M_Write => signal_ed_1_out_FSL_M_Write,
+		FSL_M_Full => signal_ed_1_out_FSL_M_Full,
+		FSL_S_Data => signal_ed_1_in_FSL_S_Data,
+		FSL_S_Control => signal_ed_1_in_FSL_S_Control,
+		FSL_S_Read => signal_ed_1_in_FSL_S_Read,
+		FSL_S_Exists => signal_ed_1_in_FSL_S_Exists,
+		FSL_S_Clk => net_gnd0,
+		FSL_FULL => signal_ed_1_FIFO_FULL,
+		FSL_Has_Data => open,
+		FSL_Control_IRQ => open
+    );
+
+  bunny_static_split2rtl_ed_2 : bunny_static_split2rtl_ed_2_ip_wrapper
+	port map (
+		FSL_Clk => sys_clk_s,
+		SYS_Rst => sys_rst_s,
+		FSL_Rst => open,
+		FSL_M_Clk => net_gnd0,
+		FSL_M_Data => signal_ed_2_out_FSL_M_Data,
+		FSL_M_Control => signal_ed_2_out_FSL_M_Control,
+		FSL_M_Write => signal_ed_2_out_FSL_M_Write,
+		FSL_M_Full => signal_ed_2_out_FSL_M_Full,
+		FSL_S_Data => signal_ed_2_in_FSL_S_Data,
+		FSL_S_Control => signal_ed_2_in_FSL_S_Control,
+		FSL_S_Read => signal_ed_2_in_FSL_S_Read,
+		FSL_S_Exists => signal_ed_2_in_FSL_S_Exists,
+		FSL_S_Clk => net_gnd0,
+		FSL_FULL => signal_ed_2_FIFO_FULL,
+		FSL_Has_Data => open,
+		FSL_Control_IRQ => open
+    );
+
+  bunny_static_split2rtl_ed_3 : bunny_static_split2rtl_ed_3_ip_wrapper
+	port map (
+		FSL_Clk => sys_clk_s,
+		SYS_Rst => sys_rst_s,
+		FSL_Rst => open,
+		FSL_M_Clk => net_gnd0,
+		FSL_M_Data => signal_ed_3_out_FSL_M_Data,
+		FSL_M_Control => signal_ed_3_out_FSL_M_Control,
+		FSL_M_Write => signal_ed_3_out_FSL_M_Write,
+		FSL_M_Full => signal_ed_3_out_FSL_M_Full,
+		FSL_S_Data => signal_ed_3_in_FSL_S_Data,
+		FSL_S_Control => signal_ed_3_in_FSL_S_Control,
+		FSL_S_Read => signal_ed_3_in_FSL_S_Read,
+		FSL_S_Exists => signal_ed_3_in_FSL_S_Exists,
+		FSL_S_Clk => net_gnd0,
+		FSL_FULL => signal_ed_3_FIFO_FULL,
+		FSL_Has_Data => open,
+		FSL_Control_IRQ => open
+    );
+
+  bunny_static_split2rtl_ed_4_5 : bunny_static_split2rtl_ed_4_5_ip_wrapper
+	port map (
+		FSL_Clk => sys_clk_s,
+		SYS_Rst => sys_rst_s,
+		FSL_Rst => open,
+		FSL_M_Clk => net_gnd0,
+		FSL_M_Data => signal_ed_4_5_out_FSL_M_Data,
+		FSL_M_Control => signal_ed_4_5_out_FSL_M_Control,
+		FSL_M_Write => signal_ed_4_5_out_FSL_M_Write,
+		FSL_M_Full => signal_ed_4_5_out_FSL_M_Full,
+		FSL_S_Data => signal_ed_4_5_in_FSL_S_Data,
+		FSL_S_Control => signal_ed_4_5_in_FSL_S_Control,
+		FSL_S_Read => signal_ed_4_5_in_FSL_S_Read,
+		FSL_S_Exists => signal_ed_4_5_in_FSL_S_Exists,
+		FSL_S_Clk => net_gnd0,
+		FSL_FULL => signal_ed_4_5_FIFO_FULL,
+		FSL_Has_Data => open,
+		FSL_Control_IRQ => open
+    );
+
+  bunny_static_split2rtl_ed_6 : bunny_static_split2rtl_ed_6_ip_wrapper
+	port map (
+		FSL_Clk => sys_clk_s,
+		SYS_Rst => sys_rst_s,
+		FSL_Rst => open,
+		FSL_M_Clk => net_gnd0,
+		FSL_M_Data => signal_ed_6_out_FSL_M_Data,
+		FSL_M_Control => signal_ed_6_out_FSL_M_Control,
+		FSL_M_Write => signal_ed_6_out_FSL_M_Write,
+		FSL_M_Full => signal_ed_6_out_FSL_M_Full,
+		FSL_S_Data => signal_ed_6_in_FSL_S_Data,
+		FSL_S_Control => signal_ed_6_in_FSL_S_Control,
+		FSL_S_Read => signal_ed_6_in_FSL_S_Read,
+		FSL_S_Exists => signal_ed_6_in_FSL_S_Exists,
+		FSL_S_Clk => net_gnd0,
+		FSL_FULL => signal_ed_6_FIFO_FULL,
+		FSL_Has_Data => open,
+		FSL_Control_IRQ => open
+    );
+
+  bunny_static_split2rtl_ed_7 : bunny_static_split2rtl_ed_7_ip_wrapper
+	port map (
+		FSL_Clk => sys_clk_s,
+		SYS_Rst => sys_rst_s,
+		FSL_Rst => open,
+		FSL_M_Clk => net_gnd0,
+		FSL_M_Data => signal_ed_7_out_FSL_M_Data,
+		FSL_M_Control => signal_ed_7_out_FSL_M_Control,
+		FSL_M_Write => signal_ed_7_out_FSL_M_Write,
+		FSL_M_Full => signal_ed_7_out_FSL_M_Full,
+		FSL_S_Data => signal_ed_7_in_FSL_S_Data,
+		FSL_S_Control => signal_ed_7_in_FSL_S_Control,
+		FSL_S_Read => signal_ed_7_in_FSL_S_Read,
+		FSL_S_Exists => signal_ed_7_in_FSL_S_Exists,
+		FSL_S_Clk => net_gnd0,
+		FSL_FULL => signal_ed_7_FIFO_FULL,
+		FSL_Has_Data => open,
+		FSL_Control_IRQ => open
+    );
+
+  bunny_static_split2rtl_ed_8 : bunny_static_split2rtl_ed_8_ip_wrapper
+	port map (
+		FSL_Clk => sys_clk_s,
+		SYS_Rst => sys_rst_s,
+		FSL_Rst => open,
+		FSL_M_Clk => net_gnd0,
+		FSL_M_Data => signal_ed_8_out_FSL_M_Data,
+		FSL_M_Control => signal_ed_8_out_FSL_M_Control,
+		FSL_M_Write => signal_ed_8_out_FSL_M_Write,
+		FSL_M_Full => signal_ed_8_out_FSL_M_Full,
+		FSL_S_Data => signal_ed_8_in_FSL_S_Data,
+		FSL_S_Control => signal_ed_8_in_FSL_S_Control,
+		FSL_S_Read => signal_ed_8_in_FSL_S_Read,
+		FSL_S_Exists => signal_ed_8_in_FSL_S_Exists,
+		FSL_S_Clk => net_gnd0,
+		FSL_FULL => signal_ed_8_FIFO_FULL,
+		FSL_Has_Data => open,
+		FSL_Control_IRQ => open
+    );
+
+  bunny_static_split2rtl_ed_9 : bunny_static_split2rtl_ed_9_ip_wrapper
+	port map (
+		FSL_Clk => sys_clk_s,
+		SYS_Rst => sys_rst_s,
+		FSL_Rst => open,
+		FSL_M_Clk => net_gnd0,
+		FSL_M_Data => signal_ed_9_out_FSL_M_Data,
+		FSL_M_Control => signal_ed_9_out_FSL_M_Control,
+		FSL_M_Write => signal_ed_9_out_FSL_M_Write,
+		FSL_M_Full => signal_ed_9_out_FSL_M_Full,
+		FSL_S_Data => signal_ed_9_in_FSL_S_Data,
+		FSL_S_Control => signal_ed_9_in_FSL_S_Control,
+		FSL_S_Read => signal_ed_9_in_FSL_S_Read,
+		FSL_S_Exists => signal_ed_9_in_FSL_S_Exists,
+		FSL_S_Clk => net_gnd0,
+		FSL_FULL => signal_ed_9_FIFO_FULL,
+		FSL_Has_Data => open,
+		FSL_Control_IRQ => open
+    );
+
+  bunny_static_split2rtl_ed_10 : bunny_static_split2rtl_ed_10_ip_wrapper
+	port map (
+		FSL_Clk => sys_clk_s,
+		SYS_Rst => sys_rst_s,
+		FSL_Rst => open,
+		FSL_M_Clk => net_gnd0,
+		FSL_M_Data => signal_ed_10_out_FSL_M_Data,
+		FSL_M_Control => signal_ed_10_out_FSL_M_Control,
+		FSL_M_Write => signal_ed_10_out_FSL_M_Write,
+		FSL_M_Full => signal_ed_10_out_FSL_M_Full,
+		FSL_S_Data => signal_ed_10_in_FSL_S_Data,
+		FSL_S_Control => signal_ed_10_in_FSL_S_Control,
+		FSL_S_Read => signal_ed_10_in_FSL_S_Read,
+		FSL_S_Exists => signal_ed_10_in_FSL_S_Exists,
+		FSL_S_Clk => net_gnd0,
+		FSL_FULL => signal_ed_10_FIFO_FULL,
+		FSL_Has_Data => open,
+		FSL_Control_IRQ => open
+    );
+
+  bunny_static_split2rtl_ed_11 : bunny_static_split2rtl_ed_11_ip_wrapper
+	port map (
+		FSL_Clk => sys_clk_s,
+		SYS_Rst => sys_rst_s,
+		FSL_Rst => open,
+		FSL_M_Clk => net_gnd0,
+		FSL_M_Data => signal_ed_11_out_FSL_M_Data,
+		FSL_M_Control => signal_ed_11_out_FSL_M_Control,
+		FSL_M_Write => signal_ed_11_out_FSL_M_Write,
+		FSL_M_Full => signal_ed_11_out_FSL_M_Full,
+		FSL_S_Data => signal_ed_11_in_FSL_S_Data,
+		FSL_S_Control => signal_ed_11_in_FSL_S_Control,
+		FSL_S_Read => signal_ed_11_in_FSL_S_Read,
+		FSL_S_Exists => signal_ed_11_in_FSL_S_Exists,
+		FSL_S_Clk => net_gnd0,
+		FSL_FULL => signal_ed_11_FIFO_FULL,
+		FSL_Has_Data => open,
+		FSL_Control_IRQ => open
+    );
+
+  bunny_static_split2rtl_ed_12 : bunny_static_split2rtl_ed_12_ip_wrapper
+	port map (
+		FSL_Clk => sys_clk_s,
+		SYS_Rst => sys_rst_s,
+		FSL_Rst => open,
+		FSL_M_Clk => net_gnd0,
+		FSL_M_Data => signal_ed_12_out_FSL_M_Data,
+		FSL_M_Control => signal_ed_12_out_FSL_M_Control,
+		FSL_M_Write => signal_ed_12_out_FSL_M_Write,
+		FSL_M_Full => signal_ed_12_out_FSL_M_Full,
+		FSL_S_Data => signal_ed_12_in_FSL_S_Data,
+		FSL_S_Control => signal_ed_12_in_FSL_S_Control,
+		FSL_S_Read => signal_ed_12_in_FSL_S_Read,
+		FSL_S_Exists => signal_ed_12_in_FSL_S_Exists,
+		FSL_S_Clk => net_gnd0,
+		FSL_FULL => signal_ed_12_FIFO_FULL,
+		FSL_Has_Data => open,
+		FSL_Control_IRQ => open
+    );
+
+  bunny_static_split2rtl_ed_13 : bunny_static_split2rtl_ed_13_ip_wrapper
+	port map (
+		FSL_Clk => sys_clk_s,
+		SYS_Rst => sys_rst_s,
+		FSL_Rst => open,
+		FSL_M_Clk => net_gnd0,
+		FSL_M_Data => signal_ed_13_out_FSL_M_Data,
+		FSL_M_Control => signal_ed_13_out_FSL_M_Control,
+		FSL_M_Write => signal_ed_13_out_FSL_M_Write,
+		FSL_M_Full => signal_ed_13_out_FSL_M_Full,
+		FSL_S_Data => signal_ed_13_in_FSL_S_Data,
+		FSL_S_Control => signal_ed_13_in_FSL_S_Control,
+		FSL_S_Read => signal_ed_13_in_FSL_S_Read,
+		FSL_S_Exists => signal_ed_13_in_FSL_S_Exists,
+		FSL_S_Clk => net_gnd0,
+		FSL_FULL => signal_ed_13_FIFO_FULL,
+		FSL_Has_Data => open,
+		FSL_Control_IRQ => open
+    );
+
+  bunny_static_split2rtl_ed_14 : bunny_static_split2rtl_ed_14_ip_wrapper
+	port map (
+		FSL_Clk => sys_clk_s,
+		SYS_Rst => sys_rst_s,
+		FSL_Rst => open,
+		FSL_M_Clk => net_gnd0,
+		FSL_M_Data => signal_ed_14_out_FSL_M_Data,
+		FSL_M_Control => signal_ed_14_out_FSL_M_Control,
+		FSL_M_Write => signal_ed_14_out_FSL_M_Write,
+		FSL_M_Full => signal_ed_14_out_FSL_M_Full,
+		FSL_S_Data => signal_ed_14_in_FSL_S_Data,
+		FSL_S_Control => signal_ed_14_in_FSL_S_Control,
+		FSL_S_Read => signal_ed_14_in_FSL_S_Read,
+		FSL_S_Exists => signal_ed_14_in_FSL_S_Exists,
+		FSL_S_Clk => net_gnd0,
+		FSL_FULL => signal_ed_14_FIFO_FULL,
+		FSL_Has_Data => open,
+		FSL_Control_IRQ => open
+    );
+
+  bunny_static_split2rtl_ed_15 : bunny_static_split2rtl_ed_15_ip_wrapper
+	port map (
+		FSL_Clk => sys_clk_s,
+		SYS_Rst => sys_rst_s,
+		FSL_Rst => open,
+		FSL_M_Clk => net_gnd0,
+		FSL_M_Data => signal_ed_15_out_FSL_M_Data,
+		FSL_M_Control => signal_ed_15_out_FSL_M_Control,
+		FSL_M_Write => signal_ed_15_out_FSL_M_Write,
+		FSL_M_Full => signal_ed_15_out_FSL_M_Full,
+		FSL_S_Data => signal_ed_15_in_FSL_S_Data,
+		FSL_S_Control => signal_ed_15_in_FSL_S_Control,
+		FSL_S_Read => signal_ed_15_in_FSL_S_Read,
+		FSL_S_Exists => signal_ed_15_in_FSL_S_Exists,
+		FSL_S_Clk => net_gnd0,
+		FSL_FULL => signal_ed_15_FIFO_FULL,
+		FSL_Has_Data => open,
+		FSL_Control_IRQ => open
+    );
+
+  bunny_static_split2rtl_ed_17 : bunny_static_split2rtl_ed_17_ip_wrapper
+	port map (
+		FSL_Clk => sys_clk_s,
+		SYS_Rst => sys_rst_s,
+		FSL_Rst => open,
+		FSL_M_Clk => net_gnd0,
+		FSL_M_Data => signal_ed_17_out_FSL_M_Data,
+		FSL_M_Control => signal_ed_17_out_FSL_M_Control,
+		FSL_M_Write => signal_ed_17_out_FSL_M_Write,
+		FSL_M_Full => signal_ed_17_out_FSL_M_Full,
+		FSL_S_Data => signal_ed_17_in_FSL_S_Data,
+		FSL_S_Control => signal_ed_17_in_FSL_S_Control,
+		FSL_S_Read => signal_ed_17_in_FSL_S_Read,
+		FSL_S_Exists => signal_ed_17_in_FSL_S_Exists,
+		FSL_S_Clk => net_gnd0,
+		FSL_FULL => signal_ed_17_FIFO_FULL,
+		FSL_Has_Data => open,
+		FSL_Control_IRQ => open
+    );
+
+  bunny_static_split2rtl_ed_18 : bunny_static_split2rtl_ed_18_ip_wrapper
+	port map (
+		FSL_Clk => sys_clk_s,
+		SYS_Rst => sys_rst_s,
+		FSL_Rst => open,
+		FSL_M_Clk => net_gnd0,
+		FSL_M_Data => signal_ed_18_out_FSL_M_Data,
+		FSL_M_Control => signal_ed_18_out_FSL_M_Control,
+		FSL_M_Write => signal_ed_18_out_FSL_M_Write,
+		FSL_M_Full => signal_ed_18_out_FSL_M_Full,
+		FSL_S_Data => signal_ed_18_in_FSL_S_Data,
+		FSL_S_Control => signal_ed_18_in_FSL_S_Control,
+		FSL_S_Read => signal_ed_18_in_FSL_S_Read,
+		FSL_S_Exists => signal_ed_18_in_FSL_S_Exists,
+		FSL_S_Clk => net_gnd0,
+		FSL_FULL => signal_ed_18_FIFO_FULL,
+		FSL_Has_Data => open,
+		FSL_Control_IRQ => open
+    );
+
+  bunny_static_split2rtl_ed_19_20 : bunny_static_split2rtl_ed_19_20_ip_wrapper
+	port map (
+		FSL_Clk => sys_clk_s,
+		SYS_Rst => sys_rst_s,
+		FSL_Rst => open,
+		FSL_M_Clk => net_gnd0,
+		FSL_M_Data => signal_ed_19_20_out_FSL_M_Data,
+		FSL_M_Control => signal_ed_19_20_out_FSL_M_Control,
+		FSL_M_Write => signal_ed_19_20_out_FSL_M_Write,
+		FSL_M_Full => signal_ed_19_20_out_FSL_M_Full,
+		FSL_S_Data => signal_ed_19_20_in_FSL_S_Data,
+		FSL_S_Control => signal_ed_19_20_in_FSL_S_Control,
+		FSL_S_Read => signal_ed_19_20_in_FSL_S_Read,
+		FSL_S_Exists => signal_ed_19_20_in_FSL_S_Exists,
+		FSL_S_Clk => net_gnd0,
+		FSL_FULL => signal_ed_19_20_FIFO_FULL,
+		FSL_Has_Data => open,
+		FSL_Control_IRQ => open
+    );
+
+  bunny_static_split2rtl_ed_16 : bunny_static_split2rtl_ed_16_ip_wrapper
+	port map (
+		FSL_Clk => sys_clk_s,
+		SYS_Rst => sys_rst_s,
+		FSL_Rst => open,
+		FSL_M_Clk => net_gnd0,
+		FSL_S_Data => signal_ed_16_in_FSL_S_Data,
+		FSL_S_Control => signal_ed_16_in_FSL_S_Control,
+		FSL_S_Read => signal_ed_16_in_FSL_S_Read,
+		FSL_S_Exists => signal_ed_16_in_FSL_S_Exists,
+		FSL_M_Data => signal_ed_16_out_FSL_M_Data,
+		FSL_M_Control => signal_ed_16_out_FSL_M_Control,
+		FSL_M_Write => signal_ed_16_out_FSL_M_Write,
+		FSL_M_Full => signal_ed_16_out_FSL_M_Full,
+		FSL_S_Clk => net_gnd0,
+		FSL_FULL => open,
+		FSL_Has_Data => open,
+		FSL_Control_IRQ => open
+    );
+
+  bunny_static_split2rtl_ed_21 : bunny_static_split2rtl_ed_21_ip_wrapper
+	port map (
+		FSL_Clk => sys_clk_s,
+		SYS_Rst => sys_rst_s,
+		FSL_Rst => open,
+		FSL_M_Clk => net_gnd0,
+		FSL_S_Data => signal_ed_21_in_FSL_S_Data,
+		FSL_S_Control => signal_ed_21_in_FSL_S_Control,
+		FSL_S_Read => signal_ed_21_in_FSL_S_Read,
+		FSL_S_Exists => signal_ed_21_in_FSL_S_Exists,
+		FSL_M_Data => signal_ed_21_out_FSL_M_Data,
+		FSL_M_Control => signal_ed_21_out_FSL_M_Control,
+		FSL_M_Write => signal_ed_21_out_FSL_M_Write,
+		FSL_M_Full => signal_ed_21_out_FSL_M_Full,
+		FSL_S_Clk => net_gnd0,
+		FSL_FULL => open,
+		FSL_Has_Data => open,
+		FSL_Control_IRQ => open
+    );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_10_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_10_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0e421e7f8be08692426c2a3df5e1213c6675896e
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_10_ip_wrapper.vhd
@@ -0,0 +1,99 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_ed_10_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_altera_fifo_1_lib;
+use compaandesign_com_altera_fifo_1_lib.all;
+
+entity bunny_static_split2rtl_ed_10_ip_wrapper is
+  port (
+    FSL_Clk : in std_logic;
+    SYS_Rst : in std_logic;
+    FSL_Rst : out std_logic;
+    FSL_M_Clk : in std_logic;
+    FSL_M_Data : in std_logic_vector(0 to 7);
+    FSL_M_Control : in std_logic;
+    FSL_M_Write : in std_logic;
+    FSL_M_Full : out std_logic;
+    FSL_S_Clk : in std_logic;
+    FSL_S_Data : out std_logic_vector(0 to 7);
+    FSL_S_Control : out std_logic;
+    FSL_S_Read : in std_logic;
+    FSL_S_Exists : out std_logic;
+    FSL_Full : out std_logic;
+    FSL_Has_Data : out std_logic;
+    FSL_Control_IRQ : out std_logic
+  );
+
+
+end bunny_static_split2rtl_ed_10_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_ed_10_ip_wrapper is
+
+  component fsl_v20 is
+	generic (
+		C_EXT_RESET_HIGH : INTEGER := 1;
+		C_ASYNC_CLKS : INTEGER := 0;
+		C_IMPL_STYLE : INTEGER := 0;
+		C_USE_CONTROL : INTEGER := 1;
+		C_FSL_DWIDTH : INTEGER := 32;
+		C_FSL_DEPTH : INTEGER := 16;
+		C_READ_CLOCK_PERIOD : INTEGER := 0
+	);
+    port (
+      FSL_Clk 	: in  std_logic;
+      SYS_Rst 	: in  std_logic;
+      FSL_Rst 	: out std_logic;
+      FSL_M_Clk 	: in  std_logic;
+      FSL_M_Data 	: in  std_logic_vector(0 to 7);
+      FSL_M_Control: in  std_logic;
+      FSL_M_Write 	: in  std_logic;
+      FSL_M_Full 	: out std_logic;
+      FSL_S_Clk 	: in  std_logic;
+      FSL_S_Data 	: out std_logic_vector(0 to 7);
+      FSL_S_Control: out std_logic;
+      FSL_S_Read 	: in  std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full 	: out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+begin
+
+  bunny_static_split2rtl_ed_10 : fsl_v20
+	generic map (
+		C_EXT_RESET_HIGH => 1,
+		C_ASYNC_CLKS => 0,
+		C_IMPL_STYLE => 0,
+		C_USE_CONTROL => 1,
+		C_FSL_DWIDTH => 8,
+		C_FSL_DEPTH => 16,
+		C_READ_CLOCK_PERIOD => 0
+	)
+    port map (
+      FSL_Clk => FSL_Clk,
+      SYS_Rst => SYS_Rst,
+      FSL_Rst => FSL_Rst,
+      FSL_M_Clk => FSL_M_Clk,
+      FSL_M_Data => FSL_M_Data,
+      FSL_M_Control => FSL_M_Control,
+      FSL_M_Write => FSL_M_Write,
+      FSL_M_Full => FSL_M_Full,
+      FSL_S_Clk => FSL_S_Clk,
+      FSL_S_Data => FSL_S_Data,
+      FSL_S_Control => FSL_S_Control,
+      FSL_S_Read => FSL_S_Read,
+      FSL_S_Exists => FSL_S_Exists,
+      FSL_Full => FSL_Full,
+      FSL_Has_Data => FSL_Has_Data,
+      FSL_Control_IRQ => FSL_Control_IRQ
+    );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_11_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_11_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d63f942fcb4daa9fb2926237739c9f248cebff80
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_11_ip_wrapper.vhd
@@ -0,0 +1,99 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_ed_11_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_altera_fifo_1_lib;
+use compaandesign_com_altera_fifo_1_lib.all;
+
+entity bunny_static_split2rtl_ed_11_ip_wrapper is
+  port (
+    FSL_Clk : in std_logic;
+    SYS_Rst : in std_logic;
+    FSL_Rst : out std_logic;
+    FSL_M_Clk : in std_logic;
+    FSL_M_Data : in std_logic_vector(0 to 7);
+    FSL_M_Control : in std_logic;
+    FSL_M_Write : in std_logic;
+    FSL_M_Full : out std_logic;
+    FSL_S_Clk : in std_logic;
+    FSL_S_Data : out std_logic_vector(0 to 7);
+    FSL_S_Control : out std_logic;
+    FSL_S_Read : in std_logic;
+    FSL_S_Exists : out std_logic;
+    FSL_Full : out std_logic;
+    FSL_Has_Data : out std_logic;
+    FSL_Control_IRQ : out std_logic
+  );
+
+
+end bunny_static_split2rtl_ed_11_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_ed_11_ip_wrapper is
+
+  component fsl_v20 is
+	generic (
+		C_EXT_RESET_HIGH : INTEGER := 1;
+		C_ASYNC_CLKS : INTEGER := 0;
+		C_IMPL_STYLE : INTEGER := 0;
+		C_USE_CONTROL : INTEGER := 1;
+		C_FSL_DWIDTH : INTEGER := 32;
+		C_FSL_DEPTH : INTEGER := 16;
+		C_READ_CLOCK_PERIOD : INTEGER := 0
+	);
+    port (
+      FSL_Clk 	: in  std_logic;
+      SYS_Rst 	: in  std_logic;
+      FSL_Rst 	: out std_logic;
+      FSL_M_Clk 	: in  std_logic;
+      FSL_M_Data 	: in  std_logic_vector(0 to 7);
+      FSL_M_Control: in  std_logic;
+      FSL_M_Write 	: in  std_logic;
+      FSL_M_Full 	: out std_logic;
+      FSL_S_Clk 	: in  std_logic;
+      FSL_S_Data 	: out std_logic_vector(0 to 7);
+      FSL_S_Control: out std_logic;
+      FSL_S_Read 	: in  std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full 	: out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+begin
+
+  bunny_static_split2rtl_ed_11 : fsl_v20
+	generic map (
+		C_EXT_RESET_HIGH => 1,
+		C_ASYNC_CLKS => 0,
+		C_IMPL_STYLE => 0,
+		C_USE_CONTROL => 1,
+		C_FSL_DWIDTH => 8,
+		C_FSL_DEPTH => 16,
+		C_READ_CLOCK_PERIOD => 0
+	)
+    port map (
+      FSL_Clk => FSL_Clk,
+      SYS_Rst => SYS_Rst,
+      FSL_Rst => FSL_Rst,
+      FSL_M_Clk => FSL_M_Clk,
+      FSL_M_Data => FSL_M_Data,
+      FSL_M_Control => FSL_M_Control,
+      FSL_M_Write => FSL_M_Write,
+      FSL_M_Full => FSL_M_Full,
+      FSL_S_Clk => FSL_S_Clk,
+      FSL_S_Data => FSL_S_Data,
+      FSL_S_Control => FSL_S_Control,
+      FSL_S_Read => FSL_S_Read,
+      FSL_S_Exists => FSL_S_Exists,
+      FSL_Full => FSL_Full,
+      FSL_Has_Data => FSL_Has_Data,
+      FSL_Control_IRQ => FSL_Control_IRQ
+    );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_12_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_12_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e03f5e272aac276d07cd86fd76c790da072c06fa
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_12_ip_wrapper.vhd
@@ -0,0 +1,99 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_ed_12_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_altera_fifo_1_lib;
+use compaandesign_com_altera_fifo_1_lib.all;
+
+entity bunny_static_split2rtl_ed_12_ip_wrapper is
+  port (
+    FSL_Clk : in std_logic;
+    SYS_Rst : in std_logic;
+    FSL_Rst : out std_logic;
+    FSL_M_Clk : in std_logic;
+    FSL_M_Data : in std_logic_vector(0 to 7);
+    FSL_M_Control : in std_logic;
+    FSL_M_Write : in std_logic;
+    FSL_M_Full : out std_logic;
+    FSL_S_Clk : in std_logic;
+    FSL_S_Data : out std_logic_vector(0 to 7);
+    FSL_S_Control : out std_logic;
+    FSL_S_Read : in std_logic;
+    FSL_S_Exists : out std_logic;
+    FSL_Full : out std_logic;
+    FSL_Has_Data : out std_logic;
+    FSL_Control_IRQ : out std_logic
+  );
+
+
+end bunny_static_split2rtl_ed_12_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_ed_12_ip_wrapper is
+
+  component fsl_v20 is
+	generic (
+		C_EXT_RESET_HIGH : INTEGER := 1;
+		C_ASYNC_CLKS : INTEGER := 0;
+		C_IMPL_STYLE : INTEGER := 0;
+		C_USE_CONTROL : INTEGER := 1;
+		C_FSL_DWIDTH : INTEGER := 32;
+		C_FSL_DEPTH : INTEGER := 16;
+		C_READ_CLOCK_PERIOD : INTEGER := 0
+	);
+    port (
+      FSL_Clk 	: in  std_logic;
+      SYS_Rst 	: in  std_logic;
+      FSL_Rst 	: out std_logic;
+      FSL_M_Clk 	: in  std_logic;
+      FSL_M_Data 	: in  std_logic_vector(0 to 7);
+      FSL_M_Control: in  std_logic;
+      FSL_M_Write 	: in  std_logic;
+      FSL_M_Full 	: out std_logic;
+      FSL_S_Clk 	: in  std_logic;
+      FSL_S_Data 	: out std_logic_vector(0 to 7);
+      FSL_S_Control: out std_logic;
+      FSL_S_Read 	: in  std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full 	: out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+begin
+
+  bunny_static_split2rtl_ed_12 : fsl_v20
+	generic map (
+		C_EXT_RESET_HIGH => 1,
+		C_ASYNC_CLKS => 0,
+		C_IMPL_STYLE => 0,
+		C_USE_CONTROL => 1,
+		C_FSL_DWIDTH => 8,
+		C_FSL_DEPTH => 1024,
+		C_READ_CLOCK_PERIOD => 0
+	)
+    port map (
+      FSL_Clk => FSL_Clk,
+      SYS_Rst => SYS_Rst,
+      FSL_Rst => FSL_Rst,
+      FSL_M_Clk => FSL_M_Clk,
+      FSL_M_Data => FSL_M_Data,
+      FSL_M_Control => FSL_M_Control,
+      FSL_M_Write => FSL_M_Write,
+      FSL_M_Full => FSL_M_Full,
+      FSL_S_Clk => FSL_S_Clk,
+      FSL_S_Data => FSL_S_Data,
+      FSL_S_Control => FSL_S_Control,
+      FSL_S_Read => FSL_S_Read,
+      FSL_S_Exists => FSL_S_Exists,
+      FSL_Full => FSL_Full,
+      FSL_Has_Data => FSL_Has_Data,
+      FSL_Control_IRQ => FSL_Control_IRQ
+    );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_13_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_13_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0d7f529402ffb9e139843087d4953ef9c22f9364
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_13_ip_wrapper.vhd
@@ -0,0 +1,99 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_ed_13_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_altera_fifo_1_lib;
+use compaandesign_com_altera_fifo_1_lib.all;
+
+entity bunny_static_split2rtl_ed_13_ip_wrapper is
+  port (
+    FSL_Clk : in std_logic;
+    SYS_Rst : in std_logic;
+    FSL_Rst : out std_logic;
+    FSL_M_Clk : in std_logic;
+    FSL_M_Data : in std_logic_vector(0 to 7);
+    FSL_M_Control : in std_logic;
+    FSL_M_Write : in std_logic;
+    FSL_M_Full : out std_logic;
+    FSL_S_Clk : in std_logic;
+    FSL_S_Data : out std_logic_vector(0 to 7);
+    FSL_S_Control : out std_logic;
+    FSL_S_Read : in std_logic;
+    FSL_S_Exists : out std_logic;
+    FSL_Full : out std_logic;
+    FSL_Has_Data : out std_logic;
+    FSL_Control_IRQ : out std_logic
+  );
+
+
+end bunny_static_split2rtl_ed_13_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_ed_13_ip_wrapper is
+
+  component fsl_v20 is
+	generic (
+		C_EXT_RESET_HIGH : INTEGER := 1;
+		C_ASYNC_CLKS : INTEGER := 0;
+		C_IMPL_STYLE : INTEGER := 0;
+		C_USE_CONTROL : INTEGER := 1;
+		C_FSL_DWIDTH : INTEGER := 32;
+		C_FSL_DEPTH : INTEGER := 16;
+		C_READ_CLOCK_PERIOD : INTEGER := 0
+	);
+    port (
+      FSL_Clk 	: in  std_logic;
+      SYS_Rst 	: in  std_logic;
+      FSL_Rst 	: out std_logic;
+      FSL_M_Clk 	: in  std_logic;
+      FSL_M_Data 	: in  std_logic_vector(0 to 7);
+      FSL_M_Control: in  std_logic;
+      FSL_M_Write 	: in  std_logic;
+      FSL_M_Full 	: out std_logic;
+      FSL_S_Clk 	: in  std_logic;
+      FSL_S_Data 	: out std_logic_vector(0 to 7);
+      FSL_S_Control: out std_logic;
+      FSL_S_Read 	: in  std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full 	: out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+begin
+
+  bunny_static_split2rtl_ed_13 : fsl_v20
+	generic map (
+		C_EXT_RESET_HIGH => 1,
+		C_ASYNC_CLKS => 0,
+		C_IMPL_STYLE => 0,
+		C_USE_CONTROL => 1,
+		C_FSL_DWIDTH => 8,
+		C_FSL_DEPTH => 1024,
+		C_READ_CLOCK_PERIOD => 0
+	)
+    port map (
+      FSL_Clk => FSL_Clk,
+      SYS_Rst => SYS_Rst,
+      FSL_Rst => FSL_Rst,
+      FSL_M_Clk => FSL_M_Clk,
+      FSL_M_Data => FSL_M_Data,
+      FSL_M_Control => FSL_M_Control,
+      FSL_M_Write => FSL_M_Write,
+      FSL_M_Full => FSL_M_Full,
+      FSL_S_Clk => FSL_S_Clk,
+      FSL_S_Data => FSL_S_Data,
+      FSL_S_Control => FSL_S_Control,
+      FSL_S_Read => FSL_S_Read,
+      FSL_S_Exists => FSL_S_Exists,
+      FSL_Full => FSL_Full,
+      FSL_Has_Data => FSL_Has_Data,
+      FSL_Control_IRQ => FSL_Control_IRQ
+    );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_14_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_14_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2639264ad12e82eb38126212c41ab83bf8e0bddc
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_14_ip_wrapper.vhd
@@ -0,0 +1,99 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_ed_14_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_altera_fifo_1_lib;
+use compaandesign_com_altera_fifo_1_lib.all;
+
+entity bunny_static_split2rtl_ed_14_ip_wrapper is
+  port (
+    FSL_Clk : in std_logic;
+    SYS_Rst : in std_logic;
+    FSL_Rst : out std_logic;
+    FSL_M_Clk : in std_logic;
+    FSL_M_Data : in std_logic_vector(0 to 7);
+    FSL_M_Control : in std_logic;
+    FSL_M_Write : in std_logic;
+    FSL_M_Full : out std_logic;
+    FSL_S_Clk : in std_logic;
+    FSL_S_Data : out std_logic_vector(0 to 7);
+    FSL_S_Control : out std_logic;
+    FSL_S_Read : in std_logic;
+    FSL_S_Exists : out std_logic;
+    FSL_Full : out std_logic;
+    FSL_Has_Data : out std_logic;
+    FSL_Control_IRQ : out std_logic
+  );
+
+
+end bunny_static_split2rtl_ed_14_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_ed_14_ip_wrapper is
+
+  component fsl_v20 is
+	generic (
+		C_EXT_RESET_HIGH : INTEGER := 1;
+		C_ASYNC_CLKS : INTEGER := 0;
+		C_IMPL_STYLE : INTEGER := 0;
+		C_USE_CONTROL : INTEGER := 1;
+		C_FSL_DWIDTH : INTEGER := 32;
+		C_FSL_DEPTH : INTEGER := 16;
+		C_READ_CLOCK_PERIOD : INTEGER := 0
+	);
+    port (
+      FSL_Clk 	: in  std_logic;
+      SYS_Rst 	: in  std_logic;
+      FSL_Rst 	: out std_logic;
+      FSL_M_Clk 	: in  std_logic;
+      FSL_M_Data 	: in  std_logic_vector(0 to 7);
+      FSL_M_Control: in  std_logic;
+      FSL_M_Write 	: in  std_logic;
+      FSL_M_Full 	: out std_logic;
+      FSL_S_Clk 	: in  std_logic;
+      FSL_S_Data 	: out std_logic_vector(0 to 7);
+      FSL_S_Control: out std_logic;
+      FSL_S_Read 	: in  std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full 	: out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+begin
+
+  bunny_static_split2rtl_ed_14 : fsl_v20
+	generic map (
+		C_EXT_RESET_HIGH => 1,
+		C_ASYNC_CLKS => 0,
+		C_IMPL_STYLE => 0,
+		C_USE_CONTROL => 1,
+		C_FSL_DWIDTH => 8,
+		C_FSL_DEPTH => 16,
+		C_READ_CLOCK_PERIOD => 0
+	)
+    port map (
+      FSL_Clk => FSL_Clk,
+      SYS_Rst => SYS_Rst,
+      FSL_Rst => FSL_Rst,
+      FSL_M_Clk => FSL_M_Clk,
+      FSL_M_Data => FSL_M_Data,
+      FSL_M_Control => FSL_M_Control,
+      FSL_M_Write => FSL_M_Write,
+      FSL_M_Full => FSL_M_Full,
+      FSL_S_Clk => FSL_S_Clk,
+      FSL_S_Data => FSL_S_Data,
+      FSL_S_Control => FSL_S_Control,
+      FSL_S_Read => FSL_S_Read,
+      FSL_S_Exists => FSL_S_Exists,
+      FSL_Full => FSL_Full,
+      FSL_Has_Data => FSL_Has_Data,
+      FSL_Control_IRQ => FSL_Control_IRQ
+    );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_15_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_15_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0e85cfd21e8677ea01d2cae914537a3ee79ba2f8
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_15_ip_wrapper.vhd
@@ -0,0 +1,99 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_ed_15_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_altera_fifo_1_lib;
+use compaandesign_com_altera_fifo_1_lib.all;
+
+entity bunny_static_split2rtl_ed_15_ip_wrapper is
+  port (
+    FSL_Clk : in std_logic;
+    SYS_Rst : in std_logic;
+    FSL_Rst : out std_logic;
+    FSL_M_Clk : in std_logic;
+    FSL_M_Data : in std_logic_vector(0 to 7);
+    FSL_M_Control : in std_logic;
+    FSL_M_Write : in std_logic;
+    FSL_M_Full : out std_logic;
+    FSL_S_Clk : in std_logic;
+    FSL_S_Data : out std_logic_vector(0 to 7);
+    FSL_S_Control : out std_logic;
+    FSL_S_Read : in std_logic;
+    FSL_S_Exists : out std_logic;
+    FSL_Full : out std_logic;
+    FSL_Has_Data : out std_logic;
+    FSL_Control_IRQ : out std_logic
+  );
+
+
+end bunny_static_split2rtl_ed_15_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_ed_15_ip_wrapper is
+
+  component fsl_v20 is
+	generic (
+		C_EXT_RESET_HIGH : INTEGER := 1;
+		C_ASYNC_CLKS : INTEGER := 0;
+		C_IMPL_STYLE : INTEGER := 0;
+		C_USE_CONTROL : INTEGER := 1;
+		C_FSL_DWIDTH : INTEGER := 32;
+		C_FSL_DEPTH : INTEGER := 16;
+		C_READ_CLOCK_PERIOD : INTEGER := 0
+	);
+    port (
+      FSL_Clk 	: in  std_logic;
+      SYS_Rst 	: in  std_logic;
+      FSL_Rst 	: out std_logic;
+      FSL_M_Clk 	: in  std_logic;
+      FSL_M_Data 	: in  std_logic_vector(0 to 7);
+      FSL_M_Control: in  std_logic;
+      FSL_M_Write 	: in  std_logic;
+      FSL_M_Full 	: out std_logic;
+      FSL_S_Clk 	: in  std_logic;
+      FSL_S_Data 	: out std_logic_vector(0 to 7);
+      FSL_S_Control: out std_logic;
+      FSL_S_Read 	: in  std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full 	: out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+begin
+
+  bunny_static_split2rtl_ed_15 : fsl_v20
+	generic map (
+		C_EXT_RESET_HIGH => 1,
+		C_ASYNC_CLKS => 0,
+		C_IMPL_STYLE => 0,
+		C_USE_CONTROL => 1,
+		C_FSL_DWIDTH => 8,
+		C_FSL_DEPTH => 16,
+		C_READ_CLOCK_PERIOD => 0
+	)
+    port map (
+      FSL_Clk => FSL_Clk,
+      SYS_Rst => SYS_Rst,
+      FSL_Rst => FSL_Rst,
+      FSL_M_Clk => FSL_M_Clk,
+      FSL_M_Data => FSL_M_Data,
+      FSL_M_Control => FSL_M_Control,
+      FSL_M_Write => FSL_M_Write,
+      FSL_M_Full => FSL_M_Full,
+      FSL_S_Clk => FSL_S_Clk,
+      FSL_S_Data => FSL_S_Data,
+      FSL_S_Control => FSL_S_Control,
+      FSL_S_Read => FSL_S_Read,
+      FSL_S_Exists => FSL_S_Exists,
+      FSL_Full => FSL_Full,
+      FSL_Has_Data => FSL_Has_Data,
+      FSL_Control_IRQ => FSL_Control_IRQ
+    );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_16_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_16_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..bbf996e5b558f340bf46078c2aa20454f6cd4623
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_16_ip_wrapper.vhd
@@ -0,0 +1,99 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_ed_16_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_common_wire_connector_1_lib;
+use compaandesign_com_common_wire_connector_1_lib.all;
+
+entity bunny_static_split2rtl_ed_16_ip_wrapper is
+  port (
+    FSL_Clk : in std_logic;
+    SYS_Rst : in std_logic;
+    FSL_Rst : out std_logic;
+    FSL_M_Clk : in std_logic;
+    FSL_M_Data : in std_logic_vector(0 to 7);
+    FSL_M_Control : in std_logic;
+    FSL_M_Write : in std_logic;
+    FSL_M_Full : out std_logic;
+    FSL_S_Clk : in std_logic;
+    FSL_S_Data : out std_logic_vector(0 to 7);
+    FSL_S_Control : out std_logic;
+    FSL_S_Read : in std_logic;
+    FSL_S_Exists : out std_logic;
+    FSL_Full : out std_logic;
+    FSL_Has_Data : out std_logic;
+    FSL_Control_IRQ : out std_logic
+  );
+
+
+end bunny_static_split2rtl_ed_16_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_ed_16_ip_wrapper is
+
+  component wire_connector is
+	generic (
+		C_EXT_RESET_HIGH : INTEGER := 1;
+		C_ASYNC_CLKS : INTEGER := 0;
+		C_IMPL_STYLE : INTEGER := 0;
+		C_USE_CONTROL : INTEGER := 1;
+		C_FSL_DWIDTH : INTEGER := 32;
+		C_FSL_DEPTH : INTEGER := 16;
+		C_READ_CLOCK_PERIOD : INTEGER := 0
+	);
+    port (
+      FSL_Clk 	: in  std_logic;
+      SYS_Rst 	: in  std_logic;
+      FSL_Rst 	: out std_logic;
+      FSL_M_Clk 	: in  std_logic;
+      FSL_M_Data 	: in  std_logic_vector(0 to 7);
+      FSL_M_Control: in  std_logic;
+      FSL_M_Write 	: in  std_logic;
+      FSL_M_Full 	: out std_logic;
+      FSL_S_Clk 	: in  std_logic;
+      FSL_S_Data 	: out std_logic_vector(0 to 7);
+      FSL_S_Control: out std_logic;
+      FSL_S_Read 	: in  std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full 	: out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+begin
+
+  bunny_static_split2rtl_ed_16 : wire_connector
+	generic map (
+		C_EXT_RESET_HIGH => 1,
+		C_ASYNC_CLKS => 0,
+		C_IMPL_STYLE => 0,
+		C_USE_CONTROL => 1,
+		C_FSL_DWIDTH => 8,
+		C_FSL_DEPTH => 16,
+		C_READ_CLOCK_PERIOD => 0
+	)
+    port map (
+      FSL_Clk => FSL_Clk,
+      SYS_Rst => SYS_Rst,
+      FSL_Rst => FSL_Rst,
+      FSL_M_Clk => FSL_M_Clk,
+      FSL_M_Data => FSL_M_Data,
+      FSL_M_Control => FSL_M_Control,
+      FSL_M_Write => FSL_M_Write,
+      FSL_M_Full => FSL_M_Full,
+      FSL_S_Clk => FSL_S_Clk,
+      FSL_S_Data => FSL_S_Data,
+      FSL_S_Control => FSL_S_Control,
+      FSL_S_Read => FSL_S_Read,
+      FSL_S_Exists => FSL_S_Exists,
+      FSL_Full => FSL_Full,
+      FSL_Has_Data => FSL_Has_Data,
+      FSL_Control_IRQ => FSL_Control_IRQ
+    );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_17_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_17_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5f320effd066994a0981b305865f7c7b18a55b57
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_17_ip_wrapper.vhd
@@ -0,0 +1,99 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_ed_17_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_altera_fifo_1_lib;
+use compaandesign_com_altera_fifo_1_lib.all;
+
+entity bunny_static_split2rtl_ed_17_ip_wrapper is
+  port (
+    FSL_Clk : in std_logic;
+    SYS_Rst : in std_logic;
+    FSL_Rst : out std_logic;
+    FSL_M_Clk : in std_logic;
+    FSL_M_Data : in std_logic_vector(0 to 31);
+    FSL_M_Control : in std_logic;
+    FSL_M_Write : in std_logic;
+    FSL_M_Full : out std_logic;
+    FSL_S_Clk : in std_logic;
+    FSL_S_Data : out std_logic_vector(0 to 31);
+    FSL_S_Control : out std_logic;
+    FSL_S_Read : in std_logic;
+    FSL_S_Exists : out std_logic;
+    FSL_Full : out std_logic;
+    FSL_Has_Data : out std_logic;
+    FSL_Control_IRQ : out std_logic
+  );
+
+
+end bunny_static_split2rtl_ed_17_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_ed_17_ip_wrapper is
+
+  component fsl_v20 is
+	generic (
+		C_EXT_RESET_HIGH : INTEGER := 1;
+		C_ASYNC_CLKS : INTEGER := 0;
+		C_IMPL_STYLE : INTEGER := 0;
+		C_USE_CONTROL : INTEGER := 1;
+		C_FSL_DWIDTH : INTEGER := 32;
+		C_FSL_DEPTH : INTEGER := 16;
+		C_READ_CLOCK_PERIOD : INTEGER := 0
+	);
+    port (
+      FSL_Clk 	: in  std_logic;
+      SYS_Rst 	: in  std_logic;
+      FSL_Rst 	: out std_logic;
+      FSL_M_Clk 	: in  std_logic;
+      FSL_M_Data 	: in  std_logic_vector(0 to 31);
+      FSL_M_Control: in  std_logic;
+      FSL_M_Write 	: in  std_logic;
+      FSL_M_Full 	: out std_logic;
+      FSL_S_Clk 	: in  std_logic;
+      FSL_S_Data 	: out std_logic_vector(0 to 31);
+      FSL_S_Control: out std_logic;
+      FSL_S_Read 	: in  std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full 	: out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+begin
+
+  bunny_static_split2rtl_ed_17 : fsl_v20
+	generic map (
+		C_EXT_RESET_HIGH => 1,
+		C_ASYNC_CLKS => 0,
+		C_IMPL_STYLE => 0,
+		C_USE_CONTROL => 1,
+		C_FSL_DWIDTH => 32,
+		C_FSL_DEPTH => 16,
+		C_READ_CLOCK_PERIOD => 0
+	)
+    port map (
+      FSL_Clk => FSL_Clk,
+      SYS_Rst => SYS_Rst,
+      FSL_Rst => FSL_Rst,
+      FSL_M_Clk => FSL_M_Clk,
+      FSL_M_Data => FSL_M_Data,
+      FSL_M_Control => FSL_M_Control,
+      FSL_M_Write => FSL_M_Write,
+      FSL_M_Full => FSL_M_Full,
+      FSL_S_Clk => FSL_S_Clk,
+      FSL_S_Data => FSL_S_Data,
+      FSL_S_Control => FSL_S_Control,
+      FSL_S_Read => FSL_S_Read,
+      FSL_S_Exists => FSL_S_Exists,
+      FSL_Full => FSL_Full,
+      FSL_Has_Data => FSL_Has_Data,
+      FSL_Control_IRQ => FSL_Control_IRQ
+    );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_18_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_18_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..115823ccbf99372f064e6893d8677b4fba918198
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_18_ip_wrapper.vhd
@@ -0,0 +1,99 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_ed_18_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_altera_fifo_1_lib;
+use compaandesign_com_altera_fifo_1_lib.all;
+
+entity bunny_static_split2rtl_ed_18_ip_wrapper is
+  port (
+    FSL_Clk : in std_logic;
+    SYS_Rst : in std_logic;
+    FSL_Rst : out std_logic;
+    FSL_M_Clk : in std_logic;
+    FSL_M_Data : in std_logic_vector(0 to 31);
+    FSL_M_Control : in std_logic;
+    FSL_M_Write : in std_logic;
+    FSL_M_Full : out std_logic;
+    FSL_S_Clk : in std_logic;
+    FSL_S_Data : out std_logic_vector(0 to 31);
+    FSL_S_Control : out std_logic;
+    FSL_S_Read : in std_logic;
+    FSL_S_Exists : out std_logic;
+    FSL_Full : out std_logic;
+    FSL_Has_Data : out std_logic;
+    FSL_Control_IRQ : out std_logic
+  );
+
+
+end bunny_static_split2rtl_ed_18_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_ed_18_ip_wrapper is
+
+  component fsl_v20 is
+	generic (
+		C_EXT_RESET_HIGH : INTEGER := 1;
+		C_ASYNC_CLKS : INTEGER := 0;
+		C_IMPL_STYLE : INTEGER := 0;
+		C_USE_CONTROL : INTEGER := 1;
+		C_FSL_DWIDTH : INTEGER := 32;
+		C_FSL_DEPTH : INTEGER := 16;
+		C_READ_CLOCK_PERIOD : INTEGER := 0
+	);
+    port (
+      FSL_Clk 	: in  std_logic;
+      SYS_Rst 	: in  std_logic;
+      FSL_Rst 	: out std_logic;
+      FSL_M_Clk 	: in  std_logic;
+      FSL_M_Data 	: in  std_logic_vector(0 to 31);
+      FSL_M_Control: in  std_logic;
+      FSL_M_Write 	: in  std_logic;
+      FSL_M_Full 	: out std_logic;
+      FSL_S_Clk 	: in  std_logic;
+      FSL_S_Data 	: out std_logic_vector(0 to 31);
+      FSL_S_Control: out std_logic;
+      FSL_S_Read 	: in  std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full 	: out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+begin
+
+  bunny_static_split2rtl_ed_18 : fsl_v20
+	generic map (
+		C_EXT_RESET_HIGH => 1,
+		C_ASYNC_CLKS => 0,
+		C_IMPL_STYLE => 0,
+		C_USE_CONTROL => 1,
+		C_FSL_DWIDTH => 32,
+		C_FSL_DEPTH => 16,
+		C_READ_CLOCK_PERIOD => 0
+	)
+    port map (
+      FSL_Clk => FSL_Clk,
+      SYS_Rst => SYS_Rst,
+      FSL_Rst => FSL_Rst,
+      FSL_M_Clk => FSL_M_Clk,
+      FSL_M_Data => FSL_M_Data,
+      FSL_M_Control => FSL_M_Control,
+      FSL_M_Write => FSL_M_Write,
+      FSL_M_Full => FSL_M_Full,
+      FSL_S_Clk => FSL_S_Clk,
+      FSL_S_Data => FSL_S_Data,
+      FSL_S_Control => FSL_S_Control,
+      FSL_S_Read => FSL_S_Read,
+      FSL_S_Exists => FSL_S_Exists,
+      FSL_Full => FSL_Full,
+      FSL_Has_Data => FSL_Has_Data,
+      FSL_Control_IRQ => FSL_Control_IRQ
+    );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_19_20_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_19_20_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..27e4681e26519750595404259a3f71bfcb437014
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_19_20_ip_wrapper.vhd
@@ -0,0 +1,99 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_ed_19_20_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_altera_fifo_1_lib;
+use compaandesign_com_altera_fifo_1_lib.all;
+
+entity bunny_static_split2rtl_ed_19_20_ip_wrapper is
+  port (
+    FSL_Clk : in std_logic;
+    SYS_Rst : in std_logic;
+    FSL_Rst : out std_logic;
+    FSL_M_Clk : in std_logic;
+    FSL_M_Data : in std_logic_vector(0 to 63);
+    FSL_M_Control : in std_logic;
+    FSL_M_Write : in std_logic;
+    FSL_M_Full : out std_logic;
+    FSL_S_Clk : in std_logic;
+    FSL_S_Data : out std_logic_vector(0 to 63);
+    FSL_S_Control : out std_logic;
+    FSL_S_Read : in std_logic;
+    FSL_S_Exists : out std_logic;
+    FSL_Full : out std_logic;
+    FSL_Has_Data : out std_logic;
+    FSL_Control_IRQ : out std_logic
+  );
+
+
+end bunny_static_split2rtl_ed_19_20_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_ed_19_20_ip_wrapper is
+
+  component fsl_v20 is
+	generic (
+		C_EXT_RESET_HIGH : INTEGER := 1;
+		C_ASYNC_CLKS : INTEGER := 0;
+		C_IMPL_STYLE : INTEGER := 0;
+		C_USE_CONTROL : INTEGER := 1;
+		C_FSL_DWIDTH : INTEGER := 32;
+		C_FSL_DEPTH : INTEGER := 16;
+		C_READ_CLOCK_PERIOD : INTEGER := 0
+	);
+    port (
+      FSL_Clk 	: in  std_logic;
+      SYS_Rst 	: in  std_logic;
+      FSL_Rst 	: out std_logic;
+      FSL_M_Clk 	: in  std_logic;
+      FSL_M_Data 	: in  std_logic_vector(0 to 63);
+      FSL_M_Control: in  std_logic;
+      FSL_M_Write 	: in  std_logic;
+      FSL_M_Full 	: out std_logic;
+      FSL_S_Clk 	: in  std_logic;
+      FSL_S_Data 	: out std_logic_vector(0 to 63);
+      FSL_S_Control: out std_logic;
+      FSL_S_Read 	: in  std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full 	: out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+begin
+
+  bunny_static_split2rtl_ed_19_20 : fsl_v20
+	generic map (
+		C_EXT_RESET_HIGH => 1,
+		C_ASYNC_CLKS => 0,
+		C_IMPL_STYLE => 0,
+		C_USE_CONTROL => 1,
+		C_FSL_DWIDTH => 64,
+		C_FSL_DEPTH => 16,
+		C_READ_CLOCK_PERIOD => 0
+	)
+    port map (
+      FSL_Clk => FSL_Clk,
+      SYS_Rst => SYS_Rst,
+      FSL_Rst => FSL_Rst,
+      FSL_M_Clk => FSL_M_Clk,
+      FSL_M_Data => FSL_M_Data,
+      FSL_M_Control => FSL_M_Control,
+      FSL_M_Write => FSL_M_Write,
+      FSL_M_Full => FSL_M_Full,
+      FSL_S_Clk => FSL_S_Clk,
+      FSL_S_Data => FSL_S_Data,
+      FSL_S_Control => FSL_S_Control,
+      FSL_S_Read => FSL_S_Read,
+      FSL_S_Exists => FSL_S_Exists,
+      FSL_Full => FSL_Full,
+      FSL_Has_Data => FSL_Has_Data,
+      FSL_Control_IRQ => FSL_Control_IRQ
+    );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_1_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_1_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..936e95f153d7c8a550dc6eab87ccf15f00adc692
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_1_ip_wrapper.vhd
@@ -0,0 +1,99 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_ed_1_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_altera_fifo_1_lib;
+use compaandesign_com_altera_fifo_1_lib.all;
+
+entity bunny_static_split2rtl_ed_1_ip_wrapper is
+  port (
+    FSL_Clk : in std_logic;
+    SYS_Rst : in std_logic;
+    FSL_Rst : out std_logic;
+    FSL_M_Clk : in std_logic;
+    FSL_M_Data : in std_logic_vector(0 to 63);
+    FSL_M_Control : in std_logic;
+    FSL_M_Write : in std_logic;
+    FSL_M_Full : out std_logic;
+    FSL_S_Clk : in std_logic;
+    FSL_S_Data : out std_logic_vector(0 to 63);
+    FSL_S_Control : out std_logic;
+    FSL_S_Read : in std_logic;
+    FSL_S_Exists : out std_logic;
+    FSL_Full : out std_logic;
+    FSL_Has_Data : out std_logic;
+    FSL_Control_IRQ : out std_logic
+  );
+
+
+end bunny_static_split2rtl_ed_1_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_ed_1_ip_wrapper is
+
+  component fsl_v20 is
+	generic (
+		C_EXT_RESET_HIGH : INTEGER := 1;
+		C_ASYNC_CLKS : INTEGER := 0;
+		C_IMPL_STYLE : INTEGER := 0;
+		C_USE_CONTROL : INTEGER := 1;
+		C_FSL_DWIDTH : INTEGER := 32;
+		C_FSL_DEPTH : INTEGER := 16;
+		C_READ_CLOCK_PERIOD : INTEGER := 0
+	);
+    port (
+      FSL_Clk 	: in  std_logic;
+      SYS_Rst 	: in  std_logic;
+      FSL_Rst 	: out std_logic;
+      FSL_M_Clk 	: in  std_logic;
+      FSL_M_Data 	: in  std_logic_vector(0 to 63);
+      FSL_M_Control: in  std_logic;
+      FSL_M_Write 	: in  std_logic;
+      FSL_M_Full 	: out std_logic;
+      FSL_S_Clk 	: in  std_logic;
+      FSL_S_Data 	: out std_logic_vector(0 to 63);
+      FSL_S_Control: out std_logic;
+      FSL_S_Read 	: in  std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full 	: out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+begin
+
+  bunny_static_split2rtl_ed_1 : fsl_v20
+	generic map (
+		C_EXT_RESET_HIGH => 1,
+		C_ASYNC_CLKS => 0,
+		C_IMPL_STYLE => 0,
+		C_USE_CONTROL => 1,
+		C_FSL_DWIDTH => 64,
+		C_FSL_DEPTH => 16,
+		C_READ_CLOCK_PERIOD => 0
+	)
+    port map (
+      FSL_Clk => FSL_Clk,
+      SYS_Rst => SYS_Rst,
+      FSL_Rst => FSL_Rst,
+      FSL_M_Clk => FSL_M_Clk,
+      FSL_M_Data => FSL_M_Data,
+      FSL_M_Control => FSL_M_Control,
+      FSL_M_Write => FSL_M_Write,
+      FSL_M_Full => FSL_M_Full,
+      FSL_S_Clk => FSL_S_Clk,
+      FSL_S_Data => FSL_S_Data,
+      FSL_S_Control => FSL_S_Control,
+      FSL_S_Read => FSL_S_Read,
+      FSL_S_Exists => FSL_S_Exists,
+      FSL_Full => FSL_Full,
+      FSL_Has_Data => FSL_Has_Data,
+      FSL_Control_IRQ => FSL_Control_IRQ
+    );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_21_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_21_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..cbf23e64c51cb6e14804fba879052da1a2adfb0b
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_21_ip_wrapper.vhd
@@ -0,0 +1,99 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_ed_21_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_common_wire_connector_1_lib;
+use compaandesign_com_common_wire_connector_1_lib.all;
+
+entity bunny_static_split2rtl_ed_21_ip_wrapper is
+  port (
+    FSL_Clk : in std_logic;
+    SYS_Rst : in std_logic;
+    FSL_Rst : out std_logic;
+    FSL_M_Clk : in std_logic;
+    FSL_M_Data : in std_logic_vector(0 to 63);
+    FSL_M_Control : in std_logic;
+    FSL_M_Write : in std_logic;
+    FSL_M_Full : out std_logic;
+    FSL_S_Clk : in std_logic;
+    FSL_S_Data : out std_logic_vector(0 to 63);
+    FSL_S_Control : out std_logic;
+    FSL_S_Read : in std_logic;
+    FSL_S_Exists : out std_logic;
+    FSL_Full : out std_logic;
+    FSL_Has_Data : out std_logic;
+    FSL_Control_IRQ : out std_logic
+  );
+
+
+end bunny_static_split2rtl_ed_21_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_ed_21_ip_wrapper is
+
+  component wire_connector is
+	generic (
+		C_EXT_RESET_HIGH : INTEGER := 1;
+		C_ASYNC_CLKS : INTEGER := 0;
+		C_IMPL_STYLE : INTEGER := 0;
+		C_USE_CONTROL : INTEGER := 1;
+		C_FSL_DWIDTH : INTEGER := 32;
+		C_FSL_DEPTH : INTEGER := 16;
+		C_READ_CLOCK_PERIOD : INTEGER := 0
+	);
+    port (
+      FSL_Clk 	: in  std_logic;
+      SYS_Rst 	: in  std_logic;
+      FSL_Rst 	: out std_logic;
+      FSL_M_Clk 	: in  std_logic;
+      FSL_M_Data 	: in  std_logic_vector(0 to 63);
+      FSL_M_Control: in  std_logic;
+      FSL_M_Write 	: in  std_logic;
+      FSL_M_Full 	: out std_logic;
+      FSL_S_Clk 	: in  std_logic;
+      FSL_S_Data 	: out std_logic_vector(0 to 63);
+      FSL_S_Control: out std_logic;
+      FSL_S_Read 	: in  std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full 	: out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+begin
+
+  bunny_static_split2rtl_ed_21 : wire_connector
+	generic map (
+		C_EXT_RESET_HIGH => 1,
+		C_ASYNC_CLKS => 0,
+		C_IMPL_STYLE => 0,
+		C_USE_CONTROL => 1,
+		C_FSL_DWIDTH => 64,
+		C_FSL_DEPTH => 16,
+		C_READ_CLOCK_PERIOD => 0
+	)
+    port map (
+      FSL_Clk => FSL_Clk,
+      SYS_Rst => SYS_Rst,
+      FSL_Rst => FSL_Rst,
+      FSL_M_Clk => FSL_M_Clk,
+      FSL_M_Data => FSL_M_Data,
+      FSL_M_Control => FSL_M_Control,
+      FSL_M_Write => FSL_M_Write,
+      FSL_M_Full => FSL_M_Full,
+      FSL_S_Clk => FSL_S_Clk,
+      FSL_S_Data => FSL_S_Data,
+      FSL_S_Control => FSL_S_Control,
+      FSL_S_Read => FSL_S_Read,
+      FSL_S_Exists => FSL_S_Exists,
+      FSL_Full => FSL_Full,
+      FSL_Has_Data => FSL_Has_Data,
+      FSL_Control_IRQ => FSL_Control_IRQ
+    );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_2_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_2_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f02b993d82d63a66effea1ee09e6b7c40f9e2a38
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_2_ip_wrapper.vhd
@@ -0,0 +1,99 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_ed_2_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_altera_fifo_1_lib;
+use compaandesign_com_altera_fifo_1_lib.all;
+
+entity bunny_static_split2rtl_ed_2_ip_wrapper is
+  port (
+    FSL_Clk : in std_logic;
+    SYS_Rst : in std_logic;
+    FSL_Rst : out std_logic;
+    FSL_M_Clk : in std_logic;
+    FSL_M_Data : in std_logic_vector(0 to 63);
+    FSL_M_Control : in std_logic;
+    FSL_M_Write : in std_logic;
+    FSL_M_Full : out std_logic;
+    FSL_S_Clk : in std_logic;
+    FSL_S_Data : out std_logic_vector(0 to 63);
+    FSL_S_Control : out std_logic;
+    FSL_S_Read : in std_logic;
+    FSL_S_Exists : out std_logic;
+    FSL_Full : out std_logic;
+    FSL_Has_Data : out std_logic;
+    FSL_Control_IRQ : out std_logic
+  );
+
+
+end bunny_static_split2rtl_ed_2_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_ed_2_ip_wrapper is
+
+  component fsl_v20 is
+	generic (
+		C_EXT_RESET_HIGH : INTEGER := 1;
+		C_ASYNC_CLKS : INTEGER := 0;
+		C_IMPL_STYLE : INTEGER := 0;
+		C_USE_CONTROL : INTEGER := 1;
+		C_FSL_DWIDTH : INTEGER := 32;
+		C_FSL_DEPTH : INTEGER := 16;
+		C_READ_CLOCK_PERIOD : INTEGER := 0
+	);
+    port (
+      FSL_Clk 	: in  std_logic;
+      SYS_Rst 	: in  std_logic;
+      FSL_Rst 	: out std_logic;
+      FSL_M_Clk 	: in  std_logic;
+      FSL_M_Data 	: in  std_logic_vector(0 to 63);
+      FSL_M_Control: in  std_logic;
+      FSL_M_Write 	: in  std_logic;
+      FSL_M_Full 	: out std_logic;
+      FSL_S_Clk 	: in  std_logic;
+      FSL_S_Data 	: out std_logic_vector(0 to 63);
+      FSL_S_Control: out std_logic;
+      FSL_S_Read 	: in  std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full 	: out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+begin
+
+  bunny_static_split2rtl_ed_2 : fsl_v20
+	generic map (
+		C_EXT_RESET_HIGH => 1,
+		C_ASYNC_CLKS => 0,
+		C_IMPL_STYLE => 0,
+		C_USE_CONTROL => 1,
+		C_FSL_DWIDTH => 64,
+		C_FSL_DEPTH => 16,
+		C_READ_CLOCK_PERIOD => 0
+	)
+    port map (
+      FSL_Clk => FSL_Clk,
+      SYS_Rst => SYS_Rst,
+      FSL_Rst => FSL_Rst,
+      FSL_M_Clk => FSL_M_Clk,
+      FSL_M_Data => FSL_M_Data,
+      FSL_M_Control => FSL_M_Control,
+      FSL_M_Write => FSL_M_Write,
+      FSL_M_Full => FSL_M_Full,
+      FSL_S_Clk => FSL_S_Clk,
+      FSL_S_Data => FSL_S_Data,
+      FSL_S_Control => FSL_S_Control,
+      FSL_S_Read => FSL_S_Read,
+      FSL_S_Exists => FSL_S_Exists,
+      FSL_Full => FSL_Full,
+      FSL_Has_Data => FSL_Has_Data,
+      FSL_Control_IRQ => FSL_Control_IRQ
+    );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_3_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_3_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e099a9bfed50958755fbbea2be470f2d3bbd8f6a
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_3_ip_wrapper.vhd
@@ -0,0 +1,99 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_ed_3_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_altera_fifo_1_lib;
+use compaandesign_com_altera_fifo_1_lib.all;
+
+entity bunny_static_split2rtl_ed_3_ip_wrapper is
+  port (
+    FSL_Clk : in std_logic;
+    SYS_Rst : in std_logic;
+    FSL_Rst : out std_logic;
+    FSL_M_Clk : in std_logic;
+    FSL_M_Data : in std_logic_vector(0 to 31);
+    FSL_M_Control : in std_logic;
+    FSL_M_Write : in std_logic;
+    FSL_M_Full : out std_logic;
+    FSL_S_Clk : in std_logic;
+    FSL_S_Data : out std_logic_vector(0 to 31);
+    FSL_S_Control : out std_logic;
+    FSL_S_Read : in std_logic;
+    FSL_S_Exists : out std_logic;
+    FSL_Full : out std_logic;
+    FSL_Has_Data : out std_logic;
+    FSL_Control_IRQ : out std_logic
+  );
+
+
+end bunny_static_split2rtl_ed_3_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_ed_3_ip_wrapper is
+
+  component fsl_v20 is
+	generic (
+		C_EXT_RESET_HIGH : INTEGER := 1;
+		C_ASYNC_CLKS : INTEGER := 0;
+		C_IMPL_STYLE : INTEGER := 0;
+		C_USE_CONTROL : INTEGER := 1;
+		C_FSL_DWIDTH : INTEGER := 32;
+		C_FSL_DEPTH : INTEGER := 16;
+		C_READ_CLOCK_PERIOD : INTEGER := 0
+	);
+    port (
+      FSL_Clk 	: in  std_logic;
+      SYS_Rst 	: in  std_logic;
+      FSL_Rst 	: out std_logic;
+      FSL_M_Clk 	: in  std_logic;
+      FSL_M_Data 	: in  std_logic_vector(0 to 31);
+      FSL_M_Control: in  std_logic;
+      FSL_M_Write 	: in  std_logic;
+      FSL_M_Full 	: out std_logic;
+      FSL_S_Clk 	: in  std_logic;
+      FSL_S_Data 	: out std_logic_vector(0 to 31);
+      FSL_S_Control: out std_logic;
+      FSL_S_Read 	: in  std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full 	: out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+begin
+
+  bunny_static_split2rtl_ed_3 : fsl_v20
+	generic map (
+		C_EXT_RESET_HIGH => 1,
+		C_ASYNC_CLKS => 0,
+		C_IMPL_STYLE => 0,
+		C_USE_CONTROL => 1,
+		C_FSL_DWIDTH => 32,
+		C_FSL_DEPTH => 16,
+		C_READ_CLOCK_PERIOD => 0
+	)
+    port map (
+      FSL_Clk => FSL_Clk,
+      SYS_Rst => SYS_Rst,
+      FSL_Rst => FSL_Rst,
+      FSL_M_Clk => FSL_M_Clk,
+      FSL_M_Data => FSL_M_Data,
+      FSL_M_Control => FSL_M_Control,
+      FSL_M_Write => FSL_M_Write,
+      FSL_M_Full => FSL_M_Full,
+      FSL_S_Clk => FSL_S_Clk,
+      FSL_S_Data => FSL_S_Data,
+      FSL_S_Control => FSL_S_Control,
+      FSL_S_Read => FSL_S_Read,
+      FSL_S_Exists => FSL_S_Exists,
+      FSL_Full => FSL_Full,
+      FSL_Has_Data => FSL_Has_Data,
+      FSL_Control_IRQ => FSL_Control_IRQ
+    );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_4_5_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_4_5_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..45ed2265e6b4acdf10d215f22fbd4095d109ea94
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_4_5_ip_wrapper.vhd
@@ -0,0 +1,99 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_ed_4_5_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_altera_fifo_1_lib;
+use compaandesign_com_altera_fifo_1_lib.all;
+
+entity bunny_static_split2rtl_ed_4_5_ip_wrapper is
+  port (
+    FSL_Clk : in std_logic;
+    SYS_Rst : in std_logic;
+    FSL_Rst : out std_logic;
+    FSL_M_Clk : in std_logic;
+    FSL_M_Data : in std_logic_vector(0 to 31);
+    FSL_M_Control : in std_logic;
+    FSL_M_Write : in std_logic;
+    FSL_M_Full : out std_logic;
+    FSL_S_Clk : in std_logic;
+    FSL_S_Data : out std_logic_vector(0 to 31);
+    FSL_S_Control : out std_logic;
+    FSL_S_Read : in std_logic;
+    FSL_S_Exists : out std_logic;
+    FSL_Full : out std_logic;
+    FSL_Has_Data : out std_logic;
+    FSL_Control_IRQ : out std_logic
+  );
+
+
+end bunny_static_split2rtl_ed_4_5_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_ed_4_5_ip_wrapper is
+
+  component fsl_v20 is
+	generic (
+		C_EXT_RESET_HIGH : INTEGER := 1;
+		C_ASYNC_CLKS : INTEGER := 0;
+		C_IMPL_STYLE : INTEGER := 0;
+		C_USE_CONTROL : INTEGER := 1;
+		C_FSL_DWIDTH : INTEGER := 32;
+		C_FSL_DEPTH : INTEGER := 16;
+		C_READ_CLOCK_PERIOD : INTEGER := 0
+	);
+    port (
+      FSL_Clk 	: in  std_logic;
+      SYS_Rst 	: in  std_logic;
+      FSL_Rst 	: out std_logic;
+      FSL_M_Clk 	: in  std_logic;
+      FSL_M_Data 	: in  std_logic_vector(0 to 31);
+      FSL_M_Control: in  std_logic;
+      FSL_M_Write 	: in  std_logic;
+      FSL_M_Full 	: out std_logic;
+      FSL_S_Clk 	: in  std_logic;
+      FSL_S_Data 	: out std_logic_vector(0 to 31);
+      FSL_S_Control: out std_logic;
+      FSL_S_Read 	: in  std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full 	: out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+begin
+
+  bunny_static_split2rtl_ed_4_5 : fsl_v20
+	generic map (
+		C_EXT_RESET_HIGH => 1,
+		C_ASYNC_CLKS => 0,
+		C_IMPL_STYLE => 0,
+		C_USE_CONTROL => 1,
+		C_FSL_DWIDTH => 32,
+		C_FSL_DEPTH => 16,
+		C_READ_CLOCK_PERIOD => 0
+	)
+    port map (
+      FSL_Clk => FSL_Clk,
+      SYS_Rst => SYS_Rst,
+      FSL_Rst => FSL_Rst,
+      FSL_M_Clk => FSL_M_Clk,
+      FSL_M_Data => FSL_M_Data,
+      FSL_M_Control => FSL_M_Control,
+      FSL_M_Write => FSL_M_Write,
+      FSL_M_Full => FSL_M_Full,
+      FSL_S_Clk => FSL_S_Clk,
+      FSL_S_Data => FSL_S_Data,
+      FSL_S_Control => FSL_S_Control,
+      FSL_S_Read => FSL_S_Read,
+      FSL_S_Exists => FSL_S_Exists,
+      FSL_Full => FSL_Full,
+      FSL_Has_Data => FSL_Has_Data,
+      FSL_Control_IRQ => FSL_Control_IRQ
+    );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_6_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_6_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0fa5f5cbb7771fdd74aeb434c0c0c4799ec4d82f
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_6_ip_wrapper.vhd
@@ -0,0 +1,99 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_ed_6_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_altera_fifo_1_lib;
+use compaandesign_com_altera_fifo_1_lib.all;
+
+entity bunny_static_split2rtl_ed_6_ip_wrapper is
+  port (
+    FSL_Clk : in std_logic;
+    SYS_Rst : in std_logic;
+    FSL_Rst : out std_logic;
+    FSL_M_Clk : in std_logic;
+    FSL_M_Data : in std_logic_vector(0 to 7);
+    FSL_M_Control : in std_logic;
+    FSL_M_Write : in std_logic;
+    FSL_M_Full : out std_logic;
+    FSL_S_Clk : in std_logic;
+    FSL_S_Data : out std_logic_vector(0 to 7);
+    FSL_S_Control : out std_logic;
+    FSL_S_Read : in std_logic;
+    FSL_S_Exists : out std_logic;
+    FSL_Full : out std_logic;
+    FSL_Has_Data : out std_logic;
+    FSL_Control_IRQ : out std_logic
+  );
+
+
+end bunny_static_split2rtl_ed_6_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_ed_6_ip_wrapper is
+
+  component fsl_v20 is
+	generic (
+		C_EXT_RESET_HIGH : INTEGER := 1;
+		C_ASYNC_CLKS : INTEGER := 0;
+		C_IMPL_STYLE : INTEGER := 0;
+		C_USE_CONTROL : INTEGER := 1;
+		C_FSL_DWIDTH : INTEGER := 32;
+		C_FSL_DEPTH : INTEGER := 16;
+		C_READ_CLOCK_PERIOD : INTEGER := 0
+	);
+    port (
+      FSL_Clk 	: in  std_logic;
+      SYS_Rst 	: in  std_logic;
+      FSL_Rst 	: out std_logic;
+      FSL_M_Clk 	: in  std_logic;
+      FSL_M_Data 	: in  std_logic_vector(0 to 7);
+      FSL_M_Control: in  std_logic;
+      FSL_M_Write 	: in  std_logic;
+      FSL_M_Full 	: out std_logic;
+      FSL_S_Clk 	: in  std_logic;
+      FSL_S_Data 	: out std_logic_vector(0 to 7);
+      FSL_S_Control: out std_logic;
+      FSL_S_Read 	: in  std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full 	: out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+begin
+
+  bunny_static_split2rtl_ed_6 : fsl_v20
+	generic map (
+		C_EXT_RESET_HIGH => 1,
+		C_ASYNC_CLKS => 0,
+		C_IMPL_STYLE => 0,
+		C_USE_CONTROL => 1,
+		C_FSL_DWIDTH => 8,
+		C_FSL_DEPTH => 16,
+		C_READ_CLOCK_PERIOD => 0
+	)
+    port map (
+      FSL_Clk => FSL_Clk,
+      SYS_Rst => SYS_Rst,
+      FSL_Rst => FSL_Rst,
+      FSL_M_Clk => FSL_M_Clk,
+      FSL_M_Data => FSL_M_Data,
+      FSL_M_Control => FSL_M_Control,
+      FSL_M_Write => FSL_M_Write,
+      FSL_M_Full => FSL_M_Full,
+      FSL_S_Clk => FSL_S_Clk,
+      FSL_S_Data => FSL_S_Data,
+      FSL_S_Control => FSL_S_Control,
+      FSL_S_Read => FSL_S_Read,
+      FSL_S_Exists => FSL_S_Exists,
+      FSL_Full => FSL_Full,
+      FSL_Has_Data => FSL_Has_Data,
+      FSL_Control_IRQ => FSL_Control_IRQ
+    );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_7_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_7_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a3d45fae7b72a9610141fb7fba98e111b3606509
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_7_ip_wrapper.vhd
@@ -0,0 +1,99 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_ed_7_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_altera_fifo_1_lib;
+use compaandesign_com_altera_fifo_1_lib.all;
+
+entity bunny_static_split2rtl_ed_7_ip_wrapper is
+  port (
+    FSL_Clk : in std_logic;
+    SYS_Rst : in std_logic;
+    FSL_Rst : out std_logic;
+    FSL_M_Clk : in std_logic;
+    FSL_M_Data : in std_logic_vector(0 to 7);
+    FSL_M_Control : in std_logic;
+    FSL_M_Write : in std_logic;
+    FSL_M_Full : out std_logic;
+    FSL_S_Clk : in std_logic;
+    FSL_S_Data : out std_logic_vector(0 to 7);
+    FSL_S_Control : out std_logic;
+    FSL_S_Read : in std_logic;
+    FSL_S_Exists : out std_logic;
+    FSL_Full : out std_logic;
+    FSL_Has_Data : out std_logic;
+    FSL_Control_IRQ : out std_logic
+  );
+
+
+end bunny_static_split2rtl_ed_7_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_ed_7_ip_wrapper is
+
+  component fsl_v20 is
+	generic (
+		C_EXT_RESET_HIGH : INTEGER := 1;
+		C_ASYNC_CLKS : INTEGER := 0;
+		C_IMPL_STYLE : INTEGER := 0;
+		C_USE_CONTROL : INTEGER := 1;
+		C_FSL_DWIDTH : INTEGER := 32;
+		C_FSL_DEPTH : INTEGER := 16;
+		C_READ_CLOCK_PERIOD : INTEGER := 0
+	);
+    port (
+      FSL_Clk 	: in  std_logic;
+      SYS_Rst 	: in  std_logic;
+      FSL_Rst 	: out std_logic;
+      FSL_M_Clk 	: in  std_logic;
+      FSL_M_Data 	: in  std_logic_vector(0 to 7);
+      FSL_M_Control: in  std_logic;
+      FSL_M_Write 	: in  std_logic;
+      FSL_M_Full 	: out std_logic;
+      FSL_S_Clk 	: in  std_logic;
+      FSL_S_Data 	: out std_logic_vector(0 to 7);
+      FSL_S_Control: out std_logic;
+      FSL_S_Read 	: in  std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full 	: out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+begin
+
+  bunny_static_split2rtl_ed_7 : fsl_v20
+	generic map (
+		C_EXT_RESET_HIGH => 1,
+		C_ASYNC_CLKS => 0,
+		C_IMPL_STYLE => 0,
+		C_USE_CONTROL => 1,
+		C_FSL_DWIDTH => 8,
+		C_FSL_DEPTH => 16,
+		C_READ_CLOCK_PERIOD => 0
+	)
+    port map (
+      FSL_Clk => FSL_Clk,
+      SYS_Rst => SYS_Rst,
+      FSL_Rst => FSL_Rst,
+      FSL_M_Clk => FSL_M_Clk,
+      FSL_M_Data => FSL_M_Data,
+      FSL_M_Control => FSL_M_Control,
+      FSL_M_Write => FSL_M_Write,
+      FSL_M_Full => FSL_M_Full,
+      FSL_S_Clk => FSL_S_Clk,
+      FSL_S_Data => FSL_S_Data,
+      FSL_S_Control => FSL_S_Control,
+      FSL_S_Read => FSL_S_Read,
+      FSL_S_Exists => FSL_S_Exists,
+      FSL_Full => FSL_Full,
+      FSL_Has_Data => FSL_Has_Data,
+      FSL_Control_IRQ => FSL_Control_IRQ
+    );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_8_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_8_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a507907f2aedde0dafb0f93f0b327263dacfe78d
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_8_ip_wrapper.vhd
@@ -0,0 +1,99 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_ed_8_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_altera_fifo_1_lib;
+use compaandesign_com_altera_fifo_1_lib.all;
+
+entity bunny_static_split2rtl_ed_8_ip_wrapper is
+  port (
+    FSL_Clk : in std_logic;
+    SYS_Rst : in std_logic;
+    FSL_Rst : out std_logic;
+    FSL_M_Clk : in std_logic;
+    FSL_M_Data : in std_logic_vector(0 to 7);
+    FSL_M_Control : in std_logic;
+    FSL_M_Write : in std_logic;
+    FSL_M_Full : out std_logic;
+    FSL_S_Clk : in std_logic;
+    FSL_S_Data : out std_logic_vector(0 to 7);
+    FSL_S_Control : out std_logic;
+    FSL_S_Read : in std_logic;
+    FSL_S_Exists : out std_logic;
+    FSL_Full : out std_logic;
+    FSL_Has_Data : out std_logic;
+    FSL_Control_IRQ : out std_logic
+  );
+
+
+end bunny_static_split2rtl_ed_8_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_ed_8_ip_wrapper is
+
+  component fsl_v20 is
+	generic (
+		C_EXT_RESET_HIGH : INTEGER := 1;
+		C_ASYNC_CLKS : INTEGER := 0;
+		C_IMPL_STYLE : INTEGER := 0;
+		C_USE_CONTROL : INTEGER := 1;
+		C_FSL_DWIDTH : INTEGER := 32;
+		C_FSL_DEPTH : INTEGER := 16;
+		C_READ_CLOCK_PERIOD : INTEGER := 0
+	);
+    port (
+      FSL_Clk 	: in  std_logic;
+      SYS_Rst 	: in  std_logic;
+      FSL_Rst 	: out std_logic;
+      FSL_M_Clk 	: in  std_logic;
+      FSL_M_Data 	: in  std_logic_vector(0 to 7);
+      FSL_M_Control: in  std_logic;
+      FSL_M_Write 	: in  std_logic;
+      FSL_M_Full 	: out std_logic;
+      FSL_S_Clk 	: in  std_logic;
+      FSL_S_Data 	: out std_logic_vector(0 to 7);
+      FSL_S_Control: out std_logic;
+      FSL_S_Read 	: in  std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full 	: out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+begin
+
+  bunny_static_split2rtl_ed_8 : fsl_v20
+	generic map (
+		C_EXT_RESET_HIGH => 1,
+		C_ASYNC_CLKS => 0,
+		C_IMPL_STYLE => 0,
+		C_USE_CONTROL => 1,
+		C_FSL_DWIDTH => 8,
+		C_FSL_DEPTH => 16,
+		C_READ_CLOCK_PERIOD => 0
+	)
+    port map (
+      FSL_Clk => FSL_Clk,
+      SYS_Rst => SYS_Rst,
+      FSL_Rst => FSL_Rst,
+      FSL_M_Clk => FSL_M_Clk,
+      FSL_M_Data => FSL_M_Data,
+      FSL_M_Control => FSL_M_Control,
+      FSL_M_Write => FSL_M_Write,
+      FSL_M_Full => FSL_M_Full,
+      FSL_S_Clk => FSL_S_Clk,
+      FSL_S_Data => FSL_S_Data,
+      FSL_S_Control => FSL_S_Control,
+      FSL_S_Read => FSL_S_Read,
+      FSL_S_Exists => FSL_S_Exists,
+      FSL_Full => FSL_Full,
+      FSL_Has_Data => FSL_Has_Data,
+      FSL_Control_IRQ => FSL_Control_IRQ
+    );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_9_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_9_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2a9f889aa9b201d3c46a236c215dd5ddfb2473f5
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_ed_9_ip_wrapper.vhd
@@ -0,0 +1,99 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_ed_9_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_altera_fifo_1_lib;
+use compaandesign_com_altera_fifo_1_lib.all;
+
+entity bunny_static_split2rtl_ed_9_ip_wrapper is
+  port (
+    FSL_Clk : in std_logic;
+    SYS_Rst : in std_logic;
+    FSL_Rst : out std_logic;
+    FSL_M_Clk : in std_logic;
+    FSL_M_Data : in std_logic_vector(0 to 7);
+    FSL_M_Control : in std_logic;
+    FSL_M_Write : in std_logic;
+    FSL_M_Full : out std_logic;
+    FSL_S_Clk : in std_logic;
+    FSL_S_Data : out std_logic_vector(0 to 7);
+    FSL_S_Control : out std_logic;
+    FSL_S_Read : in std_logic;
+    FSL_S_Exists : out std_logic;
+    FSL_Full : out std_logic;
+    FSL_Has_Data : out std_logic;
+    FSL_Control_IRQ : out std_logic
+  );
+
+
+end bunny_static_split2rtl_ed_9_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_ed_9_ip_wrapper is
+
+  component fsl_v20 is
+	generic (
+		C_EXT_RESET_HIGH : INTEGER := 1;
+		C_ASYNC_CLKS : INTEGER := 0;
+		C_IMPL_STYLE : INTEGER := 0;
+		C_USE_CONTROL : INTEGER := 1;
+		C_FSL_DWIDTH : INTEGER := 32;
+		C_FSL_DEPTH : INTEGER := 16;
+		C_READ_CLOCK_PERIOD : INTEGER := 0
+	);
+    port (
+      FSL_Clk 	: in  std_logic;
+      SYS_Rst 	: in  std_logic;
+      FSL_Rst 	: out std_logic;
+      FSL_M_Clk 	: in  std_logic;
+      FSL_M_Data 	: in  std_logic_vector(0 to 7);
+      FSL_M_Control: in  std_logic;
+      FSL_M_Write 	: in  std_logic;
+      FSL_M_Full 	: out std_logic;
+      FSL_S_Clk 	: in  std_logic;
+      FSL_S_Data 	: out std_logic_vector(0 to 7);
+      FSL_S_Control: out std_logic;
+      FSL_S_Read 	: in  std_logic;
+      FSL_S_Exists : out std_logic;
+      FSL_Full 	: out std_logic;
+      FSL_Has_Data : out std_logic;
+      FSL_Control_IRQ : out std_logic
+    );
+  end component;
+
+begin
+
+  bunny_static_split2rtl_ed_9 : fsl_v20
+	generic map (
+		C_EXT_RESET_HIGH => 1,
+		C_ASYNC_CLKS => 0,
+		C_IMPL_STYLE => 0,
+		C_USE_CONTROL => 1,
+		C_FSL_DWIDTH => 8,
+		C_FSL_DEPTH => 16,
+		C_READ_CLOCK_PERIOD => 0
+	)
+    port map (
+      FSL_Clk => FSL_Clk,
+      SYS_Rst => SYS_Rst,
+      FSL_Rst => FSL_Rst,
+      FSL_M_Clk => FSL_M_Clk,
+      FSL_M_Data => FSL_M_Data,
+      FSL_M_Control => FSL_M_Control,
+      FSL_M_Write => FSL_M_Write,
+      FSL_M_Full => FSL_M_Full,
+      FSL_S_Clk => FSL_S_Clk,
+      FSL_S_Data => FSL_S_Data,
+      FSL_S_Control => FSL_S_Control,
+      FSL_S_Read => FSL_S_Read,
+      FSL_S_Exists => FSL_S_Exists,
+      FSL_Full => FSL_Full,
+      FSL_Has_Data => FSL_Has_Data,
+      FSL_Control_IRQ => FSL_Control_IRQ
+    );
+
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_10_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_10_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f179e1776a0eeb5761cf5d90f93607f66de60094
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_10_ip_wrapper.vhd
@@ -0,0 +1,145 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_hwn_nd_10_ip_wrapper.vhd
+-- LEAF false
+-- HIER false
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_bunny_static_split2rtl_hwn_nd_10_1_lib;
+use compaandesign_com_bunny_static_split2rtl_hwn_nd_10_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_10_ip_wrapper is
+  port (
+    ND_10IP_11_Rd : out std_logic;
+    ND_10IP_11_Din : in std_logic_vector(7 downto 0);
+    ND_10IP_11_Exist : in std_logic;
+    ND_10IP_11_CLK : out std_logic;
+    ND_10IP_11_CTRL : in std_logic;
+    ND_10IP_12_Rd : out std_logic;
+    ND_10IP_12_Din : in std_logic_vector(7 downto 0);
+    ND_10IP_12_Exist : in std_logic;
+    ND_10IP_12_CLK : out std_logic;
+    ND_10IP_12_CTRL : in std_logic;
+    ND_10OP_1_Wr : out std_logic;
+    ND_10OP_1_Dout : out std_logic_vector(7 downto 0);
+    ND_10OP_1_Full : in std_logic;
+    ND_10OP_1_CLK : out std_logic;
+    ND_10OP_1_CTRL : out std_logic;
+    ND_10OP_1_d1_Wr : out std_logic;
+    ND_10OP_1_d1_Dout : out std_logic_vector(7 downto 0);
+    ND_10OP_1_d1_Full : in std_logic;
+    ND_10OP_1_d1_CLK : out std_logic;
+    ND_10OP_1_d1_CTRL : out std_logic;
+    ND_10OP_1_d2_Wr : out std_logic;
+    ND_10OP_1_d2_Dout : out std_logic_vector(7 downto 0);
+    ND_10OP_1_d2_Full : in std_logic;
+    ND_10OP_1_d2_CLK : out std_logic;
+    ND_10OP_1_d2_CTRL : out std_logic;
+    PARAM_DT : in std_logic_vector(10 downto 0);
+    PARAM_LD : in std_logic;
+    STOP : out std_logic;
+    ERROR : out std_logic;
+    BLOCK_RD : out std_logic;
+    RST : in std_logic;
+    CLK : in std_logic
+  );
+  
+  
+end bunny_static_split2rtl_hwn_nd_10_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_hwn_nd_10_ip_wrapper is
+
+  component bunny_static_split2rtl_hwn_nd_10 is
+	generic (
+		RESET_HIGH : NATURAL := 1;
+		PAR_WIDTH : NATURAL := 16;
+		QUANT : NATURAL := 32;
+		WRAP : BOOLEAN := true;
+		STIM_DIR : STRING := "hwn_nd_10"
+	);
+	port (
+		ND_10IP_11_Rd : out std_logic;
+		ND_10IP_11_Din : in std_logic_vector(7 downto 0);
+		ND_10IP_11_Exist : in std_logic;
+		ND_10IP_11_CLK : out std_logic;
+		ND_10IP_11_CTRL : in std_logic;
+		ND_10IP_12_Rd : out std_logic;
+		ND_10IP_12_Din : in std_logic_vector(7 downto 0);
+		ND_10IP_12_Exist : in std_logic;
+		ND_10IP_12_CLK : out std_logic;
+		ND_10IP_12_CTRL : in std_logic;
+		ND_10OP_1_Wr : out std_logic;
+		ND_10OP_1_Dout : out std_logic_vector(7 downto 0);
+		ND_10OP_1_Full : in std_logic;
+		ND_10OP_1_CLK : out std_logic;
+		ND_10OP_1_CTRL : out std_logic;
+		ND_10OP_1_d1_Wr : out std_logic;
+		ND_10OP_1_d1_Dout : out std_logic_vector(7 downto 0);
+		ND_10OP_1_d1_Full : in std_logic;
+		ND_10OP_1_d1_CLK : out std_logic;
+		ND_10OP_1_d1_CTRL : out std_logic;
+		ND_10OP_1_d2_Wr : out std_logic;
+		ND_10OP_1_d2_Dout : out std_logic_vector(7 downto 0);
+		ND_10OP_1_d2_Full : in std_logic;
+		ND_10OP_1_d2_CLK : out std_logic;
+		ND_10OP_1_d2_CTRL : out std_logic;
+		PARAM_DT : in std_logic_vector(10 downto 0);
+		PARAM_LD : in std_logic;
+		STOP : out std_logic;
+		ERROR : out std_logic;
+		BLOCK_RD : out std_logic;
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+end component;
+
+begin
+
+bunny_static_split2rtl_hwn_nd_10_ip_wrapper_ip : bunny_static_split2rtl_hwn_nd_10
+	generic map (
+		RESET_HIGH => 1,
+		PAR_WIDTH => 1,
+		QUANT => 32,
+		WRAP => true,
+		STIM_DIR => "compaandesign_com/bunny_static_split2rtl/hwn_nd_10/tb/data/"
+	)
+    port map (
+		ND_10IP_11_Rd => ND_10IP_11_Rd,
+		ND_10IP_11_Din => ND_10IP_11_Din,
+		ND_10IP_11_Exist => ND_10IP_11_Exist,
+		ND_10IP_11_CLK => ND_10IP_11_CLK,
+		ND_10IP_11_CTRL => ND_10IP_11_CTRL,
+		ND_10IP_12_Rd => ND_10IP_12_Rd,
+		ND_10IP_12_Din => ND_10IP_12_Din,
+		ND_10IP_12_Exist => ND_10IP_12_Exist,
+		ND_10IP_12_CLK => ND_10IP_12_CLK,
+		ND_10IP_12_CTRL => ND_10IP_12_CTRL,
+		ND_10OP_1_Wr => ND_10OP_1_Wr,
+		ND_10OP_1_Dout => ND_10OP_1_Dout,
+		ND_10OP_1_Full => ND_10OP_1_Full,
+		ND_10OP_1_CLK => ND_10OP_1_CLK,
+		ND_10OP_1_CTRL => ND_10OP_1_CTRL,
+		ND_10OP_1_d1_Wr => ND_10OP_1_d1_Wr,
+		ND_10OP_1_d1_Dout => ND_10OP_1_d1_Dout,
+		ND_10OP_1_d1_Full => ND_10OP_1_d1_Full,
+		ND_10OP_1_d1_CLK => ND_10OP_1_d1_CLK,
+		ND_10OP_1_d1_CTRL => ND_10OP_1_d1_CTRL,
+		ND_10OP_1_d2_Wr => ND_10OP_1_d2_Wr,
+		ND_10OP_1_d2_Dout => ND_10OP_1_d2_Dout,
+		ND_10OP_1_d2_Full => ND_10OP_1_d2_Full,
+		ND_10OP_1_d2_CLK => ND_10OP_1_d2_CLK,
+		ND_10OP_1_d2_CTRL => ND_10OP_1_d2_CTRL,
+		PARAM_DT => PARAM_DT,
+		PARAM_LD => PARAM_LD,
+		STOP => STOP,
+		ERROR => ERROR,
+		BLOCK_RD => BLOCK_RD,
+		RST => RST,
+		CLK => CLK
+    );
+  
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_11_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_11_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4a37677898eab90d418fc164d075187ffd71dc4e
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_11_ip_wrapper.vhd
@@ -0,0 +1,64 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_hwn_nd_11_ip_wrapper.vhd
+-- LEAF false
+-- HIER false
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_common_const_connector_1_lib;
+use compaandesign_com_common_const_connector_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_11_ip_wrapper is
+  port (
+    FSL_M_Wr : out std_logic;
+    FSL_M_Dout : out std_logic_vector(7 downto 0);
+    FSL_M_Full : in std_logic;
+    FSL_M_CLK : out std_logic;
+    FSL_M_CTRL : out std_logic;
+    RST : in std_logic;
+    CLK : in std_logic
+  );
+  
+  
+end bunny_static_split2rtl_hwn_nd_11_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_hwn_nd_11_ip_wrapper is
+
+  component common_const_connector is
+	generic (
+		C_FSL_CONST : INTEGER := 0;
+		C_FSL_DWIDTH : INTEGER := 32
+	);
+	port (
+		FSL_M_Wr : out std_logic;
+		FSL_M_Dout : out std_logic_vector(7 downto 0);
+		FSL_M_Full : in std_logic;
+		FSL_M_CLK : out std_logic;
+		FSL_M_CTRL : out std_logic;
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+end component;
+
+begin
+
+bunny_static_split2rtl_hwn_nd_11_ip_wrapper_ip : common_const_connector
+	generic map (
+		C_FSL_CONST => 0,
+		C_FSL_DWIDTH => 8
+	)
+    port map (
+		FSL_M_Wr => FSL_M_Wr,
+		FSL_M_Dout => FSL_M_Dout,
+		FSL_M_Full => FSL_M_Full,
+		FSL_M_CLK => FSL_M_CLK,
+		FSL_M_CTRL => FSL_M_CTRL,
+		RST => RST,
+		CLK => CLK
+    );
+  
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_12_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_12_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..51b21db36dc3114180d1b531a576bf3cf97111f0
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_12_ip_wrapper.vhd
@@ -0,0 +1,160 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_hwn_nd_12_ip_wrapper.vhd
+-- LEAF false
+-- HIER false
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_bunny_static_split2rtl_hwn_nd_12_1_lib;
+use compaandesign_com_bunny_static_split2rtl_hwn_nd_12_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_12_ip_wrapper is
+  port (
+    ND_12IP_13_Rd : out std_logic;
+    ND_12IP_13_Din : in std_logic_vector(7 downto 0);
+    ND_12IP_13_Exist : in std_logic;
+    ND_12IP_13_CLK : out std_logic;
+    ND_12IP_13_CTRL : in std_logic;
+    ND_12IP_14_Rd : out std_logic;
+    ND_12IP_14_Din : in std_logic_vector(7 downto 0);
+    ND_12IP_14_Exist : in std_logic;
+    ND_12IP_14_CLK : out std_logic;
+    ND_12IP_14_CTRL : in std_logic;
+    ND_12IP_15_Rd : out std_logic;
+    ND_12IP_15_Din : in std_logic_vector(7 downto 0);
+    ND_12IP_15_Exist : in std_logic;
+    ND_12IP_15_CLK : out std_logic;
+    ND_12IP_15_CTRL : in std_logic;
+    ND_12IP_16_Rd : out std_logic;
+    ND_12IP_16_Din : in std_logic_vector(7 downto 0);
+    ND_12IP_16_Exist : in std_logic;
+    ND_12IP_16_CLK : out std_logic;
+    ND_12IP_16_CTRL : in std_logic;
+    ND_12OP_1_Wr : out std_logic;
+    ND_12OP_1_Dout : out std_logic_vector(31 downto 0);
+    ND_12OP_1_Full : in std_logic;
+    ND_12OP_1_CLK : out std_logic;
+    ND_12OP_1_CTRL : out std_logic;
+    ND_12OP_1_d1_Wr : out std_logic;
+    ND_12OP_1_d1_Dout : out std_logic_vector(31 downto 0);
+    ND_12OP_1_d1_Full : in std_logic;
+    ND_12OP_1_d1_CLK : out std_logic;
+    ND_12OP_1_d1_CTRL : out std_logic;
+    PARAM_DT : in std_logic_vector(10 downto 0);
+    PARAM_LD : in std_logic;
+    STOP : out std_logic;
+    ERROR : out std_logic;
+    BLOCK_RD : out std_logic;
+    RST : in std_logic;
+    CLK : in std_logic
+  );
+  
+  
+end bunny_static_split2rtl_hwn_nd_12_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_hwn_nd_12_ip_wrapper is
+
+  component bunny_static_split2rtl_hwn_nd_12 is
+	generic (
+		RESET_HIGH : NATURAL := 1;
+		PAR_WIDTH : NATURAL := 16;
+		QUANT : NATURAL := 32;
+		WRAP : BOOLEAN := true;
+		STIM_DIR : STRING := "hwn_nd_12"
+	);
+	port (
+		ND_12IP_13_Rd : out std_logic;
+		ND_12IP_13_Din : in std_logic_vector(7 downto 0);
+		ND_12IP_13_Exist : in std_logic;
+		ND_12IP_13_CLK : out std_logic;
+		ND_12IP_13_CTRL : in std_logic;
+		ND_12IP_14_Rd : out std_logic;
+		ND_12IP_14_Din : in std_logic_vector(7 downto 0);
+		ND_12IP_14_Exist : in std_logic;
+		ND_12IP_14_CLK : out std_logic;
+		ND_12IP_14_CTRL : in std_logic;
+		ND_12IP_15_Rd : out std_logic;
+		ND_12IP_15_Din : in std_logic_vector(7 downto 0);
+		ND_12IP_15_Exist : in std_logic;
+		ND_12IP_15_CLK : out std_logic;
+		ND_12IP_15_CTRL : in std_logic;
+		ND_12IP_16_Rd : out std_logic;
+		ND_12IP_16_Din : in std_logic_vector(7 downto 0);
+		ND_12IP_16_Exist : in std_logic;
+		ND_12IP_16_CLK : out std_logic;
+		ND_12IP_16_CTRL : in std_logic;
+		ND_12OP_1_Wr : out std_logic;
+		ND_12OP_1_Dout : out std_logic_vector(31 downto 0);
+		ND_12OP_1_Full : in std_logic;
+		ND_12OP_1_CLK : out std_logic;
+		ND_12OP_1_CTRL : out std_logic;
+		ND_12OP_1_d1_Wr : out std_logic;
+		ND_12OP_1_d1_Dout : out std_logic_vector(31 downto 0);
+		ND_12OP_1_d1_Full : in std_logic;
+		ND_12OP_1_d1_CLK : out std_logic;
+		ND_12OP_1_d1_CTRL : out std_logic;
+		PARAM_DT : in std_logic_vector(10 downto 0);
+		PARAM_LD : in std_logic;
+		STOP : out std_logic;
+		ERROR : out std_logic;
+		BLOCK_RD : out std_logic;
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+end component;
+
+begin
+
+bunny_static_split2rtl_hwn_nd_12_ip_wrapper_ip : bunny_static_split2rtl_hwn_nd_12
+	generic map (
+		RESET_HIGH => 1,
+		PAR_WIDTH => 1,
+		QUANT => 32,
+		WRAP => true,
+		STIM_DIR => "compaandesign_com/bunny_static_split2rtl/hwn_nd_12/tb/data/"
+	)
+    port map (
+		ND_12IP_13_Rd => ND_12IP_13_Rd,
+		ND_12IP_13_Din => ND_12IP_13_Din,
+		ND_12IP_13_Exist => ND_12IP_13_Exist,
+		ND_12IP_13_CLK => ND_12IP_13_CLK,
+		ND_12IP_13_CTRL => ND_12IP_13_CTRL,
+		ND_12IP_14_Rd => ND_12IP_14_Rd,
+		ND_12IP_14_Din => ND_12IP_14_Din,
+		ND_12IP_14_Exist => ND_12IP_14_Exist,
+		ND_12IP_14_CLK => ND_12IP_14_CLK,
+		ND_12IP_14_CTRL => ND_12IP_14_CTRL,
+		ND_12IP_15_Rd => ND_12IP_15_Rd,
+		ND_12IP_15_Din => ND_12IP_15_Din,
+		ND_12IP_15_Exist => ND_12IP_15_Exist,
+		ND_12IP_15_CLK => ND_12IP_15_CLK,
+		ND_12IP_15_CTRL => ND_12IP_15_CTRL,
+		ND_12IP_16_Rd => ND_12IP_16_Rd,
+		ND_12IP_16_Din => ND_12IP_16_Din,
+		ND_12IP_16_Exist => ND_12IP_16_Exist,
+		ND_12IP_16_CLK => ND_12IP_16_CLK,
+		ND_12IP_16_CTRL => ND_12IP_16_CTRL,
+		ND_12OP_1_Wr => ND_12OP_1_Wr,
+		ND_12OP_1_Dout => ND_12OP_1_Dout,
+		ND_12OP_1_Full => ND_12OP_1_Full,
+		ND_12OP_1_CLK => ND_12OP_1_CLK,
+		ND_12OP_1_CTRL => ND_12OP_1_CTRL,
+		ND_12OP_1_d1_Wr => ND_12OP_1_d1_Wr,
+		ND_12OP_1_d1_Dout => ND_12OP_1_d1_Dout,
+		ND_12OP_1_d1_Full => ND_12OP_1_d1_Full,
+		ND_12OP_1_d1_CLK => ND_12OP_1_d1_CLK,
+		ND_12OP_1_d1_CTRL => ND_12OP_1_d1_CTRL,
+		PARAM_DT => PARAM_DT,
+		PARAM_LD => PARAM_LD,
+		STOP => STOP,
+		ERROR => ERROR,
+		BLOCK_RD => BLOCK_RD,
+		RST => RST,
+		CLK => CLK
+    );
+  
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_13_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_13_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..02db90f4e16b74b93369ab788918d882b583a89e
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_13_ip_wrapper.vhd
@@ -0,0 +1,115 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_hwn_nd_13_ip_wrapper.vhd
+-- LEAF false
+-- HIER false
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_bunny_static_split2rtl_hwn_nd_13_1_lib;
+use compaandesign_com_bunny_static_split2rtl_hwn_nd_13_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_13_ip_wrapper is
+  port (
+    ND_13IP_17_Rd : out std_logic;
+    ND_13IP_17_Din : in std_logic_vector(31 downto 0);
+    ND_13IP_17_Exist : in std_logic;
+    ND_13IP_17_CLK : out std_logic;
+    ND_13IP_17_CTRL : in std_logic;
+    ND_13IP_18_Rd : out std_logic;
+    ND_13IP_18_Din : in std_logic_vector(31 downto 0);
+    ND_13IP_18_Exist : in std_logic;
+    ND_13IP_18_CLK : out std_logic;
+    ND_13IP_18_CTRL : in std_logic;
+    ND_13OP_1_d1_ND_13OP_1_Wr : out std_logic;
+    ND_13OP_1_d1_ND_13OP_1_Dout : out std_logic_vector(63 downto 0);
+    ND_13OP_1_d1_ND_13OP_1_Full : in std_logic;
+    ND_13OP_1_d1_ND_13OP_1_CLK : out std_logic;
+    ND_13OP_1_d1_ND_13OP_1_CTRL : out std_logic;
+    PARAM_DT : in std_logic_vector(10 downto 0);
+    PARAM_LD : in std_logic;
+    STOP : out std_logic;
+    ERROR : out std_logic;
+    BLOCK_RD : out std_logic;
+    RST : in std_logic;
+    CLK : in std_logic
+  );
+  
+  
+end bunny_static_split2rtl_hwn_nd_13_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_hwn_nd_13_ip_wrapper is
+
+  component bunny_static_split2rtl_hwn_nd_13 is
+	generic (
+		RESET_HIGH : NATURAL := 1;
+		PAR_WIDTH : NATURAL := 16;
+		QUANT : NATURAL := 32;
+		WRAP : BOOLEAN := true;
+		STIM_DIR : STRING := "hwn_nd_13"
+	);
+	port (
+		ND_13IP_17_Rd : out std_logic;
+		ND_13IP_17_Din : in std_logic_vector(31 downto 0);
+		ND_13IP_17_Exist : in std_logic;
+		ND_13IP_17_CLK : out std_logic;
+		ND_13IP_17_CTRL : in std_logic;
+		ND_13IP_18_Rd : out std_logic;
+		ND_13IP_18_Din : in std_logic_vector(31 downto 0);
+		ND_13IP_18_Exist : in std_logic;
+		ND_13IP_18_CLK : out std_logic;
+		ND_13IP_18_CTRL : in std_logic;
+		ND_13OP_1_d1_ND_13OP_1_Wr : out std_logic;
+		ND_13OP_1_d1_ND_13OP_1_Dout : out std_logic_vector(63 downto 0);
+		ND_13OP_1_d1_ND_13OP_1_Full : in std_logic;
+		ND_13OP_1_d1_ND_13OP_1_CLK : out std_logic;
+		ND_13OP_1_d1_ND_13OP_1_CTRL : out std_logic;
+		PARAM_DT : in std_logic_vector(10 downto 0);
+		PARAM_LD : in std_logic;
+		STOP : out std_logic;
+		ERROR : out std_logic;
+		BLOCK_RD : out std_logic;
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+end component;
+
+begin
+
+bunny_static_split2rtl_hwn_nd_13_ip_wrapper_ip : bunny_static_split2rtl_hwn_nd_13
+	generic map (
+		RESET_HIGH => 1,
+		PAR_WIDTH => 1,
+		QUANT => 32,
+		WRAP => true,
+		STIM_DIR => "compaandesign_com/bunny_static_split2rtl/hwn_nd_13/tb/data/"
+	)
+    port map (
+		ND_13IP_17_Rd => ND_13IP_17_Rd,
+		ND_13IP_17_Din => ND_13IP_17_Din,
+		ND_13IP_17_Exist => ND_13IP_17_Exist,
+		ND_13IP_17_CLK => ND_13IP_17_CLK,
+		ND_13IP_17_CTRL => ND_13IP_17_CTRL,
+		ND_13IP_18_Rd => ND_13IP_18_Rd,
+		ND_13IP_18_Din => ND_13IP_18_Din,
+		ND_13IP_18_Exist => ND_13IP_18_Exist,
+		ND_13IP_18_CLK => ND_13IP_18_CLK,
+		ND_13IP_18_CTRL => ND_13IP_18_CTRL,
+		ND_13OP_1_d1_ND_13OP_1_Wr => ND_13OP_1_d1_ND_13OP_1_Wr,
+		ND_13OP_1_d1_ND_13OP_1_Dout => ND_13OP_1_d1_ND_13OP_1_Dout,
+		ND_13OP_1_d1_ND_13OP_1_Full => ND_13OP_1_d1_ND_13OP_1_Full,
+		ND_13OP_1_d1_ND_13OP_1_CLK => ND_13OP_1_d1_ND_13OP_1_CLK,
+		ND_13OP_1_d1_ND_13OP_1_CTRL => ND_13OP_1_d1_ND_13OP_1_CTRL,
+		PARAM_DT => PARAM_DT,
+		PARAM_LD => PARAM_LD,
+		STOP => STOP,
+		ERROR => ERROR,
+		BLOCK_RD => BLOCK_RD,
+		RST => RST,
+		CLK => CLK
+    );
+  
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_14_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_14_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..60d1aa70beb40a9404964e77a369a775b96d7c0a
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_14_ip_wrapper.vhd
@@ -0,0 +1,115 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_hwn_nd_14_ip_wrapper.vhd
+-- LEAF false
+-- HIER false
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_bunny_static_split2rtl_hwn_nd_14_1_lib;
+use compaandesign_com_bunny_static_split2rtl_hwn_nd_14_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_14_ip_wrapper is
+  port (
+    ND_14IP_20_ND_14IP_19_Rd : out std_logic;
+    ND_14IP_20_ND_14IP_19_Din : in std_logic_vector(63 downto 0);
+    ND_14IP_20_ND_14IP_19_Exist : in std_logic;
+    ND_14IP_20_ND_14IP_19_CLK : out std_logic;
+    ND_14IP_20_ND_14IP_19_CTRL : in std_logic;
+    ND_14IP_21_Rd : out std_logic;
+    ND_14IP_21_Din : in std_logic_vector(63 downto 0);
+    ND_14IP_21_Exist : in std_logic;
+    ND_14IP_21_CLK : out std_logic;
+    ND_14IP_21_CTRL : in std_logic;
+    data_out_Wr : out std_logic;
+    data_out_Dout : out std_logic_vector(63 downto 0);
+    data_out_Full : in std_logic;
+    data_out_CLK : out std_logic;
+    data_out_CTRL : out std_logic;
+    PARAM_DT : in std_logic_vector(10 downto 0);
+    PARAM_LD : in std_logic;
+    STOP : out std_logic;
+    ERROR : out std_logic;
+    BLOCK_RD : out std_logic;
+    RST : in std_logic;
+    CLK : in std_logic
+  );
+  
+  
+end bunny_static_split2rtl_hwn_nd_14_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_hwn_nd_14_ip_wrapper is
+
+  component bunny_static_split2rtl_hwn_nd_14 is
+	generic (
+		RESET_HIGH : NATURAL := 1;
+		PAR_WIDTH : NATURAL := 16;
+		QUANT : NATURAL := 32;
+		WRAP : BOOLEAN := true;
+		STIM_DIR : STRING := "hwn_nd_14"
+	);
+	port (
+		ND_14IP_20_ND_14IP_19_Rd : out std_logic;
+		ND_14IP_20_ND_14IP_19_Din : in std_logic_vector(63 downto 0);
+		ND_14IP_20_ND_14IP_19_Exist : in std_logic;
+		ND_14IP_20_ND_14IP_19_CLK : out std_logic;
+		ND_14IP_20_ND_14IP_19_CTRL : in std_logic;
+		ND_14IP_21_Rd : out std_logic;
+		ND_14IP_21_Din : in std_logic_vector(63 downto 0);
+		ND_14IP_21_Exist : in std_logic;
+		ND_14IP_21_CLK : out std_logic;
+		ND_14IP_21_CTRL : in std_logic;
+		data_out_Wr : out std_logic;
+		data_out_Dout : out std_logic_vector(63 downto 0);
+		data_out_Full : in std_logic;
+		data_out_CLK : out std_logic;
+		data_out_CTRL : out std_logic;
+		PARAM_DT : in std_logic_vector(10 downto 0);
+		PARAM_LD : in std_logic;
+		STOP : out std_logic;
+		ERROR : out std_logic;
+		BLOCK_RD : out std_logic;
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+end component;
+
+begin
+
+bunny_static_split2rtl_hwn_nd_14_ip_wrapper_ip : bunny_static_split2rtl_hwn_nd_14
+	generic map (
+		RESET_HIGH => 1,
+		PAR_WIDTH => 1,
+		QUANT => 32,
+		WRAP => true,
+		STIM_DIR => "compaandesign_com/bunny_static_split2rtl/hwn_nd_14/tb/data/"
+	)
+    port map (
+		ND_14IP_20_ND_14IP_19_Rd => ND_14IP_20_ND_14IP_19_Rd,
+		ND_14IP_20_ND_14IP_19_Din => ND_14IP_20_ND_14IP_19_Din,
+		ND_14IP_20_ND_14IP_19_Exist => ND_14IP_20_ND_14IP_19_Exist,
+		ND_14IP_20_ND_14IP_19_CLK => ND_14IP_20_ND_14IP_19_CLK,
+		ND_14IP_20_ND_14IP_19_CTRL => ND_14IP_20_ND_14IP_19_CTRL,
+		ND_14IP_21_Rd => ND_14IP_21_Rd,
+		ND_14IP_21_Din => ND_14IP_21_Din,
+		ND_14IP_21_Exist => ND_14IP_21_Exist,
+		ND_14IP_21_CLK => ND_14IP_21_CLK,
+		ND_14IP_21_CTRL => ND_14IP_21_CTRL,
+		data_out_Wr => data_out_Wr,
+		data_out_Dout => data_out_Dout,
+		data_out_Full => data_out_Full,
+		data_out_CLK => data_out_CLK,
+		data_out_CTRL => data_out_CTRL,
+		PARAM_DT => PARAM_DT,
+		PARAM_LD => PARAM_LD,
+		STOP => STOP,
+		ERROR => ERROR,
+		BLOCK_RD => BLOCK_RD,
+		RST => RST,
+		CLK => CLK
+    );
+  
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_2_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_2_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d3f23c79241f7a9245dd27d83a6f051fe9a79f13
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_2_ip_wrapper.vhd
@@ -0,0 +1,115 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_hwn_nd_2_ip_wrapper.vhd
+-- LEAF false
+-- HIER false
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_bunny_static_split2rtl_hwn_nd_2_1_lib;
+use compaandesign_com_bunny_static_split2rtl_hwn_nd_2_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_2_ip_wrapper is
+  port (
+    data_in_Rd : out std_logic;
+    data_in_Din : in std_logic_vector(63 downto 0);
+    data_in_Exist : in std_logic;
+    data_in_CLK : out std_logic;
+    data_in_CTRL : in std_logic;
+    ND_2OP_1_Wr : out std_logic;
+    ND_2OP_1_Dout : out std_logic_vector(63 downto 0);
+    ND_2OP_1_Full : in std_logic;
+    ND_2OP_1_CLK : out std_logic;
+    ND_2OP_1_CTRL : out std_logic;
+    ND_2OP_1_d1_Wr : out std_logic;
+    ND_2OP_1_d1_Dout : out std_logic_vector(63 downto 0);
+    ND_2OP_1_d1_Full : in std_logic;
+    ND_2OP_1_d1_CLK : out std_logic;
+    ND_2OP_1_d1_CTRL : out std_logic;
+    PARAM_DT : in std_logic_vector(10 downto 0);
+    PARAM_LD : in std_logic;
+    STOP : out std_logic;
+    ERROR : out std_logic;
+    BLOCK_RD : out std_logic;
+    RST : in std_logic;
+    CLK : in std_logic
+  );
+  
+  
+end bunny_static_split2rtl_hwn_nd_2_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_hwn_nd_2_ip_wrapper is
+
+  component bunny_static_split2rtl_hwn_nd_2 is
+	generic (
+		RESET_HIGH : NATURAL := 1;
+		PAR_WIDTH : NATURAL := 16;
+		QUANT : NATURAL := 32;
+		WRAP : BOOLEAN := true;
+		STIM_DIR : STRING := "hwn_nd_2"
+	);
+	port (
+		data_in_Rd : out std_logic;
+		data_in_Din : in std_logic_vector(63 downto 0);
+		data_in_Exist : in std_logic;
+		data_in_CLK : out std_logic;
+		data_in_CTRL : in std_logic;
+		ND_2OP_1_Wr : out std_logic;
+		ND_2OP_1_Dout : out std_logic_vector(63 downto 0);
+		ND_2OP_1_Full : in std_logic;
+		ND_2OP_1_CLK : out std_logic;
+		ND_2OP_1_CTRL : out std_logic;
+		ND_2OP_1_d1_Wr : out std_logic;
+		ND_2OP_1_d1_Dout : out std_logic_vector(63 downto 0);
+		ND_2OP_1_d1_Full : in std_logic;
+		ND_2OP_1_d1_CLK : out std_logic;
+		ND_2OP_1_d1_CTRL : out std_logic;
+		PARAM_DT : in std_logic_vector(10 downto 0);
+		PARAM_LD : in std_logic;
+		STOP : out std_logic;
+		ERROR : out std_logic;
+		BLOCK_RD : out std_logic;
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+end component;
+
+begin
+
+bunny_static_split2rtl_hwn_nd_2_ip_wrapper_ip : bunny_static_split2rtl_hwn_nd_2
+	generic map (
+		RESET_HIGH => 1,
+		PAR_WIDTH => 1,
+		QUANT => 32,
+		WRAP => true,
+		STIM_DIR => "compaandesign_com/bunny_static_split2rtl/hwn_nd_2/tb/data/"
+	)
+    port map (
+		data_in_Rd => data_in_Rd,
+		data_in_Din => data_in_Din,
+		data_in_Exist => data_in_Exist,
+		data_in_CLK => data_in_CLK,
+		data_in_CTRL => data_in_CTRL,
+		ND_2OP_1_Wr => ND_2OP_1_Wr,
+		ND_2OP_1_Dout => ND_2OP_1_Dout,
+		ND_2OP_1_Full => ND_2OP_1_Full,
+		ND_2OP_1_CLK => ND_2OP_1_CLK,
+		ND_2OP_1_CTRL => ND_2OP_1_CTRL,
+		ND_2OP_1_d1_Wr => ND_2OP_1_d1_Wr,
+		ND_2OP_1_d1_Dout => ND_2OP_1_d1_Dout,
+		ND_2OP_1_d1_Full => ND_2OP_1_d1_Full,
+		ND_2OP_1_d1_CLK => ND_2OP_1_d1_CLK,
+		ND_2OP_1_d1_CTRL => ND_2OP_1_d1_CTRL,
+		PARAM_DT => PARAM_DT,
+		PARAM_LD => PARAM_LD,
+		STOP => STOP,
+		ERROR => ERROR,
+		BLOCK_RD => BLOCK_RD,
+		RST => RST,
+		CLK => CLK
+    );
+  
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_3_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_3_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..71bf0985dd452f7866961afe4c4c090337f84252
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_3_ip_wrapper.vhd
@@ -0,0 +1,64 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_hwn_nd_3_ip_wrapper.vhd
+-- LEAF false
+-- HIER false
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_common_const_connector_1_lib;
+use compaandesign_com_common_const_connector_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_3_ip_wrapper is
+  port (
+    FSL_M_Wr : out std_logic;
+    FSL_M_Dout : out std_logic_vector(63 downto 0);
+    FSL_M_Full : in std_logic;
+    FSL_M_CLK : out std_logic;
+    FSL_M_CTRL : out std_logic;
+    RST : in std_logic;
+    CLK : in std_logic
+  );
+  
+  
+end bunny_static_split2rtl_hwn_nd_3_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_hwn_nd_3_ip_wrapper is
+
+  component common_const_connector is
+	generic (
+		C_FSL_CONST : INTEGER := 0;
+		C_FSL_DWIDTH : INTEGER := 32
+	);
+	port (
+		FSL_M_Wr : out std_logic;
+		FSL_M_Dout : out std_logic_vector(63 downto 0);
+		FSL_M_Full : in std_logic;
+		FSL_M_CLK : out std_logic;
+		FSL_M_CTRL : out std_logic;
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+end component;
+
+begin
+
+bunny_static_split2rtl_hwn_nd_3_ip_wrapper_ip : common_const_connector
+	generic map (
+		C_FSL_CONST => 0,
+		C_FSL_DWIDTH => 64
+	)
+    port map (
+		FSL_M_Wr => FSL_M_Wr,
+		FSL_M_Dout => FSL_M_Dout,
+		FSL_M_Full => FSL_M_Full,
+		FSL_M_CLK => FSL_M_CLK,
+		FSL_M_CTRL => FSL_M_CTRL,
+		RST => RST,
+		CLK => CLK
+    );
+  
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_4_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_4_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9fbcb3f238082b9368216242a6eadf2a3b648f77
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_4_ip_wrapper.vhd
@@ -0,0 +1,88 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_hwn_nd_4_ip_wrapper.vhd
+-- LEAF false
+-- HIER false
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_bunny_static_split2rtl_hwn_nd_4_1_lib;
+use compaandesign_com_bunny_static_split2rtl_hwn_nd_4_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_4_ip_wrapper is
+  port (
+    rf_count : out std_logic_vector(31 downto 0);
+    ND_4IP_1_Rd : out std_logic;
+    ND_4IP_1_Din : in std_logic_vector(63 downto 0);
+    ND_4IP_1_Exist : in std_logic;
+    ND_4IP_1_CLK : out std_logic;
+    ND_4IP_1_CTRL : in std_logic;
+    PARAM_DT : in std_logic_vector(10 downto 0);
+    PARAM_LD : in std_logic;
+    STOP : out std_logic;
+    ERROR : out std_logic;
+    BLOCK_RD : out std_logic;
+    RST : in std_logic;
+    CLK : in std_logic
+  );
+  
+  
+end bunny_static_split2rtl_hwn_nd_4_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_hwn_nd_4_ip_wrapper is
+
+  component bunny_static_split2rtl_hwn_nd_4 is
+	generic (
+		RESET_HIGH : NATURAL := 1;
+		PAR_WIDTH : NATURAL := 16;
+		QUANT : NATURAL := 32;
+		WRAP : BOOLEAN := true;
+		STIM_DIR : STRING := "hwn_nd_4"
+	);
+	port (
+		rf_count : out std_logic_vector(31 downto 0);
+		ND_4IP_1_Rd : out std_logic;
+		ND_4IP_1_Din : in std_logic_vector(63 downto 0);
+		ND_4IP_1_Exist : in std_logic;
+		ND_4IP_1_CLK : out std_logic;
+		ND_4IP_1_CTRL : in std_logic;
+		PARAM_DT : in std_logic_vector(10 downto 0);
+		PARAM_LD : in std_logic;
+		STOP : out std_logic;
+		ERROR : out std_logic;
+		BLOCK_RD : out std_logic;
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+end component;
+
+begin
+
+bunny_static_split2rtl_hwn_nd_4_ip_wrapper_ip : bunny_static_split2rtl_hwn_nd_4
+	generic map (
+		RESET_HIGH => 1,
+		PAR_WIDTH => 1,
+		QUANT => 32,
+		WRAP => true,
+		STIM_DIR => "compaandesign_com/bunny_static_split2rtl/hwn_nd_4/tb/data/"
+	)
+    port map (
+		rf_count => rf_count,
+		ND_4IP_1_Rd => ND_4IP_1_Rd,
+		ND_4IP_1_Din => ND_4IP_1_Din,
+		ND_4IP_1_Exist => ND_4IP_1_Exist,
+		ND_4IP_1_CLK => ND_4IP_1_CLK,
+		ND_4IP_1_CTRL => ND_4IP_1_CTRL,
+		PARAM_DT => PARAM_DT,
+		PARAM_LD => PARAM_LD,
+		STOP => STOP,
+		ERROR => ERROR,
+		BLOCK_RD => BLOCK_RD,
+		RST => RST,
+		CLK => CLK
+    );
+  
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_5_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_5_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..55a8b727c4b83baa579d355f6e1381f69818b7fa
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_5_ip_wrapper.vhd
@@ -0,0 +1,115 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_hwn_nd_5_ip_wrapper.vhd
+-- LEAF false
+-- HIER false
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_bunny_static_split2rtl_hwn_nd_5_1_lib;
+use compaandesign_com_bunny_static_split2rtl_hwn_nd_5_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_5_ip_wrapper is
+  port (
+    ND_5IP_2_Rd : out std_logic;
+    ND_5IP_2_Din : in std_logic_vector(63 downto 0);
+    ND_5IP_2_Exist : in std_logic;
+    ND_5IP_2_CLK : out std_logic;
+    ND_5IP_2_CTRL : in std_logic;
+    ND_5OP_1_Wr : out std_logic;
+    ND_5OP_1_Dout : out std_logic_vector(31 downto 0);
+    ND_5OP_1_Full : in std_logic;
+    ND_5OP_1_CLK : out std_logic;
+    ND_5OP_1_CTRL : out std_logic;
+    ND_5OP_2_d1_ND_5OP_2_Wr : out std_logic;
+    ND_5OP_2_d1_ND_5OP_2_Dout : out std_logic_vector(31 downto 0);
+    ND_5OP_2_d1_ND_5OP_2_Full : in std_logic;
+    ND_5OP_2_d1_ND_5OP_2_CLK : out std_logic;
+    ND_5OP_2_d1_ND_5OP_2_CTRL : out std_logic;
+    PARAM_DT : in std_logic_vector(10 downto 0);
+    PARAM_LD : in std_logic;
+    STOP : out std_logic;
+    ERROR : out std_logic;
+    BLOCK_RD : out std_logic;
+    RST : in std_logic;
+    CLK : in std_logic
+  );
+  
+  
+end bunny_static_split2rtl_hwn_nd_5_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_hwn_nd_5_ip_wrapper is
+
+  component bunny_static_split2rtl_hwn_nd_5 is
+	generic (
+		RESET_HIGH : NATURAL := 1;
+		PAR_WIDTH : NATURAL := 16;
+		QUANT : NATURAL := 32;
+		WRAP : BOOLEAN := true;
+		STIM_DIR : STRING := "hwn_nd_5"
+	);
+	port (
+		ND_5IP_2_Rd : out std_logic;
+		ND_5IP_2_Din : in std_logic_vector(63 downto 0);
+		ND_5IP_2_Exist : in std_logic;
+		ND_5IP_2_CLK : out std_logic;
+		ND_5IP_2_CTRL : in std_logic;
+		ND_5OP_1_Wr : out std_logic;
+		ND_5OP_1_Dout : out std_logic_vector(31 downto 0);
+		ND_5OP_1_Full : in std_logic;
+		ND_5OP_1_CLK : out std_logic;
+		ND_5OP_1_CTRL : out std_logic;
+		ND_5OP_2_d1_ND_5OP_2_Wr : out std_logic;
+		ND_5OP_2_d1_ND_5OP_2_Dout : out std_logic_vector(31 downto 0);
+		ND_5OP_2_d1_ND_5OP_2_Full : in std_logic;
+		ND_5OP_2_d1_ND_5OP_2_CLK : out std_logic;
+		ND_5OP_2_d1_ND_5OP_2_CTRL : out std_logic;
+		PARAM_DT : in std_logic_vector(10 downto 0);
+		PARAM_LD : in std_logic;
+		STOP : out std_logic;
+		ERROR : out std_logic;
+		BLOCK_RD : out std_logic;
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+end component;
+
+begin
+
+bunny_static_split2rtl_hwn_nd_5_ip_wrapper_ip : bunny_static_split2rtl_hwn_nd_5
+	generic map (
+		RESET_HIGH => 1,
+		PAR_WIDTH => 1,
+		QUANT => 32,
+		WRAP => true,
+		STIM_DIR => "compaandesign_com/bunny_static_split2rtl/hwn_nd_5/tb/data/"
+	)
+    port map (
+		ND_5IP_2_Rd => ND_5IP_2_Rd,
+		ND_5IP_2_Din => ND_5IP_2_Din,
+		ND_5IP_2_Exist => ND_5IP_2_Exist,
+		ND_5IP_2_CLK => ND_5IP_2_CLK,
+		ND_5IP_2_CTRL => ND_5IP_2_CTRL,
+		ND_5OP_1_Wr => ND_5OP_1_Wr,
+		ND_5OP_1_Dout => ND_5OP_1_Dout,
+		ND_5OP_1_Full => ND_5OP_1_Full,
+		ND_5OP_1_CLK => ND_5OP_1_CLK,
+		ND_5OP_1_CTRL => ND_5OP_1_CTRL,
+		ND_5OP_2_d1_ND_5OP_2_Wr => ND_5OP_2_d1_ND_5OP_2_Wr,
+		ND_5OP_2_d1_ND_5OP_2_Dout => ND_5OP_2_d1_ND_5OP_2_Dout,
+		ND_5OP_2_d1_ND_5OP_2_Full => ND_5OP_2_d1_ND_5OP_2_Full,
+		ND_5OP_2_d1_ND_5OP_2_CLK => ND_5OP_2_d1_ND_5OP_2_CLK,
+		ND_5OP_2_d1_ND_5OP_2_CTRL => ND_5OP_2_d1_ND_5OP_2_CTRL,
+		PARAM_DT => PARAM_DT,
+		PARAM_LD => PARAM_LD,
+		STOP => STOP,
+		ERROR => ERROR,
+		BLOCK_RD => BLOCK_RD,
+		RST => RST,
+		CLK => CLK
+    );
+  
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_6_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_6_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a5504cd2f4313edb26afad47e87c514b1d0041f6
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_6_ip_wrapper.vhd
@@ -0,0 +1,145 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_hwn_nd_6_ip_wrapper.vhd
+-- LEAF false
+-- HIER false
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_bunny_static_split2rtl_hwn_nd_6_1_lib;
+use compaandesign_com_bunny_static_split2rtl_hwn_nd_6_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_6_ip_wrapper is
+  port (
+    ND_6IP_3_Rd : out std_logic;
+    ND_6IP_3_Din : in std_logic_vector(31 downto 0);
+    ND_6IP_3_Exist : in std_logic;
+    ND_6IP_3_CLK : out std_logic;
+    ND_6IP_3_CTRL : in std_logic;
+    ND_6IP_5_ND_6IP_4_Rd : out std_logic;
+    ND_6IP_5_ND_6IP_4_Din : in std_logic_vector(31 downto 0);
+    ND_6IP_5_ND_6IP_4_Exist : in std_logic;
+    ND_6IP_5_ND_6IP_4_CLK : out std_logic;
+    ND_6IP_5_ND_6IP_4_CTRL : in std_logic;
+    ND_6OP_1_Wr : out std_logic;
+    ND_6OP_1_Dout : out std_logic_vector(7 downto 0);
+    ND_6OP_1_Full : in std_logic;
+    ND_6OP_1_CLK : out std_logic;
+    ND_6OP_1_CTRL : out std_logic;
+    ND_6OP_2_Wr : out std_logic;
+    ND_6OP_2_Dout : out std_logic_vector(7 downto 0);
+    ND_6OP_2_Full : in std_logic;
+    ND_6OP_2_CLK : out std_logic;
+    ND_6OP_2_CTRL : out std_logic;
+    ND_6OP_3_Wr : out std_logic;
+    ND_6OP_3_Dout : out std_logic_vector(7 downto 0);
+    ND_6OP_3_Full : in std_logic;
+    ND_6OP_3_CLK : out std_logic;
+    ND_6OP_3_CTRL : out std_logic;
+    PARAM_DT : in std_logic_vector(10 downto 0);
+    PARAM_LD : in std_logic;
+    STOP : out std_logic;
+    ERROR : out std_logic;
+    BLOCK_RD : out std_logic;
+    RST : in std_logic;
+    CLK : in std_logic
+  );
+  
+  
+end bunny_static_split2rtl_hwn_nd_6_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_hwn_nd_6_ip_wrapper is
+
+  component bunny_static_split2rtl_hwn_nd_6 is
+	generic (
+		RESET_HIGH : NATURAL := 1;
+		PAR_WIDTH : NATURAL := 16;
+		QUANT : NATURAL := 32;
+		WRAP : BOOLEAN := true;
+		STIM_DIR : STRING := "hwn_nd_6"
+	);
+	port (
+		ND_6IP_3_Rd : out std_logic;
+		ND_6IP_3_Din : in std_logic_vector(31 downto 0);
+		ND_6IP_3_Exist : in std_logic;
+		ND_6IP_3_CLK : out std_logic;
+		ND_6IP_3_CTRL : in std_logic;
+		ND_6IP_5_ND_6IP_4_Rd : out std_logic;
+		ND_6IP_5_ND_6IP_4_Din : in std_logic_vector(31 downto 0);
+		ND_6IP_5_ND_6IP_4_Exist : in std_logic;
+		ND_6IP_5_ND_6IP_4_CLK : out std_logic;
+		ND_6IP_5_ND_6IP_4_CTRL : in std_logic;
+		ND_6OP_1_Wr : out std_logic;
+		ND_6OP_1_Dout : out std_logic_vector(7 downto 0);
+		ND_6OP_1_Full : in std_logic;
+		ND_6OP_1_CLK : out std_logic;
+		ND_6OP_1_CTRL : out std_logic;
+		ND_6OP_2_Wr : out std_logic;
+		ND_6OP_2_Dout : out std_logic_vector(7 downto 0);
+		ND_6OP_2_Full : in std_logic;
+		ND_6OP_2_CLK : out std_logic;
+		ND_6OP_2_CTRL : out std_logic;
+		ND_6OP_3_Wr : out std_logic;
+		ND_6OP_3_Dout : out std_logic_vector(7 downto 0);
+		ND_6OP_3_Full : in std_logic;
+		ND_6OP_3_CLK : out std_logic;
+		ND_6OP_3_CTRL : out std_logic;
+		PARAM_DT : in std_logic_vector(10 downto 0);
+		PARAM_LD : in std_logic;
+		STOP : out std_logic;
+		ERROR : out std_logic;
+		BLOCK_RD : out std_logic;
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+end component;
+
+begin
+
+bunny_static_split2rtl_hwn_nd_6_ip_wrapper_ip : bunny_static_split2rtl_hwn_nd_6
+	generic map (
+		RESET_HIGH => 1,
+		PAR_WIDTH => 1,
+		QUANT => 32,
+		WRAP => true,
+		STIM_DIR => "compaandesign_com/bunny_static_split2rtl/hwn_nd_6/tb/data/"
+	)
+    port map (
+		ND_6IP_3_Rd => ND_6IP_3_Rd,
+		ND_6IP_3_Din => ND_6IP_3_Din,
+		ND_6IP_3_Exist => ND_6IP_3_Exist,
+		ND_6IP_3_CLK => ND_6IP_3_CLK,
+		ND_6IP_3_CTRL => ND_6IP_3_CTRL,
+		ND_6IP_5_ND_6IP_4_Rd => ND_6IP_5_ND_6IP_4_Rd,
+		ND_6IP_5_ND_6IP_4_Din => ND_6IP_5_ND_6IP_4_Din,
+		ND_6IP_5_ND_6IP_4_Exist => ND_6IP_5_ND_6IP_4_Exist,
+		ND_6IP_5_ND_6IP_4_CLK => ND_6IP_5_ND_6IP_4_CLK,
+		ND_6IP_5_ND_6IP_4_CTRL => ND_6IP_5_ND_6IP_4_CTRL,
+		ND_6OP_1_Wr => ND_6OP_1_Wr,
+		ND_6OP_1_Dout => ND_6OP_1_Dout,
+		ND_6OP_1_Full => ND_6OP_1_Full,
+		ND_6OP_1_CLK => ND_6OP_1_CLK,
+		ND_6OP_1_CTRL => ND_6OP_1_CTRL,
+		ND_6OP_2_Wr => ND_6OP_2_Wr,
+		ND_6OP_2_Dout => ND_6OP_2_Dout,
+		ND_6OP_2_Full => ND_6OP_2_Full,
+		ND_6OP_2_CLK => ND_6OP_2_CLK,
+		ND_6OP_2_CTRL => ND_6OP_2_CTRL,
+		ND_6OP_3_Wr => ND_6OP_3_Wr,
+		ND_6OP_3_Dout => ND_6OP_3_Dout,
+		ND_6OP_3_Full => ND_6OP_3_Full,
+		ND_6OP_3_CLK => ND_6OP_3_CLK,
+		ND_6OP_3_CTRL => ND_6OP_3_CTRL,
+		PARAM_DT => PARAM_DT,
+		PARAM_LD => PARAM_LD,
+		STOP => STOP,
+		ERROR => ERROR,
+		BLOCK_RD => BLOCK_RD,
+		RST => RST,
+		CLK => CLK
+    );
+  
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_7_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_7_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..dae72f647a1bb3234b3203f081bd70476f786787
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_7_ip_wrapper.vhd
@@ -0,0 +1,145 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_hwn_nd_7_ip_wrapper.vhd
+-- LEAF false
+-- HIER false
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_bunny_static_split2rtl_hwn_nd_7_1_lib;
+use compaandesign_com_bunny_static_split2rtl_hwn_nd_7_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_7_ip_wrapper is
+  port (
+    ND_7IP_6_Rd : out std_logic;
+    ND_7IP_6_Din : in std_logic_vector(7 downto 0);
+    ND_7IP_6_Exist : in std_logic;
+    ND_7IP_6_CLK : out std_logic;
+    ND_7IP_6_CTRL : in std_logic;
+    ND_7IP_7_Rd : out std_logic;
+    ND_7IP_7_Din : in std_logic_vector(7 downto 0);
+    ND_7IP_7_Exist : in std_logic;
+    ND_7IP_7_CLK : out std_logic;
+    ND_7IP_7_CTRL : in std_logic;
+    ND_7IP_8_Rd : out std_logic;
+    ND_7IP_8_Din : in std_logic_vector(7 downto 0);
+    ND_7IP_8_Exist : in std_logic;
+    ND_7IP_8_CLK : out std_logic;
+    ND_7IP_8_CTRL : in std_logic;
+    ND_7OP_1_Wr : out std_logic;
+    ND_7OP_1_Dout : out std_logic_vector(7 downto 0);
+    ND_7OP_1_Full : in std_logic;
+    ND_7OP_1_CLK : out std_logic;
+    ND_7OP_1_CTRL : out std_logic;
+    ND_7OP_1_d1_Wr : out std_logic;
+    ND_7OP_1_d1_Dout : out std_logic_vector(7 downto 0);
+    ND_7OP_1_d1_Full : in std_logic;
+    ND_7OP_1_d1_CLK : out std_logic;
+    ND_7OP_1_d1_CTRL : out std_logic;
+    PARAM_DT : in std_logic_vector(10 downto 0);
+    PARAM_LD : in std_logic;
+    STOP : out std_logic;
+    ERROR : out std_logic;
+    BLOCK_RD : out std_logic;
+    RST : in std_logic;
+    CLK : in std_logic
+  );
+  
+  
+end bunny_static_split2rtl_hwn_nd_7_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_hwn_nd_7_ip_wrapper is
+
+  component bunny_static_split2rtl_hwn_nd_7 is
+	generic (
+		RESET_HIGH : NATURAL := 1;
+		PAR_WIDTH : NATURAL := 16;
+		QUANT : NATURAL := 32;
+		WRAP : BOOLEAN := true;
+		STIM_DIR : STRING := "hwn_nd_7"
+	);
+	port (
+		ND_7IP_6_Rd : out std_logic;
+		ND_7IP_6_Din : in std_logic_vector(7 downto 0);
+		ND_7IP_6_Exist : in std_logic;
+		ND_7IP_6_CLK : out std_logic;
+		ND_7IP_6_CTRL : in std_logic;
+		ND_7IP_7_Rd : out std_logic;
+		ND_7IP_7_Din : in std_logic_vector(7 downto 0);
+		ND_7IP_7_Exist : in std_logic;
+		ND_7IP_7_CLK : out std_logic;
+		ND_7IP_7_CTRL : in std_logic;
+		ND_7IP_8_Rd : out std_logic;
+		ND_7IP_8_Din : in std_logic_vector(7 downto 0);
+		ND_7IP_8_Exist : in std_logic;
+		ND_7IP_8_CLK : out std_logic;
+		ND_7IP_8_CTRL : in std_logic;
+		ND_7OP_1_Wr : out std_logic;
+		ND_7OP_1_Dout : out std_logic_vector(7 downto 0);
+		ND_7OP_1_Full : in std_logic;
+		ND_7OP_1_CLK : out std_logic;
+		ND_7OP_1_CTRL : out std_logic;
+		ND_7OP_1_d1_Wr : out std_logic;
+		ND_7OP_1_d1_Dout : out std_logic_vector(7 downto 0);
+		ND_7OP_1_d1_Full : in std_logic;
+		ND_7OP_1_d1_CLK : out std_logic;
+		ND_7OP_1_d1_CTRL : out std_logic;
+		PARAM_DT : in std_logic_vector(10 downto 0);
+		PARAM_LD : in std_logic;
+		STOP : out std_logic;
+		ERROR : out std_logic;
+		BLOCK_RD : out std_logic;
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+end component;
+
+begin
+
+bunny_static_split2rtl_hwn_nd_7_ip_wrapper_ip : bunny_static_split2rtl_hwn_nd_7
+	generic map (
+		RESET_HIGH => 1,
+		PAR_WIDTH => 1,
+		QUANT => 32,
+		WRAP => true,
+		STIM_DIR => "compaandesign_com/bunny_static_split2rtl/hwn_nd_7/tb/data/"
+	)
+    port map (
+		ND_7IP_6_Rd => ND_7IP_6_Rd,
+		ND_7IP_6_Din => ND_7IP_6_Din,
+		ND_7IP_6_Exist => ND_7IP_6_Exist,
+		ND_7IP_6_CLK => ND_7IP_6_CLK,
+		ND_7IP_6_CTRL => ND_7IP_6_CTRL,
+		ND_7IP_7_Rd => ND_7IP_7_Rd,
+		ND_7IP_7_Din => ND_7IP_7_Din,
+		ND_7IP_7_Exist => ND_7IP_7_Exist,
+		ND_7IP_7_CLK => ND_7IP_7_CLK,
+		ND_7IP_7_CTRL => ND_7IP_7_CTRL,
+		ND_7IP_8_Rd => ND_7IP_8_Rd,
+		ND_7IP_8_Din => ND_7IP_8_Din,
+		ND_7IP_8_Exist => ND_7IP_8_Exist,
+		ND_7IP_8_CLK => ND_7IP_8_CLK,
+		ND_7IP_8_CTRL => ND_7IP_8_CTRL,
+		ND_7OP_1_Wr => ND_7OP_1_Wr,
+		ND_7OP_1_Dout => ND_7OP_1_Dout,
+		ND_7OP_1_Full => ND_7OP_1_Full,
+		ND_7OP_1_CLK => ND_7OP_1_CLK,
+		ND_7OP_1_CTRL => ND_7OP_1_CTRL,
+		ND_7OP_1_d1_Wr => ND_7OP_1_d1_Wr,
+		ND_7OP_1_d1_Dout => ND_7OP_1_d1_Dout,
+		ND_7OP_1_d1_Full => ND_7OP_1_d1_Full,
+		ND_7OP_1_d1_CLK => ND_7OP_1_d1_CLK,
+		ND_7OP_1_d1_CTRL => ND_7OP_1_d1_CTRL,
+		PARAM_DT => PARAM_DT,
+		PARAM_LD => PARAM_LD,
+		STOP => STOP,
+		ERROR => ERROR,
+		BLOCK_RD => BLOCK_RD,
+		RST => RST,
+		CLK => CLK
+    );
+  
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_8_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_8_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..774c4f68e43d40220b6ce183a9b82823131bf271
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_8_ip_wrapper.vhd
@@ -0,0 +1,100 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_hwn_nd_8_ip_wrapper.vhd
+-- LEAF false
+-- HIER false
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_bunny_static_split2rtl_hwn_nd_8_1_lib;
+use compaandesign_com_bunny_static_split2rtl_hwn_nd_8_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_8_ip_wrapper is
+  port (
+    ND_8IP_9_Rd : out std_logic;
+    ND_8IP_9_Din : in std_logic_vector(7 downto 0);
+    ND_8IP_9_Exist : in std_logic;
+    ND_8IP_9_CLK : out std_logic;
+    ND_8IP_9_CTRL : in std_logic;
+    ND_8OP_1_Wr : out std_logic;
+    ND_8OP_1_Dout : out std_logic_vector(7 downto 0);
+    ND_8OP_1_Full : in std_logic;
+    ND_8OP_1_CLK : out std_logic;
+    ND_8OP_1_CTRL : out std_logic;
+    PARAM_DT : in std_logic_vector(10 downto 0);
+    PARAM_LD : in std_logic;
+    STOP : out std_logic;
+    ERROR : out std_logic;
+    BLOCK_RD : out std_logic;
+    RST : in std_logic;
+    CLK : in std_logic
+  );
+  
+  
+end bunny_static_split2rtl_hwn_nd_8_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_hwn_nd_8_ip_wrapper is
+
+  component bunny_static_split2rtl_hwn_nd_8 is
+	generic (
+		RESET_HIGH : NATURAL := 1;
+		PAR_WIDTH : NATURAL := 16;
+		QUANT : NATURAL := 32;
+		WRAP : BOOLEAN := true;
+		STIM_DIR : STRING := "hwn_nd_8"
+	);
+	port (
+		ND_8IP_9_Rd : out std_logic;
+		ND_8IP_9_Din : in std_logic_vector(7 downto 0);
+		ND_8IP_9_Exist : in std_logic;
+		ND_8IP_9_CLK : out std_logic;
+		ND_8IP_9_CTRL : in std_logic;
+		ND_8OP_1_Wr : out std_logic;
+		ND_8OP_1_Dout : out std_logic_vector(7 downto 0);
+		ND_8OP_1_Full : in std_logic;
+		ND_8OP_1_CLK : out std_logic;
+		ND_8OP_1_CTRL : out std_logic;
+		PARAM_DT : in std_logic_vector(10 downto 0);
+		PARAM_LD : in std_logic;
+		STOP : out std_logic;
+		ERROR : out std_logic;
+		BLOCK_RD : out std_logic;
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+end component;
+
+begin
+
+bunny_static_split2rtl_hwn_nd_8_ip_wrapper_ip : bunny_static_split2rtl_hwn_nd_8
+	generic map (
+		RESET_HIGH => 1,
+		PAR_WIDTH => 1,
+		QUANT => 32,
+		WRAP => true,
+		STIM_DIR => "compaandesign_com/bunny_static_split2rtl/hwn_nd_8/tb/data/"
+	)
+    port map (
+		ND_8IP_9_Rd => ND_8IP_9_Rd,
+		ND_8IP_9_Din => ND_8IP_9_Din,
+		ND_8IP_9_Exist => ND_8IP_9_Exist,
+		ND_8IP_9_CLK => ND_8IP_9_CLK,
+		ND_8IP_9_CTRL => ND_8IP_9_CTRL,
+		ND_8OP_1_Wr => ND_8OP_1_Wr,
+		ND_8OP_1_Dout => ND_8OP_1_Dout,
+		ND_8OP_1_Full => ND_8OP_1_Full,
+		ND_8OP_1_CLK => ND_8OP_1_CLK,
+		ND_8OP_1_CTRL => ND_8OP_1_CTRL,
+		PARAM_DT => PARAM_DT,
+		PARAM_LD => PARAM_LD,
+		STOP => STOP,
+		ERROR => ERROR,
+		BLOCK_RD => BLOCK_RD,
+		RST => RST,
+		CLK => CLK
+    );
+  
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_9_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_9_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d04d69a11d039bcfde0b067f087bcb74b4a7cf23
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_9_ip_wrapper.vhd
@@ -0,0 +1,103 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_hwn_nd_9_ip_wrapper.vhd
+-- LEAF false
+-- HIER false
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_bunny_static_split2rtl_hwn_nd_9_1_lib;
+use compaandesign_com_bunny_static_split2rtl_hwn_nd_9_1_lib.all;
+
+entity bunny_static_split2rtl_hwn_nd_9_ip_wrapper is
+  port (
+    rf_brightness : in std_logic_vector(31 downto 0);
+    ND_9IP_10_Rd : out std_logic;
+    ND_9IP_10_Din : in std_logic_vector(7 downto 0);
+    ND_9IP_10_Exist : in std_logic;
+    ND_9IP_10_CLK : out std_logic;
+    ND_9IP_10_CTRL : in std_logic;
+    ND_9OP_1_Wr : out std_logic;
+    ND_9OP_1_Dout : out std_logic_vector(7 downto 0);
+    ND_9OP_1_Full : in std_logic;
+    ND_9OP_1_CLK : out std_logic;
+    ND_9OP_1_CTRL : out std_logic;
+    PARAM_DT : in std_logic_vector(10 downto 0);
+    PARAM_LD : in std_logic;
+    STOP : out std_logic;
+    ERROR : out std_logic;
+    BLOCK_RD : out std_logic;
+    RST : in std_logic;
+    CLK : in std_logic
+  );
+  
+  
+end bunny_static_split2rtl_hwn_nd_9_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_hwn_nd_9_ip_wrapper is
+
+  component bunny_static_split2rtl_hwn_nd_9 is
+	generic (
+		RESET_HIGH : NATURAL := 1;
+		PAR_WIDTH : NATURAL := 16;
+		QUANT : NATURAL := 32;
+		WRAP : BOOLEAN := true;
+		STIM_DIR : STRING := "hwn_nd_9"
+	);
+	port (
+		rf_brightness : in std_logic_vector(31 downto 0);
+		ND_9IP_10_Rd : out std_logic;
+		ND_9IP_10_Din : in std_logic_vector(7 downto 0);
+		ND_9IP_10_Exist : in std_logic;
+		ND_9IP_10_CLK : out std_logic;
+		ND_9IP_10_CTRL : in std_logic;
+		ND_9OP_1_Wr : out std_logic;
+		ND_9OP_1_Dout : out std_logic_vector(7 downto 0);
+		ND_9OP_1_Full : in std_logic;
+		ND_9OP_1_CLK : out std_logic;
+		ND_9OP_1_CTRL : out std_logic;
+		PARAM_DT : in std_logic_vector(10 downto 0);
+		PARAM_LD : in std_logic;
+		STOP : out std_logic;
+		ERROR : out std_logic;
+		BLOCK_RD : out std_logic;
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+end component;
+
+begin
+
+bunny_static_split2rtl_hwn_nd_9_ip_wrapper_ip : bunny_static_split2rtl_hwn_nd_9
+	generic map (
+		RESET_HIGH => 1,
+		PAR_WIDTH => 1,
+		QUANT => 32,
+		WRAP => true,
+		STIM_DIR => "compaandesign_com/bunny_static_split2rtl/hwn_nd_9/tb/data/"
+	)
+    port map (
+		rf_brightness => rf_brightness,
+		ND_9IP_10_Rd => ND_9IP_10_Rd,
+		ND_9IP_10_Din => ND_9IP_10_Din,
+		ND_9IP_10_Exist => ND_9IP_10_Exist,
+		ND_9IP_10_CLK => ND_9IP_10_CLK,
+		ND_9IP_10_CTRL => ND_9IP_10_CTRL,
+		ND_9OP_1_Wr => ND_9OP_1_Wr,
+		ND_9OP_1_Dout => ND_9OP_1_Dout,
+		ND_9OP_1_Full => ND_9OP_1_Full,
+		ND_9OP_1_CLK => ND_9OP_1_CLK,
+		ND_9OP_1_CTRL => ND_9OP_1_CTRL,
+		PARAM_DT => PARAM_DT,
+		PARAM_LD => PARAM_LD,
+		STOP => STOP,
+		ERROR => ERROR,
+		BLOCK_RD => BLOCK_RD,
+		RST => RST,
+		CLK => CLK
+    );
+  
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_register_rf_ip_wrapper.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_register_rf_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8ff3301994cd7b6de6ce8f4303ce50347bbe38c7
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_register_rf_ip_wrapper.vhd
@@ -0,0 +1,105 @@
+-------------------------------------------------------------------------------
+-- bunny_static_split2rtl_register_rf_ip_wrapper.vhd
+-- LEAF true
+-- HIER false
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+ -- library UNISIM;
+ -- use UNISIM.VCOMPONENTS.ALL;
+
+library compaandesign_com_bunny_static_split2rtl_register_rf_1_lib;
+use compaandesign_com_bunny_static_split2rtl_register_rf_1_lib.all;
+
+entity bunny_static_split2rtl_register_rf_ip_wrapper is
+  port (
+    address : in std_logic_vector(18 downto 0);
+    read_data : out std_logic_vector(31 downto 0);
+    read_en : in std_logic;
+    write_en : in std_logic;
+    write_data : in std_logic_vector(31 downto 0);
+    pci_clk : in std_logic;
+    commit_rf_read_data : in std_logic_vector(31 downto 0);
+    commit_rf_read_en : out std_logic;
+    commit_rf_write_en : out std_logic;
+    commit_rf_write_data : out std_logic_vector(31 downto 0);
+    brightness_rf_read_data : in std_logic_vector(31 downto 0);
+    brightness_rf_read_en : out std_logic;
+    brightness_rf_write_en : out std_logic;
+    brightness_rf_write_data : out std_logic_vector(31 downto 0);
+    count_rf_read_data : in std_logic_vector(31 downto 0);
+    count_rf_read_en : out std_logic;
+    count_rf_write_en : out std_logic;
+    count_rf_write_data : out std_logic_vector(31 downto 0);
+    RST : in std_logic;
+    CLK : in std_logic
+  );
+  
+  
+end bunny_static_split2rtl_register_rf_ip_wrapper;
+
+architecture STRUCTURE of bunny_static_split2rtl_register_rf_ip_wrapper is
+
+  component register_rf is
+	generic (
+		C_commit_rf_address : std_logic_vector := B"0000000000000000000";
+		C_brightness_rf_address : std_logic_vector := B"0000000000000000100";
+		C_count_rf_address : std_logic_vector := B"0000000000000001000"
+	);
+	port (
+		address : in std_logic_vector(18 downto 0);
+		read_data : out std_logic_vector(31 downto 0);
+		read_en : in std_logic;
+		write_en : in std_logic;
+		write_data : in std_logic_vector(31 downto 0);
+		pci_clk : in std_logic;
+		commit_rf_read_data : in std_logic_vector(31 downto 0);
+		commit_rf_read_en : out std_logic;
+		commit_rf_write_en : out std_logic;
+		commit_rf_write_data : out std_logic_vector(31 downto 0);
+		brightness_rf_read_data : in std_logic_vector(31 downto 0);
+		brightness_rf_read_en : out std_logic;
+		brightness_rf_write_en : out std_logic;
+		brightness_rf_write_data : out std_logic_vector(31 downto 0);
+		count_rf_read_data : in std_logic_vector(31 downto 0);
+		count_rf_read_en : out std_logic;
+		count_rf_write_en : out std_logic;
+		count_rf_write_data : out std_logic_vector(31 downto 0);
+		RST : in std_logic;
+		CLK : in std_logic
+	);
+end component;
+
+begin
+
+bunny_static_split2rtl_register_rf_ip_wrapper_ip : register_rf
+	generic map (
+		C_commit_rf_address => B"0000000000000000000",
+		C_brightness_rf_address => B"0000000000000000100",
+		C_count_rf_address => B"0000000000000001000"
+	)
+    port map (
+		address => address,
+		read_data => read_data,
+		read_en => read_en,
+		write_en => write_en,
+		write_data => write_data,
+		pci_clk => pci_clk,
+		commit_rf_read_data => commit_rf_read_data,
+		commit_rf_read_en => commit_rf_read_en,
+		commit_rf_write_en => commit_rf_write_en,
+		commit_rf_write_data => commit_rf_write_data,
+		brightness_rf_read_data => brightness_rf_read_data,
+		brightness_rf_read_en => brightness_rf_read_en,
+		brightness_rf_write_en => brightness_rf_write_en,
+		brightness_rf_write_data => brightness_rf_write_data,
+		count_rf_read_data => count_rf_read_data,
+		count_rf_read_en => count_rf_read_en,
+		count_rf_write_en => count_rf_write_en,
+		count_rf_write_data => count_rf_write_data,
+		RST => RST,
+		CLK => CLK
+    );
+  
+end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/bunny_static_split/src/vhdl/system_ext_TB.vhd b/applications/compaan/libraries/bunny_static_split/src/vhdl/system_ext_TB.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..fa44f5565c9a5a9c080a5f835f07eeb52eb92033
--- /dev/null
+++ b/applications/compaan/libraries/bunny_static_split/src/vhdl/system_ext_TB.vhd
@@ -0,0 +1,421 @@
+-- System TestBench; automatically generated by KpnMapper
+-- Use this file to test the system generated by XPS
+-- The interface of the tested System includes only the FIFO interfaces
+-- declared as external interfaces and not the FIFO interfaces connected
+-- to platform FIFOs
+-- To generate a System with complete interface select the *noboard* platform option
+-- 
+-- =====================================================================================
+-- To use this testbench file you have to:
+--   1. Set propper Time-Out interval (constant TIMEOUT)
+--   2. If you read stimuli from files, provide a path to the directory that contains the stimuli files (constant STIM_DIR)
+--   3. For each input select whether stimuli is read from a file (default) or from a table (see processes *_STIM_DRV)
+--   4. For each output select whether stimuli is read from a file (default) or from a table (see processes *_STIM_CMP)
+--   5. For each stimuli that is read from a table fill the stimuli data in the table (constant *_STIM)
+-- =====================================================================================
+-- 
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library std;
+use std.textio.all;
+
+entity system_ext_TB is
+end system_ext_TB;
+
+architecture RTL of system_ext_TB is
+
+    constant CLK_PERIOD   : TIME    := 10 ns;            -- Period of the system clock
+    constant RESET_LENGTH : natural := 5;                -- Reset duration [clock cycles]
+    constant STIM_DELAY   : natural := RESET_LENGTH + 5; -- When stimuli supply starts [clock cycles]
+    --
+    -- Set Time-0ut interval sufficienly long for your application to complete
+    constant TIMEOUT : natural := 10000000;    -- Time-Out [clock cycles]
+    --
+    constant STIM_DIR        : string := "D:/Bureaublad/Astron/Bijbaan/compaan/workspace/bunny_static_split/vhdl_altera/";   -- Provide here the path to your stimuli files directory
+    -- Input stimuli files: to provide data streams to input FIFOs
+    constant STIM_FILE_data_in    : string := "STIM_FILE_data_in.txt";
+    constant STIM_FILE_data_out    : string := "STIM_FILE_data_out.txt";
+
+    signal   ENDSIM       : boolean := false;    -- Simulation has finished
+    signal   ENDSTIM_IN   : boolean := false;    -- All input stimuli has been sent
+    signal   ENDSTIM_OUT  : boolean := false;    -- All expected data has been received
+    signal   ENDTIMEOUT   : boolean := false;    -- Simulation Time-Out has occured
+    signal   timeout_cntr : natural;
+    signal   ERROR_SYS    : boolean := false;    -- Error: Some of te system nodes indicated error
+    signal   ERROR_OUT    : boolean := false;    -- Error: Detected output data differs from the expected output data
+    signal   FIRST_ERROR  : time;                -- The time when the first error occured
+    signal   ENDSTOP      : boolean := false;    -- All system nodes have flagged 'Stop'
+
+    -- 
+    -- Component Under Test
+    component bunny_static_split is
+    port (
+        -- FIFO_In Interface: data_in
+        data_in_Data    : in  std_logic_vector(63 downto 0);  
+        data_in_Control : in  std_logic;  
+        data_in_Read    : out std_logic;  
+        data_in_Exists  : in  std_logic;  
+
+        -- FIFO_Out Interface: data_out
+        data_out_Data    : out std_logic_vector(63 downto 0);  
+        data_out_Control : out std_logic;  
+        data_out_Write   : out std_logic;  
+        data_out_Full    : in  std_logic;  
+
+        TEST_STOP : out std_logic_vector(13 downto 0);  
+        TEST_ERROR : out std_logic_vector(13 downto 0);  
+        TEST_FIFO_FULL : out std_logic_vector(18 downto 0);  
+        TEST_BLOCK_RD : out std_logic_vector(13 downto 0);  
+        address : in  std_logic_vector(18 downto 0);  
+        read_data : out std_logic_vector(31 downto 0);  
+        read_en : in  std_logic;  
+        write_en : in  std_logic;  
+        write_data : in  std_logic_vector(31 downto 0);  
+        pci_clk : in  std_logic;  
+        --
+        KPN_CLK              : in  std_logic;
+        KPN_RST              : in  std_logic
+    );
+    end component;
+    -- 
+    signal RST      : STD_LOGIC := '0';
+    signal CLK      : STD_LOGIC := '0';
+    -- 
+    type FIFO_SRC_REC is record
+        Data        : integer;
+        Control     : std_logic;
+        Read        : std_logic;
+        Exists      : std_logic;
+        -- 
+        Count       : natural;
+        Done        : boolean;
+    end record;
+    -- 
+    type FIFO_SNK_REC is record
+        Data        : integer;
+        Control     : std_logic;
+        Write       : std_logic;
+        Full        : std_logic;
+        -- 
+        Count       : natural;
+        Done        : boolean;
+        Error       : boolean;
+        First_error : time;
+    end record;
+    -- 
+    signal data_in    : FIFO_SRC_REC;
+    signal data_out    : FIFO_SNK_REC;
+    -- 
+    signal data_in_Data           : std_logic_vector(63 downto 0);
+    signal data_out_Data           : std_logic_vector(63 downto 0);
+    signal TEST_STOP           : std_logic_vector(13 downto 0);
+    signal TEST_ERROR           : std_logic_vector(13 downto 0);
+    signal TEST_FIFO_FULL           : std_logic_vector(18 downto 0);
+    signal TEST_BLOCK_RD           : std_logic_vector(13 downto 0);
+    signal address           : std_logic_vector(18 downto 0);
+    signal read_data           : std_logic_vector(31 downto 0);
+    signal read_en           : std_logic;
+    signal write_en           : std_logic;
+    signal write_data           : std_logic_vector(31 downto 0);
+    signal pci_clk           : std_logic;
+    --
+    -- record keeping values of input and output stimuli
+    type STIM_REC is record
+        Data    : integer;
+        Control : std_logic;
+    end record;
+    --
+    -- Function that reads a STIM_REC from a (stimuli) file
+    impure function FREAD_STIM(file F : TEXT) return STIM_REC is
+        variable VECTOR    : STIM_REC;
+        variable IN_LINE   : LINE;
+    begin
+        readline(F ,IN_LINE);
+        read(IN_LINE, VECTOR.Data);
+        deallocate(IN_LINE);
+        VECTOR.Control := '0';    -- Control bit is not used at the moment
+        return VECTOR;
+    end;
+    --
+    -- table of records
+    type STIM_ARRAY is array(positive range <>) of STIM_REC;
+    --
+    -- Stimuli can be read either from a file or from the constant tables below
+    -- If you will use constant tables, uncomment below those you need
+--    constant data_in_STIM : STIM_ARRAY := (
+--    -- Provide your stimuli here
+--    -- ( Data, Control),
+--    -- e.g. (  0, '0'),
+--    -- e.g. (  0, '0') 
+--    );
+    --
+--    constant data_out_STIM : STIM_ARRAY := (
+--    -- Provide your stimuli here
+--    -- ( Data, Control),
+--    -- e.g. (  0, '0'),
+--    -- e.g. (  0, '0') 
+--    );
+    --
+begin
+    --
+    -- =============================================
+    -- = System Under Test 
+    -- =============================================
+    SUT : bunny_static_split port map(
+        --
+        data_in_Data    => data_in_Data    ,
+        data_in_Control => data_in.Control ,
+        data_in_Read    => data_in.Read    ,
+        data_in_Exists  => data_in.Exists  ,
+        --
+        data_out_Data    => data_out_Data    ,
+        data_out_Control => data_out.Control ,
+        data_out_Write   => data_out.Write   ,
+        data_out_Full    => data_out.Full    ,
+        TEST_STOP    => TEST_STOP    ,
+        TEST_ERROR    => TEST_ERROR    ,
+        TEST_FIFO_FULL    => TEST_FIFO_FULL    ,
+        TEST_BLOCK_RD    => TEST_BLOCK_RD    ,
+        address      => address    ,
+        read_data    => read_data    ,
+        read_en      => read_en    ,
+        write_en      => write_en    ,
+        write_data      => write_data    ,
+        pci_clk      => pci_clk    ,
+        --
+        KPN_CLK              => CLK,
+        KPN_RST              => RST   
+    );
+    --
+    pci_clk <= CLK;
+    --
+    data_in_Data      <= STD_LOGIC_VECTOR(TO_SIGNED(data_in.Data,   data_in_Data'Length));
+    data_out.Data      <= TO_INTEGER(SIGNED(data_out_Data));
+
+    -- Adjust these values to changes values in the Register file to change parameters and shmem
+reg_file : process    
+    variable read_in : std_logic_vector(31 downto 0);
+begin	    	
+    address <= (others => '0');
+    write_en <= '0';
+    read_en <= '0';
+    address <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,19));
+    write_data <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,32));
+
+-- wait for 100ns;	
+--     address <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,19));
+--     write_data <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,32));
+--     wait for 1*CLK_PERIOD;
+--     write_en <= '1';
+--     wait for 2*CLK_PERIOD;
+--     write_en <= '0';
+--     wait for 1*CLK_PERIOD;
+--     --read_en <= '1';
+--     wait for 2*CLK_PERIOD;
+--     --read_en <= '0';
+--     wait for 1*CLK_PERIOD;
+--     wait for 300ns;	
+    wait;	
+end process;
+
+    --
+    -- Stimuli Driver for input stream : data_in
+    data_in_STIM_DRV : process
+        variable VECTOR    : STIM_REC;
+        file     STIM_FILE : TEXT open READ_MODE is STIM_DIR&STIM_FILE_data_in;
+    begin
+        data_in.Exists <= '0';
+        data_in.Count  <=  0;
+        data_in.Done   <=  false;
+        wait for STIM_DELAY*CLK_PERIOD;
+        wait until rising_edge(CLK);
+----------------------------------------------
+--        -- Uncomment if stimuli for data_in is read from a constant tables
+--        for i in data_in_STIM'range loop
+--            VECTOR:= data_in_STIM(i);
+----------------------------------------------
+        -- Uncomment if stimuli for data_in is read from a file
+        while not( endfile(STIM_FILE)) loop
+            VECTOR := FREAD_STIM(STIM_FILE);
+--------------------------------------------
+            data_in.Data    <= VECTOR.Data;
+            data_in.Control <= VECTOR.Control;
+            data_in.Exists  <= '1';
+            L1: loop
+                wait until rising_edge(CLK);
+                exit L1 when (data_in.Read = '1');
+            end loop L1;
+            data_in.Count <= data_in.Count + 1;
+        end loop;
+        data_in.Exists <= '0';
+        data_in.Done <= true;
+        wait for 10*CLK_PERIOD;
+        wait;
+    end process;
+    --
+    ENDSTIM_IN <= data_in.Done;
+    --
+    -- Stimuli Comparator for output stream data_out
+    data_out_STIM_CMP : process
+        variable VECTOR     : STIM_REC;
+        file     STIM_FILE  : TEXT open READ_MODE is STIM_DIR&STIM_FILE_data_out;
+    begin
+        data_out.Full  <= '1';
+        data_out.Count <= 0;
+        data_out.Done  <= false;
+        data_out.Error <= false;
+        wait for STIM_DELAY*CLK_PERIOD;
+        wait until rising_edge(CLK);
+----------------------------------------------
+--        -- Uncomment if stimuli for data_out is read from a constant tables
+--        for i in data_out_STIM'range loop
+--            VECTOR := data_out_STIM(i);
+----------------------------------------------
+        -- Uncomment if stimuli for data_out is read from a file
+        while not( endfile(STIM_FILE)) loop
+            VECTOR := FREAD_STIM(STIM_FILE);
+----------------------------------------------
+            --
+            data_out.Full  <= '0';
+            L1: loop
+                wait until rising_edge(CLK);
+                exit L1 when (data_out.Write = '1');
+            end loop L1;
+            data_out.Count <= data_out.Count + 1;
+            if (data_out.Data /= VECTOR.Data) then
+                report "TB_ERROR: Output 'data_out': the detected value " & integer'image(data_out.Data) & " differs from the expected value " & integer'image(VECTOR.Data) & "!!! (@time " & time'image(now) & ")."
+                severity WARNING;
+                if (not data_out.Error) then
+                    data_out.First_error <= now;
+                end if;
+                data_out.Error <= true;
+            end if;
+        end loop;
+        data_out.Full  <= '1';
+        data_out.Done <= true;
+        wait for 10*CLK_PERIOD;
+        wait;
+    end process;
+    --
+    ENDSTIM_OUT <= data_out.Done;
+    ERROR_OUT   <= data_out.Error;
+    --
+    -- Record the time when the first error occures
+    FIRST_ERROR_TIME : process
+    begin
+        wait until (ERROR_OUT'event and ERROR_OUT=true) or (ERROR_SYS'event and ERROR_SYS=true);
+        FIRST_ERROR <= now;
+        wait;
+    end process;
+    --
+--=============================================
+--= All Nodes stopped ?
+--=============================================
+	process(test_stop)
+		variable s : std_logic;
+		variable e : std_logic;
+	begin
+	s := '1';
+	e := '0';
+	--
+	for i in 0 to TEST_ERROR'Length-1 loop
+		s := s and test_stop(i);
+		e := e or  test_error(i);
+	end loop;
+	--
+		ENDSTOP   <= (s = '1');
+		ERROR_SYS <= (e = '1');
+	--
+	end process;
+    -- Timeout counter
+    TO_CTRL : process(CLK)
+    begin
+        if (rising_edge(CLK)) then
+            if (RST = '1') then
+                timeout_cntr <= 0;
+            else
+                if (timeout_cntr = TIMEOUT) then
+                    ENDTIMEOUT <= true;
+                else
+                    timeout_cntr <= timeout_cntr + 1;
+                end if;
+            end if;
+        end if;
+    end process;
+    --
+    -- Simulation control
+    ENDSIM <= (ENDSTIM_IN and ENDSTOP and ENDSTIM_OUT) or ENDTIMEOUT;
+    --
+    PRINT_REPORT : process
+        variable ERROR_CODE : natural;
+        variable l          : line;
+    begin
+       -- write(l, "***TB_REPOT: Simulation in progress...");
+        writeline(output,l);
+        wait until ENDSIM=true;
+       -- write(l, "***TB_REPOT: Simulation END.");
+        writeline(output,l);
+        ERROR_CODE := 0;
+        -- 
+        if (ENDTIMEOUT) then
+            ERROR_CODE := ERROR_CODE + 1;
+            write(l, "***TB_REPOT: [TIMEOUT] Simulation terminated by a TIMEOUT after " & integer'image(timeout_cntr) & " clock cycles.");
+            writeline(output,l);
+            write(l, "*** ENDSTIM_IN  = " & boolean'image(ENDSTIM_IN) );
+            writeline(output,l);   
+            write(l, "*** ENDSTIM_OUT = " & boolean'image(ENDSTIM_OUT) );
+            writeline(output,l);   
+            for i in 0 to TEST_FIFO_FULL'Length-1 loop
+               if (TEST_FIFO_FULL(i)='1') then
+                  write(l, "*** TEST_FIFO_FULL(" & integer'image(i) & ") ");
+                  writeline(output,l);
+               end if;
+            end loop;
+        end if;
+        -- 
+        if (ERROR_OUT or ERROR_SYS) then
+            ERROR_CODE := ERROR_CODE + 2;
+            write(l, "***TB_REPOT: [ERROR] Simulation terminated in " & integer'image(timeout_cntr) & " cycles with ERRORS!!! First error occured at time " & time'image(FIRST_ERROR) & ".");
+            writeline(output,l);
+         --   write(l, "***TB_REPOT: [ERROR]   Flags ERROR = b");
+         --   write(l, test_error, RIGHT, test_error'Length);
+         --   writeline(output,l);
+        end if;
+        -- 
+        write(l, "***TB_REPOT: [ERROR_CODE=" & integer'image(ERROR_CODE) & "]");
+        writeline(output,l);
+        -- 
+        if (ERROR_CODE = 0) then
+            write(l, "***TB_REPOT: [OK] Simulation completed successfully in " & integer'image(timeout_cntr) & " cycles !!!");
+            writeline(output,l);
+         --   write(l, "None of the processors flagged ERROR. ");
+            writeline(output,l);
+        end if;
+        wait;
+    end process;
+    --
+    -- CLK generator
+    CLK_GEN: process
+    begin
+        if (ENDSIM=false) then
+            CLK <= '0';
+            wait for CLK_PERIOD/2;
+            CLK <= '1';
+            wait for CLK_PERIOD/2;
+        else
+            wait;
+        end if;
+    end process;
+    --
+    -- RESET generator
+    RST_GEN: process
+    begin
+        RST <='1';
+        wait for RESET_LENGTH*CLK_PERIOD;
+        RST <='0';
+        wait;
+    end process;
+    --
+end RTL;