diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index a2b2573d3fe5c47537a708c42824a4c3f5374a5c..0b7b33c4a041a42e6eac6d535d400c2fd6ec483b 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -174,10 +174,13 @@ ARCHITECTURE str OF unb2_test IS
CONSTANT c_data_w_64 : NATURAL := c_xgmii_data_w; -- 10GbE
-- ddr
+ CONSTANT c_ddr_ctlr_data_w : NATURAL := func_tech_ddr_ctlr_data_w(g_ddr_MB_I); -- = 576, assume both MB_I and MB_II use the same ctlr_data_w
CONSTANT c_ddr_dp_data_w : NATURAL := 144; -- DDR4 with dq_w = 72, rsl = 8 so ctrl data width = 576 and therefore the mixed width FIFO ratio is 576 /144 = 4
- CONSTANT c_ddr_dp_seq_dat_w : NATURAL := 17; -- >= 1, test sequence data width. Choose g_dp_seq_dat_w <= g_dp_data_w. The seq data gets replicated to fill g_dp_data_w.
- CONSTANT c_ddr_dp_fifo_depth : NATURAL := 2048; -- >= 2048, write FIFO depth and read FIFO depth at DP side of the FIFOs
+ CONSTANT c_ddr_dp_seq_dat_w : NATURAL := 16; -- >= 1, test sequence data width. Choose c_ddr_dp_seq_dat_w <= c_ddr_dp_data_w. The seq data gets replicated to fill c_ddr_dp_data_w.
+ CONSTANT c_ddr_dp_wr_fifo_depth : NATURAL := 256 * (c_ddr_ctlr_data_w/c_ddr_dp_data_w); -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) to make full use of M9K which have at least 256 words
+ CONSTANT c_ddr_dp_rd_fifo_depth : NATURAL := 256 * (c_ddr_ctlr_data_w/c_ddr_dp_data_w); -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) or factors of 2 more to fit max number of read bursts
CONSTANT c_ddr_db_buf_nof_data : NATURAL := 1024;
+ CONSTANT c_ddr_mixed_width_ratio : NATURAL := ratio2(c_ddr_ctlr_data_w, c_ddr_dp_data_w);
-- Block generator constants
CONSTANT c_bg_block_size : NATURAL := 900;
@@ -373,6 +376,15 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL dp_offload_tx_10GbE_src_in_arr : t_dp_siso_arr(c_nof_streams_10GbE-1 DOWNTO 0);
SIGNAL dp_offload_rx_10GbE_snk_in_arr : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
SIGNAL dp_offload_rx_10GbE_snk_out_arr : t_dp_siso_arr(c_nof_streams_10GbE-1 DOWNTO 0);
+
+ -- DDR4 MB_I and MB_II
+ SIGNAL dbg_c_ddr_ctlr_data_w : NATURAL := c_ddr_ctlr_data_w;
+ SIGNAL dbg_c_ddr_dp_data_w : NATURAL := c_ddr_dp_data_w;
+ SIGNAL dbg_c_ddr_dp_seq_dat_w : NATURAL := c_ddr_dp_seq_dat_w;
+ SIGNAL dbg_c_ddr_dp_wr_fifo_depth : NATURAL := c_ddr_dp_wr_fifo_depth;
+ SIGNAL dbg_c_ddr_dp_rd_fifo_depth : NATURAL := c_ddr_dp_rd_fifo_depth;
+ SIGNAL dbg_c_ddr_db_buf_nof_data : NATURAL := c_ddr_db_buf_nof_data;
+ SIGNAL dbg_c_ddr_mixed_width_ratio : NATURAL := c_ddr_mixed_width_ratio;
SIGNAL reg_io_ddr_MB_I_mosi : t_mem_mosi;
SIGNAL reg_io_ddr_MB_I_miso : t_mem_miso;
@@ -965,23 +977,30 @@ BEGIN
END GENERATE;
+ -----------------------------------------------------------------------------
+ -- Interface : DDR4 MB_I and MB_II
+ -----------------------------------------------------------------------------
+ ASSERT c_ddr_mixed_width_ratio>0 AND is_pow2(c_ddr_mixed_width_ratio) REPORT "unb2_test: DDR4 data widths are not an integer ratio" SEVERITY FAILURE;
+ ASSERT func_tech_ddr_ctlr_data_w(g_ddr_MB_I)=func_tech_ddr_ctlr_data_w(g_ddr_MB_II) REPORT "unb2_test: DDR4 MB_I and MB_II must have the same ctlr data widths" SEVERITY FAILURE;
+
gen_stream_MB_I : IF c_use_MB_I = TRUE GENERATE
u_mms_io_ddr_diag : ENTITY io_ddr_lib.mms_io_ddr_diag
GENERIC MAP (
-- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
- g_dp_data_w => c_ddr_dp_data_w, -- DP data width, func_tech_ddr_ctlr_data_w(g_io_tech_ddr)/g_dp_data_w must be a power of 2 due to the mixed width FIFO
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w, -- >= 1, test sequence data width. Choose g_dp_seq_dat_w <= g_dp_data_w. The seq data gets replicated to fill g_dp_data_w.
- g_dp_fifo_depth => c_ddr_dp_fifo_depth, -- >= 2048, write FIFO depth and read FIFO depth at DP side of the FIFOs
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
-- IO_DDR
- g_io_tech_ddr => g_ddr_MB_I,
+ g_io_tech_ddr => g_ddr_MB_I,
-- DIAG data buffer
- g_db_use_db => FALSE,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ g_db_use_db => FALSE,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
)
PORT MAP (
---------------------------------------------------------------------------
@@ -1048,9 +1067,10 @@ BEGIN
g_sim_model_ddr => g_sim_model_ddr,
g_technology => g_technology,
- g_dp_data_w => c_ddr_dp_data_w, -- DP data width, func_tech_ddr_ctlr_data_w(g_io_tech_ddr)/g_dp_data_w must be a power of 2 due to the mixed width FIFO
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w, -- >= 1, test sequence data width. Choose g_dp_seq_dat_w <= g_dp_data_w. The seq data gets replicated to fill g_dp_data_w.
- g_dp_fifo_depth => c_ddr_dp_fifo_depth, -- >= 2048, write FIFO depth and read FIFO depth at DP side of the FIFOs
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
-- IO_DDR
g_io_tech_ddr => g_ddr_MB_II,