From 2306c606e73710a53ef8c27796722ae9306c037d Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Mon, 8 May 2023 16:58:37 +0200
Subject: [PATCH] Support g_fifo_af_xon
---
libraries/base/dp/src/vhdl/dp_fifo_fill.vhd | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd
index c77ea4adc2..f3e379027b 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd
@@ -48,7 +48,8 @@ ENTITY dp_fifo_fill IS
g_use_complex : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
g_fifo_fill : NATURAL := 0;
g_fifo_size : NATURAL := 256; -- (32+2) * 256 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin : NATURAL := 4; -- Nof words below max (full) at which fifo is considered almost full
+ g_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full for snk_out.ready
+ g_fifo_af_xon : NATURAL := 0; -- >=0, Nof words below max (full) at which fifo is considered almost full for snk_out.xon
g_fifo_rl : NATURAL := 1 -- use RL=0 for internal show ahead FIFO, default use RL=1 for internal normal FIFO
);
PORT (
@@ -95,6 +96,7 @@ BEGIN
g_fifo_fill => g_fifo_fill,
g_fifo_size => g_fifo_size,
g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
g_fifo_rl => g_fifo_rl
)
PORT MAP (
--
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