diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
index 21f703cf9f691ffcbc7f16d9813d6ba0e873ff6b..24bb76e9513ce0d4c81e2494110c1d5b93f66b34 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
@@ -46,6 +46,7 @@
-- > as 7 # default
-- > as 12 # for detailed debugging
-- > run -a
+-- Takes about 45 m
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib, lofar2_unb2b_sdp_station_lib;
@@ -87,6 +88,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_bf IS
CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
+ CONSTANT c_stat_data_sz : NATURAL := c_longword_sz/c_word_sz; -- = 2
CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value
CONSTANT c_lo_factor : REAL := 1.0 - c_percentage; -- lower boundary
@@ -109,7 +111,8 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_bf IS
CONSTANT c_exp_beamlet_power_sp_0 : REAL := c_exp_wg_power_sp_0 * c_exp_sp_beamlet_power_ratio;
TYPE t_real_arr IS ARRAY (INTEGER RANGE <>) OF REAL;
- TyPE t_slv_64_subbands_arr IS ARRAY (INTEGER RANGE <>) OF t_slv_64_arr(0 TO c_sdp_S_sub_bf);
+ TYPE t_slv_64_subbands_arr IS ARRAY (INTEGER RANGE <>) OF t_slv_64_arr(0 TO c_sdp_N_sub);
+ TYPE t_slv_64_beamlets_arr IS ARRAY (INTEGER RANGE <>) OF t_slv_64_arr(0 TO c_sdp_S_sub_bf);
-- MM
CONSTANT c_mm_file_reg_ppsh : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
@@ -127,31 +130,36 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_bf IS
SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
-- WG
- SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+ SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
-- WPFB
- SIGNAL sp_subband_powers_arr2 : t_slv_64_subbands_arr(c_sdp_N_beamsets*c_sdp_N_pol-1 DOWNTO 0); -- [sp][sub]
+ SIGNAL sp_subband_powers_arr2 : t_slv_64_subbands_arr(c_sdp_N_pol-1 DOWNTO 0); -- [sp][sub]
- SIGNAL sp_beamlet_powers_arr2 : t_slv_64_subbands_arr(c_sdp_N_beamsets*c_sdp_N_pol-1 DOWNTO 0); -- [sp][sub]
+ SIGNAL sp_beamlet_powers_arr2 : t_slv_64_beamlets_arr(c_sdp_N_beamsets*c_sdp_N_pol_bf-1 DOWNTO 0); -- [sp][sub]
SIGNAL sp_beamlet_power_0 : REAL;
- SIGNAL sp_beamlet_power_sum : t_real_arr(c_sdp_N_beamsets*c_sdp_N_pol-1 DOWNTO 0) := (OTHERS=>0.0);
+ SIGNAL sp_beamlet_power_sum : t_real_arr(c_sdp_N_beamsets*c_sdp_N_pol_bf-1 DOWNTO 0) := (OTHERS=>0.0);
SIGNAL sp_beamlet_power_sum_0 : REAL;
SIGNAL sp_beamlet_power_ratio_0 : REAL;
SIGNAL sp_beamlet_power_sum_ratio_0 : REAL;
SIGNAL sp_beamlet_power_leakage_sum_0 : REAL;
-- 10GbE
- CONSTANT c_exp_beamlet_index : NATURAL := NATURAL(c_subband_sp_0) * c_sdp_N_pol;
- CONSTANT c_exp_beamlet_re : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"81"; --Derived from simulation
- CONSTANT c_exp_beamlet_im : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"7F"; --Derived from simulation
+ CONSTANT c_exp_beamlet_index : NATURAL := NATURAL(c_subband_sp_0) * c_sdp_N_pol_bf;
+ CONSTANT c_exp_beamlet_re : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"81"; -- = -127, derived from simulation
+ CONSTANT c_exp_beamlet_im : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"7F"; -- = +127, derived from simulation
- SIGNAL beamlet_arr2_re : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block-1 DOWNTO 0);
- SIGNAL beamlet_arr2_im : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block-1 DOWNTO 0);
+ SIGNAL dbg_beamlet_arr_re : t_slv_8_arr(c_sdp_cep_nof_blocks_per_packet-1 DOWNTO 0); -- [3:0]
+ SIGNAL dbg_beamlet_arr_im : t_slv_8_arr(c_sdp_cep_nof_blocks_per_packet-1 DOWNTO 0); -- [3:0]
+ SIGNAL dbg_beamlet_cnt : NATURAL;
+ SIGNAL dbg_beamlet_valid : STD_LOGIC;
- SIGNAL tr_10GbE_src_out : t_dp_sosi;
- SIGNAL tr_ref_clk_312 : STD_LOGIC := '0';
- SIGNAL tr_ref_clk_156 : STD_LOGIC := '0';
- SIGNAL tr_ref_rst_156 : STD_LOGIC := '0';
+ SIGNAL beamlet_arr2_re : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf-1 DOWNTO 0); -- [488 * 2-1:0] = [975:0]
+ SIGNAL beamlet_arr2_im : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf-1 DOWNTO 0); -- [488 * 2-1:0] = [975:0]
+
+ SIGNAL tr_10GbE_src_out : t_dp_sosi;
+ SIGNAL tr_ref_clk_312 : STD_LOGIC := '0';
+ SIGNAL tr_ref_clk_156 : STD_LOGIC := '0';
+ SIGNAL tr_ref_rst_156 : STD_LOGIC := '0';
-- DUT
SIGNAL ext_clk : STD_LOGIC := '0';
@@ -192,7 +200,6 @@ BEGIN
eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
SA_CLK <= NOT SA_CLK AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz)
- pps_rst <= '0' AFTER c_ext_clk_period*2;
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
@@ -316,13 +323,12 @@ BEGIN
VARIABLE v_sp_beamlet_power : REAL;
VARIABLE v_sp_subband_power : REAL;
VARIABLE v_W, v_T, v_U, v_S, v_B : NATURAL; -- array indicies
+ VARIABLE v_re, v_im : INTEGER;
+ VARIABLE v_re_exp, v_im_exp : INTEGER;
BEGIN
-- Wait for DUT power up after reset
WAIT FOR 1 us;
-
- proc_common_wait_until_hi_lo(ext_clk, ext_pps);
-
----------------------------------------------------------------------------
-- Enable UDP offload (dp_xonoff) of beamset 0
----------------------------------------------------------------------------
@@ -332,11 +338,15 @@ BEGIN
----------------------------------------------------------------------------
-- Enable BS
----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ -- Release PPS pulser, to get first PPS now and to start BSN source
+ WAIT FOR 1 us;
+ pps_rst <= '0';
+
----------------------------------------------------------------------------
-- Enable WG
----------------------------------------------------------------------------
@@ -372,17 +382,18 @@ BEGIN
---------------------------------------------------------------------------
-- . the subband statistics are c_wpfb_sim.stat_data_sz = 2 word power values.
-- . there are c_sdp_N_sub = 512 subbands per signal path
- -- . one complex WPFB can process two real inputs A, B
+ -- . one complex WPFB can process two real inputs A, B, is c_sdp_Q_fft = c_sdp_N_pol = 2
-- . the subbands are output alternately so A0 B0 A1 B1 ... A511 B511 for input A, B
-- . the subband statistics multiple WPFB units appear in order in the ram_st_sst address map
-- . the subband statistics are stored first lo word 0 then hi word 1
-
- FOR I IN 0 TO c_sdp_N_pol*c_sdp_S_sub_bf*(c_longword_sz/c_word_sz)-1 LOOP
- v_W := I MOD (c_longword_sz/c_word_sz);
- v_T := (I / (c_longword_sz/c_word_sz)) MOD c_sdp_N_pol;
- v_U := I / (c_sdp_N_pol*(c_longword_sz/c_word_sz)*c_sdp_S_sub_bf);
+
+ FOR I IN 0 TO c_sdp_N_pol*c_sdp_N_sub*c_stat_data_sz-1 LOOP -- 2048 = 2 * 512 * 64/32
+ v_W := I MOD c_stat_data_sz; -- 0, 1 per statistics word
+ v_T := (I / c_stat_data_sz) MOD c_sdp_N_pol; -- 0, 1 per pol
+ v_U := I / (c_sdp_N_pol*c_stat_data_sz*c_sdp_N_sub); -- / 2048
v_S := v_T + v_U * c_sdp_N_pol;
- v_B := (I / (c_sdp_N_pol*(c_longword_sz/c_word_sz))) MOD c_sdp_S_sub_bf;
+ v_B := (I / (c_sdp_N_pol*c_stat_data_sz)) MOD c_sdp_N_sub; -- 0:511 per dual pol
+ -- Only read sp 0, pol 0 (v_S = 0)
IF v_S=0 THEN
IF v_W=0 THEN
-- low part
@@ -399,27 +410,27 @@ BEGIN
---------------------------------------------------------------------------
-- Read beamlet statistics
---------------------------------------------------------------------------
- -- . the beamlet statistics are (c_longword_sz/c_word_sz) = 2 word power values.
+ -- . the beamlet statistics are c_stat_data_sz = 2 word power values.
-- . there are c_sdp_S_sub_bf = 488 subbands per signal path
-- . the subbands are output alternately so A0 B0 A1 B1 ... A5487 B487 for input A, B
-- . the subband statistics multiple units appear in order in the ram_st_bst address map
-- . the subband statistics are stored first lo word 0 then hi word 1
- -- . Only read beamset 0, pol 0
- FOR I IN 0 TO c_sdp_N_pol*c_sdp_S_sub_bf*(c_longword_sz/c_word_sz)-1 LOOP
- v_W := I MOD (c_longword_sz/c_word_sz);
- v_T := (I / (c_longword_sz/c_word_sz)) MOD c_sdp_N_pol;
- v_U := I / (c_sdp_N_pol*(c_longword_sz/c_word_sz)*c_sdp_S_sub_bf);
- v_S := v_T + v_U * c_sdp_N_pol;
- v_B := (I / (c_sdp_N_pol*(c_longword_sz/c_word_sz))) MOD c_sdp_S_sub_bf;
+ FOR I IN 0 TO c_sdp_N_pol_bf*c_sdp_S_sub_bf*c_stat_data_sz-1 LOOP
+ v_W := I MOD c_stat_data_sz;
+ v_T := (I / c_stat_data_sz) MOD c_sdp_N_pol_bf;
+ v_U := I / (c_sdp_N_pol_bf*c_stat_data_sz*c_sdp_S_sub_bf);
+ v_S := v_T + v_U * c_sdp_N_pol_bf;
+ v_B := (I / (c_sdp_N_pol_bf*c_stat_data_sz)) MOD c_sdp_S_sub_bf;
+ -- Only read beamset 0, pol 0 (v_S = 0)
IF v_S=0 THEN
IF v_W=0 THEN
-- low part
- --mmf_mm_bus_rd(c_mm_file_ram_st_bst, I+(c_sdp_N_pol*c_sdp_N_sub*(c_longword_sz/c_word_sz)), rd_data, tb_clk);
+ --mmf_mm_bus_rd(c_mm_file_ram_st_bst, I+(c_sdp_N_pol_bf*c_sdp_N_sub*c_stat_data_sz), rd_data, tb_clk);
mmf_mm_bus_rd(c_mm_file_ram_st_bst, I, rd_data, tb_clk);
sp_beamlet_powers_arr2(v_S)(v_B)(31 DOWNTO 0) <= rd_data;
ELSE
-- high part
- --mmf_mm_bus_rd(c_mm_file_ram_st_bst, I+(c_sdp_N_pol*c_sdp_N_sub*(c_longword_sz/c_word_sz)), rd_data, tb_clk);
+ --mmf_mm_bus_rd(c_mm_file_ram_st_bst, I+(c_sdp_N_pol_bf*c_sdp_N_sub*c_stat_data_sz), rd_data, tb_clk);
mmf_mm_bus_rd(c_mm_file_ram_st_bst, I, rd_data, tb_clk);
sp_beamlet_powers_arr2(v_S)(v_B)(63 DOWNTO 32) <= rd_data;
@@ -436,47 +447,49 @@ BEGIN
-- sp_beamlet_power_sum is the sum of all subband powers per SP, this value will be close to sp_beamlet_power
-- because the input is a sinus, so most power will be in 1 subband. The sp_beamlet_power_leakage_sum shows
-- how much power from the input sinus at a specific subband has leaked into the 511 other subbands.
- sp_beamlet_power_0 <= REAL(TO_UINT(sp_beamlet_powers_arr2(0)(INTEGER(ROUND(c_subband_sp_0)))(61 DOWNTO 30)))*2.0**30 +
+ sp_beamlet_power_0 <=
+ REAL(TO_UINT(sp_beamlet_powers_arr2(0)(INTEGER(ROUND(c_subband_sp_0)))(61 DOWNTO 30)))*2.0**30 +
REAL(TO_UINT(sp_beamlet_powers_arr2(0)(INTEGER(ROUND(c_subband_sp_0)))(29 DOWNTO 0)));
sp_beamlet_power_sum_0 <= sp_beamlet_power_sum(0);
proc_common_wait_some_cycles(tb_clk, 1);
-
---------------------------------------------------------------------------
-- Read 10GbE Stream
---------------------------------------------------------------------------
+ -- Wait until start of a beamlet packet, capture only first block in packet
proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.sop);
FOR I IN 0 TO 8 LOOP -- Packet header is 9.25 words wide, which can be discarded
proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.valid);
proc_common_wait_some_cycles(ext_clk, 1);
END LOOP;
- -- First word contains 3 beamlets + 1 header part
- beamlet_arr2_re(0) <= tr_10GbE_src_out.data(7 DOWNTO 0);
+ -- First word contains 1.5 dual pol (= XY, X) beamlets + 1 header part
+ beamlet_arr2_re(0) <= tr_10GbE_src_out.data(7 DOWNTO 0); -- X
beamlet_arr2_im(0) <= tr_10GbE_src_out.data(15 DOWNTO 8);
- beamlet_arr2_re(1) <= tr_10GbE_src_out.data(23 DOWNTO 16);
+ beamlet_arr2_re(1) <= tr_10GbE_src_out.data(23 DOWNTO 16); -- Y
beamlet_arr2_im(1) <= tr_10GbE_src_out.data(31 DOWNTO 24);
- beamlet_arr2_re(2) <= tr_10GbE_src_out.data(39 DOWNTO 32);
+ beamlet_arr2_re(2) <= tr_10GbE_src_out.data(39 DOWNTO 32); -- X
beamlet_arr2_im(2) <= tr_10GbE_src_out.data(47 DOWNTO 40);
proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.valid);
proc_common_wait_some_cycles(ext_clk, 1);
- FOR I IN 1 TO (c_sdp_cep_nof_beamlets_per_block/4)-1 LOOP
- beamlet_arr2_re(I*4 -1) <= tr_10GbE_src_out.data(7 DOWNTO 0);
+ -- 2 dual pol beamlets (= Y, XY, X) /64b data word
+ FOR I IN 1 TO (c_sdp_cep_nof_beamlets_per_block/2)-1 LOOP
+ beamlet_arr2_re(I*4 -1) <= tr_10GbE_src_out.data(7 DOWNTO 0); -- Y
beamlet_arr2_im(I*4 -1) <= tr_10GbE_src_out.data(15 DOWNTO 8);
- beamlet_arr2_re(I*4 +0) <= tr_10GbE_src_out.data(23 DOWNTO 16);
+ beamlet_arr2_re(I*4 +0) <= tr_10GbE_src_out.data(23 DOWNTO 16); -- X
beamlet_arr2_im(I*4 +0) <= tr_10GbE_src_out.data(31 DOWNTO 24);
- beamlet_arr2_re(I*4 +1) <= tr_10GbE_src_out.data(39 DOWNTO 32);
+ beamlet_arr2_re(I*4 +1) <= tr_10GbE_src_out.data(39 DOWNTO 32); -- Y
beamlet_arr2_im(I*4 +1) <= tr_10GbE_src_out.data(47 DOWNTO 40);
- beamlet_arr2_re(I*4 +2) <= tr_10GbE_src_out.data(55 DOWNTO 48);
+ beamlet_arr2_re(I*4 +2) <= tr_10GbE_src_out.data(55 DOWNTO 48); -- X
beamlet_arr2_im(I*4 +2) <= tr_10GbE_src_out.data(63 DOWNTO 56);
proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.valid);
proc_common_wait_some_cycles(ext_clk, 1);
END LOOP;
-
- beamlet_arr2_re(c_sdp_cep_nof_beamlets_per_block-1) <= tr_10GbE_src_out.data(55 DOWNTO 48);
- beamlet_arr2_im(c_sdp_cep_nof_beamlets_per_block-1) <= tr_10GbE_src_out.data(63 DOWNTO 56);
+ -- Last word contains last 0.5 (= Y) dual pol beamlet
+ beamlet_arr2_re(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf-1) <= tr_10GbE_src_out.data(55 DOWNTO 48); -- Y
+ beamlet_arr2_im(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf-1) <= tr_10GbE_src_out.data(63 DOWNTO 56);
---------------------------------------------------------------------------
-- Verify subband statistics
@@ -522,8 +535,10 @@ BEGIN
---------------------------------------------------------------------------
-- Verify 10GbE UDP offload
---------------------------------------------------------------------------
- ASSERT beamlet_arr2_re(c_exp_beamlet_index) = c_exp_beamlet_re REPORT "Wrong 10GbE output (re)" SEVERITY ERROR;
- ASSERT beamlet_arr2_im(c_exp_beamlet_index) = c_exp_beamlet_im REPORT "Wrong 10GbE output (im)" SEVERITY ERROR;
+ v_re := TO_SINT(beamlet_arr2_re(c_exp_beamlet_index)); v_re_exp := TO_SINT(c_exp_beamlet_re);
+ v_im := TO_SINT(beamlet_arr2_im(c_exp_beamlet_index)); v_im_exp := TO_SINT(c_exp_beamlet_im);
+ ASSERT v_re = v_re_exp REPORT "Wrong 10GbE output (re) " & INTEGER'IMAGE(v_re) & " != " & INTEGER'IMAGE(v_re_exp) SEVERITY ERROR;
+ ASSERT v_im = v_im_exp REPORT "Wrong 10GbE output (im) " & INTEGER'IMAGE(v_re) & " != " & INTEGER'IMAGE(v_re_exp) SEVERITY ERROR;
---------------------------------------------------------------------------
-- End Simulation
@@ -534,4 +549,66 @@ BEGIN
WAIT;
END PROCESS;
+ -----------------------------------------------------------------------------
+ -- Debugging signals
+ -----------------------------------------------------------------------------
+ -- Show received beamlets from 10GbE stream in Wave Window
+ -- . expect c_nof_block_per_sync / c_sdp_cep_nof_blocks_per_packet * c_sdp_N_beamsets
+ -- = 16 / 4 * 2 = 4 * 2 = 8 packets per sync interval
+ -- . expect c_sdp_cep_nof_beamlets_per_block = c_sdp_S_sub_bf = 488 dual pol
+ -- and complex beamlets per packet, so 2 dual pol beamlets/64b data word.
+ p_dbg_10GbE_beamlets : PROCESS
+ BEGIN
+ -- Wait until start of (next) beamlet packet
+ dbg_beamlet_cnt <= 0;
+ dbg_beamlet_valid <= '0';
+ proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.sop);
+ FOR I IN 0 TO 8 LOOP -- Packet header is 9.25 words wide, which can be discarded
+ proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.valid);
+ -- Use at least one WAIT instead of proc_common_wait_some_cycles() to avoid Modelsim warning:
+ -- (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
+ WAIT UNTIL rising_edge(ext_clk);
+ END LOOP;
+
+ -- First word contains 1.5 dual pol (= XY, X) beamlets + 1 header part
+ dbg_beamlet_arr_re(0) <= tr_10GbE_src_out.data(7 DOWNTO 0); -- X
+ dbg_beamlet_arr_im(0) <= tr_10GbE_src_out.data(15 DOWNTO 8);
+ dbg_beamlet_arr_re(1) <= tr_10GbE_src_out.data(23 DOWNTO 16); -- Y
+ dbg_beamlet_arr_im(1) <= tr_10GbE_src_out.data(31 DOWNTO 24);
+ dbg_beamlet_arr_re(2) <= tr_10GbE_src_out.data(39 DOWNTO 32); -- X
+ dbg_beamlet_arr_im(2) <= tr_10GbE_src_out.data(47 DOWNTO 40);
+ dbg_beamlet_arr_re(3) <= (OTHERS => '1'); -- mark unused octet by 0xFF = -1
+ dbg_beamlet_arr_im(3) <= (OTHERS => '1'); -- mark unused octet by 0xFF = -1
+ dbg_beamlet_cnt <= dbg_beamlet_cnt + 3;
+ dbg_beamlet_valid <= '1';
+ proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.valid);
+ proc_common_wait_some_cycles(ext_clk, 1);
+ -- 2 dual pol beamlets (= Y, XY, X) /64b data word
+ FOR I IN 1 TO (c_sdp_cep_nof_beamlets_per_block*c_sdp_cep_nof_blocks_per_packet/2)-1 LOOP
+ dbg_beamlet_arr_re(0) <= tr_10GbE_src_out.data(7 DOWNTO 0); -- Y
+ dbg_beamlet_arr_im(0) <= tr_10GbE_src_out.data(15 DOWNTO 8);
+ dbg_beamlet_arr_re(1) <= tr_10GbE_src_out.data(23 DOWNTO 16); -- X
+ dbg_beamlet_arr_im(1) <= tr_10GbE_src_out.data(31 DOWNTO 24);
+ dbg_beamlet_arr_re(2) <= tr_10GbE_src_out.data(39 DOWNTO 32); -- Y
+ dbg_beamlet_arr_im(2) <= tr_10GbE_src_out.data(47 DOWNTO 40);
+ dbg_beamlet_arr_re(3) <= tr_10GbE_src_out.data(55 DOWNTO 48); -- X
+ dbg_beamlet_arr_im(3) <= tr_10GbE_src_out.data(63 DOWNTO 56);
+ dbg_beamlet_cnt <= (dbg_beamlet_cnt + 4) MOD c_sdp_cep_nof_beamlets_per_block; -- 4 blocks/packet
+ dbg_beamlet_valid <= '1';
+ proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.valid);
+ proc_common_wait_some_cycles(ext_clk, 1);
+ END LOOP;
+ -- Last word contains last 0.5 (= Y) dual pol beamlet
+ dbg_beamlet_arr_re(0) <= tr_10GbE_src_out.data(55 DOWNTO 48); -- Y
+ dbg_beamlet_arr_im(0) <= tr_10GbE_src_out.data(63 DOWNTO 56);
+ dbg_beamlet_arr_re(1) <= (OTHERS => '1'); -- mark unused octet by 0xFF = -1
+ dbg_beamlet_arr_im(1) <= (OTHERS => '1'); -- mark unused octet by 0xFF = -1
+ dbg_beamlet_arr_re(2) <= (OTHERS => '1'); -- mark unused octet by 0xFF = -1
+ dbg_beamlet_arr_im(2) <= (OTHERS => '1'); -- mark unused octet by 0xFF = -1
+ dbg_beamlet_arr_re(3) <= (OTHERS => '1'); -- mark unused octet by 0xFF = -1
+ dbg_beamlet_arr_im(3) <= (OTHERS => '1'); -- mark unused octet by 0xFF = -1
+ dbg_beamlet_cnt <= dbg_beamlet_cnt + 1;
+ dbg_beamlet_valid <= '1';
+ END PROCESS;
+
END tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd
index a074912f158de3a06665064efad16d4bc15d5e06..c3cd741d7fb6f3a0ed5ecdaa41b34cab956ef939 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd
@@ -35,6 +35,7 @@
-- > as 7 # default
-- > as 12 # for detailed debugging
-- > run -a
+-- Takes about 10 m
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib, eth_lib;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
index 4cdb49bef0859e4a0806939659c6fa8b1b179e26..be921d69725e723ca1cc8c42cd2cfb3c6f22f0b5 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
@@ -46,6 +46,7 @@
-- > as 7 # default
-- > as 12 # for detailed debugging
-- > run -a
+-- Takes about 45 m
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib, lofar2_unb2c_sdp_station_lib;
@@ -87,7 +88,8 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_bf IS
CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
-
+ CONSTANT c_stat_data_sz : NATURAL := c_longword_sz/c_word_sz; -- = 2
+
CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value
CONSTANT c_lo_factor : REAL := 1.0 - c_percentage; -- lower boundary
CONSTANT c_hi_factor : REAL := 1.0 + c_percentage; -- higher boundary
@@ -109,7 +111,8 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_bf IS
CONSTANT c_exp_beamlet_power_sp_0 : REAL := c_exp_wg_power_sp_0 * c_exp_sp_beamlet_power_ratio;
TYPE t_real_arr IS ARRAY (INTEGER RANGE <>) OF REAL;
- TyPE t_slv_64_subbands_arr IS ARRAY (INTEGER RANGE <>) OF t_slv_64_arr(0 TO c_sdp_S_sub_bf);
+ TYPE t_slv_64_subbands_arr IS ARRAY (INTEGER RANGE <>) OF t_slv_64_arr(0 TO c_sdp_N_sub);
+ TYPE t_slv_64_beamlets_arr IS ARRAY (INTEGER RANGE <>) OF t_slv_64_arr(0 TO c_sdp_S_sub_bf);
-- MM
CONSTANT c_mm_file_reg_ppsh : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
@@ -127,31 +130,36 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_bf IS
SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
-- WG
- SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+ SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
-- WPFB
- SIGNAL sp_subband_powers_arr2 : t_slv_64_subbands_arr(c_sdp_N_beamsets*c_sdp_N_pol-1 DOWNTO 0); -- [sp][sub]
+ SIGNAL sp_subband_powers_arr2 : t_slv_64_subbands_arr(c_sdp_N_pol-1 DOWNTO 0); -- [sp][sub]
- SIGNAL sp_beamlet_powers_arr2 : t_slv_64_subbands_arr(c_sdp_N_beamsets*c_sdp_N_pol-1 DOWNTO 0); -- [sp][sub]
+ SIGNAL sp_beamlet_powers_arr2 : t_slv_64_beamlets_arr(c_sdp_N_beamsets*c_sdp_N_pol_bf-1 DOWNTO 0); -- [sp][sub]
SIGNAL sp_beamlet_power_0 : REAL;
- SIGNAL sp_beamlet_power_sum : t_real_arr(c_sdp_N_beamsets*c_sdp_N_pol-1 DOWNTO 0) := (OTHERS=>0.0);
+ SIGNAL sp_beamlet_power_sum : t_real_arr(c_sdp_N_beamsets*c_sdp_N_pol_bf-1 DOWNTO 0) := (OTHERS=>0.0);
SIGNAL sp_beamlet_power_sum_0 : REAL;
SIGNAL sp_beamlet_power_ratio_0 : REAL;
SIGNAL sp_beamlet_power_sum_ratio_0 : REAL;
SIGNAL sp_beamlet_power_leakage_sum_0 : REAL;
-- 10GbE
- CONSTANT c_exp_beamlet_index : NATURAL := NATURAL(c_subband_sp_0) * c_sdp_N_pol;
- CONSTANT c_exp_beamlet_re : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"81"; --Derived from simulation
- CONSTANT c_exp_beamlet_im : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"7F"; --Derived from simulation
+ CONSTANT c_exp_beamlet_index : NATURAL := NATURAL(c_subband_sp_0) * c_sdp_N_pol_bf;
+ CONSTANT c_exp_beamlet_re : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"81"; -- = -127, derived from simulation
+ CONSTANT c_exp_beamlet_im : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"7F"; -- = +127, derived from simulation
- SIGNAL beamlet_arr2_re : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block-1 DOWNTO 0);
- SIGNAL beamlet_arr2_im : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block-1 DOWNTO 0);
+ SIGNAL dbg_beamlet_arr_re : t_slv_8_arr(c_sdp_cep_nof_blocks_per_packet-1 DOWNTO 0); -- [3:0]
+ SIGNAL dbg_beamlet_arr_im : t_slv_8_arr(c_sdp_cep_nof_blocks_per_packet-1 DOWNTO 0); -- [3:0]
+ SIGNAL dbg_beamlet_cnt : NATURAL;
+ SIGNAL dbg_beamlet_valid : STD_LOGIC;
- SIGNAL tr_10GbE_src_out : t_dp_sosi;
- SIGNAL tr_ref_clk_312 : STD_LOGIC := '0';
- SIGNAL tr_ref_clk_156 : STD_LOGIC := '0';
- SIGNAL tr_ref_rst_156 : STD_LOGIC := '0';
+ SIGNAL beamlet_arr2_re : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf-1 DOWNTO 0); -- [488 * 2-1:0] = [975:0]
+ SIGNAL beamlet_arr2_im : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf-1 DOWNTO 0); -- [488 * 2-1:0] = [975:0]
+
+ SIGNAL tr_10GbE_src_out : t_dp_sosi;
+ SIGNAL tr_ref_clk_312 : STD_LOGIC := '0';
+ SIGNAL tr_ref_clk_156 : STD_LOGIC := '0';
+ SIGNAL tr_ref_rst_156 : STD_LOGIC := '0';
-- DUT
SIGNAL ext_clk : STD_LOGIC := '0';
@@ -298,13 +306,12 @@ BEGIN
VARIABLE v_sp_beamlet_power : REAL;
VARIABLE v_sp_subband_power : REAL;
VARIABLE v_W, v_T, v_U, v_S, v_B : NATURAL; -- array indicies
+ VARIABLE v_re, v_im : INTEGER;
+ VARIABLE v_re_exp, v_im_exp : INTEGER;
BEGIN
-- Wait for DUT power up after reset
WAIT FOR 1 us;
- proc_common_wait_until_hi_lo(ext_clk, ext_pps);
-
-
----------------------------------------------------------------------------
-- Enable UDP offload (dp_xonoff) of beamset 0
----------------------------------------------------------------------------
@@ -319,6 +326,10 @@ BEGIN
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ -- Release PPS pulser, to get first PPS now and to start BSN source
+ WAIT FOR 1 us;
+ pps_rst <= '0';
+
----------------------------------------------------------------------------
-- Enable WG
----------------------------------------------------------------------------
@@ -354,17 +365,18 @@ BEGIN
---------------------------------------------------------------------------
-- . the subband statistics are c_wpfb_sim.stat_data_sz = 2 word power values.
-- . there are c_sdp_N_sub = 512 subbands per signal path
- -- . one complex WPFB can process two real inputs A, B
+ -- . one complex WPFB can process two real inputs A, B, is c_sdp_Q_fft = c_sdp_N_pol = 2
-- . the subbands are output alternately so A0 B0 A1 B1 ... A511 B511 for input A, B
-- . the subband statistics multiple WPFB units appear in order in the ram_st_sst address map
-- . the subband statistics are stored first lo word 0 then hi word 1
- FOR I IN 0 TO c_sdp_N_pol*c_sdp_S_sub_bf*(c_longword_sz/c_word_sz)-1 LOOP
- v_W := I MOD (c_longword_sz/c_word_sz);
- v_T := (I / (c_longword_sz/c_word_sz)) MOD c_sdp_N_pol;
- v_U := I / (c_sdp_N_pol*(c_longword_sz/c_word_sz)*c_sdp_S_sub_bf);
+ FOR I IN 0 TO c_sdp_N_pol*c_sdp_N_sub*c_stat_data_sz-1 LOOP -- 2048 = 2 * 512 * 64/32
+ v_W := I MOD c_stat_data_sz; -- 0, 1 per statistics word
+ v_T := (I / c_stat_data_sz) MOD c_sdp_N_pol; -- 0, 1 per pol
+ v_U := I / (c_sdp_N_pol*c_stat_data_sz*c_sdp_N_sub); -- / 2048
v_S := v_T + v_U * c_sdp_N_pol;
- v_B := (I / (c_sdp_N_pol*(c_longword_sz/c_word_sz))) MOD c_sdp_S_sub_bf;
+ v_B := (I / (c_sdp_N_pol*c_stat_data_sz)) MOD c_sdp_N_sub; -- 0:511 per dual pol
+ -- Only read sp 0, pol 0 (v_S = 0)
IF v_S=0 THEN
IF v_W=0 THEN
-- low part
@@ -381,27 +393,27 @@ BEGIN
---------------------------------------------------------------------------
-- Read beamlet statistics
---------------------------------------------------------------------------
- -- . the beamlet statistics are (c_longword_sz/c_word_sz) = 2 word power values.
+ -- . the beamlet statistics are c_stat_data_sz = 2 word power values.
-- . there are c_sdp_S_sub_bf = 488 subbands per signal path
-- . the subbands are output alternately so A0 B0 A1 B1 ... A5487 B487 for input A, B
-- . the subband statistics multiple units appear in order in the ram_st_bst address map
-- . the subband statistics are stored first lo word 0 then hi word 1
- -- . Only read beamset 0, pol 0
- FOR I IN 0 TO c_sdp_N_pol*c_sdp_S_sub_bf*(c_longword_sz/c_word_sz)-1 LOOP
- v_W := I MOD (c_longword_sz/c_word_sz);
- v_T := (I / (c_longword_sz/c_word_sz)) MOD c_sdp_N_pol;
- v_U := I / (c_sdp_N_pol*(c_longword_sz/c_word_sz)*c_sdp_S_sub_bf);
- v_S := v_T + v_U * c_sdp_N_pol;
- v_B := (I / (c_sdp_N_pol*(c_longword_sz/c_word_sz))) MOD c_sdp_S_sub_bf;
+ FOR I IN 0 TO c_sdp_N_pol_bf*c_sdp_S_sub_bf*c_stat_data_sz-1 LOOP
+ v_W := I MOD c_stat_data_sz;
+ v_T := (I / c_stat_data_sz) MOD c_sdp_N_pol_bf;
+ v_U := I / (c_sdp_N_pol_bf*c_stat_data_sz*c_sdp_S_sub_bf);
+ v_S := v_T + v_U * c_sdp_N_pol_bf;
+ v_B := (I / (c_sdp_N_pol_bf*c_stat_data_sz)) MOD c_sdp_S_sub_bf;
+ -- Only read beamset 0, pol 0 (v_S = 0)
IF v_S=0 THEN
IF v_W=0 THEN
-- low part
- --mmf_mm_bus_rd(c_mm_file_ram_st_bst, I+(c_sdp_N_pol*c_sdp_N_sub*(c_longword_sz/c_word_sz)), rd_data, tb_clk);
+ --mmf_mm_bus_rd(c_mm_file_ram_st_bst, I+(c_sdp_N_pol_bf*c_sdp_N_sub*c_stat_data_sz), rd_data, tb_clk);
mmf_mm_bus_rd(c_mm_file_ram_st_bst, I, rd_data, tb_clk);
sp_beamlet_powers_arr2(v_S)(v_B)(31 DOWNTO 0) <= rd_data;
ELSE
-- high part
- --mmf_mm_bus_rd(c_mm_file_ram_st_bst, I+(c_sdp_N_pol*c_sdp_N_sub*(c_longword_sz/c_word_sz)), rd_data, tb_clk);
+ --mmf_mm_bus_rd(c_mm_file_ram_st_bst, I+(c_sdp_N_pol_bf*c_sdp_N_sub*c_stat_data_sz), rd_data, tb_clk);
mmf_mm_bus_rd(c_mm_file_ram_st_bst, I, rd_data, tb_clk);
sp_beamlet_powers_arr2(v_S)(v_B)(63 DOWNTO 32) <= rd_data;
@@ -418,47 +430,49 @@ BEGIN
-- sp_beamlet_power_sum is the sum of all subband powers per SP, this value will be close to sp_beamlet_power
-- because the input is a sinus, so most power will be in 1 subband. The sp_beamlet_power_leakage_sum shows
-- how much power from the input sinus at a specific subband has leaked into the 511 other subbands.
- sp_beamlet_power_0 <= REAL(TO_UINT(sp_beamlet_powers_arr2(0)(INTEGER(ROUND(c_subband_sp_0)))(61 DOWNTO 30)))*2.0**30 +
+ sp_beamlet_power_0 <=
+ REAL(TO_UINT(sp_beamlet_powers_arr2(0)(INTEGER(ROUND(c_subband_sp_0)))(61 DOWNTO 30)))*2.0**30 +
REAL(TO_UINT(sp_beamlet_powers_arr2(0)(INTEGER(ROUND(c_subband_sp_0)))(29 DOWNTO 0)));
sp_beamlet_power_sum_0 <= sp_beamlet_power_sum(0);
proc_common_wait_some_cycles(tb_clk, 1);
-
---------------------------------------------------------------------------
-- Read 10GbE Stream
---------------------------------------------------------------------------
+ -- Wait until start of a beamlet packet, capture only first block in packet
proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.sop);
FOR I IN 0 TO 8 LOOP -- Packet header is 9.25 words wide, which can be discarded
proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.valid);
proc_common_wait_some_cycles(ext_clk, 1);
END LOOP;
-
- -- First word contains 3 beamlets + 1 header part
- beamlet_arr2_re(0) <= tr_10GbE_src_out.data(7 DOWNTO 0);
+
+ -- First word contains 1.5 dual pol (= XY, X) beamlets + 1 header part
+ beamlet_arr2_re(0) <= tr_10GbE_src_out.data(7 DOWNTO 0); -- X
beamlet_arr2_im(0) <= tr_10GbE_src_out.data(15 DOWNTO 8);
- beamlet_arr2_re(1) <= tr_10GbE_src_out.data(23 DOWNTO 16);
+ beamlet_arr2_re(1) <= tr_10GbE_src_out.data(23 DOWNTO 16); -- Y
beamlet_arr2_im(1) <= tr_10GbE_src_out.data(31 DOWNTO 24);
- beamlet_arr2_re(2) <= tr_10GbE_src_out.data(39 DOWNTO 32);
+ beamlet_arr2_re(2) <= tr_10GbE_src_out.data(39 DOWNTO 32); -- X
beamlet_arr2_im(2) <= tr_10GbE_src_out.data(47 DOWNTO 40);
proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.valid);
proc_common_wait_some_cycles(ext_clk, 1);
- FOR I IN 1 TO (c_sdp_cep_nof_beamlets_per_block/4)-1 LOOP
- beamlet_arr2_re(I*4 -1) <= tr_10GbE_src_out.data(7 DOWNTO 0);
+ -- 2 dual pol beamlets (= Y, XY, X) /64b data word
+ FOR I IN 1 TO (c_sdp_cep_nof_beamlets_per_block/2)-1 LOOP
+ beamlet_arr2_re(I*4 -1) <= tr_10GbE_src_out.data(7 DOWNTO 0); -- Y
beamlet_arr2_im(I*4 -1) <= tr_10GbE_src_out.data(15 DOWNTO 8);
- beamlet_arr2_re(I*4 +0) <= tr_10GbE_src_out.data(23 DOWNTO 16);
+ beamlet_arr2_re(I*4 +0) <= tr_10GbE_src_out.data(23 DOWNTO 16); -- X
beamlet_arr2_im(I*4 +0) <= tr_10GbE_src_out.data(31 DOWNTO 24);
- beamlet_arr2_re(I*4 +1) <= tr_10GbE_src_out.data(39 DOWNTO 32);
+ beamlet_arr2_re(I*4 +1) <= tr_10GbE_src_out.data(39 DOWNTO 32); -- Y
beamlet_arr2_im(I*4 +1) <= tr_10GbE_src_out.data(47 DOWNTO 40);
- beamlet_arr2_re(I*4 +2) <= tr_10GbE_src_out.data(55 DOWNTO 48);
+ beamlet_arr2_re(I*4 +2) <= tr_10GbE_src_out.data(55 DOWNTO 48); -- X
beamlet_arr2_im(I*4 +2) <= tr_10GbE_src_out.data(63 DOWNTO 56);
proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.valid);
proc_common_wait_some_cycles(ext_clk, 1);
END LOOP;
-
- beamlet_arr2_re(c_sdp_cep_nof_beamlets_per_block-1) <= tr_10GbE_src_out.data(55 DOWNTO 48);
- beamlet_arr2_im(c_sdp_cep_nof_beamlets_per_block-1) <= tr_10GbE_src_out.data(63 DOWNTO 56);
+ -- Last word contains last 0.5 (= Y) dual pol beamlet
+ beamlet_arr2_re(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf-1) <= tr_10GbE_src_out.data(55 DOWNTO 48); -- Y
+ beamlet_arr2_im(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf-1) <= tr_10GbE_src_out.data(63 DOWNTO 56);
---------------------------------------------------------------------------
-- Verify subband statistics
@@ -503,9 +517,11 @@ BEGIN
---------------------------------------------------------------------------
-- Verify 10GbE UDP offload
- ---------------------------------------------------------------------------
- ASSERT beamlet_arr2_re(c_exp_beamlet_index) = c_exp_beamlet_re REPORT "Wrong 10GbE output (re)" SEVERITY ERROR;
- ASSERT beamlet_arr2_im(c_exp_beamlet_index) = c_exp_beamlet_im REPORT "Wrong 10GbE output (im)" SEVERITY ERROR;
+ ---------------------------------------------------------------------------
+ v_re := TO_SINT(beamlet_arr2_re(c_exp_beamlet_index)); v_re_exp := TO_SINT(c_exp_beamlet_re);
+ v_im := TO_SINT(beamlet_arr2_im(c_exp_beamlet_index)); v_im_exp := TO_SINT(c_exp_beamlet_im);
+ ASSERT v_re = v_re_exp REPORT "Wrong 10GbE output (re) " & INTEGER'IMAGE(v_re) & " != " & INTEGER'IMAGE(v_re_exp) SEVERITY ERROR;
+ ASSERT v_im = v_im_exp REPORT "Wrong 10GbE output (im) " & INTEGER'IMAGE(v_re) & " != " & INTEGER'IMAGE(v_re_exp) SEVERITY ERROR;
---------------------------------------------------------------------------
-- End Simulation
@@ -516,4 +532,66 @@ BEGIN
WAIT;
END PROCESS;
+ -----------------------------------------------------------------------------
+ -- Debugging signals
+ -----------------------------------------------------------------------------
+ -- Show received beamlets from 10GbE stream in Wave Window
+ -- . expect c_nof_block_per_sync / c_sdp_cep_nof_blocks_per_packet * c_sdp_N_beamsets
+ -- = 16 / 4 * 2 = 4 * 2 = 8 packets per sync interval
+ -- . expect c_sdp_cep_nof_beamlets_per_block = c_sdp_S_sub_bf = 488 dual pol
+ -- and complex beamlets per packet, so 2 dual pol beamlets/64b data word.
+ p_dbg_10GbE_beamlets : PROCESS
+ BEGIN
+ -- Wait until start of (next) beamlet packet
+ dbg_beamlet_cnt <= 0;
+ dbg_beamlet_valid <= '0';
+ proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.sop);
+ FOR I IN 0 TO 8 LOOP -- Packet header is 9.25 words wide, which can be discarded
+ proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.valid);
+ -- Use at least one WAIT instead of proc_common_wait_some_cycles() to avoid Modelsim warning:
+ -- (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
+ WAIT UNTIL rising_edge(ext_clk);
+ END LOOP;
+
+ -- First word contains 1.5 dual pol (= XY, X) beamlets + 1 header part
+ dbg_beamlet_arr_re(0) <= tr_10GbE_src_out.data(7 DOWNTO 0); -- X
+ dbg_beamlet_arr_im(0) <= tr_10GbE_src_out.data(15 DOWNTO 8);
+ dbg_beamlet_arr_re(1) <= tr_10GbE_src_out.data(23 DOWNTO 16); -- Y
+ dbg_beamlet_arr_im(1) <= tr_10GbE_src_out.data(31 DOWNTO 24);
+ dbg_beamlet_arr_re(2) <= tr_10GbE_src_out.data(39 DOWNTO 32); -- X
+ dbg_beamlet_arr_im(2) <= tr_10GbE_src_out.data(47 DOWNTO 40);
+ dbg_beamlet_arr_re(3) <= (OTHERS => '1'); -- mark unused octet by 0xFF = -1
+ dbg_beamlet_arr_im(3) <= (OTHERS => '1'); -- mark unused octet by 0xFF = -1
+ dbg_beamlet_cnt <= dbg_beamlet_cnt + 3;
+ dbg_beamlet_valid <= '1';
+ proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.valid);
+ proc_common_wait_some_cycles(ext_clk, 1);
+ -- 2 dual pol beamlets (= Y, XY, X) /64b data word
+ FOR I IN 1 TO (c_sdp_cep_nof_beamlets_per_block*c_sdp_cep_nof_blocks_per_packet/2)-1 LOOP
+ dbg_beamlet_arr_re(0) <= tr_10GbE_src_out.data(7 DOWNTO 0); -- Y
+ dbg_beamlet_arr_im(0) <= tr_10GbE_src_out.data(15 DOWNTO 8);
+ dbg_beamlet_arr_re(1) <= tr_10GbE_src_out.data(23 DOWNTO 16); -- X
+ dbg_beamlet_arr_im(1) <= tr_10GbE_src_out.data(31 DOWNTO 24);
+ dbg_beamlet_arr_re(2) <= tr_10GbE_src_out.data(39 DOWNTO 32); -- Y
+ dbg_beamlet_arr_im(2) <= tr_10GbE_src_out.data(47 DOWNTO 40);
+ dbg_beamlet_arr_re(3) <= tr_10GbE_src_out.data(55 DOWNTO 48); -- X
+ dbg_beamlet_arr_im(3) <= tr_10GbE_src_out.data(63 DOWNTO 56);
+ dbg_beamlet_cnt <= (dbg_beamlet_cnt + 4) MOD c_sdp_cep_nof_beamlets_per_block; -- 4 blocks/packet
+ dbg_beamlet_valid <= '1';
+ proc_common_wait_until_high(ext_clk, tr_10GbE_src_out.valid);
+ proc_common_wait_some_cycles(ext_clk, 1);
+ END LOOP;
+ -- Last word contains last 0.5 (= Y) dual pol beamlet
+ dbg_beamlet_arr_re(0) <= tr_10GbE_src_out.data(55 DOWNTO 48); -- Y
+ dbg_beamlet_arr_im(0) <= tr_10GbE_src_out.data(63 DOWNTO 56);
+ dbg_beamlet_arr_re(1) <= (OTHERS => '1'); -- mark unused octet by 0xFF = -1
+ dbg_beamlet_arr_im(1) <= (OTHERS => '1'); -- mark unused octet by 0xFF = -1
+ dbg_beamlet_arr_re(2) <= (OTHERS => '1'); -- mark unused octet by 0xFF = -1
+ dbg_beamlet_arr_im(2) <= (OTHERS => '1'); -- mark unused octet by 0xFF = -1
+ dbg_beamlet_arr_re(3) <= (OTHERS => '1'); -- mark unused octet by 0xFF = -1
+ dbg_beamlet_arr_im(3) <= (OTHERS => '1'); -- mark unused octet by 0xFF = -1
+ dbg_beamlet_cnt <= dbg_beamlet_cnt + 1;
+ dbg_beamlet_valid <= '1';
+ END PROCESS;
+
END tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd
index cfacdffbc7d26617dd39f21a9be9443f5ed508f9..5930355ea60378745c482fe374b8f529f4f51448 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd
@@ -35,6 +35,7 @@
-- > as 7 # default
-- > as 12 # for detailed debugging
-- > run -a
+-- Takes about 10 m
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2c_sdp_station_lib, eth_lib;
diff --git a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
index 00aac656e5fdc2a1e9e1520dc3efa2cd3a427cb7..505bdf3885dfaca54168fb75366cd85742ff30fb 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
@@ -527,6 +527,7 @@ PACKAGE BODY tb_common_pkg IS
SIGNAL tb_end : IN STD_LOGIC) IS
BEGIN
WHILE tb_end='0' LOOP
+ ASSERT NOW < c_timeout REPORT "Test bench timeout." SEVERITY ERROR;
ASSERT NOW < c_timeout REPORT "Test bench timeout." SEVERITY FAILURE;
WAIT FOR 1 us;
END LOOP;
diff --git a/libraries/technology/jesd204b/hdllib.cfg b/libraries/technology/jesd204b/hdllib.cfg
index f17f1df54b2bcbe1c4f2cb21451d8437387ae75c..490134d6585a1c4038e1561c1adca5c92f7c3be1 100644
--- a/libraries/technology/jesd204b/hdllib.cfg
+++ b/libraries/technology/jesd204b/hdllib.cfg
@@ -15,16 +15,14 @@ synth_files =
tech_jesd204b.vhd
test_bench_files =
+ tech_jesd204b_tx.vhd
tb_tech_jesd204b.vhd
regression_test_vhdl =
-# FIXME: broken, need fixing
-# tb_tech_jesd204b.vhd
+ tb_tech_jesd204b.vhd
-
[modelsim_project_file]
modelsim_copy_files =
wave_tb_tech_jesd204b.do .
-
[quartus_project_file]
diff --git a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
index 7b5bffd1a0cf32f33c9667b2f55f30c874017266..8653d132d75b96794ef2fd80f55b31f38b6bedcf 100644
--- a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
+++ b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
@@ -18,26 +18,29 @@
--
-------------------------------------------------------------------------------
--- Author: J Hargreaves
+-- Author: J Hargreaves, E. Kooistra
-- Purpose: Tb for tech_jesd204b IP
-- Description:
-- Includes 3 JESD transmit sources to test multichannel syncronization
-- Relative delays between TX and RX channels can be varied by editing c_delay_*
-- Used default technology e1sg
--- ToDo: Make a tb_tb to run several test cases automatically
+-- Remark:
+-- The self checking is minimal. It only checks that Tx data from the DAC in
+-- the tb does come out the JESD Rx. Some more data and strobe testing would
+-- be nice, but is not needed because it works on HW.
-- Usage:
-- Load sim # check that design can load in vsim
-- > as 3 # check that the hierarchy for g_design_name is complete (or use do wave_tb_tech_jesd204b.do)
--- > run 120us # enough time to reset and syncronize the JESD IP
+-- > run -a # enough time to reset and syncronize the JESD IP
-LIBRARY IEEE, common_lib, ip_arria10_e1sg_jesd204b_lib, dp_lib; --, tech_jesd204b_lib;
+LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-USE ip_arria10_e1sg_jesd204b_lib.ip_arria10_e1sg_jesd204b_component_pkg.ALL;
+USE work.tech_jesd204b_component_pkg.ALL;
ENTITY tb_tech_jesd204b IS
END tb_tech_jesd204b;
@@ -54,6 +57,11 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
CONSTANT c_nof_jesd204b_tx : NATURAL := 3; -- number of jesd204b input sources to instantiate
CONSTANT c_nof_streams_jesd204b : NATURAL := 12; -- number of jesd204b receiver channels
+ CONSTANT c_jesd204b_rx_data_w : NATURAL :=32;
+ CONSTANT c_jesd204b_rx_somf_w : NATURAL :=c_jesd204b_rx_data_w/8; -- One somf bit per octet
+ CONSTANT c_jesd204b_rx_framer_data_w : NATURAL :=c_jesd204b_rx_data_w/2; -- IP outputs two samples in parallel
+ CONSTANT c_jesd204b_rx_framer_somf_w : NATURAL :=c_jesd204b_rx_somf_w/2; -- IP outputs two samples in parallel
+
-- Transport delays
TYPE t_time_arr IS ARRAY (0 TO c_nof_streams_jesd204b-1) OF TIME;
CONSTANT c_delay_data_arr : t_time_arr := (4000 ps,
@@ -82,8 +90,6 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
1000 ps) ; -- transport delays clock source to adc(tx)
CONSTANT c_delay_sysreftofpga : TIME := 10200 ps;
-
-
-- clocks and resets for the jesd204b tx
SIGNAL txlink_clk : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
SIGNAL dev_sync_n : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
@@ -107,6 +113,7 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
-- Tb
SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL tb_timeout : STD_LOGIC := '0';
SIGNAL sim_done : STD_LOGIC := '0';
-- mm control buses
@@ -126,6 +133,16 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
SIGNAL rx_sysref : STD_LOGIC := '0';
SIGNAL rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
+ -- Debug signals for rx_sosi_arr
+ SIGNAL rx_sosi : t_dp_sosi;
+ SIGNAL rx_sosi_data : STD_LOGIC_VECTOR(c_jesd204b_rx_framer_data_w-1 DOWNTO 0); -- 16 bit samples
+ SIGNAL rx_sosi_channel : STD_LOGIC_VECTOR(c_jesd204b_rx_framer_somf_w-1 DOWNTO 0); -- two samples
+ SIGNAL rx_sosi_valid : STD_LOGIC;
+ SIGNAL rx_sosi_sync : STD_LOGIC;
+ SIGNAL rx_sosi_sop : STD_LOGIC;
+ SIGNAL rx_sosi_eop : STD_LOGIC;
+ SIGNAL rx_sosi_valid_arr : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+
SIGNAL jesd204b_sampclk_fpga : STD_LOGIC := '1';
SIGNAL jesd204b_sampclk_adc : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
SIGNAL jesd204b_sysref_fpga : STD_LOGIC;
@@ -165,7 +182,7 @@ BEGIN
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
- u_jesd204b: ENTITY work.tech_jesd204b
+ u_jesd204b : ENTITY work.tech_jesd204b
GENERIC MAP(
g_sim => c_sim,
g_nof_streams => c_nof_streams_jesd204b,
@@ -218,105 +235,99 @@ BEGIN
-----------------------------------------------------------------------------
gen_jesd204b_tx : FOR i IN 0 TO c_nof_jesd204b_tx-1 GENERATE
- u_ip_arria10_e1sg_jesd204b_tx : ip_arria10_e1sg_jesd204b_tx
- PORT MAP
- (
- csr_cf => OPEN,
- csr_cs => OPEN,
- csr_f => OPEN,
- csr_hd => OPEN,
- csr_k => OPEN,
- csr_l => OPEN,
- csr_lane_powerdown => open, --out
- csr_m => OPEN,
- csr_n => OPEN,
- csr_np => OPEN,
- csr_tx_testmode => OPEN,
- csr_tx_testpattern_a => OPEN,
- csr_tx_testpattern_b => OPEN,
- csr_tx_testpattern_c => OPEN,
- csr_tx_testpattern_d => OPEN,
- csr_s => OPEN,
- dev_sync_n => dev_sync_n(i), --out
- jesd204_tx_avs_chipselect => avs_chipselect(i), --jesd204b_mosi_arr(i).chipselect,
- jesd204_tx_avs_address => avs_address(i),
- jesd204_tx_avs_read => avs_read(i),
- jesd204_tx_avs_readdata => avs_readdata(i),
- jesd204_tx_avs_waitrequest => open,
- jesd204_tx_avs_write => '0',
- jesd204_tx_avs_writedata => (others => '0'),
- jesd204_tx_avs_clk => mm_clk,
- jesd204_tx_avs_rst_n => avs_rst_n,
- jesd204_tx_dlb_data => open, -- debug/loopback testing
- jesd204_tx_dlb_kchar_data => open, -- debug/loopback testing
- jesd204_tx_frame_ready => jesd204b_tx_frame_ready(i),
- jesd204_tx_frame_error => '0',
- jesd204_tx_int => OPEN, -- Connected to status IO in example design
- jesd204_tx_link_data => jesd204b_tx_link_data_arr(i), --in
- jesd204_tx_link_valid => jesd204b_tx_link_valid(i), --in
- jesd204_tx_link_ready => jesd204b_tx_link_ready(i), --out
- mdev_sync_n => dev_sync_n(i), --in
- pll_locked => pll_locked, --in
- sync_n => jesd204b_sync_n_adc(i), --in
- tx_analogreset => tx_analogreset,
- tx_bonding_clocks => tx_bonding_clocks,--: in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
- tx_cal_busy => open,
- tx_digitalreset => tx_digitalreset,
- tx_serial_data => serial_tx(i downto i),
- txlink_clk => txlink_clk(i),
- txlink_rst_n_reset_n => txlink_rst_n,
- txphy_clk => txphy_clk(i downto i),
- somf => OPEN,
- sysref => jesd204b_sysref_adc(i)
- );
+ -- Tb DAC
+ u_tech_jesd204b_tx : ENTITY work.tech_jesd204b_tx
+ PORT MAP (
+ csr_cf => OPEN,
+ csr_cs => OPEN,
+ csr_f => OPEN,
+ csr_hd => OPEN,
+ csr_k => OPEN,
+ csr_l => OPEN,
+ csr_lane_powerdown => open, --out
+ csr_m => OPEN,
+ csr_n => OPEN,
+ csr_np => OPEN,
+ csr_tx_testmode => OPEN,
+ csr_tx_testpattern_a => OPEN,
+ csr_tx_testpattern_b => OPEN,
+ csr_tx_testpattern_c => OPEN,
+ csr_tx_testpattern_d => OPEN,
+ csr_s => OPEN,
+ dev_sync_n => dev_sync_n(i), --out
+ jesd204_tx_avs_chipselect => avs_chipselect(i), --jesd204b_mosi_arr(i).chipselect,
+ jesd204_tx_avs_address => avs_address(i),
+ jesd204_tx_avs_read => avs_read(i),
+ jesd204_tx_avs_readdata => avs_readdata(i),
+ jesd204_tx_avs_waitrequest => open,
+ jesd204_tx_avs_write => '0',
+ jesd204_tx_avs_writedata => (others => '0'),
+ jesd204_tx_avs_clk => mm_clk,
+ jesd204_tx_avs_rst_n => avs_rst_n,
+ jesd204_tx_dlb_data => open, -- debug/loopback testing
+ jesd204_tx_dlb_kchar_data => open, -- debug/loopback testing
+ jesd204_tx_frame_ready => jesd204b_tx_frame_ready(i),
+ jesd204_tx_frame_error => '0',
+ jesd204_tx_int => OPEN, -- Connected to status IO in example design
+ jesd204_tx_link_data => jesd204b_tx_link_data_arr(i), --in
+ jesd204_tx_link_valid => jesd204b_tx_link_valid(i), --in
+ jesd204_tx_link_ready => jesd204b_tx_link_ready(i), --out
+ mdev_sync_n => dev_sync_n(i), --in
+ pll_locked => pll_locked, --in
+ sync_n => jesd204b_sync_n_adc(i), --in
+ tx_analogreset => tx_analogreset,
+ tx_bonding_clocks => tx_bonding_clocks,--: in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
+ tx_cal_busy => open,
+ tx_digitalreset => tx_digitalreset,
+ tx_serial_data => serial_tx(i downto i),
+ txlink_clk => txlink_clk(i),
+ txlink_rst_n_reset_n => txlink_rst_n,
+ txphy_clk => txphy_clk(i downto i),
+ somf => OPEN,
+ sysref => jesd204b_sysref_adc(i)
+ );
-- Generate test pattern at each ADC
-
proc_data : PROCESS (jesd204b_sampclk_adc(i), mm_rst)
- VARIABLE data : INTEGER := 0;
- VARIABLE even_sample : BOOLEAN := TRUE;
+ VARIABLE v_data : INTEGER := 0;
+ VARIABLE v_even_sample : BOOLEAN := TRUE;
BEGIN
IF mm_rst = '1' THEN
jesd204b_tx_link_data_arr(i) <= (others => '0');
jesd204b_tx_link_valid(i) <= '0';
txlink_clk(i) <= '0';
- data := 0;
- even_sample := TRUE;
- ELSE
- IF rising_edge(jesd204b_sampclk_adc(i)) THEN
- txlink_clk(i) <= not txlink_clk(i);
- jesd204b_sysref_adc_1(i) <= jesd204b_sysref_adc(i);
- jesd204b_sysref_adc_2(i) <= jesd204b_sysref_adc_1(i);
-
- --generate a positive and negative going pulse after the rising edge of SYSREF
- IF (jesd204b_sysref_adc(i) = '1' and jesd204b_sysref_adc_1(i) = '0') THEN
- data := 1000;
- ELSIF (jesd204b_sysref_adc_1(i) = '1' and jesd204b_sysref_adc_2(i) = '0') THEN
- data := -1000;
- ELSE
- data := 0;
- END IF;
-
- -- Frame the data to 32 bits at half the rate
- IF(jesd204b_tx_link_ready(i) = '0') THEN
- even_sample := TRUE;
- ELSE
- even_sample := not even_sample;
- END IF;
- IF (even_sample = TRUE) THEN
- jesd204b_tx_link_data_arr(i)(15 downto 0) <= TO_SVEC(data, 16);
- jesd204b_tx_link_valid(i) <= '0';
- ELSE
- jesd204b_tx_link_data_arr(i)(31 downto 16) <= TO_SVEC(data, 16);
- jesd204b_tx_link_valid(i) <= '1';
- END IF;
+ v_data := 0;
+ v_even_sample := TRUE;
+ ELSIF rising_edge(jesd204b_sampclk_adc(i)) THEN
+ txlink_clk(i) <= not txlink_clk(i);
+ jesd204b_sysref_adc_1(i) <= jesd204b_sysref_adc(i);
+ jesd204b_sysref_adc_2(i) <= jesd204b_sysref_adc_1(i);
+
+ --generate a positive and negative going pulse after the rising edge of SYSREF
+ IF (jesd204b_sysref_adc(i) = '1' and jesd204b_sysref_adc_1(i) = '0') THEN
+ v_data := 1000;
+ ELSIF (jesd204b_sysref_adc_1(i) = '1' and jesd204b_sysref_adc_2(i) = '0') THEN
+ v_data := -1000;
+ ELSE
+ v_data := 0;
+ END IF;
+ -- Frame the data to 32 bits at half the rate
+ IF(jesd204b_tx_link_ready(i) = '0') THEN
+ v_even_sample := TRUE;
+ ELSE
+ v_even_sample := not v_even_sample;
+ END IF;
+ IF (v_even_sample = TRUE) THEN
+ jesd204b_tx_link_data_arr(i)(15 downto 0) <= TO_SVEC(v_data, 16);
+ jesd204b_tx_link_valid(i) <= '0';
+ ELSE
+ jesd204b_tx_link_data_arr(i)(31 downto 16) <= TO_SVEC(v_data, 16);
+ jesd204b_tx_link_valid(i) <= '1';
END IF;
END IF;
END PROCESS;
-
-
END GENERATE;
@@ -362,20 +373,20 @@ BEGIN
-- clock source process
-- generate the sysref pulses
proc_sysref : PROCESS (jesd204b_sampclk, mm_rst)
- VARIABLE count : NATURAL := 0;
+ VARIABLE v_count : NATURAL := 0;
BEGIN
IF mm_rst = '1' THEN
jesd204b_sysref <= '0';
- count := 0;
+ v_count := 0;
ELSE
IF rising_edge(jesd204b_sampclk) THEN
- IF (count = c_sysref_period-1) THEN
- count := 0;
+ IF (v_count = c_sysref_period-1) THEN
+ v_count := 0;
ELSE
- count := count + 1;
+ v_count := v_count + 1;
END IF;
- IF count > c_sysref_period-1-c_sysref_pulselength THEN
+ IF v_count > c_sysref_period-1-c_sysref_pulselength THEN
jesd204b_sysref <= '1';
ELSE
jesd204b_sysref <= '0';
@@ -463,13 +474,37 @@ BEGIN
END LOOP;
END PROCESS;
+ ------------------------------------------------------------------------------
+ -- Debug signals
+ ------------------------------------------------------------------------------
+
+ -- Wire rx_sosi_arr(0), because for some reason rx_sosi_arr does not show with as in wave window
+ rx_sosi <= rx_sosi_arr(0);
+ rx_sosi_data <= rx_sosi.data(rx_sosi_data'RANGE);
+ rx_sosi_channel <= rx_sosi.channel(rx_sosi_channel'RANGE);
+ rx_sosi_valid <= rx_sosi.valid;
+ rx_sosi_sync <= rx_sosi.sync;
+ rx_sosi_sop <= rx_sosi.sop;
+ rx_sosi_eop <= rx_sosi.eop;
+
+ rx_sosi_valid_arr <= func_dp_stream_arr_get(rx_sosi_arr, "VALID");
+
------------------------------------------------------------------------------
-- Simulation end
------------------------------------------------------------------------------
- sim_done <= '1' when rx_sosi_arr(0).valid = '1' and rx_sosi_arr(1).valid = '1' and rx_sosi_arr(2).valid = '1' else '0';
- tb_end <= '0', '1' after 110 us;
+ sim_done <= '1' when rx_sosi_arr(0).valid = '1' and rx_sosi_arr(1).valid = '1' and rx_sosi_arr(2).valid = '1' else '0';
+
+ p_tb_end : PROCESS
+ BEGIN
+ WAIT FOR 2 * c_sysref_period * c_jesd204b_sampclk_period;
+
+ ASSERT sim_done = '1' REPORT "No rx samples were received." SEVERITY ERROR;
+ WAIT FOR 10 us;
+ tb_end <= '1';
+ END PROCESS;
- proc_common_stop_simulation(TRUE, 1000, jesd204b_sampclk, sim_done, tb_end);
+ proc_common_timeout_failure(200 us, tb_timeout); -- ERROR: end simulation if it fails to end in time
+ proc_common_stop_simulation(tb_end); -- OK: end simulation
END tb;
diff --git a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
index 7b109077f7c9445b8e33762c4a91776bdfdc0f14..b3eeb7fd74d1395b249ddd07e7cc541a2b6c80fd 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
@@ -35,6 +35,9 @@ PACKAGE tech_jesd204b_component_pkg IS
-- ip_arria10_e1sg
------------------------------------------------------------------------------
+ ------------------------------------------------------------------------------
+ -- RX ONLY
+ ------------------------------------------------------------------------------
COMPONENT ip_arria10_e1sg_jesd204b IS
GENERIC (
g_sim : BOOLEAN := FALSE;
@@ -43,7 +46,7 @@ PACKAGE tech_jesd204b_component_pkg IS
g_direction : STRING := "RX_ONLY"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
g_jesd_freq : STRING := "200MHz"
);
- PORT (
+ PORT (
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
@@ -70,10 +73,67 @@ PACKAGE tech_jesd204b_component_pkg IS
);
END COMPONENT;
+ ------------------------------------------------------------------------------
+ -- TX ONLY, 1 channel
+ ------------------------------------------------------------------------------
+ component ip_arria10_e1sg_jesd204b_tx is
+ port (
+ csr_cf : out std_logic_vector(4 downto 0); -- export
+ csr_cs : out std_logic_vector(1 downto 0); -- export
+ csr_f : out std_logic_vector(7 downto 0); -- export
+ csr_hd : out std_logic; -- export
+ csr_k : out std_logic_vector(4 downto 0); -- export
+ csr_l : out std_logic_vector(4 downto 0); -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
+ csr_m : out std_logic_vector(7 downto 0); -- export
+ csr_n : out std_logic_vector(4 downto 0); -- export
+ csr_np : out std_logic_vector(4 downto 0); -- export
+ csr_s : out std_logic_vector(4 downto 0); -- export
+ csr_tx_testmode : out std_logic_vector(3 downto 0); -- export
+ csr_tx_testpattern_a : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_b : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_c : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_d : out std_logic_vector(31 downto 0); -- export
+ dev_sync_n : out std_logic; -- export
+ jesd204_tx_avs_chipselect : in std_logic := 'X'; -- chipselect
+ jesd204_tx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ jesd204_tx_avs_read : in std_logic := 'X'; -- read
+ jesd204_tx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
+ jesd204_tx_avs_waitrequest : out std_logic; -- waitrequest
+ jesd204_tx_avs_write : in std_logic := 'X'; -- write
+ jesd204_tx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ jesd204_tx_avs_clk : in std_logic := 'X'; -- clk
+ jesd204_tx_avs_rst_n : in std_logic := 'X'; -- reset_n
+ jesd204_tx_dlb_data : out std_logic_vector(31 downto 0); -- export
+ jesd204_tx_dlb_kchar_data : out std_logic_vector(3 downto 0); -- export
+ jesd204_tx_frame_error : in std_logic := 'X'; -- export
+ jesd204_tx_frame_ready : out std_logic; -- export
+ jesd204_tx_int : out std_logic; -- irq
+ jesd204_tx_link_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ jesd204_tx_link_valid : in std_logic := 'X'; -- valid
+ jesd204_tx_link_ready : out std_logic; -- ready
+ mdev_sync_n : in std_logic := 'X'; -- export
+ pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
+ somf : out std_logic_vector(3 downto 0); -- export
+ sync_n : in std_logic := 'X'; -- export
+ sysref : in std_logic := 'X'; -- export
+ tx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_analogreset
+ tx_bonding_clocks : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
+ tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy
+ tx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_digitalreset
+ tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data
+ txlink_clk : in std_logic := 'X'; -- clk
+ txlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ txphy_clk : out std_logic_vector(0 downto 0) -- export
+ );
+ end component;
+
+
------------------------------------------------------------------------------
-- ip_arria10_e2sg
------------------------------------------------------------------------------
+ -- RX ONLY
COMPONENT ip_arria10_e2sg_jesd204b IS
GENERIC (
g_sim : BOOLEAN := FALSE;
@@ -81,7 +141,7 @@ PACKAGE tech_jesd204b_component_pkg IS
g_nof_sync_n : NATURAL := 1;
g_direction : STRING := "RX_ONLY" -- "TX_RX", "TX_ONLY", "RX_ONLY"
);
- PORT (
+ PORT (
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
@@ -106,6 +166,59 @@ PACKAGE tech_jesd204b_component_pkg IS
);
END COMPONENT;
+ -- TX ONLY, 1 channel
+ component ip_arria10_e2sg_jesd204b_tx is
+ port (
+ csr_cf : out std_logic_vector(4 downto 0); -- export
+ csr_cs : out std_logic_vector(1 downto 0); -- export
+ csr_f : out std_logic_vector(7 downto 0); -- export
+ csr_hd : out std_logic; -- export
+ csr_k : out std_logic_vector(4 downto 0); -- export
+ csr_l : out std_logic_vector(4 downto 0); -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
+ csr_m : out std_logic_vector(7 downto 0); -- export
+ csr_n : out std_logic_vector(4 downto 0); -- export
+ csr_np : out std_logic_vector(4 downto 0); -- export
+ csr_s : out std_logic_vector(4 downto 0); -- export
+ csr_tx_testmode : out std_logic_vector(3 downto 0); -- export
+ csr_tx_testpattern_a : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_b : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_c : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_d : out std_logic_vector(31 downto 0); -- export
+ dev_sync_n : out std_logic; -- export
+ jesd204_tx_avs_chipselect : in std_logic := 'X'; -- chipselect
+ jesd204_tx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ jesd204_tx_avs_read : in std_logic := 'X'; -- read
+ jesd204_tx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
+ jesd204_tx_avs_waitrequest : out std_logic; -- waitrequest
+ jesd204_tx_avs_write : in std_logic := 'X'; -- write
+ jesd204_tx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ jesd204_tx_avs_clk : in std_logic := 'X'; -- clk
+ jesd204_tx_avs_rst_n : in std_logic := 'X'; -- reset_n
+ jesd204_tx_dlb_data : out std_logic_vector(31 downto 0); -- export
+ jesd204_tx_dlb_kchar_data : out std_logic_vector(3 downto 0); -- export
+ jesd204_tx_frame_error : in std_logic := 'X'; -- export
+ jesd204_tx_frame_ready : out std_logic; -- export
+ jesd204_tx_int : out std_logic; -- irq
+ jesd204_tx_link_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ jesd204_tx_link_valid : in std_logic := 'X'; -- valid
+ jesd204_tx_link_ready : out std_logic; -- ready
+ mdev_sync_n : in std_logic := 'X'; -- export
+ pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
+ somf : out std_logic_vector(3 downto 0); -- export
+ sync_n : in std_logic := 'X'; -- export
+ sysref : in std_logic := 'X'; -- export
+ tx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_analogreset
+ tx_bonding_clocks : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
+ tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy
+ tx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_digitalreset
+ tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data
+ txlink_clk : in std_logic := 'X'; -- clk
+ txlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ txphy_clk : out std_logic_vector(0 downto 0) -- export
+ );
+ end component;
+
END tech_jesd204b_component_pkg;
PACKAGE BODY tech_jesd204b_component_pkg IS
diff --git a/libraries/technology/jesd204b/tech_jesd204b_tx.vhd b/libraries/technology/jesd204b/tech_jesd204b_tx.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7662ec350b5dab82b57191a2c0a3db947c176d57
--- /dev/null
+++ b/libraries/technology/jesd204b/tech_jesd204b_tx.vhd
@@ -0,0 +1,210 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+
+-- Author : E. Kooistra
+-- Purpose: Technology selection wrapper to instantiate
+-- Provide JESD204b TX_ONLY interface for DAC to provide stimuli for ADC in a
+-- tb of RX_ONLY
+-- Description:
+-- Remark:
+-- Only used in tb_tech_jesd204b.vhd.
+-- Added because tech_jesd204b.vhd only supports RX_ONLY.
+-- Do not need an extra tech wrapper per IP, can instantiate IP directly here:
+-- . ip_arria10_e1sg_jesd204b_tx from ip_arria10_e1sg_jesd204b_lib
+-- . ip_arria10_e2sg_jesd204b_tx from ip_arria10_e2sg_jesd204b_lib
+-- The tech_jesd204b_component_pkg.vhd defines the IP components and the
+-- ip_arria10_e1sg_jesd204b_lib and ip_arria10_e2sg_jesd204b_lib LIBRARY
+-- clauses provide the IP binding.
+
+LIBRARY IEEE, technology_lib, ip_arria10_e1sg_jesd204b_lib, ip_arria10_e2sg_jesd204b_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE work.tech_jesd204b_component_pkg.ALL;
+
+ENTITY tech_jesd204b_tx IS
+ GENERIC (
+ g_technology : NATURAL := c_tech_select_default
+ );
+ PORT (
+ csr_cf : out std_logic_vector(4 downto 0); -- export
+ csr_cs : out std_logic_vector(1 downto 0); -- export
+ csr_f : out std_logic_vector(7 downto 0); -- export
+ csr_hd : out std_logic; -- export
+ csr_k : out std_logic_vector(4 downto 0); -- export
+ csr_l : out std_logic_vector(4 downto 0); -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
+ csr_m : out std_logic_vector(7 downto 0); -- export
+ csr_n : out std_logic_vector(4 downto 0); -- export
+ csr_np : out std_logic_vector(4 downto 0); -- export
+ csr_s : out std_logic_vector(4 downto 0); -- export
+ csr_tx_testmode : out std_logic_vector(3 downto 0); -- export
+ csr_tx_testpattern_a : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_b : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_c : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_d : out std_logic_vector(31 downto 0); -- export
+ dev_sync_n : out std_logic; -- export
+ jesd204_tx_avs_chipselect : in std_logic := 'X'; -- chipselect
+ jesd204_tx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ jesd204_tx_avs_read : in std_logic := 'X'; -- read
+ jesd204_tx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
+ jesd204_tx_avs_waitrequest : out std_logic; -- waitrequest
+ jesd204_tx_avs_write : in std_logic := 'X'; -- write
+ jesd204_tx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ jesd204_tx_avs_clk : in std_logic := 'X'; -- clk
+ jesd204_tx_avs_rst_n : in std_logic := 'X'; -- reset_n
+ jesd204_tx_dlb_data : out std_logic_vector(31 downto 0); -- export
+ jesd204_tx_dlb_kchar_data : out std_logic_vector(3 downto 0); -- export
+ jesd204_tx_frame_error : in std_logic := 'X'; -- export
+ jesd204_tx_frame_ready : out std_logic; -- export
+ jesd204_tx_int : out std_logic; -- irq
+ jesd204_tx_link_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ jesd204_tx_link_valid : in std_logic := 'X'; -- valid
+ jesd204_tx_link_ready : out std_logic; -- ready
+ mdev_sync_n : in std_logic := 'X'; -- export
+ pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
+ somf : out std_logic_vector(3 downto 0); -- export
+ sync_n : in std_logic := 'X'; -- export
+ sysref : in std_logic := 'X'; -- export
+ tx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_analogreset
+ tx_bonding_clocks : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
+ tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy
+ tx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_digitalreset
+ tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data
+ txlink_clk : in std_logic := 'X'; -- clk
+ txlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ txphy_clk : out std_logic_vector(0 downto 0) -- export
+ );
+END tech_jesd204b_tx;
+
+
+ARCHITECTURE str OF tech_jesd204b_tx IS
+BEGIN
+
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
+ u0 : ip_arria10_e1sg_jesd204b_tx
+ PORT MAP(
+ csr_cf => csr_cf ,
+ csr_cs => csr_cs ,
+ csr_f => csr_f ,
+ csr_hd => csr_hd ,
+ csr_k => csr_k ,
+ csr_l => csr_l ,
+ csr_lane_powerdown => csr_lane_powerdown ,
+ csr_m => csr_m ,
+ csr_n => csr_n ,
+ csr_np => csr_np ,
+ csr_s => csr_s ,
+ csr_tx_testmode => csr_tx_testmode ,
+ csr_tx_testpattern_a => csr_tx_testpattern_a ,
+ csr_tx_testpattern_b => csr_tx_testpattern_b ,
+ csr_tx_testpattern_c => csr_tx_testpattern_c ,
+ csr_tx_testpattern_d => csr_tx_testpattern_d ,
+ dev_sync_n => dev_sync_n ,
+ jesd204_tx_avs_chipselect => jesd204_tx_avs_chipselect ,
+ jesd204_tx_avs_address => jesd204_tx_avs_address ,
+ jesd204_tx_avs_read => jesd204_tx_avs_read ,
+ jesd204_tx_avs_readdata => jesd204_tx_avs_readdata ,
+ jesd204_tx_avs_waitrequest => jesd204_tx_avs_waitrequest,
+ jesd204_tx_avs_write => jesd204_tx_avs_write ,
+ jesd204_tx_avs_writedata => jesd204_tx_avs_writedata ,
+ jesd204_tx_avs_clk => jesd204_tx_avs_clk ,
+ jesd204_tx_avs_rst_n => jesd204_tx_avs_rst_n ,
+ jesd204_tx_dlb_data => jesd204_tx_dlb_data ,
+ jesd204_tx_dlb_kchar_data => jesd204_tx_dlb_kchar_data ,
+ jesd204_tx_frame_error => jesd204_tx_frame_error ,
+ jesd204_tx_frame_ready => jesd204_tx_frame_ready ,
+ jesd204_tx_int => jesd204_tx_int ,
+ jesd204_tx_link_data => jesd204_tx_link_data ,
+ jesd204_tx_link_valid => jesd204_tx_link_valid ,
+ jesd204_tx_link_ready => jesd204_tx_link_ready ,
+ mdev_sync_n => mdev_sync_n ,
+ pll_locked => pll_locked ,
+ somf => somf ,
+ sync_n => sync_n ,
+ sysref => sysref ,
+ tx_analogreset => tx_analogreset ,
+ tx_bonding_clocks => tx_bonding_clocks ,
+ tx_cal_busy => tx_cal_busy ,
+ tx_digitalreset => tx_digitalreset ,
+ tx_serial_data => tx_serial_data ,
+ txlink_clk => txlink_clk ,
+ txlink_rst_n_reset_n => txlink_rst_n_reset_n ,
+ txphy_clk => txphy_clk
+ );
+ END GENERATE;
+
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ip_arria10_e2sg_jesd204b_tx
+ PORT MAP(
+ csr_cf => csr_cf ,
+ csr_cs => csr_cs ,
+ csr_f => csr_f ,
+ csr_hd => csr_hd ,
+ csr_k => csr_k ,
+ csr_l => csr_l ,
+ csr_lane_powerdown => csr_lane_powerdown ,
+ csr_m => csr_m ,
+ csr_n => csr_n ,
+ csr_np => csr_np ,
+ csr_s => csr_s ,
+ csr_tx_testmode => csr_tx_testmode ,
+ csr_tx_testpattern_a => csr_tx_testpattern_a ,
+ csr_tx_testpattern_b => csr_tx_testpattern_b ,
+ csr_tx_testpattern_c => csr_tx_testpattern_c ,
+ csr_tx_testpattern_d => csr_tx_testpattern_d ,
+ dev_sync_n => dev_sync_n ,
+ jesd204_tx_avs_chipselect => jesd204_tx_avs_chipselect ,
+ jesd204_tx_avs_address => jesd204_tx_avs_address ,
+ jesd204_tx_avs_read => jesd204_tx_avs_read ,
+ jesd204_tx_avs_readdata => jesd204_tx_avs_readdata ,
+ jesd204_tx_avs_waitrequest => jesd204_tx_avs_waitrequest,
+ jesd204_tx_avs_write => jesd204_tx_avs_write ,
+ jesd204_tx_avs_writedata => jesd204_tx_avs_writedata ,
+ jesd204_tx_avs_clk => jesd204_tx_avs_clk ,
+ jesd204_tx_avs_rst_n => jesd204_tx_avs_rst_n ,
+ jesd204_tx_dlb_data => jesd204_tx_dlb_data ,
+ jesd204_tx_dlb_kchar_data => jesd204_tx_dlb_kchar_data ,
+ jesd204_tx_frame_error => jesd204_tx_frame_error ,
+ jesd204_tx_frame_ready => jesd204_tx_frame_ready ,
+ jesd204_tx_int => jesd204_tx_int ,
+ jesd204_tx_link_data => jesd204_tx_link_data ,
+ jesd204_tx_link_valid => jesd204_tx_link_valid ,
+ jesd204_tx_link_ready => jesd204_tx_link_ready ,
+ mdev_sync_n => mdev_sync_n ,
+ pll_locked => pll_locked ,
+ somf => somf ,
+ sync_n => sync_n ,
+ sysref => sysref ,
+ tx_analogreset => tx_analogreset ,
+ tx_bonding_clocks => tx_bonding_clocks ,
+ tx_cal_busy => tx_cal_busy ,
+ tx_digitalreset => tx_digitalreset ,
+ tx_serial_data => tx_serial_data ,
+ txlink_clk => txlink_clk ,
+ txlink_rst_n_reset_n => txlink_rst_n_reset_n ,
+ txphy_clk => txphy_clk
+ );
+ END GENERATE;
+
+END str;