From 2173d7f2c500f59a614f84269e0609138e86c5df Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 5 Jun 2014 06:12:00 +0000
Subject: [PATCH] Rename ip_altera_mf into ip_stratixiv.
---
.../technology/memory/tech_memory_component_pkg.vhd | 12 ++++++------
.../technology/memory/tech_memory_ram_cr_cw.vhd | 8 ++++----
.../technology/memory/tech_memory_ram_crw_crw.vhd | 8 ++++----
.../technology/memory/tech_memory_ram_crwk_crw.vhd | 8 ++++----
libraries/technology/memory/tech_memory_ram_r_w.vhd | 8 ++++----
libraries/technology/memory/tech_memory_rom_r.vhd | 8 ++++----
6 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/libraries/technology/memory/tech_memory_component_pkg.vhd b/libraries/technology/memory/tech_memory_component_pkg.vhd
index 2cbe4a2626..724dea4656 100644
--- a/libraries/technology/memory/tech_memory_component_pkg.vhd
+++ b/libraries/technology/memory/tech_memory_component_pkg.vhd
@@ -27,10 +27,10 @@ USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE tech_memory_component_pkg IS
-----------------------------------------------------------------------------
- -- altera_mf
+ -- ip_stratixiv
-----------------------------------------------------------------------------
- COMPONENT ip_altera_mf_ram_crwk_crw IS -- support different port data widths and corresponding address ranges
+ COMPONENT ip_stratixiv_ram_crwk_crw IS -- support different port data widths and corresponding address ranges
GENERIC (
g_adr_a_w : NATURAL := 5;
g_dat_a_w : NATURAL := 32;
@@ -59,7 +59,7 @@ PACKAGE tech_memory_component_pkg IS
);
END COMPONENT;
- COMPONENT ip_altera_mf_ram_crw_crw IS
+ COMPONENT ip_stratixiv_ram_crw_crw IS
GENERIC (
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 8;
@@ -85,7 +85,7 @@ PACKAGE tech_memory_component_pkg IS
);
END COMPONENT;
- COMPONENT ip_altera_mf_ram_cr_cw IS
+ COMPONENT ip_stratixiv_ram_cr_cw IS
GENERIC (
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 8;
@@ -106,7 +106,7 @@ PACKAGE tech_memory_component_pkg IS
);
END COMPONENT;
- COMPONENT ip_altera_mf_ram_r_w IS
+ COMPONENT ip_stratixiv_ram_r_w IS
GENERIC (
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 8;
@@ -124,7 +124,7 @@ PACKAGE tech_memory_component_pkg IS
);
END COMPONENT;
- COMPONENT ip_altera_mf_rom_r IS
+ COMPONENT ip_stratixiv_rom_r IS
GENERIC (
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 8;
diff --git a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
index 38057d929e..2ff73a9ae9 100644
--- a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
@@ -26,8 +26,8 @@ USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_altera_mf_lib;
-LIBRARY ip_xilinx_core_lib;
+LIBRARY ip_stratixiv_lib;
+LIBRARY ip_virtex4_lib;
ENTITY tech_memory_ram_cr_cw IS
GENERIC (
@@ -55,8 +55,8 @@ END tech_memory_ram_cr_cw;
ARCHITECTURE str OF tech_memory_ram_cr_cw IS
BEGIN
- gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
- u0 : ip_altera_mf_ram_cr_cw
+ gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
+ u0 : ip_stratixiv_ram_cr_cw
GENERIC MAP (g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
PORT MAP (data, rdaddress, rdclock, rdclocken, wraddress, wrclock, wrclocken, wren, q);
END GENERATE;
diff --git a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
index 9c43aebec6..f6028de057 100644
--- a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
@@ -26,8 +26,8 @@ USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_altera_mf_lib;
-LIBRARY ip_xilinx_core_lib;
+LIBRARY ip_stratixiv_lib;
+LIBRARY ip_virtex4_lib;
ENTITY tech_memory_ram_crw_crw IS
GENERIC (
@@ -62,8 +62,8 @@ ARCHITECTURE str OF tech_memory_ram_crw_crw IS
BEGIN
- gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
- u0 : ip_altera_mf_ram_crw_crw
+ gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
+ u0 : ip_stratixiv_ram_crw_crw
GENERIC MAP (g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, enable_a, enable_b, rden_a, rden_b, wren_a, wren_b, q_a, q_b);
END GENERATE;
diff --git a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
index 050f87fc64..c61877e2fa 100644
--- a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
@@ -26,8 +26,8 @@ USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_altera_mf_lib;
-LIBRARY ip_xilinx_core_lib;
+LIBRARY ip_stratixiv_lib;
+LIBRARY ip_virtex4_lib;
ENTITY tech_memory_ram_crwk_crw IS -- support different port data widths and corresponding address ranges
GENERIC (
@@ -64,8 +64,8 @@ END tech_memory_ram_crwk_crw;
ARCHITECTURE str OF tech_memory_ram_crwk_crw IS
BEGIN
- gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
- u0 : ip_altera_mf_ram_crwk_crw
+ gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
+ u0 : ip_stratixiv_ram_crwk_crw
GENERIC MAP (g_adr_a_w, g_dat_a_w, g_adr_b_w, g_dat_b_w, g_nof_words_a, g_nof_words_b, g_rd_latency, g_init_file)
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, enable_a, enable_b, rden_a, rden_b, wren_a, wren_b, q_a, q_b);
END GENERATE;
diff --git a/libraries/technology/memory/tech_memory_ram_r_w.vhd b/libraries/technology/memory/tech_memory_ram_r_w.vhd
index f0bec3b79a..c3ea69ed18 100644
--- a/libraries/technology/memory/tech_memory_ram_r_w.vhd
+++ b/libraries/technology/memory/tech_memory_ram_r_w.vhd
@@ -26,8 +26,8 @@ USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_altera_mf_lib;
-LIBRARY ip_xilinx_core_lib;
+LIBRARY ip_stratixiv_lib;
+LIBRARY ip_virtex4_lib;
ENTITY tech_memory_ram_r_w IS
GENERIC (
@@ -52,8 +52,8 @@ END tech_memory_ram_r_w;
ARCHITECTURE str OF tech_memory_ram_r_w IS
BEGIN
- gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
- u0 : ip_altera_mf_ram_r_w
+ gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
+ u0 : ip_stratixiv_ram_r_w
GENERIC MAP (g_adr_w, g_dat_w, g_nof_words, g_init_file)
PORT MAP (clock, enable, data, rdaddress, wraddress, wren, q);
END GENERATE;
diff --git a/libraries/technology/memory/tech_memory_rom_r.vhd b/libraries/technology/memory/tech_memory_rom_r.vhd
index 263aa34206..d32c852b56 100644
--- a/libraries/technology/memory/tech_memory_rom_r.vhd
+++ b/libraries/technology/memory/tech_memory_rom_r.vhd
@@ -26,8 +26,8 @@ USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_altera_mf_lib;
-LIBRARY ip_xilinx_core_lib;
+LIBRARY ip_stratixiv_lib;
+LIBRARY ip_virtex4_lib;
ENTITY tech_memory_rom_r IS
GENERIC (
@@ -48,8 +48,8 @@ END tech_memory_rom_r;
ARCHITECTURE str OF tech_memory_rom_r IS
BEGIN
- gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
- u0 : ip_altera_mf_rom_r
+ gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
+ u0 : ip_stratixiv_rom_r
GENERIC MAP (g_adr_w, g_dat_w, g_nof_words, g_init_file)
PORT MAP (address, clock, clken, q);
END GENERATE;
--
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