diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
index 696629eeab95d5fb2b1c99da91dcbd4c97b9f431..1b4f52aa78ed24b1ff765d57f4b775d0a69fadf3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
@@ -60,43 +60,43 @@ peripherals:
mm_port_names:
- REG_FPGA_TEMP_SENS
- REG_FPGA_VOLTAGE_SENS
-
+
- peripheral_name: unb2b_board/ram_scrap
mm_port_names:
- RAM_SCRAP
-
+
- peripheral_name: eth/eth
mm_port_names:
- AVS_ETH_0_TSE
- AVS_ETH_0_REG
- AVS_ETH_0_RAM
-
+
- peripheral_name: ppsh/ppsh
mm_port_names:
- PIO_PPS
-
+
- peripheral_name: epcs/epcs
parameter_overrides:
- { name: "g_epcs_addr_w", value: 32 }
mm_port_names:
- REG_EPCS
-
+
- peripheral_name: dp/dpmm
mm_port_names:
- REG_DPMM_CTRL
- REG_DPMM_DATA
-
+
- peripheral_name: dp/mmdp
mm_port_names:
- REG_MMDP_CTRL
- REG_MMDP_DATA
-
+
- peripheral_name: remu/remu
parameter_overrides:
- { name: g_data_w, value: 32 }
mm_port_names:
- REG_REMU
-
+
#############################################################################
# SDP Info
#############################################################################
@@ -104,7 +104,7 @@ peripherals:
- peripheral_name: sdp/sdp_info
mm_port_names:
- REG_SDP_INFO
-
+
#############################################################################
# Ring Info
#############################################################################
@@ -116,17 +116,17 @@ peripherals:
#############################################################################
# AIT = ADC Input and Timing (see node_adc_input_and_timing.vhd)
#############################################################################
-
+
- peripheral_name: tech_jesd204b/jesd_ctrl
mm_port_names:
- PIO_JESD_CTRL
-
+
- peripheral_name: tech_jesd204b/jesd204b_arria10
parameter_overrides:
- { name: g_nof_streams, value: c_S_pn }
mm_port_names:
- JESD204B
-
+
- peripheral_name: dp/dp_shiftram
parameter_overrides:
- { name: g_nof_streams, value: c_S_pn }
@@ -142,16 +142,16 @@ peripherals:
- { name: g_bsn_time_offset_w, value: ceil_log2(c_N_fft) }
mm_port_names:
- REG_BSN_SOURCE_V2
-
+
- peripheral_name: dp/dp_bsn_scheduler
mm_port_names:
- REG_BSN_SCHEDULER
-
+
- peripheral_name: dp/dp_bsn_monitor
peripheral_group: input
mm_port_names:
- REG_BSN_MONITOR_INPUT
-
+
- peripheral_name: diag/diag_wg_wideband
parameter_overrides:
- { name: g_nof_streams, value: c_S_pn }
@@ -165,7 +165,7 @@ peripherals:
- { name: g_nof_bins, value: c_V_si_histogram }
- { name: g_nof_data_per_sync, value: c_nof_clk_per_pps}
mm_port_names:
- - RAM_ST_HISTOGRAM
+ - RAM_ST_HISTOGRAM
- peripheral_name: aduh/aduh_mon_dc_power
parameter_overrides:
@@ -193,17 +193,17 @@ peripherals:
mm_port_names:
- REG_DIAG_DATA_BUFFER_BSN
- RAM_DIAG_DATA_BUFFER_BSN
-
+
#############################################################################
# Fsub = Subband Filterbank (from node_sdp_filterbank.vhd)
#############################################################################
-
+
- peripheral_name: si/si
parameter_overrides:
- { name: g_nof_streams, value: c_S_pn }
mm_port_names:
- REG_SI
-
+
- peripheral_name: filter/fil_ppf_w
number_of_peripherals: c_R_os # Disturb uses 2x oversample
peripheral_span: ceil_pow2(c_N_taps) * ceil_pow2(c_N_fft) * MM_BUS_SIZE # number_of_ports = ceil_pow2(c_N_taps), mm_port_span = ceil_pow2(c_N_fft) words
@@ -216,7 +216,7 @@ peripherals:
- { name: g_fil_ppf.coef_dat_w, value: c_W_fir_coef }
mm_port_names:
- RAM_FIL_COEFS
-
+
- peripheral_name: sdp/sdp_subband_equalizer
parameter_overrides:
- { name: P_pfb, value: c_R_os * c_P_pfb} # DISTURB uses 2x oversample so 2 X P_pfb
@@ -227,13 +227,13 @@ peripherals:
- peripheral_name: dp/dp_selector
mm_port_names:
- REG_DP_SELECTOR # input_select = 0 for weighted subbands, input_select = 1 for raw subbands
-
+
- peripheral_name: st/st_sst_for_sdp
parameter_overrides:
- { name: g_nof_instances, value: c_R_os * c_P_pfb} # DISTURB uses 2x oversample so 2 X P_pfb
mm_port_names:
- RAM_ST_SST
-
+
- peripheral_name: common/common_variable_delay
peripheral_group: sst
mm_port_names:
@@ -243,7 +243,7 @@ peripherals:
peripheral_group: sst
mm_port_names:
- REG_STAT_HDR_DAT_SST
-
+
- peripheral_name: dp/dp_bsn_monitor_v2
peripheral_group: sst_udp
parameter_overrides:
@@ -259,14 +259,14 @@ peripherals:
peripheral_group: xsub
mm_port_names:
- REG_BSN_SYNC_SCHEDULER_XSUB
-
+
- peripheral_name: st/st_xst_for_sdp
parameter_overrides:
- { name: g_nof_streams, value: c_P_sq }
- { name: g_nof_crosslets, value: c_N_crosslets }
mm_port_names:
- RAM_ST_XSQ
-
+
- peripheral_name: sdp/sdp_crosslets_subband_select
mm_port_names:
- REG_CROSSLETS_INFO
@@ -291,33 +291,33 @@ peripherals:
- { name: g_nof_streams, value: c_P_sq }
mm_port_names:
- REG_BSN_ALIGN_V2_XSUB
-
+
- peripheral_name: dp/dp_bsn_monitor_v2
peripheral_group: rx_align_xsub
parameter_overrides:
- { name: g_nof_streams, value: c_P_sq }
mm_port_names:
- REG_BSN_MONITOR_V2_RX_ALIGN_XSUB
-
+
- peripheral_name: dp/dp_bsn_monitor_v2
peripheral_group: aligned_xsub
parameter_overrides:
- { name: g_nof_streams, value: 1 }
mm_port_names:
- REG_BSN_MONITOR_V2_ALIGNED_XSUB
-
+
- peripheral_name: dp/dp_bsn_monitor_v2
peripheral_group: xst_udp
parameter_overrides:
- { name: g_nof_streams, value: 1 }
mm_port_names:
- REG_BSN_MONITOR_V2_XST_OFFLOAD
-
+
- peripheral_name: ring/ring_lane_info
peripheral_group: xsub
mm_port_names:
- REG_RING_LANE_INFO_XST
-
+
- peripheral_name: dp/dp_bsn_monitor_v2
peripheral_group: ring_rx
parameter_overrides:
@@ -341,7 +341,7 @@ peripherals:
- peripheral_name: dp/dp_block_validate_bsn_at_sync
mm_port_names:
- REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST
-
+
- peripheral_name: tr_10GbE/tr_10GbE_unb2legacy # For ring interface
parameter_overrides:
- { name: g_nof_macs, value: c_ring_nof_mac }
@@ -357,7 +357,7 @@ peripherals:
#############################################################################
# BF = Beamformer (from node_sdp_beamformer.vhd)
#############################################################################
-
+
- peripheral_name: reorder/reorder_col_wide
number_of_peripherals: c_N_beamsets
peripheral_span: ceil_pow2(c_P_pfb) * ceil_pow2(c_S_sub_bf * c_Q_fft) * MM_BUS_SIZE # number_of_ports = c_P_pfb, mm_port_span = ceil_pow2(c_S_sub_bf * c_Q_fft) words
@@ -382,7 +382,7 @@ peripherals:
- { name: g_nof_streams, value: c_P_sum }
mm_port_names:
- REG_BSN_ALIGN_V2_BF
-
+
- peripheral_name: dp/dp_bsn_monitor_v2
peripheral_group: rx_align_bf
number_of_peripherals: c_N_beamsets
@@ -391,7 +391,7 @@ peripherals:
- { name: g_nof_streams, value: c_P_sum }
mm_port_names:
- REG_BSN_MONITOR_V2_RX_ALIGN_BF
-
+
- peripheral_name: dp/dp_bsn_monitor_v2
peripheral_group: aligned_bf
number_of_peripherals: c_N_beamsets
@@ -400,14 +400,14 @@ peripherals:
- { name: g_nof_streams, value: 1 }
mm_port_names:
- REG_BSN_MONITOR_V2_ALIGNED_BF
-
+
- peripheral_name: ring/ring_lane_info
peripheral_group: bf
number_of_peripherals: c_N_beamsets
peripheral_span: 2 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 2 words
mm_port_names:
- REG_RING_LANE_INFO_BF
-
+
- peripheral_name: dp/dp_bsn_monitor_v2
peripheral_group: ring_rx_bf
number_of_peripherals: c_N_beamsets
@@ -451,6 +451,12 @@ peripherals:
mm_port_names:
- REG_BF_SCALE
+ - peripheral_name: sdp/sdp_bdo_destinations
+ number_of_peripherals: c_N_beamsets
+ peripheral_span: 256 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 256 words
+ mm_port_names:
+ - REG_BDO_DESTINATIONS
+
- peripheral_name: sdp/sdp_beamformer_output_hdr_dat
number_of_peripherals: c_N_beamsets
peripheral_span: 64 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 64 words
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations.ip
new file mode 100644
index 0000000000000000000000000000000000000000..12f77c1bd517e6d1e4b3d256d9dc272551a25988
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations.ip
@@ -0,0 +1,1447 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">2048</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>8</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>8</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">9</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>9</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>9</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>2048</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>11</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ip.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ip.tcl
index 1090c43d8c513a1c7a8cb3fab2907ed000cc5c92..a066064ba1d4b19838086e97fad1da7d4c621fa3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ip.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ip.tcl
@@ -46,6 +46,7 @@ set_global_assignment -name IP_FILE $IP_PATH/qsys_lofar2_unb2b_sdp_station_ram_s
set_global_assignment -name IP_FILE $IP_PATH/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
set_global_assignment -name IP_FILE $IP_PATH/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
set_global_assignment -name IP_FILE $IP_PATH/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+set_global_assignment -name IP_FILE $IP_PATH/qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations.ip
set_global_assignment -name IP_FILE $IP_PATH/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
set_global_assignment -name IP_FILE $IP_PATH/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
set_global_assignment -name IP_FILE $IP_PATH/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
index f10344966a54ff5c45c0bc68324fad76512d6225..034f54b0744429ee0314616a0febf66a80e74cc9 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
@@ -99,7 +99,7 @@
{
datum baseAddress
{
- value = "1330192";
+ value = "1332240";
type = "String";
}
}
@@ -144,7 +144,7 @@
{
datum baseAddress
{
- value = "1330120";
+ value = "1332168";
type = "String";
}
}
@@ -165,7 +165,7 @@
{
datum baseAddress
{
- value = "1330080";
+ value = "1332128";
type = "String";
}
}
@@ -298,7 +298,7 @@
{
datum baseAddress
{
- value = "2048";
+ value = "1327104";
type = "String";
}
}
@@ -410,7 +410,23 @@
{
datum baseAddress
{
- value = "1327872";
+ value = "1329920";
+ type = "String";
+ }
+ }
+ element reg_bdo_destinations
+ {
+ datum _sortIndex
+ {
+ value = "82";
+ type = "int";
+ }
+ }
+ element reg_bdo_destinations.mem
+ {
+ datum baseAddress
+ {
+ value = "2048";
type = "String";
}
}
@@ -426,7 +442,7 @@
{
datum baseAddress
{
- value = "1330064";
+ value = "1332112";
type = "String";
}
}
@@ -442,7 +458,7 @@
{
datum baseAddress
{
- value = "1329696";
+ value = "1331744";
type = "String";
}
}
@@ -458,7 +474,7 @@
{
datum baseAddress
{
- value = "1328640";
+ value = "1330688";
type = "String";
}
}
@@ -490,7 +506,7 @@
{
datum baseAddress
{
- value = "1329152";
+ value = "1331200";
type = "String";
}
}
@@ -506,7 +522,7 @@
{
datum baseAddress
{
- value = "1329824";
+ value = "1331872";
type = "String";
}
}
@@ -522,7 +538,7 @@
{
datum baseAddress
{
- value = "1329216";
+ value = "1331264";
type = "String";
}
}
@@ -538,7 +554,7 @@
{
datum baseAddress
{
- value = "1329280";
+ value = "1331328";
type = "String";
}
}
@@ -554,7 +570,7 @@
{
datum baseAddress
{
- value = "1329088";
+ value = "1331136";
type = "String";
}
}
@@ -586,7 +602,7 @@
{
datum baseAddress
{
- value = "1329024";
+ value = "1331072";
type = "String";
}
}
@@ -650,7 +666,7 @@
{
datum baseAddress
{
- value = "1329728";
+ value = "1331776";
type = "String";
}
}
@@ -666,7 +682,7 @@
{
datum baseAddress
{
- value = "1329792";
+ value = "1331840";
type = "String";
}
}
@@ -682,7 +698,7 @@
{
datum baseAddress
{
- value = "1330144";
+ value = "1332192";
type = "String";
}
}
@@ -698,7 +714,7 @@
{
datum baseAddress
{
- value = "1329856";
+ value = "1331904";
type = "String";
}
}
@@ -714,7 +730,7 @@
{
datum baseAddress
{
- value = "1329408";
+ value = "1331456";
type = "String";
}
}
@@ -730,7 +746,7 @@
{
datum baseAddress
{
- value = "1329472";
+ value = "1331520";
type = "String";
}
}
@@ -746,7 +762,7 @@
{
datum baseAddress
{
- value = "1328768";
+ value = "1330816";
type = "String";
}
}
@@ -762,7 +778,7 @@
{
datum baseAddress
{
- value = "1329664";
+ value = "1331712";
type = "String";
}
}
@@ -786,7 +802,7 @@
{
datum baseAddress
{
- value = "1330016";
+ value = "1332064";
type = "String";
}
}
@@ -818,7 +834,7 @@
{
datum baseAddress
{
- value = "1329344";
+ value = "1331392";
type = "String";
}
}
@@ -834,7 +850,7 @@
{
datum baseAddress
{
- value = "1330136";
+ value = "1332184";
type = "String";
}
}
@@ -850,7 +866,7 @@
{
datum baseAddress
{
- value = "1328896";
+ value = "1330944";
type = "String";
}
}
@@ -866,7 +882,7 @@
{
datum baseAddress
{
- value = "1330048";
+ value = "1332096";
type = "String";
}
}
@@ -887,7 +903,7 @@
{
datum baseAddress
{
- value = "1330184";
+ value = "1332232";
type = "String";
}
}
@@ -908,7 +924,7 @@
{
datum baseAddress
{
- value = "1330176";
+ value = "1332224";
type = "String";
}
}
@@ -929,7 +945,7 @@
{
datum baseAddress
{
- value = "1329920";
+ value = "1331968";
type = "String";
}
}
@@ -945,7 +961,7 @@
{
datum baseAddress
{
- value = "1329888";
+ value = "1331936";
type = "String";
}
}
@@ -966,7 +982,7 @@
{
datum baseAddress
{
- value = "1329600";
+ value = "1331648";
type = "String";
}
}
@@ -982,7 +998,7 @@
{
datum baseAddress
{
- value = "1327104";
+ value = "1329152";
type = "String";
}
}
@@ -1003,7 +1019,7 @@
{
datum baseAddress
{
- value = "1330168";
+ value = "1332216";
type = "String";
}
}
@@ -1024,7 +1040,7 @@
{
datum baseAddress
{
- value = "1330160";
+ value = "1332208";
type = "String";
}
}
@@ -1040,7 +1056,7 @@
{
datum baseAddress
{
- value = "1330096";
+ value = "1332144";
type = "String";
}
}
@@ -1056,7 +1072,7 @@
{
datum baseAddress
{
- value = "1330128";
+ value = "1332176";
type = "String";
}
}
@@ -1093,7 +1109,7 @@
{
datum baseAddress
{
- value = "1329952";
+ value = "1332000";
type = "String";
}
}
@@ -1109,7 +1125,7 @@
{
datum baseAddress
{
- value = "1330000";
+ value = "1332048";
type = "String";
}
}
@@ -1125,7 +1141,7 @@
{
datum baseAddress
{
- value = "1329984";
+ value = "1332032";
type = "String";
}
}
@@ -1157,7 +1173,7 @@
{
datum baseAddress
{
- value = "1329536";
+ value = "1331584";
type = "String";
}
}
@@ -1173,7 +1189,7 @@
{
datum baseAddress
{
- value = "1330152";
+ value = "1332200";
type = "String";
}
}
@@ -1189,7 +1205,7 @@
{
datum baseAddress
{
- value = "1330032";
+ value = "1332080";
type = "String";
}
}
@@ -1205,7 +1221,7 @@
{
datum baseAddress
{
- value = "1330112";
+ value = "1332160";
type = "String";
}
}
@@ -1221,7 +1237,7 @@
{
datum baseAddress
{
- value = "1330104";
+ value = "1332152";
type = "String";
}
}
@@ -1285,7 +1301,7 @@
{
datum baseAddress
{
- value = "1329760";
+ value = "1331808";
type = "String";
}
}
@@ -1317,7 +1333,7 @@
{
datum baseAddress
{
- value = "1328128";
+ value = "1330176";
type = "String";
}
}
@@ -1333,7 +1349,7 @@
{
datum baseAddress
{
- value = "1328384";
+ value = "1330432";
type = "String";
}
}
@@ -1375,7 +1391,7 @@
{
datum baseAddress
{
- value = "1327616";
+ value = "1329664";
type = "String";
}
}
@@ -2138,6 +2154,41 @@
internal="reg_aduh_monitor.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_bdo_destinations_address"
+ internal="reg_bdo_destinations.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bdo_destinations_clk"
+ internal="reg_bdo_destinations.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bdo_destinations_read"
+ internal="reg_bdo_destinations.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bdo_destinations_readdata"
+ internal="reg_bdo_destinations.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bdo_destinations_reset"
+ internal="reg_bdo_destinations.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bdo_destinations_write"
+ internal="reg_bdo_destinations.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bdo_destinations_writedata"
+ internal="reg_bdo_destinations.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_bf_scale_address"
internal="reg_bf_scale.address"
@@ -7088,7 +7139,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xE0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xE0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains_cross.mem' start='0x100000' end='0x110000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x110000' end='0x120000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x120000' end='0x130000' datawidth='32' /><slave name='ram_wg.mem' start='0x130000' end='0x140000' datawidth='32' /><slave name='jesd204b.mem' start='0x140000' end='0x144000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x144000' end='0x144200' datawidth='32' /><slave name='reg_wg.mem' start='0x144200' end='0x144300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x144300' end='0x144400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x144400' end='0x144500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x144500' end='0x144600' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x144600' end='0x144680' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x144680' end='0x144700' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x144700' end='0x144780' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x144780' end='0x1447C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x1447C0' end='0x144800' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x144800' end='0x144840' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x144840' end='0x144880' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x144880' end='0x1448C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x1448C0' end='0x144900' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x144900' end='0x144940' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x144940' end='0x144980' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x144980' end='0x1449C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x1449C0' end='0x144A00' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x144A00' end='0x144A20' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x144A20' end='0x144A40' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x144A40' end='0x144A60' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x144A60' end='0x144A80' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x144A80' end='0x144AA0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x144AA0' end='0x144AC0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x144AC0' end='0x144AE0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x144AE0' end='0x144B00' datawidth='32' /><slave name='reg_epcs.mem' start='0x144B00' end='0x144B20' datawidth='32' /><slave name='reg_remu.mem' start='0x144B20' end='0x144B40' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x144B40' end='0x144B50' datawidth='32' /><slave name='reg_ring_info.mem' start='0x144B50' end='0x144B60' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x144B60' end='0x144B70' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x144B70' end='0x144B80' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x144B80' end='0x144B90' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x144B90' end='0x144BA0' datawidth='32' /><slave name='pio_pps.mem' start='0x144BA0' end='0x144BB0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x144BB0' end='0x144BB8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x144BB8' end='0x144BC0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x144BC0' end='0x144BC8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x144BC8' end='0x144BD0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x144BD0' end='0x144BD8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x144BD8' end='0x144BE0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x144BE0' end='0x144BE8' datawidth='32' /><slave name='reg_si.mem' start='0x144BE8' end='0x144BF0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x144BF0' end='0x144BF8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x144BF8' end='0x144C00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x144C00' end='0x144C08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x144C08' end='0x144C10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x144C10' end='0x144C18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='reg_bdo_destinations.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xE0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xE0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains_cross.mem' start='0x100000' end='0x110000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x110000' end='0x120000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x120000' end='0x130000' datawidth='32' /><slave name='ram_wg.mem' start='0x130000' end='0x140000' datawidth='32' /><slave name='jesd204b.mem' start='0x140000' end='0x144000' datawidth='32' /><slave name='ram_scrap.mem' start='0x144000' end='0x144800' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x144800' end='0x144A00' datawidth='32' /><slave name='reg_wg.mem' start='0x144A00' end='0x144B00' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x144B00' end='0x144C00' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x144C00' end='0x144D00' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x144D00' end='0x144E00' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x144E00' end='0x144E80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x144E80' end='0x144F00' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x144F00' end='0x144F80' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x144F80' end='0x144FC0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x144FC0' end='0x145000' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x145000' end='0x145040' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x145040' end='0x145080' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x145080' end='0x1450C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x1450C0' end='0x145100' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x145100' end='0x145140' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x145140' end='0x145180' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x145180' end='0x1451C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x1451C0' end='0x145200' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x145200' end='0x145220' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x145220' end='0x145240' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x145240' end='0x145260' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x145260' end='0x145280' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x145280' end='0x1452A0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x1452A0' end='0x1452C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x1452C0' end='0x1452E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x1452E0' end='0x145300' datawidth='32' /><slave name='reg_epcs.mem' start='0x145300' end='0x145320' datawidth='32' /><slave name='reg_remu.mem' start='0x145320' end='0x145340' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x145340' end='0x145350' datawidth='32' /><slave name='reg_ring_info.mem' start='0x145350' end='0x145360' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x145360' end='0x145370' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x145370' end='0x145380' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x145380' end='0x145390' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x145390' end='0x1453A0' datawidth='32' /><slave name='pio_pps.mem' start='0x1453A0' end='0x1453B0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x1453B0' end='0x1453B8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x1453B8' end='0x1453C0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x1453C0' end='0x1453C8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x1453C8' end='0x1453D0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x1453D0' end='0x1453D8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x1453D8' end='0x1453E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x1453E0' end='0x1453E8' datawidth='32' /><slave name='reg_si.mem' start='0x1453E8' end='0x1453F0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x1453F0' end='0x1453F8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x1453F8' end='0x145400' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x145400' end='0x145408' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x145408' end='0x145410' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x145410' end='0x145418' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -14594,11 +14645,627 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>17</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="ram_scrap"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>9</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>9</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>2048</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>17</value>
+ <value>11</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -14625,37 +15292,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_scrap</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_scrap"
+ name="ram_ss_ss_wide"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -14671,7 +15338,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>9</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14735,7 +15402,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>9</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14804,7 +15471,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>2048</value>
+ <value>65536</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -15210,11 +15877,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>11</value>
+ <value>16</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -15241,37 +15908,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_scrap</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_ss_ss_wide"
+ name="ram_st_bst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -15287,7 +15954,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15351,7 +16018,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15420,7 +16087,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>16384</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -15826,11 +16493,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x4000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>14</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -15857,37 +16524,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_st_bst"
+ name="ram_st_histogram"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -15903,7 +16570,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>12</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15967,7 +16634,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>12</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16036,7 +16703,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16384</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -16442,11 +17109,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x4000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>14</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -16473,37 +17140,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_st_histogram"
+ name="ram_st_sst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -16519,7 +17186,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16583,7 +17250,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16652,7 +17319,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>131072</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -17058,11 +17725,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>17</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -17089,37 +17756,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_histogram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_st_sst"
+ name="ram_st_xsq"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -17135,7 +17802,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>15</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17199,7 +17866,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>15</width>
+ <width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17268,7 +17935,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>131072</value>
+ <value>262144</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -17674,11 +18341,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>17</value>
+ <value>18</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -17705,37 +18372,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_st_xsq"
+ name="ram_wg"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -17751,7 +18418,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>16</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17815,7 +18482,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>16</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17884,7 +18551,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>262144</value>
+ <value>65536</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -18290,11 +18957,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>18</value>
+ <value>16</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -18321,37 +18988,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_wg</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_wg"
+ name="reg_aduh_monitor"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -18367,7 +19034,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18431,7 +19098,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18500,7 +19167,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -18906,11 +19573,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -18937,37 +19604,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_wg</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_aduh_monitor"
+ name="reg_bdo_destinations"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -18983,7 +19650,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>9</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19047,7 +19714,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>9</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19116,7 +19783,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>2048</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -19522,11 +20189,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>11</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -19553,30 +20220,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bdo_destinations.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -56039,7 +56706,7 @@
version="18.0"
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
- <parameter name="baseAddress" value="0x00144c10" />
+ <parameter name="baseAddress" value="0x00145410" />
</connection>
<connection
kind="avalon"
@@ -56053,7 +56720,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_unb_sens.mem">
- <parameter name="baseAddress" value="0x00144500" />
+ <parameter name="baseAddress" value="0x00144d00" />
</connection>
<connection
kind="avalon"
@@ -56074,7 +56741,7 @@
version="18.0"
start="cpu_0.data_master"
end="pio_pps.mem">
- <parameter name="baseAddress" value="0x00144ba0" />
+ <parameter name="baseAddress" value="0x001453a0" />
</connection>
<connection
kind="avalon"
@@ -56088,63 +56755,63 @@
version="18.0"
start="cpu_0.data_master"
end="reg_remu.mem">
- <parameter name="baseAddress" value="0x00144b20" />
+ <parameter name="baseAddress" value="0x00145320" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_epcs.mem">
- <parameter name="baseAddress" value="0x00144b00" />
+ <parameter name="baseAddress" value="0x00145300" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
- <parameter name="baseAddress" value="0x00144c08" />
+ <parameter name="baseAddress" value="0x00145408" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
- <parameter name="baseAddress" value="0x00144c00" />
+ <parameter name="baseAddress" value="0x00145400" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
- <parameter name="baseAddress" value="0x00144bf8" />
+ <parameter name="baseAddress" value="0x001453f8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
- <parameter name="baseAddress" value="0x00144bf0" />
+ <parameter name="baseAddress" value="0x001453f0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
- <parameter name="baseAddress" value="0x00144ae0" />
+ <parameter name="baseAddress" value="0x001452e0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_unb_pmbus.mem">
- <parameter name="baseAddress" value="0x00144400" />
+ <parameter name="baseAddress" value="0x00144c00" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
- <parameter name="baseAddress" value="0x001449c0" />
+ <parameter name="baseAddress" value="0x001451c0" />
</connection>
<connection
kind="avalon"
@@ -56158,7 +56825,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_si.mem">
- <parameter name="baseAddress" value="0x00144be8" />
+ <parameter name="baseAddress" value="0x001453e8" />
</connection>
<connection
kind="avalon"
@@ -56172,14 +56839,14 @@
version="18.0"
start="cpu_0.data_master"
end="ram_scrap.mem">
- <parameter name="baseAddress" value="0x0800" />
+ <parameter name="baseAddress" value="0x00144000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_aduh_monitor.mem">
- <parameter name="baseAddress" value="0x00144300" />
+ <parameter name="baseAddress" value="0x00144b00" />
</connection>
<connection
kind="avalon"
@@ -56193,28 +56860,28 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_shiftram.mem">
- <parameter name="baseAddress" value="0x00144700" />
+ <parameter name="baseAddress" value="0x00144f00" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_scheduler.mem">
- <parameter name="baseAddress" value="0x00144be0" />
+ <parameter name="baseAddress" value="0x001453e0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_source_v2.mem">
- <parameter name="baseAddress" value="0x00144ac0" />
+ <parameter name="baseAddress" value="0x001452c0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_wg.mem">
- <parameter name="baseAddress" value="0x00144200" />
+ <parameter name="baseAddress" value="0x00144a00" />
</connection>
<connection
kind="avalon"
@@ -56235,7 +56902,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_selector.mem">
- <parameter name="baseAddress" value="0x00144bd8" />
+ <parameter name="baseAddress" value="0x001453d8" />
</connection>
<connection
kind="avalon"
@@ -56249,21 +56916,21 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bf_scale.mem">
- <parameter name="baseAddress" value="0x00144b90" />
+ <parameter name="baseAddress" value="0x00145390" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_hdr_dat.mem">
- <parameter name="baseAddress" value="0x00144000" />
+ <parameter name="baseAddress" value="0x00144800" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dp_xonoff.mem">
- <parameter name="baseAddress" value="0x00144b80" />
+ <parameter name="baseAddress" value="0x00145380" />
</connection>
<connection
kind="avalon"
@@ -56277,14 +56944,14 @@
version="18.0"
start="cpu_0.data_master"
end="reg_sdp_info.mem">
- <parameter name="baseAddress" value="0x00144980" />
+ <parameter name="baseAddress" value="0x00145180" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_nw_10gbe_eth10g.mem">
- <parameter name="baseAddress" value="0x00144bd0" />
+ <parameter name="baseAddress" value="0x001453d0" />
</connection>
<connection
kind="avalon"
@@ -56298,7 +56965,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_diag_data_buffer_bsn.mem">
- <parameter name="baseAddress" value="0x00144680" />
+ <parameter name="baseAddress" value="0x00144e80" />
</connection>
<connection
kind="avalon"
@@ -56312,14 +56979,14 @@
version="18.0"
start="cpu_0.data_master"
end="pio_jesd_ctrl.mem">
- <parameter name="baseAddress" value="0x00144bc8" />
+ <parameter name="baseAddress" value="0x001453c8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_sst.mem">
- <parameter name="baseAddress" value="0x00144bc0" />
+ <parameter name="baseAddress" value="0x001453c0" />
</connection>
<connection
kind="avalon"
@@ -56333,7 +57000,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_bst.mem">
- <parameter name="baseAddress" value="0x00144b70" />
+ <parameter name="baseAddress" value="0x00145370" />
</connection>
<connection
kind="avalon"
@@ -56347,7 +57014,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_crosslets_info.mem">
- <parameter name="baseAddress" value="0x00144940" />
+ <parameter name="baseAddress" value="0x00145140" />
</connection>
<connection
kind="avalon"
@@ -56361,7 +57028,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_xst.mem">
- <parameter name="baseAddress" value="0x00144bb8" />
+ <parameter name="baseAddress" value="0x001453b8" />
</connection>
<connection
kind="avalon"
@@ -56375,7 +57042,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_sync_scheduler_xsub.mem">
- <parameter name="baseAddress" value="0x00144900" />
+ <parameter name="baseAddress" value="0x00145100" />
</connection>
<connection
kind="avalon"
@@ -56389,14 +57056,14 @@
version="18.0"
start="cpu_0.data_master"
end="reg_nof_crosslets.mem">
- <parameter name="baseAddress" value="0x00144bb0" />
+ <parameter name="baseAddress" value="0x001453b0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_align_v2_xsub.mem">
- <parameter name="baseAddress" value="0x00144600" />
+ <parameter name="baseAddress" value="0x00144e00" />
</connection>
<connection
kind="avalon"
@@ -56410,14 +57077,14 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_aligned_xsub.mem">
- <parameter name="baseAddress" value="0x00144aa0" />
+ <parameter name="baseAddress" value="0x001452a0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_xst_offload.mem">
- <parameter name="baseAddress" value="0x00144a80" />
+ <parameter name="baseAddress" value="0x00145280" />
</connection>
<connection
kind="avalon"
@@ -56445,28 +57112,28 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_block_validate_err_xst.mem">
- <parameter name="baseAddress" value="0x001448c0" />
+ <parameter name="baseAddress" value="0x001450c0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dp_block_validate_bsn_at_sync_xst.mem">
- <parameter name="baseAddress" value="0x00144b60" />
+ <parameter name="baseAddress" value="0x00145360" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_ring_info.mem">
- <parameter name="baseAddress" value="0x00144b50" />
+ <parameter name="baseAddress" value="0x00145350" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_tr_10gbe_eth10g.mem">
- <parameter name="baseAddress" value="0x00144a60" />
+ <parameter name="baseAddress" value="0x00145260" />
</connection>
<connection
kind="avalon"
@@ -56480,28 +57147,28 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_sst_offload.mem">
- <parameter name="baseAddress" value="0x00144a40" />
+ <parameter name="baseAddress" value="0x00145240" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_bst_offload.mem">
- <parameter name="baseAddress" value="0x00144880" />
+ <parameter name="baseAddress" value="0x00145080" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_beamlet_output.mem">
- <parameter name="baseAddress" value="0x00144840" />
+ <parameter name="baseAddress" value="0x00145040" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_align_v2_bf.mem">
- <parameter name="baseAddress" value="0x00144a20" />
+ <parameter name="baseAddress" value="0x00145220" />
</connection>
<connection
kind="avalon"
@@ -56515,28 +57182,28 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_aligned_bf.mem">
- <parameter name="baseAddress" value="0x00144800" />
+ <parameter name="baseAddress" value="0x00145000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_ring_lane_info_bf.mem">
- <parameter name="baseAddress" value="0x00144b40" />
+ <parameter name="baseAddress" value="0x00145340" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_ring_rx_bf.mem">
- <parameter name="baseAddress" value="0x001447c0" />
+ <parameter name="baseAddress" value="0x00144fc0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_ring_tx_bf.mem">
- <parameter name="baseAddress" value="0x00144780" />
+ <parameter name="baseAddress" value="0x00144f80" />
</connection>
<connection
kind="avalon"
@@ -56550,7 +57217,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_block_validate_bsn_at_sync_bf.mem">
- <parameter name="baseAddress" value="0x00144a00" />
+ <parameter name="baseAddress" value="0x00145200" />
</connection>
<connection
kind="avalon"
@@ -56573,6 +57240,13 @@
end="ram_equalizer_gains_cross.mem">
<parameter name="baseAddress" value="0x00100000" />
</connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_bdo_destinations.mem">
+ <parameter name="baseAddress" value="0x0800" />
+ </connection>
<connection
kind="avalon"
version="18.0"
@@ -56966,6 +57640,11 @@
version="18.0"
start="clk_0.clk"
end="ram_equalizer_gains_cross.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_bdo_destinations.system" />
<connection
kind="interrupt"
version="18.0"
@@ -57382,6 +58061,11 @@
version="18.0"
start="clk_0.clk_reset"
end="ram_equalizer_gains_cross.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_bdo_destinations.system_reset" />
<connection
kind="reset"
version="18.0"
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index b293ea12e27dbbe5832679200f756b61de20950c..50813fd6e158e303f7439e6ff6cda8bcacb5dbfc 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -337,6 +337,8 @@ architecture str of lofar2_unb2b_sdp_station is
-- Beamlet Data Output header fields
signal reg_hdr_dat_copi : t_mem_copi := c_mem_copi_rst;
signal reg_hdr_dat_cipo : t_mem_cipo := c_mem_cipo_rst;
+ signal reg_bdo_destinations_copi : t_mem_copi := c_mem_mosi_rst;
+ signal reg_bdo_destinations_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Beamlet Data Output xonoff
signal reg_dp_xonoff_copi : t_mem_copi := c_mem_copi_rst;
@@ -720,6 +722,8 @@ begin
reg_bf_scale_cipo => reg_bf_scale_cipo,
reg_hdr_dat_copi => reg_hdr_dat_copi,
reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_bdo_destinations_copi => reg_bdo_destinations_copi,
+ reg_bdo_destinations_cipo => reg_bdo_destinations_cipo,
reg_dp_xonoff_copi => reg_dp_xonoff_copi,
reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
ram_st_bst_copi => ram_st_bst_copi,
@@ -917,6 +921,8 @@ begin
reg_bf_scale_cipo => reg_bf_scale_cipo,
reg_hdr_dat_copi => reg_hdr_dat_copi,
reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_bdo_destinations_copi => reg_bdo_destinations_copi,
+ reg_bdo_destinations_cipo => reg_bdo_destinations_cipo,
reg_dp_xonoff_copi => reg_dp_xonoff_copi,
reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
ram_st_bst_copi => ram_st_bst_copi,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
index f7da00a28564493a8e525870cb770b4ef89469cb..5f3c67cba2d45e3b1a17a1f40ee74994c39095fd 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
@@ -51,7 +51,7 @@ package lofar2_unb2b_sdp_station_pkg is
constant c_xsub_one : t_lofar2_unb2b_sdp_station_config := (false, true, false, false, false, 1, true, false, 1);
constant c_xsub_ring : t_lofar2_unb2b_sdp_station_config := (false, true, false, false, false, 1, true, true, 9);
-- use c_full_wg for SDP regression test on Arts-unb2b
- constant c_full_wg : t_lofar2_unb2b_sdp_station_config := (true, true, false, true, true, 1, true, true, 9);
+ constant c_full_wg : t_lofar2_unb2b_sdp_station_config := (true, true, false, true, true, 32, true, true, 9);
constant c_full : t_lofar2_unb2b_sdp_station_config := (false, true, false, true, false, 1, true, true, 9);
constant c_full_wg_os : t_lofar2_unb2b_sdp_station_config := (true, true, true, true, false, 1, true, true, 9);
-- use c_full_os for SDP on LTS-unb2b of Disturb2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
index 194e3ee4180e6c18c5a5c68184ba85ad7d511c58..7a65b2f2389ca4570b8af8e2db5ef8cc21079339 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
@@ -190,9 +190,13 @@ entity mmm_lofar2_unb2b_sdp_station is
reg_bf_scale_copi : out t_mem_copi;
reg_bf_scale_cipo : in t_mem_cipo;
- -- Beamlet Data Output header fields
+ -- Beamlet Data Output (BDO) header fields
+ -- . single destination, used when revision.nof_bdo_destinations_max = 1
reg_hdr_dat_copi : out t_mem_copi;
reg_hdr_dat_cipo : in t_mem_cipo;
+ -- . multiple destinations, used when revision.nof_bdo_destinations_max > 1
+ reg_bdo_destinations_copi : out t_mem_copi;
+ reg_bdo_destinations_cipo : in t_mem_cipo;
-- Beamlet Data Output xonoff
reg_dp_xonoff_copi : out t_mem_copi;
@@ -442,6 +446,9 @@ begin
u_mm_file_reg_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT")
port map(mm_rst, mm_clk, reg_hdr_dat_copi, reg_hdr_dat_cipo );
+ u_mm_file_reg_bdo_destinations : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BDO_DESTINATIONS")
+ port map(mm_rst, mm_clk, reg_bdo_destinations_copi, reg_bdo_destinations_cipo );
+
u_mm_file_reg_dp_xonoff : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF")
port map(mm_rst, mm_clk, reg_dp_xonoff_copi, reg_dp_xonoff_cipo );
@@ -900,6 +907,14 @@ begin
reg_hdr_dat_read_export => reg_hdr_dat_copi.rd,
reg_hdr_dat_readdata_export => reg_hdr_dat_cipo.rddata(c_word_w - 1 downto 0),
+ reg_bdo_destinations_clk_export => OPEN,
+ reg_bdo_destinations_reset_export => OPEN,
+ reg_bdo_destinations_address_export => reg_bdo_destinations_copi.address(c_sdp_reg_bdo_destinations_info_w - 1 downto 0),
+ reg_bdo_destinations_write_export => reg_bdo_destinations_copi.wr,
+ reg_bdo_destinations_writedata_export => reg_bdo_destinations_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bdo_destinations_read_export => reg_bdo_destinations_copi.rd,
+ reg_bdo_destinations_readdata_export => reg_bdo_destinations_cipo.rddata(c_word_w - 1 downto 0),
+
reg_dp_xonoff_clk_export => OPEN,
reg_dp_xonoff_reset_export => OPEN,
reg_dp_xonoff_address_export => reg_dp_xonoff_copi.address(c_sdp_reg_dp_xonoff_addr_w - 1 downto 0),
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index 5b73786a9702555b039c255550f2cb477f20c68f..22317623fe4c3cb97e9edcc11d1fda430002e025 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -27,554 +27,560 @@ package qsys_lofar2_unb2b_sdp_station_pkg is
-----------------------------------------------------------------------------
component qsys_lofar2_unb2b_sdp_station is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
- ram_bf_weights_clk_export : out std_logic; -- export
- ram_bf_weights_read_export : out std_logic; -- export
- ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_bf_weights_reset_export : out std_logic; -- export
- ram_bf_weights_write_export : out std_logic; -- export
- ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
- ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_address_export : out std_logic_vector(13 downto 0); -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_cross_address_export : out std_logic_vector(13 downto 0); -- export
- ram_equalizer_gains_cross_clk_export : out std_logic; -- export
- ram_equalizer_gains_cross_read_export : out std_logic; -- export
- ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_cross_reset_export : out std_logic; -- export
- ram_equalizer_gains_cross_write_export : out std_logic; -- export
- ram_equalizer_gains_cross_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_fil_coefs_address_export : out std_logic_vector(14 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
- ram_ss_ss_wide_clk_export : out std_logic; -- export
- ram_ss_ss_wide_read_export : out std_logic; -- export
- ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_ss_ss_wide_reset_export : out std_logic; -- export
- ram_ss_ss_wide_write_export : out std_logic; -- export
- ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
- ram_st_bst_clk_export : out std_logic; -- export
- ram_st_bst_read_export : out std_logic; -- export
- ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_bst_reset_export : out std_logic; -- export
- ram_st_bst_write_export : out std_logic; -- export
- ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
- ram_st_histogram_clk_export : out std_logic; -- export
- ram_st_histogram_read_export : out std_logic; -- export
- ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_histogram_reset_export : out std_logic; -- export
- ram_st_histogram_write_export : out std_logic; -- export
- ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_sst_address_export : out std_logic_vector(14 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
- ram_st_xsq_clk_export : out std_logic; -- export
- ram_st_xsq_read_export : out std_logic; -- export
- ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_xsq_reset_export : out std_logic; -- export
- ram_st_xsq_write_export : out std_logic; -- export
- ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bf_scale_clk_export : out std_logic; -- export
- reg_bf_scale_read_export : out std_logic; -- export
- reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bf_scale_reset_export : out std_logic; -- export
- reg_bf_scale_write_export : out std_logic; -- export
- reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_bf_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_align_v2_bf_clk_export : out std_logic; -- export
- reg_bsn_align_v2_bf_read_export : out std_logic; -- export
- reg_bsn_align_v2_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_align_v2_bf_reset_export : out std_logic; -- export
- reg_bsn_align_v2_bf_write_export : out std_logic; -- export
- reg_bsn_align_v2_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_xsub_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_align_v2_xsub_clk_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_read_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_align_v2_xsub_reset_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_write_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_aligned_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_xsub_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_aligned_xsub_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_aligned_xsub_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_beamlet_output_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_beamlet_output_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_beamlet_output_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_bst_offload_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_bst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_bst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_bf_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_align_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_xsub_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_xsub_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_align_xsub_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_sst_offload_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_sst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_sst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_source_v2_clk_export : out std_logic; -- export
- reg_bsn_source_v2_read_export : out std_logic; -- export
- reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_v2_reset_export : out std_logic; -- export
- reg_bsn_source_v2_write_export : out std_logic; -- export
- reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_crosslets_info_clk_export : out std_logic; -- export
- reg_crosslets_info_read_export : out std_logic; -- export
- reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_crosslets_info_reset_export : out std_logic; -- export
- reg_crosslets_info_write_export : out std_logic; -- export
- reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_bf_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_bf_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_block_validate_err_bf_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_read_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_bf_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_write_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_block_validate_err_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_xonoff_clk_export : out std_logic; -- export
- reg_dp_xonoff_read_export : out std_logic; -- export
- reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_reset_export : out std_logic; -- export
- reg_dp_xonoff_write_export : out std_logic; -- export
- reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
- reg_hdr_dat_clk_export : out std_logic; -- export
- reg_hdr_dat_read_export : out std_logic; -- export
- reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_reset_export : out std_logic; -- export
- reg_hdr_dat_write_export : out std_logic; -- export
- reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nof_crosslets_clk_export : out std_logic; -- export
- reg_nof_crosslets_read_export : out std_logic; -- export
- reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nof_crosslets_reset_export : out std_logic; -- export
- reg_nof_crosslets_write_export : out std_logic; -- export
- reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_nw_10gbe_mac_clk_export : out std_logic; -- export
- reg_nw_10gbe_mac_read_export : out std_logic; -- export
- reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_mac_reset_export : out std_logic; -- export
- reg_nw_10gbe_mac_write_export : out std_logic; -- export
- reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_info_clk_export : out std_logic; -- export
- reg_ring_info_read_export : out std_logic; -- export
- reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_info_reset_export : out std_logic; -- export
- reg_ring_info_write_export : out std_logic; -- export
- reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_bf_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_lane_info_bf_clk_export : out std_logic; -- export
- reg_ring_lane_info_bf_read_export : out std_logic; -- export
- reg_ring_lane_info_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_bf_reset_export : out std_logic; -- export
- reg_ring_lane_info_bf_write_export : out std_logic; -- export
- reg_ring_lane_info_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_ring_lane_info_xst_clk_export : out std_logic; -- export
- reg_ring_lane_info_xst_read_export : out std_logic; -- export
- reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_xst_reset_export : out std_logic; -- export
- reg_ring_lane_info_xst_write_export : out std_logic; -- export
- reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_stat_enable_bst_clk_export : out std_logic; -- export
- reg_stat_enable_bst_read_export : out std_logic; -- export
- reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_bst_reset_export : out std_logic; -- export
- reg_stat_enable_bst_write_export : out std_logic; -- export
- reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_sst_clk_export : out std_logic; -- export
- reg_stat_enable_sst_read_export : out std_logic; -- export
- reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_sst_reset_export : out std_logic; -- export
- reg_stat_enable_sst_write_export : out std_logic; -- export
- reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_xst_clk_export : out std_logic; -- export
- reg_stat_enable_xst_read_export : out std_logic; -- export
- reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_xst_reset_export : out std_logic; -- export
- reg_stat_enable_xst_write_export : out std_logic; -- export
- reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_stat_hdr_dat_bst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_sst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_xst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0); -- export
- reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0); -- export
- reg_tr_10gbe_mac_clk_export : out std_logic; -- export
- reg_tr_10gbe_mac_read_export : out std_logic; -- export
- reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_mac_reset_export : out std_logic; -- export
- reg_tr_10gbe_mac_write_export : out std_logic; -- export
- reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_bf_weights_clk_export : out std_logic; -- export
+ ram_bf_weights_read_export : out std_logic; -- export
+ ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_bf_weights_reset_export : out std_logic; -- export
+ ram_bf_weights_write_export : out std_logic; -- export
+ ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_equalizer_gains_clk_export : out std_logic; -- export
+ ram_equalizer_gains_cross_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_equalizer_gains_cross_clk_export : out std_logic; -- export
+ ram_equalizer_gains_cross_read_export : out std_logic; -- export
+ ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_cross_reset_export : out std_logic; -- export
+ ram_equalizer_gains_cross_write_export : out std_logic; -- export
+ ram_equalizer_gains_cross_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_read_export : out std_logic; -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_reset_export : out std_logic; -- export
+ ram_equalizer_gains_write_export : out std_logic; -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_fil_coefs_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_fil_coefs_clk_export : out std_logic; -- export
+ ram_fil_coefs_read_export : out std_logic; -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_reset_export : out std_logic; -- export
+ ram_fil_coefs_write_export : out std_logic; -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_ss_ss_wide_clk_export : out std_logic; -- export
+ ram_ss_ss_wide_read_export : out std_logic; -- export
+ ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_ss_ss_wide_reset_export : out std_logic; -- export
+ ram_ss_ss_wide_write_export : out std_logic; -- export
+ ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_st_bst_clk_export : out std_logic; -- export
+ ram_st_bst_read_export : out std_logic; -- export
+ ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_bst_reset_export : out std_logic; -- export
+ ram_st_bst_write_export : out std_logic; -- export
+ ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_st_histogram_clk_export : out std_logic; -- export
+ ram_st_histogram_read_export : out std_logic; -- export
+ ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_histogram_reset_export : out std_logic; -- export
+ ram_st_histogram_write_export : out std_logic; -- export
+ ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_sst_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_st_sst_clk_export : out std_logic; -- export
+ ram_st_sst_read_export : out std_logic; -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_reset_export : out std_logic; -- export
+ ram_st_sst_write_export : out std_logic; -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
+ ram_st_xsq_clk_export : out std_logic; -- export
+ ram_st_xsq_read_export : out std_logic; -- export
+ ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_xsq_reset_export : out std_logic; -- export
+ ram_st_xsq_write_export : out std_logic; -- export
+ ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_clk_export : out std_logic; -- export
+ ram_wg_read_export : out std_logic; -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_reset_export : out std_logic; -- export
+ ram_wg_write_export : out std_logic; -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_aduh_monitor_clk_export : out std_logic; -- export
+ reg_aduh_monitor_read_export : out std_logic; -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_aduh_monitor_reset_export : out std_logic; -- export
+ reg_aduh_monitor_write_export : out std_logic; -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bdo_destinations_address_export : out std_logic_vector(8 downto 0); -- export
+ reg_bdo_destinations_clk_export : out std_logic; -- export
+ reg_bdo_destinations_read_export : out std_logic; -- export
+ reg_bdo_destinations_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bdo_destinations_reset_export : out std_logic; -- export
+ reg_bdo_destinations_write_export : out std_logic; -- export
+ reg_bdo_destinations_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bf_scale_clk_export : out std_logic; -- export
+ reg_bf_scale_read_export : out std_logic; -- export
+ reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bf_scale_reset_export : out std_logic; -- export
+ reg_bf_scale_write_export : out std_logic; -- export
+ reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_bf_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_align_v2_bf_clk_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_read_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_align_v2_bf_reset_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_write_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_xsub_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_align_v2_xsub_clk_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_read_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_align_v2_xsub_reset_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_write_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_aligned_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_xsub_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_xsub_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_aligned_xsub_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_beamlet_output_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_beamlet_output_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_beamlet_output_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_bst_offload_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_bst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_bst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_bf_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_align_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_sst_offload_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_sst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_sst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_source_v2_clk_export : out std_logic; -- export
+ reg_bsn_source_v2_read_export : out std_logic; -- export
+ reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_v2_reset_export : out std_logic; -- export
+ reg_bsn_source_v2_write_export : out std_logic; -- export
+ reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_crosslets_info_clk_export : out std_logic; -- export
+ reg_crosslets_info_read_export : out std_logic; -- export
+ reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_crosslets_info_reset_export : out std_logic; -- export
+ reg_crosslets_info_write_export : out std_logic; -- export
+ reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_bf_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_block_validate_err_bf_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_bf_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_block_validate_err_xst_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_xst_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_selector_clk_export : out std_logic; -- export
+ reg_dp_selector_read_export : out std_logic; -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_reset_export : out std_logic; -- export
+ reg_dp_selector_write_export : out std_logic; -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_shiftram_clk_export : out std_logic; -- export
+ reg_dp_shiftram_read_export : out std_logic; -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_shiftram_reset_export : out std_logic; -- export
+ reg_dp_shiftram_write_export : out std_logic; -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_xonoff_clk_export : out std_logic; -- export
+ reg_dp_xonoff_read_export : out std_logic; -- export
+ reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_reset_export : out std_logic; -- export
+ reg_dp_xonoff_write_export : out std_logic; -- export
+ reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_hdr_dat_clk_export : out std_logic; -- export
+ reg_hdr_dat_read_export : out std_logic; -- export
+ reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_reset_export : out std_logic; -- export
+ reg_hdr_dat_write_export : out std_logic; -- export
+ reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nof_crosslets_clk_export : out std_logic; -- export
+ reg_nof_crosslets_read_export : out std_logic; -- export
+ reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nof_crosslets_reset_export : out std_logic; -- export
+ reg_nof_crosslets_write_export : out std_logic; -- export
+ reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
+ reg_nw_10gbe_mac_clk_export : out std_logic; -- export
+ reg_nw_10gbe_mac_read_export : out std_logic; -- export
+ reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_mac_reset_export : out std_logic; -- export
+ reg_nw_10gbe_mac_write_export : out std_logic; -- export
+ reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_info_clk_export : out std_logic; -- export
+ reg_ring_info_read_export : out std_logic; -- export
+ reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_info_reset_export : out std_logic; -- export
+ reg_ring_info_write_export : out std_logic; -- export
+ reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_bf_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_lane_info_bf_clk_export : out std_logic; -- export
+ reg_ring_lane_info_bf_read_export : out std_logic; -- export
+ reg_ring_lane_info_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_bf_reset_export : out std_logic; -- export
+ reg_ring_lane_info_bf_write_export : out std_logic; -- export
+ reg_ring_lane_info_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_ring_lane_info_xst_clk_export : out std_logic; -- export
+ reg_ring_lane_info_xst_read_export : out std_logic; -- export
+ reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_xst_reset_export : out std_logic; -- export
+ reg_ring_lane_info_xst_write_export : out std_logic; -- export
+ reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_sdp_info_clk_export : out std_logic; -- export
+ reg_sdp_info_read_export : out std_logic; -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_reset_export : out std_logic; -- export
+ reg_sdp_info_write_export : out std_logic; -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_si_clk_export : out std_logic; -- export
+ reg_si_read_export : out std_logic; -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_si_reset_export : out std_logic; -- export
+ reg_si_write_export : out std_logic; -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_stat_enable_bst_clk_export : out std_logic; -- export
+ reg_stat_enable_bst_read_export : out std_logic; -- export
+ reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_bst_reset_export : out std_logic; -- export
+ reg_stat_enable_bst_write_export : out std_logic; -- export
+ reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_sst_clk_export : out std_logic; -- export
+ reg_stat_enable_sst_read_export : out std_logic; -- export
+ reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_sst_reset_export : out std_logic; -- export
+ reg_stat_enable_sst_write_export : out std_logic; -- export
+ reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_xst_clk_export : out std_logic; -- export
+ reg_stat_enable_xst_read_export : out std_logic; -- export
+ reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_xst_reset_export : out std_logic; -- export
+ reg_stat_enable_xst_write_export : out std_logic; -- export
+ reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_stat_hdr_dat_bst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_sst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_xst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0); -- export
+ reg_tr_10gbe_mac_clk_export : out std_logic; -- export
+ reg_tr_10gbe_mac_read_export : out std_logic; -- export
+ reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_mac_reset_export : out std_logic; -- export
+ reg_tr_10gbe_mac_write_export : out std_logic; -- export
+ reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_clk_export : out std_logic; -- export
+ reg_wg_read_export : out std_logic; -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_reset_export : out std_logic; -- export
+ reg_wg_write_export : out std_logic; -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component qsys_lofar2_unb2b_sdp_station;
-
end qsys_lofar2_unb2b_sdp_station_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
index 094c157891d89105d8b296d010c6e380ad3933ac..9a3ae249669c8d0dc3dfb22c799c8c9b8820ba7f 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
@@ -60,43 +60,43 @@ peripherals:
mm_port_names:
- REG_FPGA_TEMP_SENS
- REG_FPGA_VOLTAGE_SENS
-
+
- peripheral_name: unb2c_board/ram_scrap
mm_port_names:
- RAM_SCRAP
-
+
- peripheral_name: eth/eth
mm_port_names:
- AVS_ETH_0_TSE
- AVS_ETH_0_REG
- AVS_ETH_0_RAM
-
+
- peripheral_name: ppsh/ppsh
mm_port_names:
- PIO_PPS
-
+
- peripheral_name: epcs/epcs
parameter_overrides:
- { name: "g_epcs_addr_w", value: 32 }
mm_port_names:
- REG_EPCS
-
+
- peripheral_name: dp/dpmm
mm_port_names:
- REG_DPMM_CTRL
- REG_DPMM_DATA
-
+
- peripheral_name: dp/mmdp
mm_port_names:
- REG_MMDP_CTRL
- REG_MMDP_DATA
-
+
- peripheral_name: remu/remu
parameter_overrides:
- { name: g_data_w, value: 32 }
mm_port_names:
- REG_REMU
-
+
#############################################################################
# SDP Info
#############################################################################
@@ -104,7 +104,7 @@ peripherals:
- peripheral_name: sdp/sdp_info
mm_port_names:
- REG_SDP_INFO
-
+
#############################################################################
# Ring Info
#############################################################################
@@ -116,17 +116,17 @@ peripherals:
#############################################################################
# AIT = ADC Input and Timing (see node_adc_input_and_timing.vhd)
#############################################################################
-
+
- peripheral_name: tech_jesd204b/jesd_ctrl
mm_port_names:
- PIO_JESD_CTRL
-
+
- peripheral_name: tech_jesd204b/jesd204b_arria10
parameter_overrides:
- { name: g_nof_streams, value: c_S_pn }
mm_port_names:
- JESD204B
-
+
- peripheral_name: dp/dp_shiftram
parameter_overrides:
- { name: g_nof_streams, value: c_S_pn }
@@ -142,16 +142,16 @@ peripherals:
- { name: g_bsn_time_offset_w, value: ceil_log2(c_N_fft) }
mm_port_names:
- REG_BSN_SOURCE_V2
-
+
- peripheral_name: dp/dp_bsn_scheduler
mm_port_names:
- REG_BSN_SCHEDULER
-
+
- peripheral_name: dp/dp_bsn_monitor
peripheral_group: input
mm_port_names:
- REG_BSN_MONITOR_INPUT
-
+
- peripheral_name: diag/diag_wg_wideband
parameter_overrides:
- { name: g_nof_streams, value: c_S_pn }
@@ -165,7 +165,7 @@ peripherals:
- { name: g_nof_bins, value: c_V_si_histogram }
- { name: g_nof_data_per_sync, value: c_nof_clk_per_pps}
mm_port_names:
- - RAM_ST_HISTOGRAM
+ - RAM_ST_HISTOGRAM
- peripheral_name: aduh/aduh_mon_dc_power
parameter_overrides:
@@ -193,17 +193,17 @@ peripherals:
mm_port_names:
- REG_DIAG_DATA_BUFFER_BSN
- RAM_DIAG_DATA_BUFFER_BSN
-
+
#############################################################################
# Fsub = Subband Filterbank (from node_sdp_filterbank.vhd)
#############################################################################
-
+
- peripheral_name: si/si
parameter_overrides:
- { name: g_nof_streams, value: c_S_pn }
mm_port_names:
- REG_SI
-
+
- peripheral_name: filter/fil_ppf_w
number_of_peripherals: c_R_os # Disturb uses 2x oversample
peripheral_span: ceil_pow2(c_N_taps) * ceil_pow2(c_N_fft) * MM_BUS_SIZE # number_of_ports = ceil_pow2(c_N_taps), mm_port_span = ceil_pow2(c_N_fft) words
@@ -216,7 +216,7 @@ peripherals:
- { name: g_fil_ppf.coef_dat_w, value: c_W_fir_coef }
mm_port_names:
- RAM_FIL_COEFS
-
+
- peripheral_name: sdp/sdp_subband_equalizer
parameter_overrides:
- { name: P_pfb, value: c_R_os * c_P_pfb} # DISTURB uses 2x oversample so 2 X P_pfb
@@ -227,13 +227,13 @@ peripherals:
- peripheral_name: dp/dp_selector
mm_port_names:
- REG_DP_SELECTOR # input_select = 0 for weighted subbands, input_select = 1 for raw subbands
-
+
- peripheral_name: st/st_sst_for_sdp
parameter_overrides:
- { name: g_nof_instances, value: c_R_os * c_P_pfb} # DISTURB uses 2x oversample so 2 X P_pfb
mm_port_names:
- RAM_ST_SST
-
+
- peripheral_name: common/common_variable_delay
peripheral_group: sst
mm_port_names:
@@ -243,7 +243,7 @@ peripherals:
peripheral_group: sst
mm_port_names:
- REG_STAT_HDR_DAT_SST
-
+
- peripheral_name: dp/dp_bsn_monitor_v2
peripheral_group: sst_udp
parameter_overrides:
@@ -259,14 +259,14 @@ peripherals:
peripheral_group: xsub
mm_port_names:
- REG_BSN_SYNC_SCHEDULER_XSUB
-
+
- peripheral_name: st/st_xst_for_sdp
parameter_overrides:
- { name: g_nof_streams, value: c_P_sq }
- { name: g_nof_crosslets, value: c_N_crosslets }
mm_port_names:
- RAM_ST_XSQ
-
+
- peripheral_name: sdp/sdp_crosslets_subband_select
mm_port_names:
- REG_CROSSLETS_INFO
@@ -291,33 +291,33 @@ peripherals:
- { name: g_nof_streams, value: c_P_sq }
mm_port_names:
- REG_BSN_ALIGN_V2_XSUB
-
+
- peripheral_name: dp/dp_bsn_monitor_v2
peripheral_group: rx_align_xsub
parameter_overrides:
- { name: g_nof_streams, value: c_P_sq }
mm_port_names:
- REG_BSN_MONITOR_V2_RX_ALIGN_XSUB
-
+
- peripheral_name: dp/dp_bsn_monitor_v2
peripheral_group: aligned_xsub
parameter_overrides:
- { name: g_nof_streams, value: 1 }
mm_port_names:
- REG_BSN_MONITOR_V2_ALIGNED_XSUB
-
+
- peripheral_name: dp/dp_bsn_monitor_v2
peripheral_group: xst_udp
parameter_overrides:
- { name: g_nof_streams, value: 1 }
mm_port_names:
- REG_BSN_MONITOR_V2_XST_OFFLOAD
-
+
- peripheral_name: ring/ring_lane_info
peripheral_group: xsub
mm_port_names:
- REG_RING_LANE_INFO_XST
-
+
- peripheral_name: dp/dp_bsn_monitor_v2
peripheral_group: ring_rx
parameter_overrides:
@@ -341,7 +341,7 @@ peripherals:
- peripheral_name: dp/dp_block_validate_bsn_at_sync
mm_port_names:
- REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST
-
+
- peripheral_name: tr_10GbE/tr_10GbE_unb2legacy # For ring interface
parameter_overrides:
- { name: g_nof_macs, value: c_ring_nof_mac }
@@ -357,7 +357,7 @@ peripherals:
#############################################################################
# BF = Beamformer (from node_sdp_beamformer.vhd)
#############################################################################
-
+
- peripheral_name: reorder/reorder_col_wide
number_of_peripherals: c_N_beamsets
peripheral_span: ceil_pow2(c_P_pfb) * ceil_pow2(c_S_sub_bf * c_Q_fft) * MM_BUS_SIZE # number_of_ports = c_P_pfb, mm_port_span = ceil_pow2(c_S_sub_bf * c_Q_fft) words
@@ -382,7 +382,7 @@ peripherals:
- { name: g_nof_streams, value: c_P_sum }
mm_port_names:
- REG_BSN_ALIGN_V2_BF
-
+
- peripheral_name: dp/dp_bsn_monitor_v2
peripheral_group: rx_align_bf
number_of_peripherals: c_N_beamsets
@@ -391,7 +391,7 @@ peripherals:
- { name: g_nof_streams, value: c_P_sum }
mm_port_names:
- REG_BSN_MONITOR_V2_RX_ALIGN_BF
-
+
- peripheral_name: dp/dp_bsn_monitor_v2
peripheral_group: aligned_bf
number_of_peripherals: c_N_beamsets
@@ -400,14 +400,14 @@ peripherals:
- { name: g_nof_streams, value: 1 }
mm_port_names:
- REG_BSN_MONITOR_V2_ALIGNED_BF
-
+
- peripheral_name: ring/ring_lane_info
peripheral_group: bf
number_of_peripherals: c_N_beamsets
peripheral_span: 2 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 2 words
mm_port_names:
- REG_RING_LANE_INFO_BF
-
+
- peripheral_name: dp/dp_bsn_monitor_v2
peripheral_group: ring_rx_bf
number_of_peripherals: c_N_beamsets
@@ -451,6 +451,12 @@ peripherals:
mm_port_names:
- REG_BF_SCALE
+ - peripheral_name: sdp/sdp_bdo_destinations
+ number_of_peripherals: c_N_beamsets
+ peripheral_span: 256 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 256 words
+ mm_port_names:
+ - REG_BDO_DESTINATIONS
+
- peripheral_name: sdp/sdp_beamformer_output_hdr_dat
number_of_peripherals: c_N_beamsets
peripheral_span: 64 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 64 words
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations.ip
new file mode 100644
index 0000000000000000000000000000000000000000..89effcf893152d6e1aa95d5bd0b6a2eeaee83730
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations</ipxact:library>
+ <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>2048</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>8</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>8</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>9</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>100000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U3F45E2SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>9</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>2048</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>9</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x800' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>11</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ip.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ip.tcl
index 43be034093d84c88518170338e1c8ed68c04c346..d0f28544360e616e1c233fc5b38d8fe9815770ae 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ip.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ip.tcl
@@ -45,6 +45,7 @@ set_global_assignment -name IP_FILE $IP_PATH/qsys_lofar2_unb2c_sdp_station_ram_s
set_global_assignment -name IP_FILE $IP_PATH/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
set_global_assignment -name IP_FILE $IP_PATH/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
set_global_assignment -name IP_FILE $IP_PATH/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
+set_global_assignment -name IP_FILE $IP_PATH/qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations.ip
set_global_assignment -name IP_FILE $IP_PATH/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
set_global_assignment -name IP_FILE $IP_PATH/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
set_global_assignment -name IP_FILE $IP_PATH/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
index 41b68e0c998079330f3758efd0485d010b0ce3ce..1e2eb5123971ca96dc706fc9664afb6afaa54ed1 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
@@ -99,7 +99,7 @@
{
datum baseAddress
{
- value = "1329680";
+ value = "1331728";
type = "String";
}
}
@@ -144,7 +144,7 @@
{
datum baseAddress
{
- value = "1329608";
+ value = "1331656";
type = "String";
}
}
@@ -165,7 +165,7 @@
{
datum baseAddress
{
- value = "1329568";
+ value = "1331616";
type = "String";
}
}
@@ -298,7 +298,7 @@
{
datum baseAddress
{
- value = "2048";
+ value = "1327104";
type = "String";
}
}
@@ -410,7 +410,23 @@
{
datum baseAddress
{
- value = "1327872";
+ value = "1329920";
+ type = "String";
+ }
+ }
+ element reg_bdo_destinations
+ {
+ datum _sortIndex
+ {
+ value = "80";
+ type = "int";
+ }
+ }
+ element reg_bdo_destinations.mem
+ {
+ datum baseAddress
+ {
+ value = "2048";
type = "String";
}
}
@@ -426,7 +442,7 @@
{
datum baseAddress
{
- value = "1329552";
+ value = "1331600";
type = "String";
}
}
@@ -442,7 +458,7 @@
{
datum baseAddress
{
- value = "1329184";
+ value = "1331232";
type = "String";
}
}
@@ -458,7 +474,7 @@
{
datum baseAddress
{
- value = "1328128";
+ value = "1330176";
type = "String";
}
}
@@ -490,7 +506,7 @@
{
datum baseAddress
{
- value = "1328640";
+ value = "1330688";
type = "String";
}
}
@@ -506,7 +522,7 @@
{
datum baseAddress
{
- value = "1329312";
+ value = "1331360";
type = "String";
}
}
@@ -522,7 +538,7 @@
{
datum baseAddress
{
- value = "1328704";
+ value = "1330752";
type = "String";
}
}
@@ -538,7 +554,7 @@
{
datum baseAddress
{
- value = "1328768";
+ value = "1330816";
type = "String";
}
}
@@ -554,7 +570,7 @@
{
datum baseAddress
{
- value = "1328576";
+ value = "1330624";
type = "String";
}
}
@@ -586,7 +602,7 @@
{
datum baseAddress
{
- value = "1328512";
+ value = "1330560";
type = "String";
}
}
@@ -650,7 +666,7 @@
{
datum baseAddress
{
- value = "1329216";
+ value = "1331264";
type = "String";
}
}
@@ -666,7 +682,7 @@
{
datum baseAddress
{
- value = "1329280";
+ value = "1331328";
type = "String";
}
}
@@ -682,7 +698,7 @@
{
datum baseAddress
{
- value = "1329632";
+ value = "1331680";
type = "String";
}
}
@@ -698,7 +714,7 @@
{
datum baseAddress
{
- value = "1329344";
+ value = "1331392";
type = "String";
}
}
@@ -714,7 +730,7 @@
{
datum baseAddress
{
- value = "1328896";
+ value = "1330944";
type = "String";
}
}
@@ -730,7 +746,7 @@
{
datum baseAddress
{
- value = "1328960";
+ value = "1331008";
type = "String";
}
}
@@ -746,7 +762,7 @@
{
datum baseAddress
{
- value = "1328256";
+ value = "1330304";
type = "String";
}
}
@@ -762,7 +778,7 @@
{
datum baseAddress
{
- value = "1329152";
+ value = "1331200";
type = "String";
}
}
@@ -778,7 +794,7 @@
{
datum baseAddress
{
- value = "1329504";
+ value = "1331552";
type = "String";
}
}
@@ -810,7 +826,7 @@
{
datum baseAddress
{
- value = "1328832";
+ value = "1330880";
type = "String";
}
}
@@ -826,7 +842,7 @@
{
datum baseAddress
{
- value = "1329624";
+ value = "1331672";
type = "String";
}
}
@@ -842,7 +858,7 @@
{
datum baseAddress
{
- value = "1328384";
+ value = "1330432";
type = "String";
}
}
@@ -858,7 +874,7 @@
{
datum baseAddress
{
- value = "1329536";
+ value = "1331584";
type = "String";
}
}
@@ -879,7 +895,7 @@
{
datum baseAddress
{
- value = "1329672";
+ value = "1331720";
type = "String";
}
}
@@ -900,7 +916,7 @@
{
datum baseAddress
{
- value = "1329664";
+ value = "1331712";
type = "String";
}
}
@@ -921,7 +937,7 @@
{
datum baseAddress
{
- value = "1329408";
+ value = "1331456";
type = "String";
}
}
@@ -937,7 +953,7 @@
{
datum baseAddress
{
- value = "1329376";
+ value = "1331424";
type = "String";
}
}
@@ -958,7 +974,7 @@
{
datum baseAddress
{
- value = "1329088";
+ value = "1331136";
type = "String";
}
}
@@ -974,7 +990,7 @@
{
datum baseAddress
{
- value = "1327104";
+ value = "1329152";
type = "String";
}
}
@@ -995,7 +1011,7 @@
{
datum baseAddress
{
- value = "1329656";
+ value = "1331704";
type = "String";
}
}
@@ -1016,7 +1032,7 @@
{
datum baseAddress
{
- value = "1329648";
+ value = "1331696";
type = "String";
}
}
@@ -1032,7 +1048,7 @@
{
datum baseAddress
{
- value = "1329584";
+ value = "1331632";
type = "String";
}
}
@@ -1048,7 +1064,7 @@
{
datum baseAddress
{
- value = "1329616";
+ value = "1331664";
type = "String";
}
}
@@ -1085,7 +1101,7 @@
{
datum baseAddress
{
- value = "1329440";
+ value = "1331488";
type = "String";
}
}
@@ -1101,7 +1117,7 @@
{
datum baseAddress
{
- value = "1329488";
+ value = "1331536";
type = "String";
}
}
@@ -1117,7 +1133,7 @@
{
datum baseAddress
{
- value = "1329472";
+ value = "1331520";
type = "String";
}
}
@@ -1149,7 +1165,7 @@
{
datum baseAddress
{
- value = "1329024";
+ value = "1331072";
type = "String";
}
}
@@ -1165,7 +1181,7 @@
{
datum baseAddress
{
- value = "1329640";
+ value = "1331688";
type = "String";
}
}
@@ -1181,7 +1197,7 @@
{
datum baseAddress
{
- value = "1329520";
+ value = "1331568";
type = "String";
}
}
@@ -1197,7 +1213,7 @@
{
datum baseAddress
{
- value = "1329600";
+ value = "1331648";
type = "String";
}
}
@@ -1213,7 +1229,7 @@
{
datum baseAddress
{
- value = "1329592";
+ value = "1331640";
type = "String";
}
}
@@ -1277,7 +1293,7 @@
{
datum baseAddress
{
- value = "1329248";
+ value = "1331296";
type = "String";
}
}
@@ -1335,7 +1351,7 @@
{
datum baseAddress
{
- value = "1327616";
+ value = "1329664";
type = "String";
}
}
@@ -2084,6 +2100,41 @@
internal="reg_aduh_monitor.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_bdo_destinations_address"
+ internal="reg_bdo_destinations.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bdo_destinations_clk"
+ internal="reg_bdo_destinations.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bdo_destinations_read"
+ internal="reg_bdo_destinations.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bdo_destinations_readdata"
+ internal="reg_bdo_destinations.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bdo_destinations_reset"
+ internal="reg_bdo_destinations.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bdo_destinations_write"
+ internal="reg_bdo_destinations.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bdo_destinations_writedata"
+ internal="reg_bdo_destinations.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_bf_scale_address"
internal="reg_bf_scale.address"
@@ -8548,7 +8599,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xE0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xE0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains_cross.mem' start='0x100000' end='0x110000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x110000' end='0x120000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x120000' end='0x130000' datawidth='32' /><slave name='ram_wg.mem' start='0x130000' end='0x140000' datawidth='32' /><slave name='jesd204b.mem' start='0x140000' end='0x144000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x144000' end='0x144200' datawidth='32' /><slave name='reg_wg.mem' start='0x144200' end='0x144300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x144300' end='0x144400' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x144400' end='0x144480' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x144480' end='0x144500' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x144500' end='0x144580' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x144580' end='0x1445C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x1445C0' end='0x144600' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x144600' end='0x144640' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x144640' end='0x144680' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x144680' end='0x1446C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x1446C0' end='0x144700' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x144700' end='0x144740' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x144740' end='0x144780' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x144780' end='0x1447C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x1447C0' end='0x144800' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x144800' end='0x144820' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x144820' end='0x144840' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x144840' end='0x144860' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x144860' end='0x144880' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x144880' end='0x1448A0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x1448A0' end='0x1448C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x1448C0' end='0x1448E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x1448E0' end='0x144900' datawidth='32' /><slave name='reg_epcs.mem' start='0x144900' end='0x144920' datawidth='32' /><slave name='reg_remu.mem' start='0x144920' end='0x144940' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x144940' end='0x144950' datawidth='32' /><slave name='reg_ring_info.mem' start='0x144950' end='0x144960' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x144960' end='0x144970' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x144970' end='0x144980' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x144980' end='0x144990' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x144990' end='0x1449A0' datawidth='32' /><slave name='pio_pps.mem' start='0x1449A0' end='0x1449B0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x1449B0' end='0x1449B8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x1449B8' end='0x1449C0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x1449C0' end='0x1449C8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x1449C8' end='0x1449D0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x1449D0' end='0x1449D8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x1449D8' end='0x1449E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x1449E0' end='0x1449E8' datawidth='32' /><slave name='reg_si.mem' start='0x1449E8' end='0x1449F0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x1449F0' end='0x1449F8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x1449F8' end='0x144A00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x144A00' end='0x144A08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x144A08' end='0x144A10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x144A10' end='0x144A18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='reg_bdo_destinations.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xE0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xE0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains_cross.mem' start='0x100000' end='0x110000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x110000' end='0x120000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x120000' end='0x130000' datawidth='32' /><slave name='ram_wg.mem' start='0x130000' end='0x140000' datawidth='32' /><slave name='jesd204b.mem' start='0x140000' end='0x144000' datawidth='32' /><slave name='ram_scrap.mem' start='0x144000' end='0x144800' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x144800' end='0x144A00' datawidth='32' /><slave name='reg_wg.mem' start='0x144A00' end='0x144B00' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x144B00' end='0x144C00' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x144C00' end='0x144C80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x144C80' end='0x144D00' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x144D00' end='0x144D80' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x144D80' end='0x144DC0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x144DC0' end='0x144E00' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x144E00' end='0x144E40' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x144E40' end='0x144E80' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x144E80' end='0x144EC0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x144EC0' end='0x144F00' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x144F00' end='0x144F40' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x144F40' end='0x144F80' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x144F80' end='0x144FC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x144FC0' end='0x145000' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x145000' end='0x145020' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x145020' end='0x145040' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x145040' end='0x145060' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x145060' end='0x145080' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x145080' end='0x1450A0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x1450A0' end='0x1450C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x1450C0' end='0x1450E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x1450E0' end='0x145100' datawidth='32' /><slave name='reg_epcs.mem' start='0x145100' end='0x145120' datawidth='32' /><slave name='reg_remu.mem' start='0x145120' end='0x145140' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x145140' end='0x145150' datawidth='32' /><slave name='reg_ring_info.mem' start='0x145150' end='0x145160' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x145160' end='0x145170' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x145170' end='0x145180' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x145180' end='0x145190' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x145190' end='0x1451A0' datawidth='32' /><slave name='pio_pps.mem' start='0x1451A0' end='0x1451B0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x1451B0' end='0x1451B8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x1451B8' end='0x1451C0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x1451C0' end='0x1451C8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x1451C8' end='0x1451D0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x1451D0' end='0x1451D8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x1451D8' end='0x1451E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x1451E0' end='0x1451E8' datawidth='32' /><slave name='reg_si.mem' start='0x1451E8' end='0x1451F0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x1451F0' end='0x1451F8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x1451F8' end='0x145200' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x145200' end='0x145208' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x145208' end='0x145210' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x145210' end='0x145218' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -21368,17 +21419,21 @@
</ports>
<assignments>
<assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>false</value>
+ <value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>false</value>
+ <value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
- <value>false</value>
+ <value>0</value>
</entry>
</assignmentValueMap>
</assignments>
@@ -21418,6 +21473,7 @@
</entry>
<entry>
<key>bridgedAddressOffset</key>
+ <value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
@@ -21799,7 +21855,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains_cross.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains_cross.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -32075,7 +32131,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bf_scale"
+ name="reg_bdo_destinations"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -32083,17 +32139,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>2</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -32102,27 +32158,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -32135,13 +32192,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -32155,7 +32210,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>9</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32224,7 +32279,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>2048</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -32380,6 +32435,166 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>9</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
<interface>
<name>read</name>
<type>conduit</type>
@@ -32444,165 +32659,6 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
</interfaces>
</boundary>
<originalModuleInfo>
@@ -32630,11 +32686,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>11</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -32663,17 +32719,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>2</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -32682,27 +32738,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -32715,13 +32772,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -32735,7 +32790,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>9</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32774,21 +32829,17 @@
</ports>
<assignments>
<assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
+ <value>false</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
+ <value>false</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
+ <value>false</value>
</entry>
</assignmentValueMap>
</assignments>
@@ -32804,7 +32855,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>2048</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -32828,7 +32879,6 @@
</entry>
<entry>
<key>bridgedAddressOffset</key>
- <value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
@@ -32961,12 +33011,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -32993,17 +33043,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -33025,17 +33075,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>9</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -33057,14 +33107,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -33076,31 +33126,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -33110,22 +33159,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -33152,14 +33203,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -33186,37 +33237,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_align_v2_bf"
+ name="reg_bf_scale"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -33224,17 +33275,17 @@
<boundary>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>2</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -33243,28 +33294,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -33277,11 +33327,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -33295,7 +33347,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33364,7 +33416,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -33521,12 +33573,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -33553,17 +33605,17 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -33585,17 +33637,17 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -33617,14 +33669,14 @@
</parameters>
</interface>
<interface>
- <name>write</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -33636,30 +33688,31 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>writedata</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -33669,24 +33722,22 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -33713,14 +33764,14 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -33771,11 +33822,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -33804,17 +33855,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>2</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -33823,28 +33874,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -33857,11 +33907,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -33875,7 +33927,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33944,7 +33996,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -34100,6 +34152,70 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
<interface>
<name>reset</name>
<type>conduit</type>
@@ -34133,12 +34249,75 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -34165,143 +34344,15 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34327,37 +34378,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_align_v2_xsub"
+ name="reg_bsn_align_v2_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -34436,7 +34487,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34505,7 +34556,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -34734,7 +34785,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34912,11 +34963,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -35016,7 +35067,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35085,7 +35136,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -35314,7 +35365,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35468,37 +35519,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_input"
+ name="reg_bsn_align_v2_xsub"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -35506,17 +35557,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>8</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -35525,27 +35576,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -35558,13 +35610,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -35578,7 +35628,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35647,7 +35697,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -35804,12 +35854,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -35836,44 +35886,12 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -35900,17 +35918,17 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -35919,28 +35937,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -35953,22 +35970,56 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -35995,14 +36046,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -36053,11 +36104,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>10</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -36086,17 +36137,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>8</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -36105,27 +36156,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -36138,13 +36190,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -36158,7 +36208,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36227,7 +36277,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -36383,70 +36433,6 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
<interface>
<name>reset</name>
<type>conduit</type>
@@ -36480,75 +36466,76 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -36606,40 +36593,104 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_aligned_bf"
+ name="reg_bsn_monitor_input"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -36647,17 +36698,17 @@
<boundary>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>8</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -36666,28 +36717,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -36700,11 +36750,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -36718,7 +36770,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36787,7 +36839,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -36944,12 +36996,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -36976,17 +37028,17 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -37008,17 +37060,17 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -37040,14 +37092,14 @@
</parameters>
</interface>
<interface>
- <name>write</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -37059,30 +37111,31 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>writedata</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -37092,24 +37145,22 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -37136,14 +37187,14 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -37194,11 +37245,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>10</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -37227,17 +37278,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>8</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -37246,28 +37297,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -37280,11 +37330,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -37298,7 +37350,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -37367,7 +37419,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -37524,12 +37576,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -37556,17 +37608,17 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -37588,17 +37640,17 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -37620,14 +37672,14 @@
</parameters>
</interface>
<interface>
- <name>write</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -37639,30 +37691,31 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>writedata</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -37672,24 +37725,22 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -37716,14 +37767,14 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -37750,37 +37801,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_aligned_xsub"
+ name="reg_bsn_monitor_v2_aligned_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -37859,7 +37910,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -37928,7 +37979,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -38157,7 +38208,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -38335,11 +38386,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -38439,7 +38490,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -38508,7 +38559,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -38737,7 +38788,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -38891,37 +38942,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_beamlet_output"
+ name="reg_bsn_monitor_v2_aligned_xsub"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -39000,7 +39051,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39069,7 +39120,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -39298,7 +39349,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39476,11 +39527,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -39580,7 +39631,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39649,7 +39700,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -39878,7 +39929,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -40032,37 +40083,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_bst_offload"
+ name="reg_bsn_monitor_v2_beamlet_output"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -41173,37 +41224,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_ring_rx_bf"
+ name="reg_bsn_monitor_v2_bst_offload"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -42314,37 +42365,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_ring_rx_xst"
+ name="reg_bsn_monitor_v2_ring_rx_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -42423,7 +42474,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -42492,7 +42543,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -42721,7 +42772,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -42899,11 +42950,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -43003,7 +43054,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -43072,7 +43123,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -43301,7 +43352,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -43455,37 +43506,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_ring_tx_bf"
+ name="reg_bsn_monitor_v2_ring_rx_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -43564,7 +43615,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -43633,7 +43684,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -43862,7 +43913,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -44040,11 +44091,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -44144,7 +44195,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -44213,7 +44264,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -44442,7 +44493,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -44596,37 +44647,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_ring_tx_xst"
+ name="reg_bsn_monitor_v2_ring_tx_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -44705,7 +44756,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -44774,7 +44825,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -45003,7 +45054,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -45181,11 +45232,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -45285,7 +45336,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -45354,7 +45405,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -45583,7 +45634,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -45737,37 +45788,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_rx_align_bf"
+ name="reg_bsn_monitor_v2_ring_tx_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -45846,7 +45897,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -45915,7 +45966,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -46144,7 +46195,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -46322,11 +46373,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -46426,7 +46477,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -46495,7 +46546,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -46724,7 +46775,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -46878,37 +46929,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_rx_align_xsub"
+ name="reg_bsn_monitor_v2_rx_align_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -46987,7 +47038,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -47056,7 +47107,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -47285,7 +47336,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -47463,11 +47514,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -47567,7 +47618,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -47636,7 +47687,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -47865,7 +47916,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -48019,37 +48070,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_sst_offload"
+ name="reg_bsn_monitor_v2_rx_align_xsub"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -48128,7 +48179,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -48197,7 +48248,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -48426,7 +48477,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -48604,11 +48655,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -48708,7 +48759,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -48777,7 +48828,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -49006,7 +49057,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -49160,37 +49211,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_xst_offload"
+ name="reg_bsn_monitor_v2_sst_offload"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -50301,37 +50352,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_scheduler"
+ name="reg_bsn_monitor_v2_xst_offload"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -50339,17 +50390,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -50358,27 +50409,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -50391,13 +50443,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -50411,7 +50461,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -50480,7 +50530,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -50637,12 +50687,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -50669,17 +50719,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -50701,17 +50751,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -50733,14 +50783,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -50752,31 +50802,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -50786,22 +50835,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -50828,14 +50879,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -50886,11 +50937,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -50919,17 +50970,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -50938,27 +50989,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -50971,13 +51023,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -50991,7 +51041,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -51060,7 +51110,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -51216,6 +51266,166 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
<interface>
<name>read</name>
<type>conduit</type>
@@ -51280,199 +51490,40 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_source_v2"
+ name="reg_bsn_scheduler"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -51488,7 +51539,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -51552,7 +51603,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -51621,7 +51672,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -52027,11 +52078,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -52068,7 +52119,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -52132,7 +52183,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -52201,7 +52252,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -52583,37 +52634,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_sync_scheduler_xsub"
+ name="reg_bsn_source_v2"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -52621,17 +52672,17 @@
<boundary>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>3</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -52640,28 +52691,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -52674,11 +52724,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -52692,7 +52744,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -52761,7 +52813,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -52918,12 +52970,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -52950,17 +53002,17 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -52982,17 +53034,17 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -53014,14 +53066,14 @@
</parameters>
</interface>
<interface>
- <name>write</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -53033,30 +53085,31 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>writedata</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -53066,24 +53119,22 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -53110,14 +53161,14 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -53168,11 +53219,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -53201,17 +53252,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>3</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -53220,28 +53271,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -53254,11 +53304,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -53272,7 +53324,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -53341,7 +53393,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -53498,12 +53550,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -53530,17 +53582,17 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -53562,17 +53614,17 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -53594,14 +53646,14 @@
</parameters>
</interface>
<interface>
- <name>write</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -53613,30 +53665,31 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>writedata</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -53646,24 +53699,22 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -53690,14 +53741,14 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -53724,37 +53775,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_crosslets_info"
+ name="reg_bsn_sync_scheduler_xsub"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -53762,17 +53813,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>4</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -53781,27 +53832,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -53814,13 +53866,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -54060,12 +54110,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -54092,17 +54142,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -54124,17 +54174,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -54156,14 +54206,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -54175,31 +54225,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -54209,22 +54258,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -54251,14 +54302,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -54342,17 +54393,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>4</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -54361,27 +54412,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -54394,13 +54446,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -54639,6 +54689,166 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
<interface>
<name>read</name>
<type>conduit</type>
@@ -54703,199 +54913,40 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_bsn"
+ name="reg_crosslets_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -54911,7 +54962,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -54975,7 +55026,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -55044,7 +55095,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -55450,11 +55501,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -55491,7 +55542,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -55555,7 +55606,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -55624,7 +55675,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -56006,37 +56057,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_block_validate_bsn_at_sync_bf"
+ name="reg_diag_data_buffer_bsn"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -56044,17 +56095,17 @@
<boundary>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -56063,28 +56114,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -56097,11 +56147,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -56115,7 +56167,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -56184,7 +56236,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -56341,12 +56393,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -56373,17 +56425,17 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -56405,17 +56457,17 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -56437,14 +56489,14 @@
</parameters>
</interface>
<interface>
- <name>write</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -56456,30 +56508,31 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>writedata</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -56489,24 +56542,22 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -56533,14 +56584,14 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -56591,11 +56642,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -56624,17 +56675,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -56643,28 +56694,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -56677,11 +56727,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -56695,7 +56747,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -56764,7 +56816,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -56921,12 +56973,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -56953,17 +57005,17 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -56985,17 +57037,17 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -57017,14 +57069,14 @@
</parameters>
</interface>
<interface>
- <name>write</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -57036,30 +57088,31 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>writedata</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -57069,24 +57122,22 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -57113,14 +57164,14 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -57147,37 +57198,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_block_validate_bsn_at_sync_xst"
+ name="reg_dp_block_validate_bsn_at_sync_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -57256,7 +57307,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -57325,7 +57376,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -57554,7 +57605,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -57732,11 +57783,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -57836,7 +57887,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -57905,7 +57956,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -58134,7 +58185,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -58288,37 +58339,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_block_validate_err_bf"
+ name="reg_dp_block_validate_bsn_at_sync_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -58397,7 +58448,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -58466,7 +58517,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -58695,7 +58746,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -58873,11 +58924,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -58977,7 +59028,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -59046,7 +59097,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -59275,7 +59326,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -59429,37 +59480,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_block_validate_err_xst"
+ name="reg_dp_block_validate_err_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -59538,7 +59589,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -59607,7 +59658,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -59836,7 +59887,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -60014,11 +60065,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -60118,7 +60169,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -60187,7 +60238,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -60416,7 +60467,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -60570,37 +60621,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_selector"
+ name="reg_dp_block_validate_err_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -60608,17 +60659,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -60627,27 +60678,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -60660,13 +60712,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -60680,7 +60730,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -60749,7 +60799,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -60906,12 +60956,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -60938,17 +60988,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -60970,17 +61020,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -61002,14 +61052,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -61021,31 +61071,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -61055,22 +61104,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -61097,14 +61148,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -61155,11 +61206,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -61188,17 +61239,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -61207,27 +61258,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -61240,13 +61292,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -61260,7 +61310,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -61329,7 +61379,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -61486,12 +61536,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -61518,44 +61568,12 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -61582,17 +61600,17 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>4</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -61601,28 +61619,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -61635,22 +61652,56 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -61677,14 +61728,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -61711,37 +61762,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_shiftram"
+ name="reg_dp_selector"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -61757,7 +61808,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -61821,7 +61872,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -61890,7 +61941,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -62296,11 +62347,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -62337,7 +62388,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -62401,7 +62452,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -62470,7 +62521,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -62852,37 +62903,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_xonoff"
+ name="reg_dp_shiftram"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -62898,7 +62949,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -62962,7 +63013,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -63031,7 +63082,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -63437,11 +63488,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -63478,7 +63529,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -63542,7 +63593,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -63611,7 +63662,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -63993,37 +64044,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_ctrl"
+ name="reg_dp_xonoff"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -64039,7 +64090,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -64103,7 +64154,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -64172,7 +64223,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -64578,11 +64629,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -64619,7 +64670,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -64683,7 +64734,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -64752,7 +64803,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -65134,37 +65185,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_data"
+ name="reg_dpmm_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -66275,37 +66326,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_epcs"
+ name="reg_dpmm_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -66321,7 +66372,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -66385,7 +66436,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -66454,7 +66505,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -66860,11 +66911,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -66901,7 +66952,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -66965,7 +67016,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -67034,7 +67085,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -67416,37 +67467,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_epcs</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_temp_sens"
+ name="reg_epcs"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -68557,37 +68608,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_epcs</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_voltage_sens"
+ name="reg_fpga_temp_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -68603,7 +68654,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -68667,7 +68718,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -68736,7 +68787,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -69142,11 +69193,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -69183,7 +69234,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -69247,7 +69298,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -69316,7 +69367,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -69698,37 +69749,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_hdr_dat"
+ name="reg_fpga_voltage_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -69744,7 +69795,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -69808,7 +69859,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -69877,7 +69928,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -70283,11 +70334,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -70324,7 +70375,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -70388,7 +70439,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -70457,7 +70508,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -70839,37 +70890,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_ctrl"
+ name="reg_hdr_dat"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -70885,7 +70936,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -70949,7 +71000,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -71018,7 +71069,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -71424,11 +71475,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -71465,7 +71516,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -71529,7 +71580,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -71598,7 +71649,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -71980,37 +72031,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_data"
+ name="reg_mmdp_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -73121,37 +73172,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_nof_crosslets"
+ name="reg_mmdp_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -73159,17 +73210,17 @@
<boundary>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -73178,28 +73229,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -73212,11 +73262,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -73456,108 +73508,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -73584,14 +73540,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -73616,12 +73572,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -73648,14 +73604,109 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_write_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -73739,17 +73790,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -73758,28 +73809,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -73792,11 +73842,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -74036,12 +74088,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -74068,17 +74120,17 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -74100,17 +74152,17 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -74132,14 +74184,14 @@
</parameters>
</interface>
<interface>
- <name>write</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -74151,30 +74203,31 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>writedata</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -74184,24 +74237,22 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -74228,14 +74279,14 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -74262,37 +74313,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_nw_10gbe_eth10g"
+ name="reg_nof_crosslets"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -74300,17 +74351,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -74319,27 +74370,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -74352,13 +74404,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -74598,12 +74648,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -74630,17 +74680,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -74662,17 +74712,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -74694,14 +74744,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -74713,31 +74763,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -74747,22 +74796,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -74789,14 +74840,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -74880,17 +74931,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -74899,27 +74950,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -74932,13 +74984,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -75177,6 +75227,166 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
<interface>
<name>read</name>
<type>conduit</type>
@@ -75241,199 +75451,40 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_nw_10gbe_mac"
+ name="reg_nw_10gbe_eth10g"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -75449,7 +75500,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -75513,7 +75564,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -75582,7 +75633,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -75988,11 +76039,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -76029,7 +76080,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -76093,7 +76144,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -76162,7 +76213,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -76544,37 +76595,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_remu"
+ name="reg_nw_10gbe_mac"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -76590,7 +76641,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -76654,7 +76705,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -76723,7 +76774,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -77129,11 +77180,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -77170,7 +77221,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -77234,7 +77285,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -77303,7 +77354,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -77685,37 +77736,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_remu</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_ring_info"
+ name="reg_remu"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -77723,17 +77774,17 @@
<boundary>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>3</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -77742,28 +77793,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -77776,11 +77826,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -77794,7 +77846,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -77863,7 +77915,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -78020,12 +78072,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -78052,17 +78104,17 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -78084,17 +78136,17 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -78116,14 +78168,14 @@
</parameters>
</interface>
<interface>
- <name>write</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -78135,30 +78187,31 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>writedata</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -78168,24 +78221,22 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -78212,14 +78263,14 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -78270,11 +78321,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -78303,17 +78354,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>3</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -78322,28 +78373,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -78356,11 +78406,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -78374,7 +78426,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -78443,7 +78495,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -78599,6 +78651,70 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
<interface>
<name>reset</name>
<type>conduit</type>
@@ -78632,12 +78748,75 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -78664,143 +78843,15 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -78826,37 +78877,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_remu</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_ring_lane_info_bf"
+ name="reg_ring_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -79967,37 +80018,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_ring_lane_info_xst"
+ name="reg_ring_lane_info_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -80076,7 +80127,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -80145,7 +80196,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -80374,7 +80425,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -80552,11 +80603,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -80656,7 +80707,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -80725,7 +80776,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -80954,7 +81005,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -81108,37 +81159,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_sdp_info"
+ name="reg_ring_lane_info_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -81146,17 +81197,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>4</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -81165,27 +81216,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -81198,13 +81250,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -81218,7 +81268,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -81287,7 +81337,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -81444,12 +81494,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -81476,17 +81526,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -81508,17 +81558,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -81540,14 +81590,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -81559,31 +81609,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -81593,22 +81642,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -81635,14 +81686,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -81693,11 +81744,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -81726,17 +81777,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>4</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -81745,27 +81796,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -81778,13 +81830,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -81798,7 +81848,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -81867,7 +81917,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -82024,12 +82074,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -82056,17 +82106,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -82088,17 +82138,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -82120,14 +82170,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -82139,31 +82189,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -82173,22 +82222,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -82215,14 +82266,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -82249,37 +82300,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_si"
+ name="reg_sdp_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -82295,7 +82346,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -82359,7 +82410,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -82428,7 +82479,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -82834,11 +82885,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -82875,7 +82926,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -82939,7 +82990,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -83008,7 +83059,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -83390,37 +83441,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_si</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_enable_bst"
+ name="reg_si"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -83436,7 +83487,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -83500,7 +83551,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -83569,7 +83620,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -83975,11 +84026,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -84016,7 +84067,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -84080,7 +84131,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -84149,7 +84200,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -84531,37 +84582,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_si</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_enable_sst"
+ name="reg_stat_enable_bst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -84577,7 +84628,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -84641,7 +84692,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -84710,7 +84761,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -85116,11 +85167,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -85157,7 +85208,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -85221,7 +85272,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -85290,7 +85341,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -85672,37 +85723,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_enable_xst"
+ name="reg_stat_enable_sst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -86813,37 +86864,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_hdr_dat_bst"
+ name="reg_stat_enable_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -86859,7 +86910,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -86923,7 +86974,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -86992,7 +87043,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -87398,11 +87449,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -87439,7 +87490,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -87503,7 +87554,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -87572,7 +87623,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -87954,37 +88005,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_hdr_dat_sst"
+ name="reg_stat_hdr_dat_bst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -88000,7 +88051,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -88064,7 +88115,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -88133,7 +88184,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -88539,11 +88590,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -88580,7 +88631,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -88644,7 +88695,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -88713,7 +88764,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -89095,37 +89146,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_hdr_dat_xst"
+ name="reg_stat_hdr_dat_sst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -90236,37 +90287,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_tr_10gbe_eth10g"
+ name="reg_stat_hdr_dat_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -90274,17 +90325,17 @@
<boundary>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -90293,28 +90344,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -90327,11 +90377,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -90345,7 +90397,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -90414,7 +90466,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -90571,12 +90623,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -90603,17 +90655,17 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -90635,17 +90687,17 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -90667,14 +90719,14 @@
</parameters>
</interface>
<interface>
- <name>write</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -90686,30 +90738,31 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>writedata</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -90719,24 +90772,22 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -90763,14 +90814,14 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -90821,11 +90872,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -90854,17 +90905,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -90873,28 +90924,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -90907,11 +90957,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -90925,7 +90977,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -90994,7 +91046,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -91151,12 +91203,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -91183,17 +91235,17 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -91215,17 +91267,17 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -91247,14 +91299,14 @@
</parameters>
</interface>
<interface>
- <name>write</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -91266,30 +91318,31 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>writedata</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -91299,24 +91352,22 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -91343,14 +91394,14 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -91377,37 +91428,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_tr_10gbe_mac"
+ name="reg_tr_10gbe_eth10g"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -91486,7 +91537,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>15</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -91555,7 +91606,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>131072</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -91784,7 +91835,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>15</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -91962,11 +92013,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>17</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -92066,7 +92117,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>15</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -92135,7 +92186,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>131072</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -92364,7 +92415,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>15</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -92518,37 +92569,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_wdi"
+ name="reg_tr_10gbe_mac"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -92556,17 +92607,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -92575,27 +92626,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -92608,13 +92660,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -92628,7 +92678,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -92697,7 +92747,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>131072</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -92854,12 +92904,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -92886,15 +92936,47 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -92918,12 +93000,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -92950,17 +93032,17 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -92969,56 +93051,25 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -93045,14 +93096,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -93103,11 +93154,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>17</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -93136,17 +93187,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -93155,27 +93206,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -93188,13 +93240,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -93208,7 +93258,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -93277,7 +93327,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>131072</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -93433,6 +93483,166 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>15</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
<interface>
<name>read</name>
<type>conduit</type>
@@ -93497,199 +93707,40 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_wdi</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_wg"
+ name="reg_wdi"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -93705,7 +93756,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -93769,7 +93820,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -93838,7 +93889,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -94244,11 +94295,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -94285,7 +94336,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -94349,7 +94400,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -94418,7 +94469,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -94800,37 +94851,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_wg</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_wdi</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="rom_system_info"
+ name="reg_wg"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -94846,7 +94897,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -94910,7 +94961,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -94979,7 +95030,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -95385,11 +95436,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -95426,7 +95477,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -95490,7 +95541,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -95559,7 +95610,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -95941,37 +95992,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_rom_system_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_wg</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="timer_0"
+ name="rom_system_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -95979,17 +96030,17 @@
<boundary>
<interfaces>
<interface>
- <name>clk</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>13</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -95998,27 +96049,26 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>irq</name>
- <type>interrupt</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>irq</name>
- <role>irq</role>
+ <name>coe_clk_export</name>
+ <role>export</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -96030,106 +96080,63 @@
</assignments>
<parameters>
<parameterValueMap>
- <entry>
- <key>associatedAddressablePoint</key>
- <value>timer_0.s1</value>
- </entry>
<entry>
<key>associatedClock</key>
- <value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bridgedReceiverOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToReceiver</key>
- </entry>
- <entry>
- <key>irqScheme</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset_n</name>
- <role>reset_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>s1</name>
+ <name>mem</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
- <name>address</name>
+ <name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>writedata</name>
- <role>writedata</role>
+ <name>avs_mem_write</name>
+ <role>write</role>
<direction>Input</direction>
- <width>16</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>16</width>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>chipselect</name>
- <role>chipselect</role>
+ <name>avs_mem_read</name>
+ <role>read</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>write_n</name>
- <role>write_n</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -96150,17 +96157,13 @@
<key>embeddedsw.configuration.isPrintableDevice</key>
<value>0</value>
</entry>
- <entry>
- <key>embeddedsw.configuration.isTimerDevice</key>
- <value>1</value>
- </entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>addressAlignment</key>
- <value>NATIVE</value>
+ <value>DYNAMIC</value>
</entry>
<entry>
<key>addressGroup</key>
@@ -96168,7 +96171,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -96180,11 +96183,1200 @@
</entry>
<entry>
<key>associatedClock</key>
- <value>clk</value>
+ <value>system</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>reset</value>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>15</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>13</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>13</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>32768</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_rom_system_info</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="timer_0"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>clk</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>irq</name>
+ <type>interrupt</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>irq</name>
+ <role>irq</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedAddressablePoint</key>
+ <value>timer_0.s1</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>reset</value>
+ </entry>
+ <entry>
+ <key>bridgedReceiverOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToReceiver</key>
+ </entry>
+ <entry>
+ <key>irqScheme</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset_n</name>
+ <role>reset_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>s1</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>16</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>16</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>chipselect</name>
+ <role>chipselect</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>write_n</name>
+ <role>write_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isTimerDevice</key>
+ <value>1</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>NATIVE</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
@@ -97280,7 +98472,7 @@
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144a10" />
+ <parameter name="baseAddress" value="0x00145210" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97360,7 +98552,7 @@
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x001449a0" />
+ <parameter name="baseAddress" value="0x001451a0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97400,7 +98592,7 @@
start="cpu_0.data_master"
end="reg_remu.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144920" />
+ <parameter name="baseAddress" value="0x00145120" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97420,7 +98612,7 @@
start="cpu_0.data_master"
end="reg_epcs.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144900" />
+ <parameter name="baseAddress" value="0x00145100" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97440,7 +98632,7 @@
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144a08" />
+ <parameter name="baseAddress" value="0x00145208" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97460,7 +98652,7 @@
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144a00" />
+ <parameter name="baseAddress" value="0x00145200" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97480,7 +98672,7 @@
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x001449f8" />
+ <parameter name="baseAddress" value="0x001451f8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97500,7 +98692,7 @@
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x001449f0" />
+ <parameter name="baseAddress" value="0x001451f0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97520,7 +98712,7 @@
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x001448e0" />
+ <parameter name="baseAddress" value="0x001450e0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97540,7 +98732,7 @@
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x001447c0" />
+ <parameter name="baseAddress" value="0x00144fc0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97580,7 +98772,7 @@
start="cpu_0.data_master"
end="reg_si.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x001449e8" />
+ <parameter name="baseAddress" value="0x001451e8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97620,7 +98812,7 @@
start="cpu_0.data_master"
end="ram_scrap.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0800" />
+ <parameter name="baseAddress" value="0x00144000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97640,7 +98832,7 @@
start="cpu_0.data_master"
end="reg_aduh_monitor.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144300" />
+ <parameter name="baseAddress" value="0x00144b00" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97680,7 +98872,7 @@
start="cpu_0.data_master"
end="reg_dp_shiftram.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144500" />
+ <parameter name="baseAddress" value="0x00144d00" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97700,7 +98892,7 @@
start="cpu_0.data_master"
end="reg_bsn_scheduler.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x001449e0" />
+ <parameter name="baseAddress" value="0x001451e0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97720,7 +98912,7 @@
start="cpu_0.data_master"
end="reg_bsn_source_v2.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x001448c0" />
+ <parameter name="baseAddress" value="0x001450c0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97740,7 +98932,7 @@
start="cpu_0.data_master"
end="reg_wg.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144200" />
+ <parameter name="baseAddress" value="0x00144a00" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97800,7 +98992,7 @@
start="cpu_0.data_master"
end="reg_dp_selector.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x001449d8" />
+ <parameter name="baseAddress" value="0x001451d8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97840,7 +99032,7 @@
start="cpu_0.data_master"
end="reg_bf_scale.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144990" />
+ <parameter name="baseAddress" value="0x00145190" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97860,7 +99052,7 @@
start="cpu_0.data_master"
end="reg_hdr_dat.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144000" />
+ <parameter name="baseAddress" value="0x00144800" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97880,7 +99072,7 @@
start="cpu_0.data_master"
end="reg_dp_xonoff.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144980" />
+ <parameter name="baseAddress" value="0x00145180" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97920,7 +99112,7 @@
start="cpu_0.data_master"
end="reg_sdp_info.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144780" />
+ <parameter name="baseAddress" value="0x00144f80" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97940,7 +99132,7 @@
start="cpu_0.data_master"
end="reg_nw_10gbe_eth10g.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x001449d0" />
+ <parameter name="baseAddress" value="0x001451d0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97980,7 +99172,7 @@
start="cpu_0.data_master"
end="reg_diag_data_buffer_bsn.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144480" />
+ <parameter name="baseAddress" value="0x00144c80" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98020,7 +99212,7 @@
start="cpu_0.data_master"
end="pio_jesd_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x001449c8" />
+ <parameter name="baseAddress" value="0x001451c8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98040,7 +99232,7 @@
start="cpu_0.data_master"
end="reg_stat_enable_sst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x001449c0" />
+ <parameter name="baseAddress" value="0x001451c0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98080,7 +99272,7 @@
start="cpu_0.data_master"
end="reg_stat_enable_bst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144970" />
+ <parameter name="baseAddress" value="0x00145170" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98120,7 +99312,7 @@
start="cpu_0.data_master"
end="reg_crosslets_info.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144740" />
+ <parameter name="baseAddress" value="0x00144f40" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98160,7 +99352,7 @@
start="cpu_0.data_master"
end="reg_stat_enable_xst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x001449b8" />
+ <parameter name="baseAddress" value="0x001451b8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98200,7 +99392,7 @@
start="cpu_0.data_master"
end="reg_bsn_sync_scheduler_xsub.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144700" />
+ <parameter name="baseAddress" value="0x00144f00" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98240,7 +99432,7 @@
start="cpu_0.data_master"
end="reg_nof_crosslets.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x001449b0" />
+ <parameter name="baseAddress" value="0x001451b0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98260,7 +99452,7 @@
start="cpu_0.data_master"
end="reg_bsn_align_v2_xsub.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144400" />
+ <parameter name="baseAddress" value="0x00144c00" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98280,7 +99472,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_aligned_xsub.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x001448a0" />
+ <parameter name="baseAddress" value="0x001450a0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98300,7 +99492,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_xst_offload.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144880" />
+ <parameter name="baseAddress" value="0x00145080" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98380,7 +99572,7 @@
start="cpu_0.data_master"
end="reg_dp_block_validate_err_xst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x001446c0" />
+ <parameter name="baseAddress" value="0x00144ec0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98400,7 +99592,7 @@
start="cpu_0.data_master"
end="reg_dp_block_validate_bsn_at_sync_xst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144960" />
+ <parameter name="baseAddress" value="0x00145160" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98420,7 +99612,7 @@
start="cpu_0.data_master"
end="reg_ring_info.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144950" />
+ <parameter name="baseAddress" value="0x00145150" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98440,7 +99632,7 @@
start="cpu_0.data_master"
end="reg_tr_10gbe_eth10g.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144860" />
+ <parameter name="baseAddress" value="0x00145060" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98500,7 +99692,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_sst_offload.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144840" />
+ <parameter name="baseAddress" value="0x00145040" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98520,7 +99712,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_bst_offload.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144680" />
+ <parameter name="baseAddress" value="0x00144e80" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98540,7 +99732,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_beamlet_output.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144640" />
+ <parameter name="baseAddress" value="0x00144e40" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98560,7 +99752,7 @@
start="cpu_0.data_master"
end="reg_bsn_align_v2_bf.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144820" />
+ <parameter name="baseAddress" value="0x00145020" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98600,7 +99792,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_aligned_bf.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144600" />
+ <parameter name="baseAddress" value="0x00144e00" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98620,7 +99812,7 @@
start="cpu_0.data_master"
end="reg_ring_lane_info_bf.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144940" />
+ <parameter name="baseAddress" value="0x00145140" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98640,7 +99832,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_ring_rx_bf.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x001445c0" />
+ <parameter name="baseAddress" value="0x00144dc0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98660,7 +99852,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_ring_tx_bf.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144580" />
+ <parameter name="baseAddress" value="0x00144d80" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98700,7 +99892,7 @@
start="cpu_0.data_master"
end="reg_dp_block_validate_bsn_at_sync_bf.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00144800" />
+ <parameter name="baseAddress" value="0x00145000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -98774,6 +99966,26 @@
<parameter name="qsys_mm.syncResets" value="FALSE" />
<parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
+ <connection
+ kind="avalon"
+ version="19.4"
+ start="cpu_0.data_master"
+ end="reg_bdo_destinations.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0800" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
<connection
kind="avalon"
version="19.4"
@@ -99261,6 +100473,11 @@
version="19.4"
start="clk_0.clk"
end="ram_equalizer_gains_cross.system" />
+ <connection
+ kind="clock"
+ version="19.4"
+ start="clk_0.clk"
+ end="reg_bdo_destinations.system" />
<connection
kind="interrupt"
version="19.4"
@@ -99669,6 +100886,11 @@
version="19.4"
start="clk_0.clk_reset"
end="ram_equalizer_gains_cross.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="clk_0.clk_reset"
+ end="reg_bdo_destinations.system_reset" />
<connection
kind="reset"
version="19.4"
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
index 6d12a8748c603307877e1ff8b00d90efd6c72014..e1121127b6c8ce995c9ee29cae088f497193767d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
@@ -160,6 +160,7 @@ use wpfb_lib.wpfb_pkg.all;
use unb2c_board_lib.unb2c_board_pkg.all;
use lofar2_sdp_lib.sdp_pkg.all;
use lofar2_sdp_lib.tb_sdp_pkg.all;
+use lofar2_sdp_lib.sdp_bdo_pkg.all;
use tech_pll_lib.tech_pll_component_pkg.all;
use lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station_pkg.all;
@@ -193,12 +194,14 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf is
constant c_revision_select : t_lofar2_unb2c_sdp_station_config := func_sel_revision_rec(c_design_name);
constant c_sim : boolean := true;
- constant c_unb_nr : natural := 0; -- UniBoard 0
- constant c_node_nr : natural := 0;
+ constant c_unb_nr : natural := 1;
+ constant c_node_nr : natural := 2;
constant c_gn_index : natural := c_unb_nr * 4 + c_node_nr; -- this node GN
constant c_init_bsn : natural := 17; -- some recognizable value >= 0
constant c_bsn_latency : natural := 5; -- used to time stimuli_done
constant c_use_bdo_transpose : boolean := c_revision_select.use_bdo_transpose;
+ constant c_nof_bdo_destinations_max : natural := c_revision_select.nof_bdo_destinations_max;
+ constant c_nof_bdo_destinations : natural := 1;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(c_gn_index, 8);
constant c_version : std_logic_vector(1 downto 0) := "00";
@@ -229,7 +232,9 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf is
constant c_cep_ip_src_addr : std_logic_vector(31 downto 0) := c_sdp_cep_ip_src_addr_31_16 & func_sdp_gn_index_to_ip_15_0(c_gn_index);
constant c_cep_udp_src_port : std_logic_vector(15 downto 0) := c_sdp_cep_udp_src_port_15_8 & c_id;
- constant c_exp_ip_header_checksum : natural := 16#5BDE#; -- value obtained from rx_sdp_cep_header.ip.header_checksum in wave window
+ -- value obtained from rx_sdp_cep_header.ip.header_checksum in wave window
+ --constant c_exp_ip_header_checksum : natural := 16#5BDE#; -- for c_unb_nr = 0, c_node_nr = 0
+ constant c_exp_ip_header_checksum : natural := 16#5ADC#; -- for c_unb_nr = 1, c_node_nr = 2
constant c_exp_beamlet_scale : natural := natural(g_beamlet_scale * real(c_sdp_unit_beamlet_scale)); -- c_sdp_unit_beamlet_scale = 2**15;
constant c_exp_beamlet_index : natural := 0; -- depends on beamset bset * c_sdp_S_sub_bf
@@ -352,6 +357,7 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf is
constant c_addr_w_ram_bf_weights : natural := ceil_log2(c_sdp_N_pol_bf * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
constant c_addr_w_reg_bf_scale : natural := 1;
constant c_addr_w_reg_hdr_dat : natural := ceil_log2(field_nof_words(c_sdp_cep_hdr_field_arr, c_word_w));
+ constant c_addr_w_reg_bdo_destinations : natural := c_sdp_reg_bdo_destinations_info_w_one;
constant c_addr_w_reg_stat_enable_bst : natural := c_sdp_reg_stat_enable_addr_w;
constant c_addr_w_reg_dp_xonoff : natural := 1;
constant c_addr_w_ram_st_bst : natural := ceil_log2(c_sdp_S_sub_bf * c_sdp_N_pol_bf * c_stat_data_sz);
@@ -363,6 +369,7 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf is
constant c_mm_span_ram_bf_weights : natural := 2**c_addr_w_ram_bf_weights;
constant c_mm_span_reg_bf_scale : natural := 2**c_addr_w_reg_bf_scale;
constant c_mm_span_reg_hdr_dat : natural := 2**c_addr_w_reg_hdr_dat;
+ constant c_mm_span_reg_bdo_destinations : natural := 2**c_addr_w_reg_bdo_destinations;
constant c_mm_span_reg_stat_enable_bst : natural := 2**c_addr_w_reg_stat_enable_bst;
constant c_mm_span_reg_dp_xonoff : natural := 2**c_addr_w_reg_dp_xonoff;
constant c_mm_span_ram_st_bst : natural := 2**c_addr_w_ram_st_bst;
@@ -382,9 +389,10 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf is
constant c_mm_file_reg_bf_scale : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BF_SCALE";
constant c_mm_file_reg_sdp_info : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_SDP_INFO";
constant c_mm_file_reg_hdr_dat : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_HDR_DAT"; -- c_sdp_N_beamsets = 2 beamsets
+ constant c_mm_file_reg_bdo_destinations : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BDO_DESTINATIONS";
-- Tb BSN moments
- constant c_stimuli_done_bsn : natural := c_init_bsn + c_bsn_latency + c_nof_block_per_sync * 3;
+ constant c_stimuli_done_bsn : natural := c_init_bsn + c_bsn_latency + c_nof_block_per_sync * 4;
constant c_verify_rx_beamlet_list_bsn : natural := c_stimuli_done_bsn - c_nof_block_per_sync;
-- Tb
@@ -412,6 +420,10 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf is
signal rd_cep_ip_dst_addr : std_logic_vector(31 downto 0);
signal rd_cep_udp_src_port : std_logic_vector(15 downto 0);
signal rd_cep_udp_dst_port : std_logic_vector(15 downto 0);
+ signal rd_nof_destinations : natural;
+ signal rd_nof_destinations_act : natural;
+ signal rd_nof_destinations_max : natural;
+ signal rd_nof_blocks_per_packet : natural;
-- WG
signal current_bsn_wg : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
@@ -679,7 +691,9 @@ begin
variable v_bsn : natural;
variable v_data_lo, v_data_hi : std_logic_vector(c_word_w - 1 downto 0);
variable v_stat_data : std_logic_vector(c_longword_w - 1 downto 0);
- variable v_len, v_span, v_offset, v_addr, v_sel : natural; -- address ranges, indices
+ variable v_len, v_span,
+ v_offset, v_offset_bdo,
+ v_addr, v_sel : natural; -- address ranges, indices
variable v_W, v_P, v_PB, v_S, v_A, v_B, v_G : natural; -- array indicies
variable v_re, v_im, v_weight : integer;
variable v_re_exp, v_im_exp : real := 0.0;
@@ -814,10 +828,26 @@ begin
mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 38, TO_SINT(c_cep_eth_src_mac(31 downto 0)), tb_clk); -- use signed to fit 32 b in INTEGER
mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 26, TO_SINT(c_cep_ip_src_addr), tb_clk); -- use signed to fit 32 b in INTEGER
mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 24, TO_UINT(c_cep_udp_src_port), tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 41, TO_UINT(c_sdp_cep_eth_dst_mac(47 downto 32)), tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 40, TO_SINT(c_sdp_cep_eth_dst_mac(31 downto 0)), tb_clk); -- use signed to fit 32 b in INTEGER
- mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 25, TO_SINT(c_sdp_cep_ip_dst_addr), tb_clk); -- use signed to fit 32 b in INTEGER
- mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 23, TO_UINT(c_sdp_cep_udp_dst_port), tb_clk);
+ if c_nof_bdo_destinations_max = 1 then
+ -- . Set destination MAC/IP/UDP via c_mm_file_reg_hdr_dat
+ mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 41, TO_UINT(c_sdp_cep_eth_dst_mac(47 downto 32)), tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 40, TO_SINT(c_sdp_cep_eth_dst_mac(31 downto 0)), tb_clk); -- use signed to fit 32 b in INTEGER
+ mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 25, TO_SINT(c_sdp_cep_ip_dst_addr), tb_clk); -- use signed to fit 32 b in INTEGER
+ mmf_mm_bus_wr(c_mm_file_reg_hdr_dat, v_offset + 23, TO_UINT(c_sdp_cep_udp_dst_port), tb_clk);
+ else
+ -- . Set nof_destinations = c_nof_bdo_destinations = 1
+ v_offset_bdo := bset * c_mm_span_reg_bdo_destinations + c_sdp_bdo_mm_nof_destinations_max * 4;
+ mmf_mm_bus_wr(c_mm_file_reg_bdo_destinations, v_offset_bdo + 0, c_nof_bdo_destinations, tb_clk);
+ -- . Set destination MAC/IP/UDP via c_mm_file_reg_bdo_destinations, for
+ -- the first and only destination
+ v_offset_bdo := bset * c_mm_span_reg_bdo_destinations;
+ mmf_mm_bus_wr(c_mm_file_reg_bdo_destinations, v_offset_bdo + 1, to_uint(c_sdp_cep_eth_dst_mac(47 downto 32)), tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bdo_destinations, v_offset_bdo, to_sint(c_sdp_cep_eth_dst_mac(31 downto 0)), tb_clk);
+ v_offset_bdo := bset * c_mm_span_reg_bdo_destinations + c_sdp_bdo_mm_nof_destinations_max * 2;
+ mmf_mm_bus_wr(c_mm_file_reg_bdo_destinations, v_offset_bdo, to_sint(c_sdp_cep_ip_dst_addr), tb_clk);
+ v_offset_bdo := bset * c_mm_span_reg_bdo_destinations + c_sdp_bdo_mm_nof_destinations_max * 3;
+ mmf_mm_bus_wr(c_mm_file_reg_bdo_destinations, v_offset_bdo, to_uint(c_sdp_cep_udp_dst_port), tb_clk);
+ end if;
proc_common_wait_cross_clock_domain_latency(c_mm_clk_period, c_ext_clk_period, c_common_cross_clock_domain_latency * 2);
-- . Read back
@@ -825,19 +855,45 @@ begin
mmf_mm_bus_rd(c_mm_file_reg_hdr_dat, v_offset + 38, rd_data, tb_clk); rd_cep_eth_src_mac(31 downto 0) <= rd_data;
mmf_mm_bus_rd(c_mm_file_reg_hdr_dat, v_offset + 26, rd_data, tb_clk); rd_cep_ip_src_addr <= rd_data;
mmf_mm_bus_rd(c_mm_file_reg_hdr_dat, v_offset + 24, rd_data, tb_clk); rd_cep_udp_src_port <= rd_data(15 downto 0);
- mmf_mm_bus_rd(c_mm_file_reg_hdr_dat, v_offset + 41, rd_data, tb_clk); rd_cep_eth_dst_mac(47 downto 32) <= rd_data(15 downto 0);
- mmf_mm_bus_rd(c_mm_file_reg_hdr_dat, v_offset + 40, rd_data, tb_clk); rd_cep_eth_dst_mac(31 downto 0) <= rd_data;
- mmf_mm_bus_rd(c_mm_file_reg_hdr_dat, v_offset + 25, rd_data, tb_clk); rd_cep_ip_dst_addr <= rd_data;
- mmf_mm_bus_rd(c_mm_file_reg_hdr_dat, v_offset + 23, rd_data, tb_clk); rd_cep_udp_dst_port <= rd_data(15 downto 0);
+ if c_nof_bdo_destinations_max = 1 then
+ -- . Read back destination MAC/IP/UDP via c_mm_file_reg_hdr_dat
+ mmf_mm_bus_rd(c_mm_file_reg_hdr_dat, v_offset + 41, rd_data, tb_clk); rd_cep_eth_dst_mac(47 downto 32) <= rd_data(15 downto 0);
+ mmf_mm_bus_rd(c_mm_file_reg_hdr_dat, v_offset + 40, rd_data, tb_clk); rd_cep_eth_dst_mac(31 downto 0) <= rd_data;
+ mmf_mm_bus_rd(c_mm_file_reg_hdr_dat, v_offset + 25, rd_data, tb_clk); rd_cep_ip_dst_addr <= rd_data;
+ mmf_mm_bus_rd(c_mm_file_reg_hdr_dat, v_offset + 23, rd_data, tb_clk); rd_cep_udp_dst_port <= rd_data(15 downto 0);
+ else
+ -- . Read back nof destinations info via c_mm_file_reg_bdo_destinations
+ v_offset_bdo := bset * c_mm_span_reg_bdo_destinations + c_sdp_bdo_mm_nof_destinations_max * 4;
+ mmf_mm_bus_rd(c_mm_file_reg_bdo_destinations, v_offset_bdo + 0, rd_data, tb_clk); rd_nof_destinations <= to_uint(rd_data(7 downto 0));
+ mmf_mm_bus_rd(c_mm_file_reg_bdo_destinations, v_offset_bdo + 1, rd_data, tb_clk); rd_nof_destinations_act <= to_uint(rd_data(7 downto 0));
+ mmf_mm_bus_rd(c_mm_file_reg_bdo_destinations, v_offset_bdo + 2, rd_data, tb_clk); rd_nof_destinations_max <= to_uint(rd_data(7 downto 0));
+ mmf_mm_bus_rd(c_mm_file_reg_bdo_destinations, v_offset_bdo + 3, rd_data, tb_clk); rd_nof_blocks_per_packet <= to_uint(rd_data(7 downto 0));
+ -- . Read back destination MAC/IP/UDP via c_mm_file_reg_bdo_destinations
+ v_offset_bdo := bset * c_mm_span_reg_bdo_destinations;
+ mmf_mm_bus_rd(c_mm_file_reg_bdo_destinations, v_offset_bdo + 1, rd_data, tb_clk); rd_cep_eth_dst_mac(47 downto 32) <= rd_data(15 downto 0);
+ mmf_mm_bus_rd(c_mm_file_reg_bdo_destinations, v_offset_bdo, rd_data, tb_clk); rd_cep_eth_dst_mac(31 downto 0) <= rd_data;
+ v_offset_bdo := bset * c_mm_span_reg_bdo_destinations + c_sdp_bdo_mm_nof_destinations_max * 2;
+ mmf_mm_bus_rd(c_mm_file_reg_bdo_destinations, v_offset_bdo, rd_data, tb_clk); rd_cep_ip_dst_addr <= rd_data;
+ v_offset_bdo := bset * c_mm_span_reg_bdo_destinations + c_sdp_bdo_mm_nof_destinations_max * 3;
+ mmf_mm_bus_rd(c_mm_file_reg_bdo_destinations, v_offset_bdo, rd_data, tb_clk); rd_cep_udp_dst_port <= rd_data(15 downto 0);
+ end if;
proc_common_wait_some_cycles(tb_clk, 1);
- -- . verify read back
+
+ -- . verify read back source MAC/IP/UDP
assert rd_cep_eth_src_mac = c_cep_eth_src_mac report "Wrong MM read rd_cep_eth_src_mac for beamset " & natural'image(bset) severity ERROR;
assert rd_cep_ip_src_addr = c_cep_ip_src_addr report "Wrong MM read rd_cep_ip_src_addr for beamset " & natural'image(bset) severity ERROR;
assert rd_cep_udp_src_port = c_cep_udp_src_port report "Wrong MM read rd_cep_udp_src_port for beamset " & natural'image(bset) severity ERROR;
+ -- . verify read back destination MAC/IP/UDP
assert rd_cep_eth_dst_mac = c_sdp_cep_eth_dst_mac report "Wrong MM read rd_cep_eth_dst_mac for beamset " & natural'image(bset) severity ERROR;
assert rd_cep_ip_dst_addr = c_sdp_cep_ip_dst_addr report "Wrong MM read rd_cep_ip_dst_addr for beamset " & natural'image(bset) severity ERROR;
assert rd_cep_udp_dst_port = c_sdp_cep_udp_dst_port report "Wrong MM read rd_cep_udp_dst_port for beamset " & natural'image(bset) severity ERROR;
-
+ if c_nof_bdo_destinations_max > 1 then
+ -- . Verify read back nof destinations info
+ assert rd_nof_destinations = c_nof_bdo_destinations report "Wrong MM read rd_nof_destinations for beamset " & natural'image(bset) severity ERROR;
+ assert rd_nof_destinations_act = c_nof_bdo_destinations report "Wrong MM read rd_nof_destinations_act for beamset " & natural'image(bset) severity ERROR;
+ assert rd_nof_destinations_max = c_nof_bdo_destinations_max report "Wrong MM read rd_nof_destinations_max for beamset " & natural'image(bset) severity ERROR;
+ assert rd_nof_blocks_per_packet = c_sdp_cep_nof_blocks_per_packet report "Wrong MM read rd_nof_blocks_per_packet for beamset " & natural'image(bset) severity ERROR;
+ end if;
----------------------------------------------------------------------------
-- Enable BST offload (not verified here, but only for view in Wave window)
----------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
index d9154faa443f87f2a84acb36e108a01eb2d24772..18a8782ce0d6a3d9e0ebd512aefa68d9bdf7e76a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
@@ -321,6 +321,8 @@ architecture str of lofar2_unb2c_sdp_station is
-- Beamlet Data Output header fields
signal reg_hdr_dat_copi : t_mem_copi := c_mem_copi_rst;
signal reg_hdr_dat_cipo : t_mem_cipo := c_mem_cipo_rst;
+ signal reg_bdo_destinations_copi : t_mem_copi := c_mem_mosi_rst;
+ signal reg_bdo_destinations_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Beamlet Data Output xonoff
signal reg_dp_xonoff_copi : t_mem_copi := c_mem_copi_rst;
@@ -686,6 +688,8 @@ begin
reg_bf_scale_cipo => reg_bf_scale_cipo,
reg_hdr_dat_copi => reg_hdr_dat_copi,
reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_bdo_destinations_copi => reg_bdo_destinations_copi,
+ reg_bdo_destinations_cipo => reg_bdo_destinations_cipo,
reg_dp_xonoff_copi => reg_dp_xonoff_copi,
reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
ram_st_bst_copi => ram_st_bst_copi,
@@ -882,6 +886,8 @@ begin
reg_bf_scale_cipo => reg_bf_scale_cipo,
reg_hdr_dat_copi => reg_hdr_dat_copi,
reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_bdo_destinations_copi => reg_bdo_destinations_copi,
+ reg_bdo_destinations_cipo => reg_bdo_destinations_cipo,
reg_dp_xonoff_copi => reg_dp_xonoff_copi,
reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
ram_st_bst_copi => ram_st_bst_copi,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
index 177d5cfa3f656620bf33c69a72e92c8420474743..6f3810e7995a00ec291322808662b30ce927f178 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
@@ -46,13 +46,13 @@ package lofar2_unb2c_sdp_station_pkg is
constant c_fsub : t_lofar2_unb2c_sdp_station_config := (false, true, false, false, false, 1, false, false, 0);
-- use c_bf on one node also to simulate bdo transpose
-- use c_bf_ring with ring also to simulate bdo identity
- constant c_bf : t_lofar2_unb2c_sdp_station_config := (false, true, false, true, true, 1, false, false, 0);
+ constant c_bf : t_lofar2_unb2c_sdp_station_config := (false, true, false, true, true, 32, false, false, 0);
constant c_bf_ring : t_lofar2_unb2c_sdp_station_config := (false, true, false, true, false, 1, false, true, 0);
constant c_xsub_one : t_lofar2_unb2c_sdp_station_config := (false, true, false, false, false, 1, true, false, 1);
constant c_xsub_ring : t_lofar2_unb2c_sdp_station_config := (false, true, false, false, false, 1, true, true, 9);
constant c_full_wg : t_lofar2_unb2c_sdp_station_config := (true, true, false, true, true, 1, true, true, 9);
-- Use c_full for LOFAR2 Station SDP operations
- constant c_full : t_lofar2_unb2c_sdp_station_config := (false, true, false, true, true, 1, true, true, 9);
+ constant c_full : t_lofar2_unb2c_sdp_station_config := (false, true, false, true, true, 32, true, true, 9);
constant c_full_wg_os : t_lofar2_unb2c_sdp_station_config := (true, true, true, true, true, 1, true, true, 9);
constant c_full_os : t_lofar2_unb2c_sdp_station_config := (false, true, true, true, true, 1, true, true, 9);
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
index 663256c83f518a47f01c77824404e95a6ad0b0a7..e7071c6a168d77c91dc93177246f5a8974e43bb2 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
@@ -183,9 +183,13 @@ entity mmm_lofar2_unb2c_sdp_station is
reg_bf_scale_copi : out t_mem_copi;
reg_bf_scale_cipo : in t_mem_cipo;
- -- Beamlet Data Output header fields
+ -- Beamlet Data Output (BDO) header fields
+ -- . single destination, used when revision.nof_bdo_destinations_max = 1
reg_hdr_dat_copi : out t_mem_copi;
reg_hdr_dat_cipo : in t_mem_cipo;
+ -- . multiple destinations, used when revision.nof_bdo_destinations_max > 1
+ reg_bdo_destinations_copi : out t_mem_copi;
+ reg_bdo_destinations_cipo : in t_mem_cipo;
-- Beamlet Data Output xonoff
reg_dp_xonoff_copi : out t_mem_copi;
@@ -429,6 +433,9 @@ begin
u_mm_file_reg_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT")
port map(mm_rst, mm_clk, reg_hdr_dat_copi, reg_hdr_dat_cipo );
+ u_mm_file_reg_bdo_destinations : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BDO_DESTINATIONS")
+ port map(mm_rst, mm_clk, reg_bdo_destinations_copi, reg_bdo_destinations_cipo );
+
u_mm_file_reg_dp_xonoff : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF")
port map(mm_rst, mm_clk, reg_dp_xonoff_copi, reg_dp_xonoff_cipo );
@@ -871,6 +878,14 @@ begin
reg_hdr_dat_read_export => reg_hdr_dat_copi.rd,
reg_hdr_dat_readdata_export => reg_hdr_dat_cipo.rddata(c_word_w - 1 downto 0),
+ reg_bdo_destinations_clk_export => OPEN,
+ reg_bdo_destinations_reset_export => OPEN,
+ reg_bdo_destinations_address_export => reg_bdo_destinations_copi.address(c_sdp_reg_bdo_destinations_info_w - 1 downto 0),
+ reg_bdo_destinations_write_export => reg_bdo_destinations_copi.wr,
+ reg_bdo_destinations_writedata_export => reg_bdo_destinations_copi.wrdata(c_word_w - 1 downto 0),
+ reg_bdo_destinations_read_export => reg_bdo_destinations_copi.rd,
+ reg_bdo_destinations_readdata_export => reg_bdo_destinations_cipo.rddata(c_word_w - 1 downto 0),
+
reg_dp_xonoff_clk_export => OPEN,
reg_dp_xonoff_reset_export => OPEN,
reg_dp_xonoff_address_export => reg_dp_xonoff_copi.address(c_sdp_reg_dp_xonoff_addr_w - 1 downto 0),
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
index 3fa9fa61c5117114f1c2adc01c8057ee2b2dd77c..dbc0101b0999e750773f652e91c5f5be62300636 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
@@ -27,540 +27,546 @@ package qsys_lofar2_unb2c_sdp_station_pkg is
-----------------------------------------------------------------------------
component qsys_lofar2_unb2c_sdp_station is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_bf_weights_reset_export : out std_logic; -- export
- ram_bf_weights_clk_export : out std_logic; -- export
- ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
- ram_bf_weights_write_export : out std_logic; -- export
- ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_bf_weights_read_export : out std_logic; -- export
- ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
- ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_address_export : out std_logic_vector(13 downto 0); -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_address_export : out std_logic_vector(14 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
- ram_ss_ss_wide_clk_export : out std_logic; -- export
- ram_ss_ss_wide_read_export : out std_logic; -- export
- ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_ss_ss_wide_reset_export : out std_logic; -- export
- ram_ss_ss_wide_write_export : out std_logic; -- export
- ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
- ram_st_bst_clk_export : out std_logic; -- export
- ram_st_bst_read_export : out std_logic; -- export
- ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_bst_reset_export : out std_logic; -- export
- ram_st_bst_write_export : out std_logic; -- export
- ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_histogram_reset_export : out std_logic; -- export
- ram_st_histogram_clk_export : out std_logic; -- export
- ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
- ram_st_histogram_write_export : out std_logic; -- export
- ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_histogram_read_export : out std_logic; -- export
- ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_address_export : out std_logic_vector(14 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
- ram_st_xsq_clk_export : out std_logic; -- export
- ram_st_xsq_read_export : out std_logic; -- export
- ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_xsq_reset_export : out std_logic; -- export
- ram_st_xsq_write_export : out std_logic; -- export
- ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bf_scale_clk_export : out std_logic; -- export
- reg_bf_scale_read_export : out std_logic; -- export
- reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bf_scale_reset_export : out std_logic; -- export
- reg_bf_scale_write_export : out std_logic; -- export
- reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_bf_reset_export : out std_logic; -- export
- reg_bsn_align_v2_bf_clk_export : out std_logic; -- export
- reg_bsn_align_v2_bf_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_align_v2_bf_write_export : out std_logic; -- export
- reg_bsn_align_v2_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_bf_read_export : out std_logic; -- export
- reg_bsn_align_v2_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_align_v2_xsub_reset_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_clk_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_align_v2_xsub_write_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_xsub_read_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_aligned_xsub_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_aligned_xsub_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_xsub_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_beamlet_output_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_beamlet_output_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_beamlet_output_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_bst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_bst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_bst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_align_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_align_xsub_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_xsub_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_xsub_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_sst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_sst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_sst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_source_v2_clk_export : out std_logic; -- export
- reg_bsn_source_v2_read_export : out std_logic; -- export
- reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_v2_reset_export : out std_logic; -- export
- reg_bsn_source_v2_write_export : out std_logic; -- export
- reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_crosslets_info_clk_export : out std_logic; -- export
- reg_crosslets_info_read_export : out std_logic; -- export
- reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_crosslets_info_reset_export : out std_logic; -- export
- reg_crosslets_info_write_export : out std_logic; -- export
- reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_bf_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_block_validate_err_bf_write_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_bf_read_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_block_validate_err_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_xonoff_clk_export : out std_logic; -- export
- reg_dp_xonoff_read_export : out std_logic; -- export
- reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_reset_export : out std_logic; -- export
- reg_dp_xonoff_write_export : out std_logic; -- export
- reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
- reg_hdr_dat_clk_export : out std_logic; -- export
- reg_hdr_dat_read_export : out std_logic; -- export
- reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_reset_export : out std_logic; -- export
- reg_hdr_dat_write_export : out std_logic; -- export
- reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nof_crosslets_reset_export : out std_logic; -- export
- reg_nof_crosslets_clk_export : out std_logic; -- export
- reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nof_crosslets_write_export : out std_logic; -- export
- reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nof_crosslets_read_export : out std_logic; -- export
- reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_nw_10gbe_mac_clk_export : out std_logic; -- export
- reg_nw_10gbe_mac_read_export : out std_logic; -- export
- reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_mac_reset_export : out std_logic; -- export
- reg_nw_10gbe_mac_write_export : out std_logic; -- export
- reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_reset_export : out std_logic; -- export
- reg_ring_info_clk_export : out std_logic; -- export
- reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_info_write_export : out std_logic; -- export
- reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_read_export : out std_logic; -- export
- reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_bf_reset_export : out std_logic; -- export
- reg_ring_lane_info_bf_clk_export : out std_logic; -- export
- reg_ring_lane_info_bf_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_lane_info_bf_write_export : out std_logic; -- export
- reg_ring_lane_info_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_bf_read_export : out std_logic; -- export
- reg_ring_lane_info_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_xst_reset_export : out std_logic; -- export
- reg_ring_lane_info_xst_clk_export : out std_logic; -- export
- reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_ring_lane_info_xst_write_export : out std_logic; -- export
- reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_xst_read_export : out std_logic; -- export
- reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_stat_enable_bst_clk_export : out std_logic; -- export
- reg_stat_enable_bst_read_export : out std_logic; -- export
- reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_bst_reset_export : out std_logic; -- export
- reg_stat_enable_bst_write_export : out std_logic; -- export
- reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_sst_clk_export : out std_logic; -- export
- reg_stat_enable_sst_read_export : out std_logic; -- export
- reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_sst_reset_export : out std_logic; -- export
- reg_stat_enable_sst_write_export : out std_logic; -- export
- reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_xst_clk_export : out std_logic; -- export
- reg_stat_enable_xst_read_export : out std_logic; -- export
- reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_xst_reset_export : out std_logic; -- export
- reg_stat_enable_xst_write_export : out std_logic; -- export
- reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_stat_hdr_dat_bst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_sst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_xst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0); -- export
- reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_mac_reset_export : out std_logic; -- export
- reg_tr_10gbe_mac_clk_export : out std_logic; -- export
- reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0); -- export
- reg_tr_10gbe_mac_write_export : out std_logic; -- export
- reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_mac_read_export : out std_logic; -- export
- reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_cross_reset_export : out std_logic; -- export
- ram_equalizer_gains_cross_clk_export : out std_logic; -- export
- ram_equalizer_gains_cross_address_export : out std_logic_vector(13 downto 0); -- export
- ram_equalizer_gains_cross_write_export : out std_logic; -- export
- ram_equalizer_gains_cross_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_cross_read_export : out std_logic; -- export
- ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_bf_weights_reset_export : out std_logic; -- export
+ ram_bf_weights_clk_export : out std_logic; -- export
+ ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_bf_weights_write_export : out std_logic; -- export
+ ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_bf_weights_read_export : out std_logic; -- export
+ ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_reset_export : out std_logic; -- export
+ ram_equalizer_gains_clk_export : out std_logic; -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_equalizer_gains_write_export : out std_logic; -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_read_export : out std_logic; -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_cross_reset_export : out std_logic; -- export
+ ram_equalizer_gains_cross_clk_export : out std_logic; -- export
+ ram_equalizer_gains_cross_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_equalizer_gains_cross_write_export : out std_logic; -- export
+ ram_equalizer_gains_cross_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_cross_read_export : out std_logic; -- export
+ ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_fil_coefs_clk_export : out std_logic; -- export
+ ram_fil_coefs_read_export : out std_logic; -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_reset_export : out std_logic; -- export
+ ram_fil_coefs_write_export : out std_logic; -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_ss_ss_wide_clk_export : out std_logic; -- export
+ ram_ss_ss_wide_read_export : out std_logic; -- export
+ ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_ss_ss_wide_reset_export : out std_logic; -- export
+ ram_ss_ss_wide_write_export : out std_logic; -- export
+ ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_st_bst_clk_export : out std_logic; -- export
+ ram_st_bst_read_export : out std_logic; -- export
+ ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_bst_reset_export : out std_logic; -- export
+ ram_st_bst_write_export : out std_logic; -- export
+ ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_histogram_reset_export : out std_logic; -- export
+ ram_st_histogram_clk_export : out std_logic; -- export
+ ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_st_histogram_write_export : out std_logic; -- export
+ ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_histogram_read_export : out std_logic; -- export
+ ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_st_sst_clk_export : out std_logic; -- export
+ ram_st_sst_read_export : out std_logic; -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_reset_export : out std_logic; -- export
+ ram_st_sst_write_export : out std_logic; -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
+ ram_st_xsq_clk_export : out std_logic; -- export
+ ram_st_xsq_read_export : out std_logic; -- export
+ ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_xsq_reset_export : out std_logic; -- export
+ ram_st_xsq_write_export : out std_logic; -- export
+ ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_clk_export : out std_logic; -- export
+ ram_wg_read_export : out std_logic; -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_reset_export : out std_logic; -- export
+ ram_wg_write_export : out std_logic; -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_aduh_monitor_clk_export : out std_logic; -- export
+ reg_aduh_monitor_read_export : out std_logic; -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_aduh_monitor_reset_export : out std_logic; -- export
+ reg_aduh_monitor_write_export : out std_logic; -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bf_scale_clk_export : out std_logic; -- export
+ reg_bf_scale_read_export : out std_logic; -- export
+ reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bf_scale_reset_export : out std_logic; -- export
+ reg_bf_scale_write_export : out std_logic; -- export
+ reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_bf_reset_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_clk_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_align_v2_bf_write_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_bf_read_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_align_v2_xsub_reset_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_clk_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_align_v2_xsub_write_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_xsub_read_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_aligned_xsub_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_xsub_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_xsub_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_beamlet_output_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_beamlet_output_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_beamlet_output_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_bst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_bst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_bst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_align_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_sst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_sst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_sst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_xst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_xst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_source_v2_clk_export : out std_logic; -- export
+ reg_bsn_source_v2_read_export : out std_logic; -- export
+ reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_v2_reset_export : out std_logic; -- export
+ reg_bsn_source_v2_write_export : out std_logic; -- export
+ reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_crosslets_info_clk_export : out std_logic; -- export
+ reg_crosslets_info_read_export : out std_logic; -- export
+ reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_crosslets_info_reset_export : out std_logic; -- export
+ reg_crosslets_info_write_export : out std_logic; -- export
+ reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_bf_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_block_validate_err_bf_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_bf_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_xst_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_block_validate_err_xst_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_xst_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_selector_clk_export : out std_logic; -- export
+ reg_dp_selector_read_export : out std_logic; -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_reset_export : out std_logic; -- export
+ reg_dp_selector_write_export : out std_logic; -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_shiftram_clk_export : out std_logic; -- export
+ reg_dp_shiftram_read_export : out std_logic; -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_shiftram_reset_export : out std_logic; -- export
+ reg_dp_shiftram_write_export : out std_logic; -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_xonoff_clk_export : out std_logic; -- export
+ reg_dp_xonoff_read_export : out std_logic; -- export
+ reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_reset_export : out std_logic; -- export
+ reg_dp_xonoff_write_export : out std_logic; -- export
+ reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_hdr_dat_clk_export : out std_logic; -- export
+ reg_hdr_dat_read_export : out std_logic; -- export
+ reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_reset_export : out std_logic; -- export
+ reg_hdr_dat_write_export : out std_logic; -- export
+ reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nof_crosslets_reset_export : out std_logic; -- export
+ reg_nof_crosslets_clk_export : out std_logic; -- export
+ reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nof_crosslets_write_export : out std_logic; -- export
+ reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nof_crosslets_read_export : out std_logic; -- export
+ reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
+ reg_nw_10gbe_mac_clk_export : out std_logic; -- export
+ reg_nw_10gbe_mac_read_export : out std_logic; -- export
+ reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_mac_reset_export : out std_logic; -- export
+ reg_nw_10gbe_mac_write_export : out std_logic; -- export
+ reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_info_reset_export : out std_logic; -- export
+ reg_ring_info_clk_export : out std_logic; -- export
+ reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_info_write_export : out std_logic; -- export
+ reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_info_read_export : out std_logic; -- export
+ reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_bf_reset_export : out std_logic; -- export
+ reg_ring_lane_info_bf_clk_export : out std_logic; -- export
+ reg_ring_lane_info_bf_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_lane_info_bf_write_export : out std_logic; -- export
+ reg_ring_lane_info_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_bf_read_export : out std_logic; -- export
+ reg_ring_lane_info_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_xst_reset_export : out std_logic; -- export
+ reg_ring_lane_info_xst_clk_export : out std_logic; -- export
+ reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_ring_lane_info_xst_write_export : out std_logic; -- export
+ reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_xst_read_export : out std_logic; -- export
+ reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_sdp_info_clk_export : out std_logic; -- export
+ reg_sdp_info_read_export : out std_logic; -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_reset_export : out std_logic; -- export
+ reg_sdp_info_write_export : out std_logic; -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_si_clk_export : out std_logic; -- export
+ reg_si_read_export : out std_logic; -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_si_reset_export : out std_logic; -- export
+ reg_si_write_export : out std_logic; -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_stat_enable_bst_clk_export : out std_logic; -- export
+ reg_stat_enable_bst_read_export : out std_logic; -- export
+ reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_bst_reset_export : out std_logic; -- export
+ reg_stat_enable_bst_write_export : out std_logic; -- export
+ reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_sst_clk_export : out std_logic; -- export
+ reg_stat_enable_sst_read_export : out std_logic; -- export
+ reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_sst_reset_export : out std_logic; -- export
+ reg_stat_enable_sst_write_export : out std_logic; -- export
+ reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_xst_clk_export : out std_logic; -- export
+ reg_stat_enable_xst_read_export : out std_logic; -- export
+ reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_xst_reset_export : out std_logic; -- export
+ reg_stat_enable_xst_write_export : out std_logic; -- export
+ reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_stat_hdr_dat_bst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_sst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_xst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_mac_reset_export : out std_logic; -- export
+ reg_tr_10gbe_mac_clk_export : out std_logic; -- export
+ reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0); -- export
+ reg_tr_10gbe_mac_write_export : out std_logic; -- export
+ reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_mac_read_export : out std_logic; -- export
+ reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_clk_export : out std_logic; -- export
+ reg_wg_read_export : out std_logic; -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_reset_export : out std_logic; -- export
+ reg_wg_write_export : out std_logic; -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bdo_destinations_reset_export : out std_logic; -- export
+ reg_bdo_destinations_clk_export : out std_logic; -- export
+ reg_bdo_destinations_address_export : out std_logic_vector(8 downto 0); -- export
+ reg_bdo_destinations_write_export : out std_logic; -- export
+ reg_bdo_destinations_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bdo_destinations_read_export : out std_logic; -- export
+ reg_bdo_destinations_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
);
end component qsys_lofar2_unb2c_sdp_station;
-
end qsys_lofar2_unb2c_sdp_station_pkg;
diff --git a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
index 3aebc0f87361b67dbb7c29fa4cd6e6d8e756efab..e10ec55d9f3bfcf729fe9bdc9bc2a382c15a9d29 100644
--- a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
+++ b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
@@ -194,23 +194,23 @@ peripherals:
peripheral_description: "SDP beamlet data output (BDO) destinations."
parameters:
# Parameters fixed in sdp_bdo_destinations_reg.vhd / sdp_pkg.vhd
- - { name: N_destinations_max, value: 32 }
+ - { name: N_bdo_destinations_max, value: 32 }
mm_ports:
# MM port for sdp_bdo_destinations_reg.vhd / mm_fields.vhd
- mm_port_name: REG_BDO_DESTINATIONS
mm_port_type: REG
- mm_port_span: 16 * MM_BUS_SIZE
+ mm_port_span: 256 * MM_BUS_SIZE # = ceil_pow2(132) * MM_BUS_SIZE
mm_port_description: |
"The SDP beamlets in a beamset can be send to 1 or multiple destinations, each identified
by destination MAC addess, IP address and UDP port.
- The number of destinations is 1 <= nof_destinations <= N_destinations_max. The actual
+ The number of destinations is 1 <= nof_destinations <= N_bdo_destinations_max. The actual
nof_destinations is reported via nof_destinations_act.
The actual number of blocks per packet depends on nof_destinations_act, and is reported
via nof_blocks_per_packet."
fields:
- - - { field_name: eth_destination_mac, number_of_fields: N_destinations_max, mm_width: 32, user_width: 48, radix: uint64, access_mode: RW, address_offset: 0x0 }
- - - { field_name: ip_destination_address, number_of_fields: N_destinations_max, mm_width: 32, access_mode: RW, address_offset: 0x100 }
- - - { field_name: udp_destination_port, number_of_fields: N_destinations_max, mm_width: 16, access_mode: RW, address_offset: 0x180 }
+ - - { field_name: eth_destination_mac, number_of_fields: N_bdo_destinations_max, mm_width: 32, user_width: 48, radix: uint64, access_mode: RW, address_offset: 0x0 }
+ - - { field_name: ip_destination_address, number_of_fields: N_bdo_destinations_max, mm_width: 32, access_mode: RW, address_offset: 0x100 }
+ - - { field_name: udp_destination_port, number_of_fields: N_bdo_destinations_max, mm_width: 16, access_mode: RW, address_offset: 0x180 }
- - { field_name: nof_destinations, mm_width: 8, access_mode: RW, address_offset: 0x200 } # = 512 = 128 * 4
- - { field_name: nof_destinations_act, mm_width: 8, access_mode: RO, address_offset: 0x204 } # = 516 = 129 * 4
- - { field_name: nof_destinations_max, mm_width: 8, access_mode: RO, address_offset: 0x208 } # = 520 = 130 * 4
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
index 16bba9218c6b21e76bb1aeacfc4dfa45e66fee83..bfdc7b5a694132d4a1999d9175097a2928b54974 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
@@ -67,24 +67,27 @@ entity node_sdp_beamformer is
mm_rst : in std_logic;
mm_clk : in std_logic;
- ram_ss_ss_wide_mosi : in t_mem_mosi := c_mem_mosi_rst;
- ram_ss_ss_wide_miso : out t_mem_miso;
- ram_bf_weights_mosi : in t_mem_mosi := c_mem_mosi_rst;
- ram_bf_weights_miso : out t_mem_miso;
- reg_bf_scale_mosi : in t_mem_mosi := c_mem_mosi_rst;
- reg_bf_scale_miso : out t_mem_miso;
- reg_hdr_dat_mosi : in t_mem_mosi := c_mem_mosi_rst;
- reg_hdr_dat_miso : out t_mem_miso;
- reg_dp_xonoff_mosi : in t_mem_mosi := c_mem_mosi_rst;
- reg_dp_xonoff_miso : out t_mem_miso;
- ram_st_bst_mosi : in t_mem_mosi := c_mem_mosi_rst;
- ram_st_bst_miso : out t_mem_miso;
- reg_stat_enable_mosi : in t_mem_mosi := c_mem_mosi_rst;
- reg_stat_enable_miso : out t_mem_miso;
- reg_stat_hdr_dat_mosi : in t_mem_mosi := c_mem_mosi_rst;
- reg_stat_hdr_dat_miso : out t_mem_miso;
- reg_bsn_align_copi : in t_mem_copi := c_mem_copi_rst;
- reg_bsn_align_cipo : out t_mem_cipo;
+ ram_ss_ss_wide_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ ram_ss_ss_wide_miso : out t_mem_miso;
+ ram_bf_weights_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ ram_bf_weights_miso : out t_mem_miso;
+ reg_bf_scale_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ reg_bf_scale_miso : out t_mem_miso;
+ reg_hdr_dat_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ reg_hdr_dat_miso : out t_mem_miso;
+ reg_bdo_destinations_copi : in t_mem_copi := c_mem_mosi_rst;
+ reg_bdo_destinations_cipo : out t_mem_cipo;
+ reg_dp_xonoff_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_xonoff_miso : out t_mem_miso;
+ ram_st_bst_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ ram_st_bst_miso : out t_mem_miso;
+ reg_stat_enable_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ reg_stat_enable_miso : out t_mem_miso;
+ reg_stat_hdr_dat_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ reg_stat_hdr_dat_miso : out t_mem_miso;
+ reg_bsn_align_copi : in t_mem_copi := c_mem_copi_rst;
+ reg_bsn_align_cipo : out t_mem_cipo;
+
reg_bsn_monitor_v2_bsn_align_input_copi : in t_mem_copi := c_mem_copi_rst;
reg_bsn_monitor_v2_bsn_align_input_cipo : out t_mem_cipo;
reg_bsn_monitor_v2_bsn_align_output_copi : in t_mem_copi := c_mem_copi_rst;
@@ -93,6 +96,7 @@ entity node_sdp_beamformer is
reg_bsn_monitor_v2_bst_offload_cipo : out t_mem_cipo;
reg_bsn_monitor_v2_beamlet_output_copi : in t_mem_copi := c_mem_copi_rst;
reg_bsn_monitor_v2_beamlet_output_cipo : out t_mem_cipo;
+
sdp_info : in t_sdp_info;
ring_info : in t_ring_info;
gn_id : in std_logic_vector(c_sdp_W_gn_id - 1 downto 0);
@@ -280,10 +284,12 @@ begin
hdr_fields_out => bdo_hdr_fields_out,
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
- reg_dp_xonoff_miso => reg_dp_xonoff_miso
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_hdr_dat_miso,
+ reg_destinations_copi => reg_bdo_destinations_copi,
+ reg_destinations_cipo => reg_bdo_destinations_cipo,
+ reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
+ reg_dp_xonoff_miso => reg_dp_xonoff_miso
);
bf_udp_sosi <= mon_bf_udp_sosi;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_destinations_reg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_destinations_reg.vhd
index 8c5d010163da02bded46c30793f8c9a655ffdd0a..35d4a7135c9afaf6b2d618c5d91cfb62c7fa5c9d 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_destinations_reg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_destinations_reg.vhd
@@ -208,8 +208,15 @@ begin
u_mm_fields: entity mm_lib.mm_fields
generic map(
- g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
- g_field_arr => c_field_arr
+ -- With g_nof_destinations_max = 31 and mac_w = 48, ip_w = 32, udp_w = 16
+ -- the expected logic FF usage is 31 * (48 + 32 + 16) + 4 * 32 ~= 3104 FF.
+ -- Use g_cross_clock_domain false to save clock domain crossing logic,
+ -- which is about 2/3 of the total logic (~ 6200 FF). This is save,
+ -- because the reg fields are set well before they are used, so any meta
+ -- stability will have settled long before that.
+ g_cross_clock_domain => false,
+ g_use_slv_in_val => false, -- use false to save logic when always slv_in_val='1'
+ g_field_arr => c_field_arr
)
port map (
mm_clk => mm_clk,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
index f730e3020f1946aa6448e27340443a8283a005d9..32cf827e7379b943f1094e86295de43e4c543b05 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
@@ -63,10 +63,8 @@ entity sdp_beamformer_output is
reg_hdr_dat_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_hdr_dat_miso : out t_mem_miso;
-
reg_destinations_copi : in t_mem_copi := c_mem_mosi_rst;
reg_destinations_cipo : out t_mem_cipo;
-
reg_dp_xonoff_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_dp_xonoff_miso : out t_mem_miso;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 6f3894ec9faecd12895f013d5075b4a5860456b2..0d029deee5d363a8e1c703dd7712f237de227266 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -526,7 +526,7 @@ package sdp_pkg is
end record;
-----------------------------------------------------------------------------
- -- MM
+ -- MM: address width to fit span of number of 32b words
-----------------------------------------------------------------------------
-- BSN monitor V2 address width
constant c_sdp_reg_bsn_monitor_v2_addr_w : natural := ceil_Log2(7);
@@ -591,6 +591,8 @@ package sdp_pkg is
constant c_sdp_reg_bsn_monitor_v2_ring_tx_bf_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bsn_monitor_v2_addr_w;
constant c_sdp_reg_dp_block_validate_err_bf_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + 4;
constant c_sdp_reg_dp_block_validate_bsn_at_sync_bf_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + 2;
+ constant c_sdp_reg_bdo_destinations_info_w_one : natural := ceil_log2(256);
+ constant c_sdp_reg_bdo_destinations_info_w : natural := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bdo_destinations_info_w_one;
-- XSUB
constant c_sdp_crosslets_index_w : natural := ceil_log2(c_sdp_N_sub);
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index a40ee3c528fcc79c9be8e97a8172b2703f15834c..5cb70ece517fb1fadfc6b05c3e0b9eebfc1ac4bc 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -239,6 +239,8 @@ entity sdp_station is
-- Beamlet Data Output header fields
reg_hdr_dat_copi : in t_mem_copi := c_mem_copi_rst;
reg_hdr_dat_cipo : out t_mem_cipo := c_mem_cipo_rst;
+ reg_bdo_destinations_copi : in t_mem_copi := c_mem_mosi_rst;
+ reg_bdo_destinations_cipo : out t_mem_cipo := c_mem_cipo_rst;
-- Beamlet Data Output xonoff
reg_dp_xonoff_copi : in t_mem_copi := c_mem_copi_rst;
@@ -410,6 +412,7 @@ architecture str of sdp_station is
constant c_addr_w_ram_bf_weights : natural := ceil_log2(c_sdp_N_pol * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
constant c_addr_w_reg_bf_scale : natural := 1;
constant c_addr_w_reg_hdr_dat : natural := ceil_log2(field_nof_words(c_sdp_cep_hdr_field_arr, c_word_w));
+ constant c_addr_w_reg_bdo_destinations : natural := c_sdp_reg_bdo_destinations_info_w_one;
constant c_addr_w_reg_dp_xonoff : natural := 1;
constant c_addr_w_ram_st_bst : natural := ceil_log2(c_sdp_S_sub_bf * c_sdp_N_pol * (c_longword_sz / c_word_sz));
constant c_addr_w_reg_bsn_align_v2_bf : natural := ceil_log2(c_dual) + c_sdp_reg_bsn_align_v2_addr_w;
@@ -480,8 +483,10 @@ architecture str of sdp_station is
signal reg_bf_scale_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets - 1 downto 0) := (others => c_mem_cipo_rst);
-- Beamlet Data Output header fields
- signal reg_hdr_dat_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets - 1 downto 0) := (others => c_mem_copi_rst);
- signal reg_hdr_dat_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets - 1 downto 0) := (others => c_mem_cipo_rst);
+ signal reg_hdr_dat_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets - 1 downto 0) := (others => c_mem_copi_rst);
+ signal reg_hdr_dat_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets - 1 downto 0) := (others => c_mem_cipo_rst);
+ signal reg_bdo_destinations_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets - 1 downto 0) := (others => c_mem_copi_rst);
+ signal reg_bdo_destinations_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets - 1 downto 0) := (others => c_mem_cipo_rst);
-- Beamlet Data Output xonoff
signal reg_dp_xonoff_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets - 1 downto 0) := (others => c_mem_copi_rst);
@@ -944,6 +949,8 @@ begin
reg_bf_scale_miso => reg_bf_scale_cipo_arr(beamset_id),
reg_hdr_dat_mosi => reg_hdr_dat_copi_arr(beamset_id),
reg_hdr_dat_miso => reg_hdr_dat_cipo_arr(beamset_id),
+ reg_bdo_destinations_copi => reg_bdo_destinations_copi_arr(beamset_id),
+ reg_bdo_destinations_cipo => reg_bdo_destinations_cipo_arr(beamset_id),
reg_dp_xonoff_mosi => reg_dp_xonoff_copi_arr(beamset_id),
reg_dp_xonoff_miso => reg_dp_xonoff_cipo_arr(beamset_id),
ram_st_bst_mosi => ram_st_bst_copi_arr(beamset_id),
@@ -1039,6 +1046,18 @@ begin
miso_arr => reg_hdr_dat_cipo_arr
);
+ u_mem_mux_reg_bdo_destinations : entity common_lib.common_mem_mux
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bdo_destinations
+ )
+ port map (
+ mosi => reg_bdo_destinations_copi,
+ miso => reg_bdo_destinations_cipo,
+ mosi_arr => reg_bdo_destinations_copi_arr,
+ miso_arr => reg_bdo_destinations_cipo_arr
+ );
+
u_mem_mux_reg_dp_xonoff : entity common_lib.common_mem_mux
generic map (
g_nof_mosi => c_sdp_N_beamsets,
diff --git a/applications/lofar2/model/readme_lofar2_model.txt b/applications/lofar2/model/readme_lofar2_model.txt
index 64336e1a03de1719fe2a296e49ec6439550abac4..225f03e057f39ee2e1c787ecf63b18aeb7bb7857 100644
--- a/applications/lofar2/model/readme_lofar2_model.txt
+++ b/applications/lofar2/model/readme_lofar2_model.txt
@@ -5,7 +5,8 @@ Contents:
1) Original LOFAR1 scripts from FilterTaskForce.zip [1]
2) Original LOFAR1 documents
3) Copied from APERTIF [3]
-4) LOFAR2.0
+4) LOFAR2.0 PFB in VHDL
+5) LOFAR2.0 Python notebooks for quantization and statistics
References:
@@ -27,7 +28,7 @@ References:
coefficients is not available anymore (For Apertif Erko looked in old
repositories back to 2005 of Lofar software and Station firmware
but could not find it.)
-
+
- pfs_coeff_final.m [1]
creates Coefficient_16KKaiser.dat, but using e.g. meld shows that
these do differ slightly within +-40 from
@@ -58,7 +59,20 @@ APERTIF uses the same PFB FIR coefficients as LOFAR1.
time and frequency domain, and optionally calls pfir_coeff_dc_adjust.m
+4) LOFAR2.0 PFB in VHDL
+
+- tb_tb_verify_pfb_wg.vhd, 2021 [4] : VHDL simulation of LOFAR1 PFB2 (pfb2_unit.vhd) and APERTIF WPFB
+ (wpfb_unit_dev.vhd) for LOFAR2.0
+
+
+5) LOFAR2.0 Python notebooks for quantization and statistics
+
+- lofar2_station_sdp_firmware_model.ipynb: SDP FW quantization levels
+- signal_statistics.ipynb: SNR improvement for beamformer, correlator and powers
-4) LOFAR2.0
+The notebook results are used in [1]. Start Jupyter notebook kernel with:
+> jupyter-notebook &
+and then navigate to the notebook script in the browser and open it.
+The results of the ipynb runs are stored as html files with the same name.
-- tb_tb_verify_pfb_wg.vhd, 2021 [4] : VHDL simulation of LOFAR1 PFB2 and APERTIF WPFB for LOFAR2.0
+[1] "L4 SDPFW Decision: LOFAR2.0 SDP Firmware Quantization Model", https://support.astron.nl/confluence/pages/viewpage.action?spaceKey=L2M&title=L4+SDPFW+Decision%3A+LOFAR2.0+SDP+Firmware+Quantization+Model
diff --git a/doc/erko_howto_tools.txt b/doc/erko_howto_tools.txt
index 63780a01fe679b928b4076062cbfea2b0652b842..e7717922ebdce05feea4252b44241e3b836e8f59 100755
--- a/doc/erko_howto_tools.txt
+++ b/doc/erko_howto_tools.txt
@@ -32,6 +32,7 @@
* Drawio
* DTS-lab unb2c
* Flake8, black
+* MATLAB
@@ -1471,6 +1472,10 @@ https://www.dataquest.io/blog/advanced-jupyter-notebooks-tutorial/
uses Markdown
+Start Jupyter notebook kernel for LOFAR2 quantization and statistics models with:
+> jupyter-notebook &
+and then navigate to the notebook script in the browser and open it.
+
Startup with:
> jupyter-lab # lab is new,
@@ -1613,3 +1618,19 @@ export PATH=~/.local/bin:$PATH
# run flake8 in dir, to check all py files in that dir and below
> flake8
+
+
+*******************************************************************************
+* MATLAB
+*******************************************************************************
+
+Can't reload '/usr/loca​l/MATLAB/R​2018a/bin/​glnxa64/libmwcoder_types.so'
+
+FIx:
+
+> ll /usr/local/MATLAB/R2018a/bin/glnxa64/
+> sudo mkdir /usr/local/MATLAB/R2018a/bin/glnxa64/exclude
+> cd /usr/local/MATLAB/R2018a/bin/glnxa64/
+> sudo mv libmwcoder_types.so exclude/
+
+restart matlab
diff --git a/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/compile_ip.tcl b/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..f161025c11587c25930a82124daf46b42d42cdfb
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/compile_ip.tcl
@@ -0,0 +1,40 @@
+# ------------------------------------------------------------------------------
+#
+# Copyright 2023
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# ------------------------------------------------------------------------------
+#
+# Author: D.F. Brouwer
+# Description:
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_complex_mult/sim"
+
+vmap altmult_complex_1910 ./work/
+
+ vcom "$IP_DIR/../altmult_complex_1910/sim/ip_agi027_xxxx_complex_mult_altmult_complex_1910_mvkwxpy.vhd" -work altmult_complex_1910
+
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_complex_mult_27b/sim"
+
+ vcom "$IP_DIR/../altmult_complex_1910/sim/ip_agi027_xxxx_complex_mult_27b_altmult_complex_1910_fuab2ya.vhd" -work altmult_complex_1910
diff --git a/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..0cf2e102e6c8b637e39ed0bee55eab956528598a
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_agi027_xxxx_altmult_complex_1910
+hdl_library_clause_name = altmult_complex_1910
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_agi027_xxxx
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $HDL_WORK/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/liborder.txt b/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/liborder.txt
new file mode 100644
index 0000000000000000000000000000000000000000..404094477eaadc47132663a8e9349ffcb66561f9
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/liborder.txt
@@ -0,0 +1,3 @@
+common: n_libs=9 lib_order=['technology', 'ip_agi027_xxxx_ram', 'tech_memory', 'ip_agi027_xxxx_fifo', 'tech_fifo', 'ip_agi027_xxxx_ddio', 'tech_iobuf', 'tst', 'common']
+
+New test order: []
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult/README.txt b/libraries/technology/ip_agi027_xxxx/complex_mult/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..a2afb13ea0e244df9b2ac0b9c724e50231fd2126
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/complex_mult/README.txt
@@ -0,0 +1,62 @@
+README.txt for $HDL_WORK/libraries/technology/ip_agi027_xxxx/complex_mult
+
+1) Porting
+2) IP component
+3) Compilation, simulation and verification
+4) Synthesis
+5) Remarks
+
+
+1) Porting
+
+The complex_mult IP was ported manually from Quartus v19.4 for Arria10_e2sg to Quartus 23.2 for Agi027_xxxx by creating it in Quartus (Qsys) using
+the same parameter settings.
+
+
+2) IP component
+
+The generated IPs are not kept in git repository, only the ip source files:
+
+ ip_agi027_xxxx_complex_mult.ip
+ ip_agi027_xxxx_complex_mult_27b.ip
+
+Therefore first the IP needs to be generated using:
+
+ generate_ip_libs iwave
+
+
+3) Compilation, simulation and verification
+
+The generated IP also contains a msim_setup.tcl file that was used to manually create:
+
+ compile_ip.tcl
+
+This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code.
+
+
+4) Synthesis
+
+No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
+
+ ip_agi027_xxxx_complex_mult.qip
+ ip_agi027_xxxx_complex_mult_27b.qip
+
+is included in the hdllib.cfg and contains what is needed to synthesize the IP.
+
+
+5) Remarks
+
+a) Use generated IP specific library clause name and IP specific lib uses sim
+
+ The generated ip_agi027_xxxx_<lib_name>.vhd uses an IP specific library name. Therefore the hdllib.cfg uses the IP
+ specific library as library clause name and, in addition, uses lib uses sim to make it known:
+
+ hdl_lib_name = ip_agi027_xxxx_<lib_name>
+ hdl_library_clause_name = ip_agi027_xxxx_<lib_name>_<ip_specific>
+ hdl_lib_uses_sim = ip_agi027_xxxx_<ip_specific>
+
+b) When multiple IPs are generated, each utilizing the same IP function but with different settings, it results in the generation of the same
+ library name, containing a different .vhd file, as opposed to the previously used unique library names. This leads to issues. To address
+ this, shared libraries are combined within a single library with the IP-specific library name in the build directory when 'generate_ip_libs'
+ is used. Therefore, a directory is manually created in 'altera_libraries' with the IP-specific library name, containing three files:
+ 'compile_ip.tcl', 'hdllib.cfg' and 'liborder'.
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult/compile_ip.tcl b/libraries/technology/ip_agi027_xxxx/complex_mult/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..dd0ade513a25242deaf1c05d565ea6ac319da0bd
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/complex_mult/compile_ip.tcl
@@ -0,0 +1,37 @@
+# ------------------------------------------------------------------------------
+#
+# Copyright 2023
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# ------------------------------------------------------------------------------
+#
+# Author: D.F. Brouwer
+# Description:
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_complex_mult/sim"
+ vcom "$IP_DIR/ip_agi027_xxxx_complex_mult.vhd"
+
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_complex_mult_27b/sim"
+ vcom "$IP_DIR/ip_agi027_xxxx_complex_mult_27b.vhd"
+
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/complex_mult/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..abeabd8feafd1d4a4ec05e31afc3843523377c24
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/complex_mult/hdllib.cfg
@@ -0,0 +1,25 @@
+hdl_lib_name = ip_agi027_xxxx_complex_mult
+hdl_library_clause_name = ip_agi027_xxxx_complex_mult_altmult_complex_1910
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_agi027_xxxx_altmult_complex_1910
+hdl_lib_technology = ip_agi027_xxxx
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $HDL_WORK/libraries/technology/ip_agi027_xxxx/complex_mult/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_xxxx_complex_mult/ip_agi027_xxxx_complex_mult.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_xxxx_complex_mult_27b/ip_agi027_xxxx_complex_mult_27b.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_agi027_xxxx_complex_mult.ip
+ ip_agi027_xxxx_complex_mult_27b.ip
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult/ip_agi027_xxxx_complex_mult.ip b/libraries/technology/ip_agi027_xxxx/complex_mult/ip_agi027_xxxx_complex_mult.ip
new file mode 100644
index 0000000000000000000000000000000000000000..3d685fe000c22b63e4cd32b7088ca86eba7b8850
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/complex_mult/ip_agi027_xxxx_complex_mult.ip
@@ -0,0 +1,769 @@
+<?xml version="1.0" ?>
+<!--Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.-->
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_complex_mult</ipxact:library>
+ <ipxact:name>altmult_complex_0</ipxact:name>
+ <ipxact:version>19.1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>dataa_real</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataa_real</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>dataa_real</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>dataa_imag</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataa_imag</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>dataa_imag</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>datab_real</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datab_real</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>datab_real</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>datab_imag</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datab_imag</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>datab_imag</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>result_real</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>result_real</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>result_real</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>output</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>result_imag</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>result_imag</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>result_imag</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>output</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clock</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="clock" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="clock" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>clock</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>aclr</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="reset" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="reset" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>aclr</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>clock</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>ena</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>ena</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>ena</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>altmult_complex</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>dataa_real</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>dataa_imag</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>datab_real</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>datab_imag</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>result_real</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>35</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>result_imag</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>35</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>clock</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>aclr</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>ena</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_complex_mult</ipxact:library>
+ <ipxact:name>altmult_complex</ipxact:name>
+ <ipxact:version>19.1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="DEVICE_FAMILY" type="string">
+ <ipxact:name>DEVICE_FAMILY</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="CBX_AUTO_BLACKBOX" type="string">
+ <ipxact:name>CBX_AUTO_BLACKBOX</ipxact:name>
+ <ipxact:displayName>CBX_AUTO_BLACKBOX</ipxact:displayName>
+ <ipxact:value>ALL</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="WIDTH_A" type="int">
+ <ipxact:name>WIDTH_A</ipxact:name>
+ <ipxact:displayName>How wide should the A input buses be?</ipxact:displayName>
+ <ipxact:value>18</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="WIDTH_B" type="int">
+ <ipxact:name>WIDTH_B</ipxact:name>
+ <ipxact:displayName>How wide should the B input buses be?</ipxact:displayName>
+ <ipxact:value>18</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="WIDTH_RESULT" type="int">
+ <ipxact:name>WIDTH_RESULT</ipxact:name>
+ <ipxact:displayName>How wide should the 'result' output bus be?</ipxact:displayName>
+ <ipxact:value>36</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="REPRESENTATION_A" type="int">
+ <ipxact:name>REPRESENTATION_A</ipxact:name>
+ <ipxact:displayName>What is the representation format for A inputs?</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="REPRESENTATION_B" type="int">
+ <ipxact:name>REPRESENTATION_B</ipxact:name>
+ <ipxact:displayName>What is the representation format for B inputs?</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_DYNAMIC_COMPLEX" type="bit">
+ <ipxact:name>GUI_DYNAMIC_COMPLEX</ipxact:name>
+ <ipxact:displayName>Dynamic Complex Mode</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="IMPLEMENTATION_STYLE" type="string">
+ <ipxact:name>IMPLEMENTATION_STYLE</ipxact:name>
+ <ipxact:displayName>Which implementation style should be used?</ipxact:displayName>
+ <ipxact:value>AUTO</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="PIPELINE" type="int">
+ <ipxact:name>PIPELINE</ipxact:name>
+ <ipxact:displayName>Output latency</ipxact:displayName>
+ <ipxact:value>3</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLEAR_TYPE" type="string">
+ <ipxact:name>GUI_CLEAR_TYPE</ipxact:name>
+ <ipxact:displayName>Clear Signal Type</ipxact:displayName>
+ <ipxact:value>ACLR</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_USE_CLKEN" type="bit">
+ <ipxact:name>GUI_USE_CLKEN</ipxact:name>
+ <ipxact:displayName>Create a Clock Enable input?</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="board" type="string">
+ <ipxact:name>board</ipxact:name>
+ <ipxact:displayName>Board</ipxact:displayName>
+ <ipxact:value>default</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>AGIB027R31A1I1VB</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element altmult_complex_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="aclr" altera:internal="altmult_complex_0.aclr" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="aclr" altera:internal="aclr"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clock" altera:internal="altmult_complex_0.clock" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="clock" altera:internal="clock"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="dataa_imag" altera:internal="altmult_complex_0.dataa_imag" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="dataa_imag" altera:internal="dataa_imag"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="dataa_real" altera:internal="altmult_complex_0.dataa_real" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="dataa_real" altera:internal="dataa_real"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="datab_imag" altera:internal="altmult_complex_0.datab_imag" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="datab_imag" altera:internal="datab_imag"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="datab_real" altera:internal="altmult_complex_0.datab_real" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="datab_real" altera:internal="datab_real"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="ena" altera:internal="altmult_complex_0.ena" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="ena" altera:internal="ena"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="result_imag" altera:internal="altmult_complex_0.result_imag" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="result_imag" altera:internal="result_imag"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="result_real" altera:internal="altmult_complex_0.result_real" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="result_real" altera:internal="result_real"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult/ip_agi027_xxxx_complex_mult_27b.ip b/libraries/technology/ip_agi027_xxxx/complex_mult/ip_agi027_xxxx_complex_mult_27b.ip
new file mode 100644
index 0000000000000000000000000000000000000000..e14c33f7db0df2922c66e5326649b668fc90de1e
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/complex_mult/ip_agi027_xxxx_complex_mult_27b.ip
@@ -0,0 +1,769 @@
+<?xml version="1.0" ?>
+<!--Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.-->
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_complex_mult_27b</ipxact:library>
+ <ipxact:name>altmult_complex_0</ipxact:name>
+ <ipxact:version>19.1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>dataa_real</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataa_real</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>dataa_real</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>dataa_imag</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataa_imag</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>dataa_imag</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>datab_real</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datab_real</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>datab_real</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>datab_imag</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datab_imag</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>datab_imag</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>result_real</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>result_real</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>result_real</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>output</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>result_imag</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>result_imag</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>result_imag</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>output</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clock</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="clock" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="clock" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>clock</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>aclr</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="reset" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="reset" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>aclr</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>clock</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>ena</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>ena</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>ena</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>altmult_complex</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>dataa_real</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>26</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>dataa_imag</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>26</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>datab_real</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>26</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>datab_imag</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>26</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>result_real</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>53</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>result_imag</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>53</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>clock</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>aclr</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>ena</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_complex_mult_27b</ipxact:library>
+ <ipxact:name>altmult_complex</ipxact:name>
+ <ipxact:version>19.1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="DEVICE_FAMILY" type="string">
+ <ipxact:name>DEVICE_FAMILY</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="CBX_AUTO_BLACKBOX" type="string">
+ <ipxact:name>CBX_AUTO_BLACKBOX</ipxact:name>
+ <ipxact:displayName>CBX_AUTO_BLACKBOX</ipxact:displayName>
+ <ipxact:value>ALL</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="WIDTH_A" type="int">
+ <ipxact:name>WIDTH_A</ipxact:name>
+ <ipxact:displayName>How wide should the A input buses be?</ipxact:displayName>
+ <ipxact:value>27</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="WIDTH_B" type="int">
+ <ipxact:name>WIDTH_B</ipxact:name>
+ <ipxact:displayName>How wide should the B input buses be?</ipxact:displayName>
+ <ipxact:value>27</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="WIDTH_RESULT" type="int">
+ <ipxact:name>WIDTH_RESULT</ipxact:name>
+ <ipxact:displayName>How wide should the 'result' output bus be?</ipxact:displayName>
+ <ipxact:value>54</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="REPRESENTATION_A" type="int">
+ <ipxact:name>REPRESENTATION_A</ipxact:name>
+ <ipxact:displayName>What is the representation format for A inputs?</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="REPRESENTATION_B" type="int">
+ <ipxact:name>REPRESENTATION_B</ipxact:name>
+ <ipxact:displayName>What is the representation format for B inputs?</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_DYNAMIC_COMPLEX" type="bit">
+ <ipxact:name>GUI_DYNAMIC_COMPLEX</ipxact:name>
+ <ipxact:displayName>Dynamic Complex Mode</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="IMPLEMENTATION_STYLE" type="string">
+ <ipxact:name>IMPLEMENTATION_STYLE</ipxact:name>
+ <ipxact:displayName>Which implementation style should be used?</ipxact:displayName>
+ <ipxact:value>AUTO</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="PIPELINE" type="int">
+ <ipxact:name>PIPELINE</ipxact:name>
+ <ipxact:displayName>Output latency</ipxact:displayName>
+ <ipxact:value>3</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLEAR_TYPE" type="string">
+ <ipxact:name>GUI_CLEAR_TYPE</ipxact:name>
+ <ipxact:displayName>Clear Signal Type</ipxact:displayName>
+ <ipxact:value>ACLR</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_USE_CLKEN" type="bit">
+ <ipxact:name>GUI_USE_CLKEN</ipxact:name>
+ <ipxact:displayName>Create a Clock Enable input?</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="board" type="string">
+ <ipxact:name>board</ipxact:name>
+ <ipxact:displayName>Board</ipxact:displayName>
+ <ipxact:value>default</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>AGIB027R31A1I1VB</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element altmult_complex_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="aclr" altera:internal="altmult_complex_0.aclr" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="aclr" altera:internal="aclr"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clock" altera:internal="altmult_complex_0.clock" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="clock" altera:internal="clock"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="dataa_imag" altera:internal="altmult_complex_0.dataa_imag" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="dataa_imag" altera:internal="dataa_imag"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="dataa_real" altera:internal="altmult_complex_0.dataa_real" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="dataa_real" altera:internal="dataa_real"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="datab_imag" altera:internal="altmult_complex_0.datab_imag" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="datab_imag" altera:internal="datab_imag"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="datab_real" altera:internal="altmult_complex_0.datab_real" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="datab_real" altera:internal="datab_real"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="ena" altera:internal="altmult_complex_0.ena" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="ena" altera:internal="ena"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="result_imag" altera:internal="altmult_complex_0.result_imag" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="result_imag" altera:internal="result_imag"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="result_real" altera:internal="altmult_complex_0.result_real" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="result_real" altera:internal="result_real"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult_rtl/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/complex_mult_rtl/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..93f2eb999ce93259e77d464a2dc33236911739ef
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/complex_mult_rtl/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_agi027_xxxx_complex_mult_rtl
+hdl_library_clause_name = ip_agi027_xxxx_complex_mult_rtl_lib
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = #Similar to the complex_mult_rtl hdllib of arria10_e1sg, e2sg, e3sge3
+
+synth_files =
+ ip_agi027_xxxx_complex_mult_rtl.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult_rtl/ip_agi027_xxxx_complex_mult_rtl.vhd b/libraries/technology/ip_agi027_xxxx/complex_mult_rtl/ip_agi027_xxxx_complex_mult_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..21af4e3cbe536a207cf2359159eabbb0b7ebd85a
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/complex_mult_rtl/ip_agi027_xxxx_complex_mult_rtl.vhd
@@ -0,0 +1,258 @@
+-- --------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -------------------------------------------------------------------------
+--
+-- Author : D.F. Brouwer
+-- Reference:
+-- Copied from */technology/ip_arria10/complex_mult_rtl/ip_arria10_complex_mult_rtl.vhd.
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--
+-- Function: Signed complex multiply
+-- p = a * b when g_conjugate_b = FALSE
+-- = (ar + j ai) * (br + j bi)
+-- = ar*br - ai*bi + j ( ar*bi + ai*br)
+--
+-- p = a * conj(b) when g_conjugate_b = TRUE
+-- = (ar + j ai) * (br - j bi)
+-- = ar*br + ai*bi + j (-ar*bi + ai*br)
+--
+-- Architectures:
+-- . rtl : uses RTL to have all registers in one clocked process
+--
+
+entity ip_agi027_xxxx_complex_mult_rtl is
+ generic (
+ g_in_a_w : positive;
+ g_in_b_w : positive;
+ g_out_p_w : positive; -- default use g_out_p_w = g_in_a_w+g_in_b_w = c_prod_w
+ g_conjugate_b : boolean := false;
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 0; -- 0 or 1
+ g_pipeline_adder : natural := 1; -- 0 or 1
+ g_pipeline_output : natural := 1 -- >= 0
+ );
+ port (
+ rst : in std_logic := '0';
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_ar : in std_logic_vector(g_in_a_w - 1 downto 0);
+ in_ai : in std_logic_vector(g_in_a_w - 1 downto 0);
+ in_br : in std_logic_vector(g_in_b_w - 1 downto 0);
+ in_bi : in std_logic_vector(g_in_b_w - 1 downto 0);
+ result_re : out std_logic_vector(g_out_p_w - 1 downto 0);
+ result_im : out std_logic_vector(g_out_p_w - 1 downto 0)
+ );
+end ip_agi027_xxxx_complex_mult_rtl;
+
+architecture str of ip_agi027_xxxx_complex_mult_rtl is
+ function RESIZE_NUM(s : signed; w : natural) return signed is
+ begin
+ -- extend sign bit or keep LS part
+ if w > s'length then
+ return resize(s, w); -- extend sign bit
+ else
+ return signed(resize(unsigned(s), w)); -- keep LSbits (= vec[w-1:0])
+ end if;
+ end;
+
+ constant c_prod_w : natural := g_in_a_w + g_in_b_w;
+ constant c_sum_w : natural := c_prod_w + 1;
+
+-- CONSTANT c_re_add_sub : STRING := sel_a_b(g_conjugate_b, "ADD", "SUB");
+-- CONSTANT c_im_add_sub : STRING := sel_a_b(g_conjugate_b, "SUB", "ADD");
+
+ -- registers
+ signal reg_ar : signed(g_in_a_w - 1 downto 0);
+ signal reg_ai : signed(g_in_a_w - 1 downto 0);
+ signal reg_br : signed(g_in_b_w - 1 downto 0);
+ signal reg_bi : signed(g_in_b_w - 1 downto 0);
+ signal reg_prod_ar_br : signed(c_prod_w - 1 downto 0); -- re
+ signal reg_prod_ai_bi : signed(c_prod_w - 1 downto 0);
+ signal reg_prod_ai_br : signed(c_prod_w - 1 downto 0); -- im
+ signal reg_prod_ar_bi : signed(c_prod_w - 1 downto 0);
+ signal reg_sum_re : signed(c_sum_w - 1 downto 0);
+ signal reg_sum_im : signed(c_sum_w - 1 downto 0);
+ signal reg_result_re : signed(g_out_p_w - 1 downto 0);
+ signal reg_result_im : signed(g_out_p_w - 1 downto 0);
+
+ -- combinatorial
+ signal nxt_ar : signed(g_in_a_w - 1 downto 0);
+ signal nxt_ai : signed(g_in_a_w - 1 downto 0);
+ signal nxt_br : signed(g_in_b_w - 1 downto 0);
+ signal nxt_bi : signed(g_in_b_w - 1 downto 0);
+ signal nxt_prod_ar_br : signed(c_prod_w - 1 downto 0); -- re
+ signal nxt_prod_ai_bi : signed(c_prod_w - 1 downto 0);
+ signal nxt_prod_ai_br : signed(c_prod_w - 1 downto 0); -- im
+ signal nxt_prod_ar_bi : signed(c_prod_w - 1 downto 0);
+ signal nxt_sum_re : signed(c_sum_w - 1 downto 0);
+ signal nxt_sum_im : signed(c_sum_w - 1 downto 0);
+ signal nxt_result_re : signed(g_out_p_w - 1 downto 0);
+ signal nxt_result_im : signed(g_out_p_w - 1 downto 0);
+
+ -- the active signals
+ signal ar : signed(g_in_a_w - 1 downto 0);
+ signal ai : signed(g_in_a_w - 1 downto 0);
+ signal br : signed(g_in_b_w - 1 downto 0);
+ signal bi : signed(g_in_b_w - 1 downto 0);
+ signal prod_ar_br : signed(c_prod_w - 1 downto 0); -- re
+ signal prod_ai_bi : signed(c_prod_w - 1 downto 0);
+ signal prod_ai_br : signed(c_prod_w - 1 downto 0); -- im
+ signal prod_ar_bi : signed(c_prod_w - 1 downto 0);
+ signal sum_re : signed(c_sum_w - 1 downto 0);
+ signal sum_im : signed(c_sum_w - 1 downto 0);
+begin
+ ------------------------------------------------------------------------------
+ -- Registers
+ ------------------------------------------------------------------------------
+
+ -- Put all potential registers in a single process for optimal DSP inferrence
+ -- Use rst only if it is supported by the DSP primitive, else leave it at '0'
+ p_reg : process (rst, clk)
+ begin
+ if rising_edge(clk) then
+ if rst = '1' then
+ reg_ar <= (others => '0');
+ reg_ai <= (others => '0');
+ reg_br <= (others => '0');
+ reg_bi <= (others => '0');
+ reg_prod_ar_br <= (others => '0');
+ reg_prod_ai_bi <= (others => '0');
+ reg_prod_ai_br <= (others => '0');
+ reg_prod_ar_bi <= (others => '0');
+ reg_sum_re <= (others => '0');
+ reg_sum_im <= (others => '0');
+ reg_result_re <= (others => '0');
+ reg_result_im <= (others => '0');
+ elsif clken = '1' then
+ reg_ar <= nxt_ar; -- inputs
+ reg_ai <= nxt_ai;
+ reg_br <= nxt_br;
+ reg_bi <= nxt_bi;
+ reg_prod_ar_br <= nxt_prod_ar_br; -- products for re
+ reg_prod_ai_bi <= nxt_prod_ai_bi;
+ reg_prod_ai_br <= nxt_prod_ai_br; -- products for im
+ reg_prod_ar_bi <= nxt_prod_ar_bi;
+ reg_sum_re <= nxt_sum_re; -- sum
+ reg_sum_im <= nxt_sum_im;
+ reg_result_re <= nxt_result_re; -- result sum after optional register stage
+ reg_result_im <= nxt_result_im;
+ end if;
+ end if;
+ end process;
+
+ ------------------------------------------------------------------------------
+ -- Inputs
+ ------------------------------------------------------------------------------
+
+ nxt_ar <= signed(in_ar);
+ nxt_ai <= signed(in_ai);
+ nxt_br <= signed(in_br);
+ nxt_bi <= signed(in_bi);
+
+ no_input_reg : if g_pipeline_input = 0 generate -- wired
+ ar <= nxt_ar;
+ ai <= nxt_ai;
+ br <= nxt_br;
+ bi <= nxt_bi;
+ end generate;
+
+ gen_input_reg : if g_pipeline_input > 0 generate -- register input
+ ar <= reg_ar;
+ ai <= reg_ai;
+ br <= reg_br;
+ bi <= reg_bi;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Products
+ ------------------------------------------------------------------------------
+
+ nxt_prod_ar_br <= ar * br; -- products for re
+ nxt_prod_ai_bi <= ai * bi;
+ nxt_prod_ai_br <= ai * br; -- products for im
+ nxt_prod_ar_bi <= ar * bi;
+
+ no_product_reg : if g_pipeline_product = 0 generate -- wired
+ prod_ar_br <= nxt_prod_ar_br;
+ prod_ai_bi <= nxt_prod_ai_bi;
+ prod_ai_br <= nxt_prod_ai_br;
+ prod_ar_bi <= nxt_prod_ar_bi;
+ end generate;
+ gen_product_reg : if g_pipeline_product > 0 generate -- register
+ prod_ar_br <= reg_prod_ar_br;
+ prod_ai_bi <= reg_prod_ai_bi;
+ prod_ai_br <= reg_prod_ai_br;
+ prod_ar_bi <= reg_prod_ar_bi;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Sum
+ ------------------------------------------------------------------------------
+
+ -- Re
+ -- . "ADD" for a*conj(b) : ar*br + ai*bi
+ -- . "SUB" for a*b : ar*br - ai*bi
+ gen_re_add : if g_conjugate_b generate
+ nxt_sum_re <= RESIZE_NUM(prod_ar_br, c_sum_w) + prod_ai_bi;
+ end generate;
+
+ gen_re_sub : if not g_conjugate_b generate
+ nxt_sum_re <= RESIZE_NUM(prod_ar_br, c_sum_w) - prod_ai_bi;
+ end generate;
+
+ -- Im
+ -- . "ADD" for a*b : ai*br + ar*bi
+ -- . "SUB" for a*conj(b) : ai*br - ar*bi
+ gen_im_add : if not g_conjugate_b generate
+ nxt_sum_im <= RESIZE_NUM(prod_ai_br, c_sum_w) + prod_ar_bi;
+ end generate;
+
+ gen_im_sub : if g_conjugate_b generate
+ nxt_sum_im <= RESIZE_NUM(prod_ai_br, c_sum_w) - prod_ar_bi;
+ end generate;
+
+ no_adder_reg : if g_pipeline_adder = 0 generate -- wired
+ sum_re <= nxt_sum_re;
+ sum_im <= nxt_sum_im;
+ end generate;
+ gen_adder_reg : if g_pipeline_adder > 0 generate -- register
+ sum_re <= reg_sum_re;
+ sum_im <= reg_sum_im;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Result sum after optional rounding
+ ------------------------------------------------------------------------------
+
+ nxt_result_re <= RESIZE_NUM(sum_re, g_out_p_w);
+ nxt_result_im <= RESIZE_NUM(sum_im, g_out_p_w);
+
+ no_result_reg : if g_pipeline_output = 0 generate -- wired
+ result_re <= std_logic_vector(nxt_result_re);
+ result_im <= std_logic_vector(nxt_result_im);
+ end generate;
+ gen_result_reg : if g_pipeline_output > 0 generate -- register
+ result_re <= std_logic_vector(reg_result_re);
+ result_im <= std_logic_vector(reg_result_im);
+ end generate;
+end architecture;
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult_rtl_canonical/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/complex_mult_rtl_canonical/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..62325a9ea818bfd48e4d3e9f2a54e7dd0ea7a906
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/complex_mult_rtl_canonical/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_agi027_xxxx_complex_mult_rtl_canonical
+hdl_library_clause_name = ip_agi027_xxxx_complex_mult_rtl_canonical_lib
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = #Similar to the complex_mult_rtl_canonical hdllib of arria10_e1sg, e2sg, e3sge3
+synth_files =
+ ip_agi027_xxxx_complex_mult_rtl_canonical.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult_rtl_canonical/ip_agi027_xxxx_complex_mult_rtl_canonical.vhd b/libraries/technology/ip_agi027_xxxx/complex_mult_rtl_canonical/ip_agi027_xxxx_complex_mult_rtl_canonical.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b5c614401604866a7d2b4d6f1af781eab36080f2
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/complex_mult_rtl_canonical/ip_agi027_xxxx_complex_mult_rtl_canonical.vhd
@@ -0,0 +1,270 @@
+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author :
+-- . D.F. Brouwer
+-- Purpose:
+-- . RTL complex multiplier, canonical version (3 simple multipliers).
+-- Description:
+-- . re = ((ar+ai)*(br-bi))+(ar*bi-ai*br)
+-- im = ar*bi+ai*br
+-- Remark:
+-- . g_conjugate_b is not supported!
+-- Reference:
+-- . Copied from */technology/ip_arria10/complex_mult_rtl_canonical/ip_arria10_complex_mult_rtl_canonical.vhd, authored by Daniel van der Schuur
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity ip_agi027_xxxx_complex_mult_rtl_canonical is
+ generic (
+ g_in_a_w : positive;
+ g_in_b_w : positive;
+ g_out_p_w : positive; -- default use g_out_p_w = g_in_a_w+g_in_b_w = c_prod_w
+-- g_conjugate_b : BOOLEAN := FALSE;
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 0; -- 0 or 1
+ g_pipeline_adder : natural := 1; -- 0 or 1
+ g_pipeline_output : natural := 1 -- >= 0
+ );
+ port (
+ rst : in std_logic := '0';
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_ar : in std_logic_vector(g_in_a_w - 1 downto 0);
+ in_ai : in std_logic_vector(g_in_a_w - 1 downto 0);
+ in_br : in std_logic_vector(g_in_b_w - 1 downto 0);
+ in_bi : in std_logic_vector(g_in_b_w - 1 downto 0);
+ result_re : out std_logic_vector(g_out_p_w - 1 downto 0);
+ result_im : out std_logic_vector(g_out_p_w - 1 downto 0)
+ );
+end ip_agi027_xxxx_complex_mult_rtl_canonical;
+
+architecture str of ip_agi027_xxxx_complex_mult_rtl_canonical is
+ function RESIZE_NUM(s : signed; w : natural) return signed is
+ begin
+ -- extend sign bit or keep LS part
+ if w > s'length then
+ return resize(s, w); -- extend sign bit
+ else
+ return signed(resize(unsigned(s), w)); -- keep LSbits (= vec[w-1:0])
+ end if;
+ end;
+
+ function largest(n, m : integer) return integer is
+ begin
+ if n > m then
+ return n;
+ else
+ return m;
+ end if;
+ end;
+
+ -----------------------------------------------------------------------------
+ -- Multiply / add output signals
+ -- . re = ((ar+ai)*(br-bi))+(ar*bi-ai*br)
+ -- im = ar*bi+ai*br
+ -----------------------------------------------------------------------------
+ constant c_sum_ar_ai_w : natural := g_in_a_w + 1; -- sum_ar_ai
+ constant c_sum_br_bi_w : natural := g_in_b_w + 1; -- sum_br_bi
+ constant c_prod_w : natural := g_in_a_w + g_in_b_w; -- prod_ar_bi, prod_ai_br
+ constant c_sum_prod_w : natural := c_prod_w + 1; -- sum_prod_ar_bi_prod_ai_br
+ constant c_prod_sum_w : natural := c_sum_ar_ai_w + c_sum_br_bi_w; -- prod_sum_ar_ai_sum_br_bi
+ constant c_sum_im_w : natural := c_prod_w + 1; -- sum_im
+ constant c_sum_re_w : natural := largest(c_sum_prod_w, c_prod_sum_w) + 1; -- sum_re
+
+ signal sum_ar_ai : signed(c_sum_ar_ai_w - 1 downto 0); -- ar+ai : used in re
+ signal sum_br_bi : signed(c_sum_br_bi_w - 1 downto 0); -- br-bi : used in re
+ signal sum_prod_ar_bi_prod_ai_br : signed(c_sum_prod_w - 1 downto 0); -- ar*bi-ai*br : used in re
+ signal sum_im : signed(c_sum_im_w - 1 downto 0); -- ar*bi+ai*br : im
+ signal sum_re : signed(c_sum_re_w - 1 downto 0); -- ((ar+ai)*(br-bi))+(ar*bi-ai*br) : re
+
+ signal prod_ar_bi : signed(c_prod_w - 1 downto 0); -- ar*bi : used in re and im
+ signal prod_ai_br : signed(c_prod_w - 1 downto 0); -- ai*br : used in re and im
+ signal prod_sum_ar_ai_sum_br_bi : signed(c_prod_sum_w - 1 downto 0); -- (ar+ai)*(br-bi) : used in re
+
+ -----------------------------------------------------------------------------
+ -- register signals
+ -----------------------------------------------------------------------------
+ signal ar : signed(g_in_a_w - 1 downto 0);
+ signal ai : signed(g_in_a_w - 1 downto 0);
+ signal br : signed(g_in_b_w - 1 downto 0);
+ signal bi : signed(g_in_b_w - 1 downto 0);
+
+ signal nxt_ar : signed(g_in_a_w - 1 downto 0);
+ signal nxt_ai : signed(g_in_a_w - 1 downto 0);
+ signal nxt_br : signed(g_in_b_w - 1 downto 0);
+ signal nxt_bi : signed(g_in_b_w - 1 downto 0);
+
+ signal reg_ar : signed(g_in_a_w - 1 downto 0);
+ signal reg_ai : signed(g_in_a_w - 1 downto 0);
+ signal reg_br : signed(g_in_b_w - 1 downto 0);
+ signal reg_bi : signed(g_in_b_w - 1 downto 0);
+
+ signal nxt_sum_ar_ai : signed(c_sum_ar_ai_w - 1 downto 0);
+ signal nxt_sum_br_bi : signed(c_sum_br_bi_w - 1 downto 0);
+ signal nxt_sum_prod_ar_bi_prod_ai_br : signed(c_sum_prod_w - 1 downto 0);
+ signal nxt_sum_im : signed(c_sum_im_w - 1 downto 0);
+ signal nxt_sum_re : signed(c_sum_re_w - 1 downto 0);
+
+ signal nxt_prod_ar_bi : signed(c_prod_w - 1 downto 0);
+ signal nxt_prod_ai_br : signed(c_prod_w - 1 downto 0);
+ signal nxt_prod_sum_ar_ai_sum_br_bi : signed(c_prod_sum_w - 1 downto 0);
+
+ signal reg_sum_ar_ai : signed(c_sum_ar_ai_w - 1 downto 0);
+ signal reg_sum_br_bi : signed(c_sum_br_bi_w - 1 downto 0);
+ signal reg_sum_prod_ar_bi_prod_ai_br : signed(c_sum_prod_w - 1 downto 0);
+ signal reg_sum_im : signed(c_sum_im_w - 1 downto 0);
+ signal reg_sum_re : signed(c_sum_re_w - 1 downto 0);
+
+ signal reg_prod_ar_bi : signed(c_prod_w - 1 downto 0);
+ signal reg_prod_ai_br : signed(c_prod_w - 1 downto 0);
+ signal reg_prod_sum_ar_ai_sum_br_bi : signed(c_prod_sum_w - 1 downto 0);
+
+ signal nxt_result_re : signed(g_out_p_w - 1 downto 0);
+ signal nxt_result_im : signed(g_out_p_w - 1 downto 0);
+
+ signal reg_result_re : signed(g_out_p_w - 1 downto 0);
+ signal reg_result_im : signed(g_out_p_w - 1 downto 0);
+begin
+ ------------------------------------------------------------------------------
+ -- Registers
+ ------------------------------------------------------------------------------
+
+ -- Put all potential registers in a single process for optimal DSP inferrence
+ -- Use rst only if it is supported by the DSP primitive, else leave it at '0'
+ p_reg : process (rst, clk)
+ begin
+ if rising_edge(clk) then
+ if rst = '1' then
+ reg_ar <= (others => '0');
+ reg_ai <= (others => '0');
+ reg_br <= (others => '0');
+ reg_bi <= (others => '0');
+
+ reg_sum_ar_ai <= (others => '0');
+ reg_sum_br_bi <= (others => '0');
+ reg_sum_prod_ar_bi_prod_ai_br <= (others => '0');
+ reg_sum_im <= (others => '0');
+ reg_sum_re <= (others => '0');
+
+ reg_prod_ar_bi <= (others => '0');
+ reg_prod_ai_br <= (others => '0');
+ reg_prod_sum_ar_ai_sum_br_bi <= (others => '0');
+ elsif clken = '1' then
+ reg_ar <= nxt_ar;
+ reg_ai <= nxt_ai;
+ reg_br <= nxt_br;
+ reg_bi <= nxt_bi;
+
+ reg_sum_ar_ai <= nxt_sum_ar_ai;
+ reg_sum_br_bi <= nxt_sum_br_bi;
+ reg_sum_prod_ar_bi_prod_ai_br <= nxt_sum_prod_ar_bi_prod_ai_br;
+ reg_sum_im <= nxt_sum_im;
+ reg_sum_re <= nxt_sum_re;
+
+ reg_prod_ar_bi <= nxt_prod_ar_bi;
+ reg_prod_ai_br <= nxt_prod_ai_br;
+ reg_prod_sum_ar_ai_sum_br_bi <= nxt_prod_sum_ar_ai_sum_br_bi;
+ end if;
+ end if;
+ end process;
+
+ ------------------------------------------------------------------------------
+ -- Inputs
+ ------------------------------------------------------------------------------
+ nxt_ar <= signed(in_ar);
+ nxt_ai <= signed(in_ai);
+ nxt_br <= signed(in_br);
+ nxt_bi <= signed(in_bi);
+
+ no_input_reg : if g_pipeline_input = 0 generate -- wired
+ ar <= nxt_ar;
+ ai <= nxt_ai;
+ br <= nxt_br;
+ bi <= nxt_bi;
+ end generate;
+
+ gen_input_reg : if g_pipeline_input > 0 generate -- register input
+ ar <= reg_ar;
+ ai <= reg_ai;
+ br <= reg_br;
+ bi <= reg_bi;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Sums
+ ------------------------------------------------------------------------------
+ nxt_sum_ar_ai <= RESIZE_NUM(ar, c_sum_ar_ai_w) + ai;
+ nxt_sum_br_bi <= RESIZE_NUM(br, c_sum_br_bi_w) + bi;
+ nxt_sum_prod_ar_bi_prod_ai_br <= RESIZE_NUM(prod_ar_bi, c_prod_sum_w) + prod_ai_br;
+ nxt_sum_re <= RESIZE_NUM(prod_sum_ar_ai_sum_br_bi, c_prod_sum_w), sum_prod_ar_bi_prod_ai_br;
+ nxt_sum_im <= RESIZE_NUM(prod_ai_br, c_sum_im_w) + prod_ar_bi;
+
+ no_adder_reg : if g_pipeline_adder = 0 generate -- wired
+ sum_ar_ai <= nxt_sum_ar_ai;
+ sum_br_bi <= nxt_sum_br_bi;
+ sum_prod_ar_bi_prod_ai_br <= nxt_sum_prod_ar_bi_prod_ai_br;
+ sum_re <= nxt_sum_re;
+ sum_im <= nxt_sum_im;
+ end generate;
+ gen_adder_reg : if g_pipeline_adder > 0 generate -- register
+ sum_ar_ai <= reg_sum_ar_ai;
+ sum_br_bi <= reg_sum_br_bi;
+ sum_prod_ar_bi_prod_ai_br <= reg_sum_prod_ar_bi_prod_ai_br;
+ sum_re <= reg_sum_re;
+ sum_im <= reg_sum_im;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Products
+ ------------------------------------------------------------------------------
+ nxt_prod_ar_bi <= ar * bi;
+ nxt_prod_ai_br <= ai * br;
+ nxt_prod_sum_ar_ai_sum_br_bi <= sum_ar_ai * sum_br_bi;
+
+ no_product_reg : if g_pipeline_product = 0 generate -- wired
+ prod_ar_bi <= nxt_prod_ar_bi;
+ prod_ai_br <= nxt_prod_ai_br;
+ prod_sum_ar_ai_sum_br_bi <= nxt_prod_sum_ar_ai_sum_br_bi;
+ end generate;
+ gen_product_reg : if g_pipeline_product > 0 generate -- register
+ prod_ar_bi <= reg_prod_ar_bi;
+ prod_ai_br <= reg_prod_ai_br;
+ prod_sum_ar_ai_sum_br_bi <= reg_prod_sum_ar_ai_sum_br_bi;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Result sum after optional rounding
+ ------------------------------------------------------------------------------
+
+ nxt_result_re <= RESIZE_NUM(sum_re, g_out_p_w);
+ nxt_result_im <= RESIZE_NUM(sum_im, g_out_p_w);
+
+ no_result_reg : if g_pipeline_output = 0 generate -- wired
+ result_re <= std_logic_vector(nxt_result_re);
+ result_im <= std_logic_vector(nxt_result_im);
+ end generate;
+ gen_result_reg : if g_pipeline_output > 0 generate -- register
+ result_re <= std_logic_vector(reg_result_re);
+ result_im <= std_logic_vector(reg_result_im);
+ end generate;
+end architecture;
diff --git a/libraries/technology/ip_agi027_xxxx/mult/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/mult/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..c3fee94e62efa14bd0d9dbda4e779bef03ec1338
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/mult/hdllib.cfg
@@ -0,0 +1,18 @@
+hdl_lib_name = ip_agi027_xxxx_mult
+hdl_library_clause_name = ip_agi027_xxxx_mult_lib
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = #Similar to the mult hdllib of arria10_e1sg, e2sg, e3sge3
+
+synth_files =
+ ip_agi027_xxxx_mult.vhd
+ ip_agi027_xxxx_mult_rtl.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_lpm_mult.ip b/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_lpm_mult.ip
new file mode 100644
index 0000000000000000000000000000000000000000..9572d6da95176a10e3750a013786484330bfd6ba
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_lpm_mult.ip
@@ -0,0 +1,523 @@
+<?xml version="1.0" ?>
+<!--Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.-->
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_lpm_mult</ipxact:library>
+ <ipxact:name>lpm_mult_0</ipxact:name>
+ <ipxact:version>19.2.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>dataa</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataa</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>dataa</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>result</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>result</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>result</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>output</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>datab</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datab</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>datab</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clock</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="clock" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="clock" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>clock</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clken</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clken</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>clken</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>lpm_mult</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>dataa</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>result</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>35</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>datab</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>clock</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>clken</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_lpm_mult</ipxact:library>
+ <ipxact:name>lpm_mult</ipxact:name>
+ <ipxact:version>19.2.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="DEVICE_FAMILY" type="string">
+ <ipxact:name>DEVICE_FAMILY</ipxact:name>
+ <ipxact:displayName>Device Family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_WIDTH_A" type="int">
+ <ipxact:name>GUI_WIDTH_A</ipxact:name>
+ <ipxact:displayName>Dataa width</ipxact:displayName>
+ <ipxact:value>18</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_WIDTH_B" type="int">
+ <ipxact:name>GUI_WIDTH_B</ipxact:name>
+ <ipxact:displayName>Datab width</ipxact:displayName>
+ <ipxact:value>18</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_WIDTH_P" type="int">
+ <ipxact:name>GUI_WIDTH_P</ipxact:name>
+ <ipxact:displayName>Value</ipxact:displayName>
+ <ipxact:value>36</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CONSTANT_B" type="int">
+ <ipxact:name>GUI_CONSTANT_B</ipxact:name>
+ <ipxact:displayName>Value</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_LATENCY" type="int">
+ <ipxact:name>GUI_LATENCY</ipxact:name>
+ <ipxact:displayName>Latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLEAR_TYPE" type="string">
+ <ipxact:name>GUI_CLEAR_TYPE</ipxact:name>
+ <ipxact:displayName>Clear Signal Type</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN" type="bit">
+ <ipxact:name>GUI_CLKEN</ipxact:name>
+ <ipxact:displayName>Create a 'clken' clock enable clock</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_USE_MULT" type="int">
+ <ipxact:name>GUI_USE_MULT</ipxact:name>
+ <ipxact:displayName>Type</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_AUTO_SIZE_RESULT" type="int">
+ <ipxact:name>GUI_AUTO_SIZE_RESULT</ipxact:name>
+ <ipxact:displayName>Type</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_B_IS_CONSTANT" type="int">
+ <ipxact:name>GUI_B_IS_CONSTANT</ipxact:name>
+ <ipxact:displayName>Does the 'datab' input bus have a constant value?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_SIGNED_MULT" type="int">
+ <ipxact:name>GUI_SIGNED_MULT</ipxact:name>
+ <ipxact:displayName>Which type of multiplication do you want?</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_IMPLEMENTATION" type="int">
+ <ipxact:name>GUI_IMPLEMENTATION</ipxact:name>
+ <ipxact:displayName>Which multiplier implementation should be used?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_PIPELINE" type="int">
+ <ipxact:name>GUI_PIPELINE</ipxact:name>
+ <ipxact:displayName>Pipeline</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_OPTIMIZE" type="int">
+ <ipxact:name>GUI_OPTIMIZE</ipxact:name>
+ <ipxact:displayName>Type</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="board" type="string">
+ <ipxact:name>board</ipxact:name>
+ <ipxact:displayName>Board</ipxact:displayName>
+ <ipxact:value>default</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>AGIB027R31A1I1VB</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element lpm_mult_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="clken" altera:internal="lpm_mult_0.clken" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="clken" altera:internal="clken"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clock" altera:internal="lpm_mult_0.clock" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="clock" altera:internal="clock"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="dataa" altera:internal="lpm_mult_0.dataa" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="dataa" altera:internal="dataa"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="datab" altera:internal="lpm_mult_0.datab" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="datab" altera:internal="datab"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="result" altera:internal="lpm_mult_0.result" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="result" altera:internal="result"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_mult.vhd b/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_mult.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..57521504991262d3080b830b266a0c50db9ec394
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_mult.vhd
@@ -0,0 +1,122 @@
+-- --------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -------------------------------------------------------------------------
+--
+-- Author : D.F. Brouwer
+-- Purpose:
+-- RadioHDL wrapper / Instantiate MULTiplier IP with generics
+-- Reference:
+-- Copied from */technology/ip_arria10/mult/ip_arria10_mult.vhd and add component declaration lpm_mult from
+-- generated/lpm_mult_1920/sim/ip_agi027_xxxx_lpm_mult_lpm_mult_1920_sphm57q.vhd
+-- Remark:
+-- Directly instantiate LPM component.
+-- The Agilex 7 (agi027_xxxx) supports the lpm library, so the copied file can be reused.
+-- This is checked by making the IP files on the basis of the generic and port of the entity, and also the generic and port map.
+-- The IP file will also remain present in the folder, so that the settings can be reproduced later.
+
+library IEEE;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library lpm;
+use lpm.lpm_components.all;
+
+ entity ip_agi027_xxxx_mult is
+ generic (
+ g_in_a_w : positive := 18; -- Width of the data A port
+ g_in_b_w : positive := 18; -- Width of the data B port
+ g_out_p_w : positive := 36; -- Width of the result port
+-- g_out_s_w : POSITIVE := 1; -- Width of the sum port (not used in current designs)
+ g_nof_mult : positive := 1; -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 1; -- 0 or 1
+ g_pipeline_output : natural := 1; -- >= 0
+ g_representation : string := "SIGNED" -- or "UNSIGNED"
+ );
+ port (
+ clk : in std_logic;
+ clken : in std_logic := '1';
+-- aclr : IN STD_LOGIC := '0'; (not used in current designs)
+ in_a : in std_logic_vector(g_nof_mult * g_in_a_w - 1 downto 0);
+ in_b : in std_logic_vector(g_nof_mult * g_in_b_w - 1 downto 0);
+-- sum : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_s_w-1 DOWNTO 0) := (OTHERS => '0'); (not used in current designs)
+ out_p : out std_logic_vector(g_nof_mult * (g_in_a_w + g_in_b_w) - 1 downto 0)
+ );
+ end ip_agi027_xxxx_mult;
+
+architecture str of ip_agi027_xxxx_mult is
+ constant c_pipeline : natural := g_pipeline_input + g_pipeline_product + g_pipeline_output;
+
+ -- When g_out_p_w < g_in_a_w+g_in_b_w then the LPM_MULT truncates the LSbits of the product. Therefore
+ -- define c_prod_w to be able to let common_mult truncate the LSBits of the product.
+ constant c_prod_w : natural := g_in_a_w + g_in_b_w;
+
+ component lpm_mult
+ generic (
+ lpm_hint : string;
+ lpm_pipeline : natural;
+ lpm_representation : string;
+ lpm_type : string;
+ lpm_widtha : natural;
+ lpm_widthb : natural;
+ -- lpm_widths : natural;
+ lpm_widthp : natural
+ );
+ port (
+ dataa : in std_logic_vector(g_nof_mult * g_in_a_w - 1 downto 0);
+ datab : in std_logic_vector(g_nof_mult * g_in_a_w - 1 downto 0);
+ -- sum : in STD_LOGIC_VECTOR((g_nof_mult*g_in_s_w-1 DOWNTO 0) := (OTHERS => '0'); (not used in current designs)
+ -- aclr : in STD_LOGIC; (not used in current designs)
+ clock : in std_logic;
+ clken : in std_logic;
+ result : out std_logic_vector(g_nof_mult * (g_in_a_w + g_in_b_w) - 1 downto 0)
+ );
+ end component;
+
+ signal prod : std_logic_vector(g_nof_mult * c_prod_w - 1 downto 0);
+begin
+ gen_mult : for I in 0 to g_nof_mult - 1 generate
+ m : lpm_mult
+ generic map (
+ lpm_hint => "MAXIMIZE_SPEED=5", -- default "UNUSED"
+ lpm_pipeline => c_pipeline,
+ lpm_representation => g_representation,
+ lpm_type => "LPM_MULT",
+ lpm_widtha => g_in_a_w,
+ lpm_widthb => g_in_b_w,
+-- lpm_widths => g_in_s_w, (Partial sum input with not used in current designs)
+ lpm_widthp => c_prod_w
+ )
+ port map (
+ dataa => in_a((I + 1) * g_in_a_w - 1 downto I * g_in_a_w),
+ datab => in_b((I + 1) * g_in_b_w - 1 downto I * g_in_b_w),
+ -- sum => sum((I+1)*g_in_s_w-1 DOWNTO I*g_in_s_w), -- partial sum input is not used in current designs
+ -- aclr => aclr, -- async clear input is not used in current designs
+ clock => clk,
+ clken => clken,
+ result => prod((I + 1) * c_prod_w - 1 downto I * c_prod_w)
+ );
+
+ out_p <= prod;
+---- Truncate MSbits, also for signed (common_pkg.vhd for explanation of RESIZE_SVEC)
+-- out_p((I+1)*g_out_p_w-1 DOWNTO I*g_out_p_w) <= RESIZE_SVEC(prod((I+1)*c_prod_w-1 DOWNTO I*c_prod_w), g_out_p_w) WHEN g_representation="SIGNED" ELSE
+-- RESIZE_UVEC(prod((I+1)*c_prod_w-1 DOWNTO I*c_prod_w), g_out_p_w);
+ end generate;
+
+end str;
diff --git a/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_mult_rtl.vhd b/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_mult_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c9a49693fffeb60693a373a586c834e5179b99b7
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_mult_rtl.vhd
@@ -0,0 +1,144 @@
+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author : D.F. Brouwer
+-- Purpose:
+-- RadioHDL wrapper
+-- Reference:
+-- Copied from */technology/ip_arria10/mult/ip_arria10_mult_rtl.vhd
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+-- no support for rounding in this RTL architecture
+ entity ip_agi027_xxxx_mult_rtl is
+ generic (
+ g_in_a_w : positive := 18;
+ g_in_b_w : positive := 18;
+ g_out_p_w : positive := 36; -- c_prod_w = g_in_a_w+g_in_b_w, use smaller g_out_p_w to truncate MSbits, or larger g_out_p_w to extend MSbits
+ g_nof_mult : positive := 1; -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 1; -- 0 or 1
+ g_pipeline_output : natural := 1; -- >= 0
+ g_representation : string := "SIGNED" -- or "UNSIGNED"
+ );
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_a : in std_logic_vector(g_nof_mult * g_in_a_w - 1 downto 0);
+ in_b : in std_logic_vector(g_nof_mult * g_in_b_w - 1 downto 0);
+ out_p : out std_logic_vector(g_nof_mult * (g_in_a_w + g_in_b_w) - 1 downto 0)
+ );
+ end ip_agi027_xxxx_mult_rtl;
+
+architecture str of ip_agi027_xxxx_mult_rtl is
+ constant c_prod_w : natural := g_in_a_w + g_in_b_w;
+
+ -- registers
+ signal reg_a : std_logic_vector(in_a'range);
+ signal reg_b : std_logic_vector(in_b'range);
+ signal reg_prod : std_logic_vector(g_nof_mult * c_prod_w - 1 downto 0);
+ signal reg_result : std_logic_vector(out_p'range);
+
+ -- combinatorial
+ signal nxt_a : std_logic_vector(in_a'range);
+ signal nxt_b : std_logic_vector(in_b'range);
+ signal nxt_prod : std_logic_vector(g_nof_mult * c_prod_w - 1 downto 0);
+ signal nxt_result : std_logic_vector(out_p'range);
+
+ -- the active signals
+ signal inp_a : std_logic_vector(in_a'range);
+ signal inp_b : std_logic_vector(in_b'range);
+ signal prod : std_logic_vector(g_nof_mult * c_prod_w - 1 downto 0); -- stage dependent on g_pipeline_product being 0 or 1
+ signal result : std_logic_vector(out_p'range); -- stage dependent on g_pipeline_output being 0 or 1
+begin
+ ------------------------------------------------------------------------------
+ -- Registers
+ ------------------------------------------------------------------------------
+
+ -- Put all potential registers in a single process for optimal DSP inferrence
+ -- Use rst only if it is supported by the DSP primitive, else leave it at '0'
+ p_reg : process (rst, clk)
+ begin
+ if rst = '1' then
+ reg_a <= (others => '0');
+ reg_b <= (others => '0');
+ reg_prod <= (others => '0');
+ reg_result <= (others => '0');
+ elsif rising_edge(clk) then
+ if clken = '1' then
+ reg_a <= nxt_a;
+ reg_b <= nxt_b;
+ reg_prod <= nxt_prod;
+ reg_result <= nxt_result;
+ end if;
+ end if;
+ end process;
+
+ ------------------------------------------------------------------------------
+ -- Inputs
+ ------------------------------------------------------------------------------
+
+ nxt_a <= in_a;
+ nxt_b <= in_b;
+
+ no_input_reg : if g_pipeline_input = 0 generate -- wired
+ inp_a <= nxt_a;
+ inp_b <= nxt_b;
+ end generate;
+
+ gen_input_reg : if g_pipeline_input > 0 generate -- register input
+ inp_a <= reg_a;
+ inp_b <= reg_b;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Products
+ ------------------------------------------------------------------------------
+
+ gen_mult : for I in 0 to g_nof_mult - 1 generate
+ nxt_prod((I + 1) * c_prod_w - 1 downto I * c_prod_w) <=
+ std_logic_vector( signed(inp_a((I + 1) * g_in_a_w - 1 downto I * g_in_a_w)) * signed(inp_b((I + 1) * g_in_b_w - 1 downto I * g_in_b_w))) when g_representation = "SIGNED" else
+ std_logic_vector(unsigned(inp_a((I + 1) * g_in_a_w - 1 downto I * g_in_a_w)) * unsigned(inp_b((I + 1) * g_in_b_w - 1 downto I * g_in_b_w)));
+ end generate;
+
+ no_product_reg : if g_pipeline_product = 0 generate -- wired
+ prod <= nxt_prod;
+ end generate;
+ gen_product_reg : if g_pipeline_product > 0 generate -- register
+ prod <= reg_prod;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Results
+ ------------------------------------------------------------------------------
+ nxt_result <= prod;
+
+ no_result_reg : if g_pipeline_output = 0 generate -- wired
+ result <= nxt_result;
+ end generate;
+ gen_result_reg : if g_pipeline_output > 0 generate -- register
+ result <= reg_result;
+ end generate;
+
+out_p <= result;
+end str;
diff --git a/libraries/technology/ip_agi027_xxxx/mult_add2/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/mult_add2/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..10de323cf0dba3baf8f4687065085848bbb2f75c
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/mult_add2/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_agi027_xxxx_mult_add2
+hdl_library_clause_name = ip_agi027_xxxx_mult_add2_lib
+hdl_lib_uses_synth = technology common
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_agi027_xxxx
+
+synth_files =
+ ip_agi027_xxxx_mult_add2_rtl.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_agi027_xxxx/mult_add2/ip_agi027_xxxx_mult_add2_rtl.vhd b/libraries/technology/ip_agi027_xxxx/mult_add2/ip_agi027_xxxx_mult_add2_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6a3bcf3cab6b2d1f2e20d17f2d46bcd517adc46d
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/mult_add2/ip_agi027_xxxx_mult_add2_rtl.vhd
@@ -0,0 +1,201 @@
+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author : D.F. Brouwer
+-- Purpose:
+-- RadioHDL wrapper
+-- Reference:
+-- Copied from */technology/ip_arria10_e2sg/mult_add2/ip_arria10_e2sg_mult_add2.vhd,
+-- that is based on ip_stratixiv_mult_add2_rtl
+
+library IEEE, common_lib;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use common_lib.common_pkg.all;
+
+------------------------------------------------------------------------------
+-- Function:
+-- . res = a0 * b0 + a1 * b1
+-- . res = a0 * b0 - a1 * b1
+------------------------------------------------------------------------------
+
+entity ip_agi027_xxxx_mult_add2_rtl is
+ generic (
+ g_in_a_w : positive;
+ g_in_b_w : positive;
+ g_res_w : positive; -- g_in_a_w + g_in_b_w + log2(2)
+ g_force_dsp : boolean := true; -- when TRUE resize input width to >= 18
+ g_add_sub : string := "ADD"; -- or "SUB"
+ g_nof_mult : integer := 2; -- fixed
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 0; -- 0 or 1
+ g_pipeline_adder : natural := 1; -- 0 or 1
+ g_pipeline_output : natural := 1 -- >= 0
+ );
+ port (
+ rst : in std_logic := '0';
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_a : in std_logic_vector(g_nof_mult * g_in_a_w - 1 downto 0);
+ in_b : in std_logic_vector(g_nof_mult * g_in_b_w - 1 downto 0);
+ res : out std_logic_vector(g_res_w - 1 downto 0)
+ );
+end ip_agi027_xxxx_mult_add2_rtl;
+
+architecture str of ip_agi027_xxxx_mult_add2_rtl is
+ -- Extra output pipelining is only needed when g_pipeline_output > 1
+ constant c_pipeline_output : natural := sel_a_b(g_pipeline_output > 0, g_pipeline_output - 1, 0);
+
+ constant c_prod_w : natural := g_in_a_w + g_in_b_w;
+ constant c_sum_w : natural := c_prod_w + 1;
+
+ -- registers
+ signal reg_a0 : signed(g_in_a_w - 1 downto 0);
+ signal reg_b0 : signed(g_in_b_w - 1 downto 0);
+ signal reg_a1 : signed(g_in_a_w - 1 downto 0);
+ signal reg_b1 : signed(g_in_b_w - 1 downto 0);
+ signal reg_prod0 : signed(c_prod_w - 1 downto 0);
+ signal reg_prod1 : signed(c_prod_w - 1 downto 0);
+ signal reg_sum : signed(c_sum_w - 1 downto 0);
+ signal reg_result : signed(g_res_w - 1 downto 0);
+
+ -- combinatorial
+ signal nxt_a0 : signed(g_in_a_w - 1 downto 0);
+ signal nxt_b0 : signed(g_in_b_w - 1 downto 0);
+ signal nxt_a1 : signed(g_in_a_w - 1 downto 0);
+ signal nxt_b1 : signed(g_in_b_w - 1 downto 0);
+ signal nxt_prod0 : signed(c_prod_w - 1 downto 0);
+ signal nxt_prod1 : signed(c_prod_w - 1 downto 0);
+ signal nxt_sum : signed(c_sum_w - 1 downto 0);
+ signal nxt_result : signed(g_res_w - 1 downto 0);
+
+ -- the active signals
+ signal a0 : signed(g_in_a_w - 1 downto 0);
+ signal b0 : signed(g_in_b_w - 1 downto 0);
+ signal a1 : signed(g_in_a_w - 1 downto 0);
+ signal b1 : signed(g_in_b_w - 1 downto 0);
+ signal prod0 : signed(c_prod_w - 1 downto 0);
+ signal prod1 : signed(c_prod_w - 1 downto 0);
+ signal sum : signed(c_sum_w - 1 downto 0);
+ signal result : signed(g_res_w - 1 downto 0);
+begin
+ ------------------------------------------------------------------------------
+ -- Registers
+ ------------------------------------------------------------------------------
+
+ -- Put all potential registers in a single process for optimal DSP inferrence
+ -- Use rst only if it is supported by the DSP primitive, else leave it at '0'
+ p_reg : process (rst, clk)
+ begin
+ if rising_edge(clk) then
+ if rst = '1' then
+ reg_a0 <= (others => '0');
+ reg_b0 <= (others => '0');
+ reg_a1 <= (others => '0');
+ reg_b1 <= (others => '0');
+ reg_prod0 <= (others => '0');
+ reg_prod1 <= (others => '0');
+ reg_sum <= (others => '0');
+ reg_result <= (others => '0');
+ elsif clken = '1' then
+ reg_a0 <= nxt_a0; -- inputs
+ reg_b0 <= nxt_b0;
+ reg_a1 <= nxt_a1;
+ reg_b1 <= nxt_b1;
+ reg_prod0 <= nxt_prod0; -- products
+ reg_prod1 <= nxt_prod1;
+ reg_sum <= nxt_sum; -- sum
+ reg_result <= nxt_result; -- result sum after optional rounding
+ end if;
+ end if;
+ end process;
+
+ ------------------------------------------------------------------------------
+ -- Inputs
+ ------------------------------------------------------------------------------
+
+ nxt_a0 <= signed(in_a( g_in_a_w - 1 downto 0));
+ nxt_b0 <= signed(in_b( g_in_b_w - 1 downto 0));
+ nxt_a1 <= signed(in_a(2 * g_in_a_w - 1 downto g_in_a_w));
+ nxt_b1 <= signed(in_b(2 * g_in_b_w - 1 downto g_in_b_w));
+
+ no_input_reg : if g_pipeline_input = 0 generate -- wired
+ a0 <= nxt_a0;
+ b0 <= nxt_b0;
+ a1 <= nxt_a1;
+ b1 <= nxt_b1;
+ end generate;
+
+ gen_input_reg : if g_pipeline_input > 0 generate -- register input
+ a0 <= reg_a0;
+ b0 <= reg_b0;
+ a1 <= reg_a1;
+ b1 <= reg_b1;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Products
+ ------------------------------------------------------------------------------
+
+ nxt_prod0 <= a0 * b0;
+ nxt_prod1 <= a1 * b1;
+
+ no_product_reg : if g_pipeline_product = 0 generate -- wired
+ prod0 <= nxt_prod0;
+ prod1 <= nxt_prod1;
+ end generate;
+ gen_product_reg : if g_pipeline_product > 0 generate -- register
+ prod0 <= reg_prod0;
+ prod1 <= reg_prod1;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Sum
+ ------------------------------------------------------------------------------
+ gen_add : if g_add_sub = "ADD" generate
+ nxt_sum <= RESIZE_NUM(prod0, c_sum_w) + prod1;
+ end generate;
+
+ gen_sub : if g_add_sub = "SUB" generate
+ nxt_sum <= RESIZE_NUM(prod0, c_sum_w) - prod1;
+ end generate;
+
+ no_adder_reg : if g_pipeline_adder = 0 generate -- wired
+ sum <= nxt_sum;
+ end generate;
+ gen_adder_reg : if g_pipeline_adder > 0 generate -- register
+ sum <= reg_sum;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Result sum after optional rounding
+ ------------------------------------------------------------------------------
+
+ nxt_result <= RESIZE_NUM(sum, g_res_w);
+
+ no_result_reg : if g_pipeline_output = 0 generate -- wired
+ result <= nxt_result;
+ end generate;
+ gen_result_reg : if g_pipeline_output > 0 generate -- register
+ result <= reg_result;
+ end generate;
+
+ res <= std_logic_vector(result);
+end str;
diff --git a/libraries/technology/ip_agi027_xxxx/mult_add4/compile_ip.tcl b/libraries/technology/ip_agi027_xxxx/mult_add4/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..111fd4da2b3c2c649ae7091d1381cf9beb99b82c
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/mult_add4/compile_ip.tcl
@@ -0,0 +1,38 @@
+# ------------------------------------------------------------------------------
+#
+# Copyright (C) 2023
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# ------------------------------------------------------------------------------
+# Author: D.F. Brouwer
+# Description:
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_mult_add4/sim"
+
+vmap ip_agi027_xxxx_mult_add4 ./work/
+vmap altera_mult_add_1920 ./work/
+
+
+ vcom "$IP_DIR/../altera_mult_add_1920/sim/ip_agi027_xxxx_mult_add4_altera_mult_add_1920_ljq3huq.vhd" -work altera_mult_add_1920
+ vcom "$IP_DIR/ip_agi027_xxxx_mult_add4.vhd" -work ip_agi027_xxxx_mult_add4
diff --git a/libraries/technology/ip_agi027_xxxx/mult_add4/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/mult_add4/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..e4bc0f9bac292993339fceabc984dbc5ea265ec3
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/mult_add4/hdllib.cfg
@@ -0,0 +1,21 @@
+hdl_lib_name = ip_agi027_xxxx_mult_add4
+hdl_library_clause_name = ip_agi027_xxxx_mult_add4_lib
+hdl_lib_uses_synth = technology common
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_agi027_xxxx
+
+synth_files =
+ ip_agi027_xxxx_mult_add4_rtl.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_agi027_xxxx_mult_add4.ip
+
diff --git a/libraries/technology/ip_agi027_xxxx/mult_add4/ip_agi027_xxxx_mult_add4.ip b/libraries/technology/ip_agi027_xxxx/mult_add4/ip_agi027_xxxx_mult_add4.ip
new file mode 100644
index 0000000000000000000000000000000000000000..8b6eb98f7206626a9a2954a385ec3beee08e5f97
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/mult_add4/ip_agi027_xxxx_mult_add4.ip
@@ -0,0 +1,1508 @@
+<?xml version="1.0" ?>
+<!--Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.-->
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_mult_add4</ipxact:library>
+ <ipxact:name>mult_add_0</ipxact:name>
+ <ipxact:version>19.2.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>result</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>result</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>result</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>output</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>dataa_0</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataa_0</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>dataa_0</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>dataa_1</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataa_1</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>dataa_1</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>dataa_2</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataa_2</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>dataa_2</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>dataa_3</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataa_3</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>dataa_3</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>datab_0</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datab_0</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>datab_0</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>datab_1</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datab_1</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>datab_1</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>datab_2</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datab_2</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>datab_2</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>datab_3</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datab_3</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>datab_3</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clock0</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="clock" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="clock" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>clock0</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>ena0</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>ena0</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>ena0</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>aclr0</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="reset" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="reset" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>aclr0</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>clock0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>altera_mult_add</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>result</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>37</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>dataa_0</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>dataa_1</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>dataa_2</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>dataa_3</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>datab_0</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>datab_1</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>datab_2</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>datab_3</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>clock0</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>ena0</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>aclr0</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_mult_add4</ipxact:library>
+ <ipxact:name>altera_mult_add</ipxact:name>
+ <ipxact:version>19.2.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="number_of_multipliers" type="int">
+ <ipxact:name>number_of_multipliers</ipxact:name>
+ <ipxact:displayName>What is the number of multipliers?</ipxact:displayName>
+ <ipxact:value>4</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="width_a" type="int">
+ <ipxact:name>width_a</ipxact:name>
+ <ipxact:displayName>How wide should the A input buses be?</ipxact:displayName>
+ <ipxact:value>18</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="width_b" type="int">
+ <ipxact:name>width_b</ipxact:name>
+ <ipxact:displayName>How wide should the B input buses be?</ipxact:displayName>
+ <ipxact:value>18</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="width_result" type="int">
+ <ipxact:name>width_result</ipxact:name>
+ <ipxact:displayName>How wide should the 'result' output bus be?</ipxact:displayName>
+ <ipxact:value>38</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_4th_asynchronous_clear" type="bit">
+ <ipxact:name>gui_4th_asynchronous_clear</ipxact:name>
+ <ipxact:displayName>Create a 4th asynchronous clear input option</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_associated_clock_enable" type="bit">
+ <ipxact:name>gui_associated_clock_enable</ipxact:name>
+ <ipxact:displayName>Create an associated clock enable for each clock</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_output_register" type="bit">
+ <ipxact:name>gui_output_register</ipxact:name>
+ <ipxact:displayName>Register output of the adder unit</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_output_register_clock" type="string">
+ <ipxact:name>gui_output_register_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_output_register_aclr" type="string">
+ <ipxact:name>gui_output_register_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_output_register_sclr" type="string">
+ <ipxact:name>gui_output_register_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_multiplier1_direction" type="string">
+ <ipxact:name>gui_multiplier1_direction</ipxact:name>
+ <ipxact:displayName>What operation should be perfomed on outputs of the first pair of multipliers</ipxact:displayName>
+ <ipxact:value>ADD</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_addnsub_multiplier_register1" type="bit">
+ <ipxact:name>gui_addnsub_multiplier_register1</ipxact:name>
+ <ipxact:displayName>Register 'addnsub1' input</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_addnsub_multiplier_register1_clock" type="string">
+ <ipxact:name>gui_addnsub_multiplier_register1_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_addnsub_multiplier_aclr1" type="string">
+ <ipxact:name>gui_addnsub_multiplier_aclr1</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_addnsub_multiplier_sclr1" type="string">
+ <ipxact:name>gui_addnsub_multiplier_sclr1</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_multiplier3_direction" type="string">
+ <ipxact:name>gui_multiplier3_direction</ipxact:name>
+ <ipxact:displayName>What operation should be perfomed on outputs of the second pair of multipliers</ipxact:displayName>
+ <ipxact:value>ADD</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_addnsub_multiplier_register3" type="bit">
+ <ipxact:name>gui_addnsub_multiplier_register3</ipxact:name>
+ <ipxact:displayName>Register 'addnsub3' input</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_addnsub_multiplier_register3_clock" type="string">
+ <ipxact:name>gui_addnsub_multiplier_register3_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_addnsub_multiplier_aclr3" type="string">
+ <ipxact:name>gui_addnsub_multiplier_aclr3</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_addnsub_multiplier_sclr3" type="string">
+ <ipxact:name>gui_addnsub_multiplier_sclr3</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_use_subnadd" type="bit">
+ <ipxact:name>gui_use_subnadd</ipxact:name>
+ <ipxact:displayName>Enable 'use_subnadd'</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_representation_a" type="string">
+ <ipxact:name>gui_representation_a</ipxact:name>
+ <ipxact:displayName>What is the representation format for Multipliers A inputs?</ipxact:displayName>
+ <ipxact:value>SIGNED</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_register_signa" type="bit">
+ <ipxact:name>gui_register_signa</ipxact:name>
+ <ipxact:displayName>Register 'signa' input</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_register_signa_clock" type="string">
+ <ipxact:name>gui_register_signa_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_register_signa_aclr" type="string">
+ <ipxact:name>gui_register_signa_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_register_signa_sclr" type="string">
+ <ipxact:name>gui_register_signa_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_representation_b" type="string">
+ <ipxact:name>gui_representation_b</ipxact:name>
+ <ipxact:displayName>What is the representation format for Multipliers B inputs?</ipxact:displayName>
+ <ipxact:value>SIGNED</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_register_signb" type="bit">
+ <ipxact:name>gui_register_signb</ipxact:name>
+ <ipxact:displayName>Register 'signb' input</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_register_signb_clock" type="string">
+ <ipxact:name>gui_register_signb_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_register_signb_aclr" type="string">
+ <ipxact:name>gui_register_signb_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_register_signb_sclr" type="string">
+ <ipxact:name>gui_register_signb_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_input_register_a" type="bit">
+ <ipxact:name>gui_input_register_a</ipxact:name>
+ <ipxact:displayName>Register input A of the multiplier</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_input_register_a_clock" type="string">
+ <ipxact:name>gui_input_register_a_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_input_register_a_aclr" type="string">
+ <ipxact:name>gui_input_register_a_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_input_register_a_sclr" type="string">
+ <ipxact:name>gui_input_register_a_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_input_register_b" type="bit">
+ <ipxact:name>gui_input_register_b</ipxact:name>
+ <ipxact:displayName>Register input B of the multiplier</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_input_register_b_clock" type="string">
+ <ipxact:name>gui_input_register_b_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_input_register_b_aclr" type="string">
+ <ipxact:name>gui_input_register_b_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_input_register_b_sclr" type="string">
+ <ipxact:name>gui_input_register_b_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_multiplier_a_input" type="string">
+ <ipxact:name>gui_multiplier_a_input</ipxact:name>
+ <ipxact:displayName>What is the input A of the multiplier connected to?</ipxact:displayName>
+ <ipxact:value>Multiplier input</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_scanouta_register" type="bit">
+ <ipxact:name>gui_scanouta_register</ipxact:name>
+ <ipxact:displayName>Register output of the scan chain</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_scanouta_register_clock" type="string">
+ <ipxact:name>gui_scanouta_register_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_scanouta_register_aclr" type="string">
+ <ipxact:name>gui_scanouta_register_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_scanouta_register_sclr" type="string">
+ <ipxact:name>gui_scanouta_register_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_multiplier_b_input" type="string">
+ <ipxact:name>gui_multiplier_b_input</ipxact:name>
+ <ipxact:displayName>What is the input B of the multiplier connected to?</ipxact:displayName>
+ <ipxact:value>Multiplier input</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_multiplier_register" type="bit">
+ <ipxact:name>gui_multiplier_register</ipxact:name>
+ <ipxact:displayName>Register output of the multiplier</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_multiplier_register_clock" type="string">
+ <ipxact:name>gui_multiplier_register_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_multiplier_register_aclr" type="string">
+ <ipxact:name>gui_multiplier_register_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_multiplier_register_sclr" type="string">
+ <ipxact:name>gui_multiplier_register_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="preadder_mode" type="string">
+ <ipxact:name>preadder_mode</ipxact:name>
+ <ipxact:displayName>Select preadder mode</ipxact:displayName>
+ <ipxact:value>SIMPLE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_preadder_direction" type="string">
+ <ipxact:name>gui_preadder_direction</ipxact:name>
+ <ipxact:displayName>Select preadder direction</ipxact:displayName>
+ <ipxact:value>ADD</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="width_c" type="int">
+ <ipxact:name>width_c</ipxact:name>
+ <ipxact:displayName>How wide should the C input buses be?</ipxact:displayName>
+ <ipxact:value>16</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_datac_input_register" type="bit">
+ <ipxact:name>gui_datac_input_register</ipxact:name>
+ <ipxact:displayName>Register datac input</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_datac_input_register_clock" type="string">
+ <ipxact:name>gui_datac_input_register_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_datac_input_register_aclr" type="string">
+ <ipxact:name>gui_datac_input_register_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_datac_input_register_sclr" type="string">
+ <ipxact:name>gui_datac_input_register_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="width_coef" type="int">
+ <ipxact:name>width_coef</ipxact:name>
+ <ipxact:displayName>How wide should the coef width be?</ipxact:displayName>
+ <ipxact:value>18</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_coef_register" type="bit">
+ <ipxact:name>gui_coef_register</ipxact:name>
+ <ipxact:displayName>Register the coefsel inputs</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_coef_register_clock" type="string">
+ <ipxact:name>gui_coef_register_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_coef_register_aclr" type="string">
+ <ipxact:name>gui_coef_register_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_coef_register_sclr" type="string">
+ <ipxact:name>gui_coef_register_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef0_0" type="int">
+ <ipxact:name>coef0_0</ipxact:name>
+ <ipxact:displayName>Coef0_0</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef0_1" type="int">
+ <ipxact:name>coef0_1</ipxact:name>
+ <ipxact:displayName>Coef0_1</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef0_2" type="int">
+ <ipxact:name>coef0_2</ipxact:name>
+ <ipxact:displayName>Coef0_2</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef0_3" type="int">
+ <ipxact:name>coef0_3</ipxact:name>
+ <ipxact:displayName>Coef0_3</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef0_4" type="int">
+ <ipxact:name>coef0_4</ipxact:name>
+ <ipxact:displayName>Coef0_4</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef0_5" type="int">
+ <ipxact:name>coef0_5</ipxact:name>
+ <ipxact:displayName>Coef0_5</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef0_6" type="int">
+ <ipxact:name>coef0_6</ipxact:name>
+ <ipxact:displayName>Coef0_6</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef0_7" type="int">
+ <ipxact:name>coef0_7</ipxact:name>
+ <ipxact:displayName>Coef0_7</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef1_0" type="int">
+ <ipxact:name>coef1_0</ipxact:name>
+ <ipxact:displayName>Coef1_0</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef1_1" type="int">
+ <ipxact:name>coef1_1</ipxact:name>
+ <ipxact:displayName>Coef1_1</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef1_2" type="int">
+ <ipxact:name>coef1_2</ipxact:name>
+ <ipxact:displayName>Coef1_2</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef1_3" type="int">
+ <ipxact:name>coef1_3</ipxact:name>
+ <ipxact:displayName>Coef1_3</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef1_4" type="int">
+ <ipxact:name>coef1_4</ipxact:name>
+ <ipxact:displayName>Coef1_4</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef1_5" type="int">
+ <ipxact:name>coef1_5</ipxact:name>
+ <ipxact:displayName>Coef1_5</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef1_6" type="int">
+ <ipxact:name>coef1_6</ipxact:name>
+ <ipxact:displayName>Coef1_6</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef1_7" type="int">
+ <ipxact:name>coef1_7</ipxact:name>
+ <ipxact:displayName>Coef1_7</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef2_0" type="int">
+ <ipxact:name>coef2_0</ipxact:name>
+ <ipxact:displayName>Coef2_0</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef2_1" type="int">
+ <ipxact:name>coef2_1</ipxact:name>
+ <ipxact:displayName>Coef2_1</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef2_2" type="int">
+ <ipxact:name>coef2_2</ipxact:name>
+ <ipxact:displayName>Coef2_2</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef2_3" type="int">
+ <ipxact:name>coef2_3</ipxact:name>
+ <ipxact:displayName>Coef2_3</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef2_4" type="int">
+ <ipxact:name>coef2_4</ipxact:name>
+ <ipxact:displayName>Coef2_4</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef2_5" type="int">
+ <ipxact:name>coef2_5</ipxact:name>
+ <ipxact:displayName>Coef2_5</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef2_6" type="int">
+ <ipxact:name>coef2_6</ipxact:name>
+ <ipxact:displayName>Coef2_6</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef2_7" type="int">
+ <ipxact:name>coef2_7</ipxact:name>
+ <ipxact:displayName>Coef2_7</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef3_0" type="int">
+ <ipxact:name>coef3_0</ipxact:name>
+ <ipxact:displayName>Coef3_0</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef3_1" type="int">
+ <ipxact:name>coef3_1</ipxact:name>
+ <ipxact:displayName>Coef3_1</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef3_2" type="int">
+ <ipxact:name>coef3_2</ipxact:name>
+ <ipxact:displayName>Coef3_2</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef3_3" type="int">
+ <ipxact:name>coef3_3</ipxact:name>
+ <ipxact:displayName>Coef3_3</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef3_4" type="int">
+ <ipxact:name>coef3_4</ipxact:name>
+ <ipxact:displayName>Coef3_4</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef3_5" type="int">
+ <ipxact:name>coef3_5</ipxact:name>
+ <ipxact:displayName>Coef3_5</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef3_6" type="int">
+ <ipxact:name>coef3_6</ipxact:name>
+ <ipxact:displayName>Coef3_6</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef3_7" type="int">
+ <ipxact:name>coef3_7</ipxact:name>
+ <ipxact:displayName>Coef3_7</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="accumulator" type="string">
+ <ipxact:name>accumulator</ipxact:name>
+ <ipxact:displayName>Enable accumulator?</ipxact:displayName>
+ <ipxact:value>NO</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="accum_direction" type="string">
+ <ipxact:name>accum_direction</ipxact:name>
+ <ipxact:displayName>What is the accumulator operation type?</ipxact:displayName>
+ <ipxact:value>ADD</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_ena_preload_const" type="bit">
+ <ipxact:name>gui_ena_preload_const</ipxact:name>
+ <ipxact:displayName>Enable preload constant</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_accumulate_port_select" type="int">
+ <ipxact:name>gui_accumulate_port_select</ipxact:name>
+ <ipxact:displayName>What is the input of accumulate port connected to?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="loadconst_value" type="int">
+ <ipxact:name>loadconst_value</ipxact:name>
+ <ipxact:displayName>Select value for preload constant</ipxact:displayName>
+ <ipxact:value>64</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_accum_sload_register_clock" type="string">
+ <ipxact:name>gui_accum_sload_register_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_accum_sload_register_aclr" type="string">
+ <ipxact:name>gui_accum_sload_register_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_accum_sload_register_sclr" type="string">
+ <ipxact:name>gui_accum_sload_register_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_double_accum" type="bit">
+ <ipxact:name>gui_double_accum</ipxact:name>
+ <ipxact:displayName>Enable double accumulator</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="chainout_adder" type="string">
+ <ipxact:name>chainout_adder</ipxact:name>
+ <ipxact:displayName>Enable chainout adder</ipxact:displayName>
+ <ipxact:value>NO</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="chainout_adder_direction" type="string">
+ <ipxact:name>chainout_adder_direction</ipxact:name>
+ <ipxact:displayName>What is the chainout adder operation type?</ipxact:displayName>
+ <ipxact:value>ADD</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="port_negate" type="string">
+ <ipxact:name>port_negate</ipxact:name>
+ <ipxact:displayName>Enable 'negate' input for chainout adder?</ipxact:displayName>
+ <ipxact:value>PORT_UNUSED</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="negate_register" type="string">
+ <ipxact:name>negate_register</ipxact:name>
+ <ipxact:displayName>Register 'negate' input?</ipxact:displayName>
+ <ipxact:value>UNREGISTERED</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="negate_aclr" type="string">
+ <ipxact:name>negate_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="negate_sclr" type="string">
+ <ipxact:name>negate_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_systolic_delay" type="bit">
+ <ipxact:name>gui_systolic_delay</ipxact:name>
+ <ipxact:displayName>Enable systolic delay registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_systolic_delay_clock" type="string">
+ <ipxact:name>gui_systolic_delay_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_systolic_delay_aclr" type="string">
+ <ipxact:name>gui_systolic_delay_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_systolic_delay_sclr" type="string">
+ <ipxact:name>gui_systolic_delay_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_pipelining" type="int">
+ <ipxact:name>gui_pipelining</ipxact:name>
+ <ipxact:displayName>Do you want to add pipeline register to the input?</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="latency" type="int">
+ <ipxact:name>latency</ipxact:name>
+ <ipxact:displayName>Please specify the number of latency clock cycles</ipxact:displayName>
+ <ipxact:value>3</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_input_latency_clock" type="string">
+ <ipxact:name>gui_input_latency_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_input_latency_aclr" type="string">
+ <ipxact:name>gui_input_latency_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>ACLR0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_input_latency_sclr" type="string">
+ <ipxact:name>gui_input_latency_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="selected_device_family" type="string">
+ <ipxact:name>selected_device_family</ipxact:name>
+ <ipxact:displayName>selected_device_family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="reg_autovec_sim" type="bit">
+ <ipxact:name>reg_autovec_sim</ipxact:name>
+ <ipxact:displayName>reg_autovec_sim</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="board" type="string">
+ <ipxact:name>board</ipxact:name>
+ <ipxact:displayName>Board</ipxact:displayName>
+ <ipxact:value>default</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>AGIB027R31A1I1VB</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element mult_add_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="aclr0" altera:internal="mult_add_0.aclr0" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="aclr0" altera:internal="aclr0"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clock0" altera:internal="mult_add_0.clock0" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="clock0" altera:internal="clock0"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="dataa_0" altera:internal="mult_add_0.dataa_0" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="dataa_0" altera:internal="dataa_0"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="dataa_1" altera:internal="mult_add_0.dataa_1" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="dataa_1" altera:internal="dataa_1"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="dataa_2" altera:internal="mult_add_0.dataa_2" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="dataa_2" altera:internal="dataa_2"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="dataa_3" altera:internal="mult_add_0.dataa_3" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="dataa_3" altera:internal="dataa_3"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="datab_0" altera:internal="mult_add_0.datab_0" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="datab_0" altera:internal="datab_0"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="datab_1" altera:internal="mult_add_0.datab_1" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="datab_1" altera:internal="datab_1"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="datab_2" altera:internal="mult_add_0.datab_2" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="datab_2" altera:internal="datab_2"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="datab_3" altera:internal="mult_add_0.datab_3" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="datab_3" altera:internal="datab_3"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="ena0" altera:internal="mult_add_0.ena0" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="ena0" altera:internal="ena0"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="result" altera:internal="mult_add_0.result" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="result" altera:internal="result"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/libraries/technology/ip_agi027_xxxx/mult_add4/ip_agi027_xxxx_mult_add4_rtl.vhd b/libraries/technology/ip_agi027_xxxx/mult_add4/ip_agi027_xxxx_mult_add4_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..da79fb61756bc0a4a08fc46e942d2731f2033ce7
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/mult_add4/ip_agi027_xxxx_mult_add4_rtl.vhd
@@ -0,0 +1,274 @@
+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author : D.F. Brouwer
+-- Purpose:
+-- RadioHDL wrapper
+-- Reference:
+-- Copied from */technology/ip_arria10_e2sg/mult_add4/ip_arria10_e2sg_mult_add2.vhd
+
+library IEEE, common_lib;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use common_lib.common_pkg.all;
+
+-- Function:
+-- . res = (a0 * b0 +- a1 * b1) +- (a2 * b2 +- a3 * b3)
+
+entity ip_agi027_xxxx_mult_add4_rtl is
+ generic (
+ g_in_a_w : positive;
+ g_in_b_w : positive;
+ g_res_w : positive; -- g_in_a_w + g_in_b_w + log2(4)
+ g_force_dsp : boolean := true; -- when TRUE resize input width to >= 18
+ g_add_sub0 : string := "ADD"; -- or "SUB"
+ g_add_sub1 : string := "ADD"; -- or "SUB"
+ g_add_sub : string := "ADD"; -- or "SUB" only available with rtl architecture
+ g_nof_mult : integer := 4; -- fixed
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 0; -- 0 or 1
+ g_pipeline_adder : natural := 1; -- 0 or 1, first sum
+ g_pipeline_output : natural := 1 -- >= 0, second sum and optional rounding
+ );
+ port (
+ rst : in std_logic := '0';
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_a : in std_logic_vector(g_nof_mult * g_in_a_w - 1 downto 0);
+ in_b : in std_logic_vector(g_nof_mult * g_in_b_w - 1 downto 0);
+ res : out std_logic_vector(g_res_w - 1 downto 0)
+ );
+end ip_agi027_xxxx_mult_add4_rtl;
+
+architecture str of ip_agi027_xxxx_mult_add4_rtl is
+ -- Extra output pipelining is only needed when g_pipeline_output > 1
+ constant c_pipeline_output : natural := sel_a_b(g_pipeline_output > 0, g_pipeline_output - 1, 0);
+
+ -- registers
+ signal reg_a0 : signed(g_in_a_w - 1 downto 0);
+ signal reg_b0 : signed(g_in_b_w - 1 downto 0);
+ signal reg_a1 : signed(g_in_a_w - 1 downto 0);
+ signal reg_b1 : signed(g_in_b_w - 1 downto 0);
+ signal reg_a2 : signed(g_in_a_w - 1 downto 0);
+ signal reg_b2 : signed(g_in_b_w - 1 downto 0);
+ signal reg_a3 : signed(g_in_a_w - 1 downto 0);
+ signal reg_b3 : signed(g_in_b_w - 1 downto 0);
+ signal reg_prod0 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal reg_prod1 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal reg_prod2 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal reg_prod3 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal reg_sum0 : signed(g_in_a_w + g_in_b_w downto 0);
+ signal reg_sum1 : signed(g_in_a_w + g_in_b_w downto 0);
+ signal reg_result : signed(res'range);
+
+ -- combinatorial
+ signal nxt_a0 : signed(g_in_a_w - 1 downto 0);
+ signal nxt_b0 : signed(g_in_b_w - 1 downto 0);
+ signal nxt_a1 : signed(g_in_a_w - 1 downto 0);
+ signal nxt_b1 : signed(g_in_b_w - 1 downto 0);
+ signal nxt_a2 : signed(g_in_a_w - 1 downto 0);
+ signal nxt_b2 : signed(g_in_b_w - 1 downto 0);
+ signal nxt_a3 : signed(g_in_a_w - 1 downto 0);
+ signal nxt_b3 : signed(g_in_b_w - 1 downto 0);
+ signal nxt_prod0 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal nxt_prod1 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal nxt_prod2 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal nxt_prod3 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal nxt_sum0 : signed(g_in_a_w + g_in_b_w downto 0);
+ signal nxt_sum1 : signed(g_in_a_w + g_in_b_w downto 0);
+ signal nxt_result : signed(res'range);
+
+ -- the active signals
+ signal a0 : signed(g_in_a_w - 1 downto 0);
+ signal b0 : signed(g_in_b_w - 1 downto 0);
+ signal a1 : signed(g_in_a_w - 1 downto 0);
+ signal b1 : signed(g_in_b_w - 1 downto 0);
+ signal a2 : signed(g_in_a_w - 1 downto 0);
+ signal b2 : signed(g_in_b_w - 1 downto 0);
+ signal a3 : signed(g_in_a_w - 1 downto 0);
+ signal b3 : signed(g_in_b_w - 1 downto 0);
+ signal prod0 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal prod1 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal prod2 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal prod3 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal sum0 : signed(g_in_a_w + g_in_b_w downto 0);
+ signal sum1 : signed(g_in_a_w + g_in_b_w downto 0);
+ signal sum : signed(g_in_a_w + g_in_b_w + 1 downto 0);
+ signal result : signed(res'range);
+begin
+ ------------------------------------------------------------------------------
+ -- Registers
+ ------------------------------------------------------------------------------
+
+ -- Put all potential registers in a single process for optimal DSP inferrence
+ -- Use rst only if it is supported by the DSP primitive, else leave it at '0'
+ p_reg : process (rst, clk)
+ begin
+ if rising_edge(clk) then
+ if rst = '1' then
+ reg_a0 <= (others => '0');
+ reg_b0 <= (others => '0');
+ reg_a1 <= (others => '0');
+ reg_b1 <= (others => '0');
+ reg_a2 <= (others => '0');
+ reg_b2 <= (others => '0');
+ reg_a3 <= (others => '0');
+ reg_b3 <= (others => '0');
+ reg_prod0 <= (others => '0');
+ reg_prod1 <= (others => '0');
+ reg_prod2 <= (others => '0');
+ reg_prod3 <= (others => '0');
+ reg_sum0 <= (others => '0');
+ reg_sum1 <= (others => '0');
+ reg_result <= (others => '0');
+ elsif clken = '1' then
+ reg_a0 <= nxt_a0; -- inputs
+ reg_b0 <= nxt_b0;
+ reg_a1 <= nxt_a1;
+ reg_b1 <= nxt_b1;
+ reg_a2 <= nxt_a2;
+ reg_b2 <= nxt_b2;
+ reg_a3 <= nxt_a3;
+ reg_b3 <= nxt_b3;
+ reg_prod0 <= nxt_prod0; -- products
+ reg_prod1 <= nxt_prod1;
+ reg_prod2 <= nxt_prod2;
+ reg_prod3 <= nxt_prod3;
+ reg_sum0 <= nxt_sum0; -- first sum
+ reg_sum1 <= nxt_sum1;
+ reg_result <= nxt_result; -- result second sum after optional rounding
+ end if;
+ end if;
+ end process;
+
+ ------------------------------------------------------------------------------
+ -- Inputs
+ ------------------------------------------------------------------------------
+
+ nxt_a0 <= signed(in_a( g_in_a_w - 1 downto 0));
+ nxt_b0 <= signed(in_b( g_in_b_w - 1 downto 0));
+ nxt_a1 <= signed(in_a(2 * g_in_a_w - 1 downto g_in_a_w));
+ nxt_b1 <= signed(in_b(2 * g_in_b_w - 1 downto g_in_b_w));
+ nxt_a2 <= signed(in_a(3 * g_in_a_w - 1 downto 2 * g_in_a_w));
+ nxt_b2 <= signed(in_b(3 * g_in_b_w - 1 downto 2 * g_in_b_w));
+ nxt_a3 <= signed(in_a(4 * g_in_a_w - 1 downto 3 * g_in_a_w));
+ nxt_b3 <= signed(in_b(4 * g_in_b_w - 1 downto 3 * g_in_b_w));
+
+ no_input_reg : if g_pipeline_input = 0 generate -- wired
+ a0 <= nxt_a0;
+ b0 <= nxt_b0;
+ a1 <= nxt_a1;
+ b1 <= nxt_b1;
+ a2 <= nxt_a2;
+ b2 <= nxt_b2;
+ a3 <= nxt_a3;
+ b3 <= nxt_b3;
+ end generate;
+
+ gen_input_reg : if g_pipeline_input > 0 generate -- register input
+ a0 <= reg_a0;
+ b0 <= reg_b0;
+ a1 <= reg_a1;
+ b1 <= reg_b1;
+ a2 <= reg_a2;
+ b2 <= reg_b2;
+ a3 <= reg_a3;
+ b3 <= reg_b3;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Products
+ ------------------------------------------------------------------------------
+
+ nxt_prod0 <= a0 * b0;
+ nxt_prod1 <= a1 * b1;
+ nxt_prod2 <= a2 * b2;
+ nxt_prod3 <= a3 * b3;
+
+ no_product_reg : if g_pipeline_product = 0 generate -- wired
+ prod0 <= nxt_prod0;
+ prod1 <= nxt_prod1;
+ prod2 <= nxt_prod2;
+ prod3 <= nxt_prod3;
+ end generate;
+ gen_product_reg : if g_pipeline_product > 0 generate -- register
+ prod0 <= reg_prod0;
+ prod1 <= reg_prod1;
+ prod2 <= reg_prod2;
+ prod3 <= reg_prod3;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- First sum
+ ------------------------------------------------------------------------------
+ gen_add0 : if g_add_sub0 = "ADD" generate
+ nxt_sum0 <= RESIZE_NUM(prod0, sum0'length) + prod1;
+ end generate;
+
+ gen_sub0 : if g_add_sub0 = "SUB" generate
+ nxt_sum0 <= RESIZE_NUM(prod0, sum0'length) - prod1;
+ end generate;
+
+ gen_add1 : if g_add_sub1 = "ADD" generate
+ nxt_sum1 <= RESIZE_NUM(prod2, sum1'length) + prod3;
+ end generate;
+
+ gen_sub1 : if g_add_sub1 = "SUB" generate
+ nxt_sum1 <= RESIZE_NUM(prod2, sum1'length) - prod3;
+ end generate;
+
+ -- Optinal first sum register
+ no_adder_reg : if g_pipeline_adder = 0 generate -- wired
+ sum0 <= nxt_sum0;
+ sum1 <= nxt_sum1;
+ end generate;
+ gen_adder_reg : if g_pipeline_adder > 0 generate -- register
+ sum0 <= reg_sum0;
+ sum1 <= reg_sum1;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Second sum
+ ------------------------------------------------------------------------------
+
+ -- No register for second sum, gets combined with result register
+ gen_add : if g_add_sub = "ADD" generate
+ sum <= RESIZE_NUM(sum0, sum'length) + sum1;
+ end generate;
+
+ gen_sub : if g_add_sub = "SUB" generate
+ sum <= RESIZE_NUM(sum0, sum'length) - sum1;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Result sum after optional rounding
+ ------------------------------------------------------------------------------
+
+ nxt_result <= RESIZE_NUM(sum, res'length);
+
+ no_result_reg : if g_pipeline_output = 0 generate -- wired
+ result <= nxt_result;
+ end generate;
+ gen_result_reg : if g_pipeline_output > 0 generate -- register
+ result <= reg_result;
+ end generate;
+
+ res <= std_logic_vector(result);
+end str;
diff --git a/libraries/technology/ip_arria10/complex_mult_rtl/hdllib.cfg b/libraries/technology/ip_arria10/complex_mult_rtl/hdllib.cfg
index c117b1a36852672fbeab89e222e6d6bade9f6414..772a81cadece2b7b5fec0eece6c64ca8afb7e032 100644
--- a/libraries/technology/ip_arria10/complex_mult_rtl/hdllib.cfg
+++ b/libraries/technology/ip_arria10/complex_mult_rtl/hdllib.cfg
@@ -2,7 +2,7 @@ hdl_lib_name = ip_arria10_complex_mult_rtl
hdl_library_clause_name = ip_arria10_complex_mult_rtl_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-hdl_lib_technology = #ip_arria10 This file is also used for arria10_e3sge3 and arria10_e1sg
+hdl_lib_technology = #ip_arria10 This file is also used for arria10_e3sge3, arria10_e1sg and arria10_e2sg. It can be used for other (new) technologies. Leave hdl_lib_technology empty.
synth_files =
ip_arria10_complex_mult_rtl.vhd
diff --git a/libraries/technology/ip_arria10/complex_mult_rtl_canonical/hdllib.cfg b/libraries/technology/ip_arria10/complex_mult_rtl_canonical/hdllib.cfg
index a8446b153d87f2590f26bcbd290c5f7a78143d8c..bb6e480fe3d45b596e127c6411d62e7040141fc4 100644
--- a/libraries/technology/ip_arria10/complex_mult_rtl_canonical/hdllib.cfg
+++ b/libraries/technology/ip_arria10/complex_mult_rtl_canonical/hdllib.cfg
@@ -2,7 +2,7 @@ hdl_lib_name = ip_arria10_complex_mult_rtl_canonical
hdl_library_clause_name = ip_arria10_complex_mult_rtl_canonical_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-hdl_lib_technology = #ip_arria10 This file is also used for arria10_e3sge3 and arria10_e1sg
+hdl_lib_technology = #ip_arria10 This file is also used for arria10_e3sge3, arria10_e1sg and arria10_e2sg. It can be used for other (new) technologies. Leave hdl_lib_technology empty.
synth_files =
ip_arria10_complex_mult_rtl_canonical.vhd
diff --git a/libraries/technology/ip_arria10/mult/hdllib.cfg b/libraries/technology/ip_arria10/mult/hdllib.cfg
index 261e2d6efcfec39cbc60d57a4f2cb1cb01301ea2..75ed0b9a50eac50f8c3d59522a54d38a4e9ff83e 100644
--- a/libraries/technology/ip_arria10/mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10/mult/hdllib.cfg
@@ -2,7 +2,7 @@ hdl_lib_name = ip_arria10_mult
hdl_library_clause_name = ip_arria10_mult_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-hdl_lib_technology =
+hdl_lib_technology = #ip_arria10 This file is also used for arria10_e3sge3, arria10_e1sg and arria10_e2sg. It can be used for other (new) technologies. Leave hdl_lib_technology empty.
synth_files =
ip_arria10_mult.vhd
diff --git a/libraries/technology/mult/hdllib.cfg b/libraries/technology/mult/hdllib.cfg
index 6cec72909f1987c343efe91bf4226b69ef007453..1febdded2e79c181d0a9437ff1a00ce6ec36d014 100644
--- a/libraries/technology/mult/hdllib.cfg
+++ b/libraries/technology/mult/hdllib.cfg
@@ -6,13 +6,20 @@ hdl_lib_uses_synth = common technology
ip_arria10_complex_mult
ip_arria10_complex_mult_rtl
ip_arria10_complex_mult_rtl_canonical
- ip_arria10_e1sg_complex_mult
ip_arria10_e3sge3_mult_add4
+ ip_arria10_e1sg_complex_mult
ip_arria10_e1sg_mult_add4
ip_arria10_e1sg_mult_add2
+ ip_arria10_e2sg_complex_mult
ip_arria10_e2sg_mult_add4
ip_arria10_e2sg_mult_add2
- ip_arria10_e2sg_complex_mult
+ ip_agi027_xxxx_complex_mult
+ ip_agi027_xxxx_complex_mult_rtl
+ ip_agi027_xxxx_complex_mult_rtl_canonical
+ ip_agi027_xxxx_mult
+ ip_agi027_xxxx_mult_add4
+ ip_agi027_xxxx_mult_add2
+
hdl_lib_uses_sim =
hdl_lib_technology =
@@ -21,13 +28,19 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_mult ip_arria10_mult_lib
ip_arria10_complex_mult ip_arria10_complex_mult_altmult_complex_150
ip_arria10_complex_mult_rtl ip_arria10_complex_mult_rtl_lib
- ip_arria10_e1sg_complex_mult ip_arria10_e1sg_complex_mult_altmult_complex_180
ip_arria10_e3sge3_mult_add4 ip_arria10_e3sge3_mult_add4_lib
+ ip_arria10_e1sg_complex_mult ip_arria10_e1sg_complex_mult_altmult_complex_180
ip_arria10_e1sg_mult_add4 ip_arria10_e1sg_mult_add4_lib
ip_arria10_e1sg_mult_add2 ip_arria10_e1sg_mult_add2_lib
+ ip_arria10_e2sg_complex_mult ip_arria10_e2sg_complex_mult_altmult_complex_1910
ip_arria10_e2sg_mult_add4 ip_arria10_e2sg_mult_add4_lib
ip_arria10_e2sg_mult_add2 ip_arria10_e2sg_mult_add2_lib
- ip_arria10_e2sg_complex_mult ip_arria10_e2sg_complex_mult_altmult_complex_1910
+ ip_agi027_xxxx_complex_mult ip_agi027_xxxx_complex_mult_altmult_complex_1910
+ ip_agi027_xxxx_complex_mult_rtl ip_agi027_xxxx_complex_mult_rtl_lib
+ ip_agi027_xxxx_mult ip_agi027_xxxx_mult_lib
+ ip_agi027_xxxx_mult_add4 ip_agi027_xxxx_mult_add4_lib
+ ip_agi027_xxxx_mult_add2 ip_agi027_xxxx_mult_add2_lib
+
synth_files =
diff --git a/libraries/technology/mult/tech_complex_mult.vhd b/libraries/technology/mult/tech_complex_mult.vhd
index d11e36bb05a80b51423d6641bf2b06f5d2859735..168d165e910e62c27e7b80f5fd8ed747e2e194e1 100644
--- a/libraries/technology/mult/tech_complex_mult.vhd
+++ b/libraries/technology/mult/tech_complex_mult.vhd
@@ -1,25 +1,25 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2009
+-- Copyright 2009-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
-- Author : E. Kooistra
+-- Changed by : D.F. Brouwer
-- Purpose : Wrapper for complex multiplier IP
-- Decription :
--
@@ -42,7 +42,7 @@
-- The largest value for pi = min**2 + min**2.
-- The largest value for pr = min**2 - min*max < largest pi.
--
--- The largest pi = 2 * min**2 = 2**(c_dsp_dat_w-1), so it just does not
+-- The largest pi = 2 * min**2 = 2**(c_dsp_prod_w-1), so it just does not
-- fit in c_dsp_prod_w, but largest pi - 1 = 2**(c_dsp_dat_w-1) - 1 does
-- fit, so all other input values fit. In DSP systems the input value
-- (min + j*min) typically never occurs.
@@ -63,13 +63,14 @@ use work.tech_mult_component_pkg.all;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
library ip_stratixiv_mult_lib;
---LIBRARY ip_arria10_mult_lib;
---LIBRARY ip_arria10_mult_rtl_lib;
library ip_arria10_complex_mult_altmult_complex_150;
library ip_arria10_e1sg_complex_mult_altmult_complex_180;
library ip_arria10_e2sg_complex_mult_altmult_complex_1910;
+library ip_agi027_xxxx_complex_mult_altmult_complex_1910;
library ip_arria10_complex_mult_rtl_lib;
+library ip_agi027_xxxx_complex_mult_rtl_lib;
library ip_arria10_complex_mult_rtl_canonical_lib;
+library ip_agi027_xxxx_complex_mult_rtl_canonical_lib;
entity tech_complex_mult is
generic (
@@ -212,6 +213,31 @@ begin
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
end generate;
+ gen_ip_agi027_xxxx_ip : if g_variant = "IP" and g_technology = c_tech_agi027_xxxx and c_dsp_dat_w <= c_dsp_mult_18_w generate
+ -- Adapt DSP input widths
+ ar <= RESIZE_SVEC(in_ar, c_dsp_mult_18_w);
+ ai <= RESIZE_SVEC(in_ai, c_dsp_mult_18_w);
+ br <= RESIZE_SVEC(in_br, c_dsp_mult_18_w);
+ bi <= RESIZE_SVEC(in_bi, c_dsp_mult_18_w) when g_conjugate_b = false else TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_18_w);
+
+ u0 : ip_agi027_xxxx_complex_mult
+ port map (
+ aclr => rst,
+ clock => clk,
+ dataa_imag => ai,
+ dataa_real => ar,
+ datab_imag => bi,
+ datab_real => br,
+ ena => clken,
+ result_imag => mult_im,
+ result_real => mult_re
+ );
+
+ -- Back to true input widths and then resize for output width
+ result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
+ result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
+ end generate;
+
-----------------------------------------------------------------------------
-- IP variants for > 18 bit and <= 27 bit
-----------------------------------------------------------------------------
@@ -266,6 +292,31 @@ begin
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
end generate;
+ gen_ip_agi027_xxxx_ip_27b : if g_variant = "IP" and g_technology = c_tech_agi027_xxxx and c_dsp_dat_w > c_dsp_mult_18_w and c_dsp_dat_w <= c_dsp_mult_27_w generate
+ -- Adapt DSP input widths
+ ar <= RESIZE_SVEC(in_ar, c_dsp_mult_27_w);
+ ai <= RESIZE_SVEC(in_ai, c_dsp_mult_27_w);
+ br <= RESIZE_SVEC(in_br, c_dsp_mult_27_w);
+ bi <= RESIZE_SVEC(in_bi, c_dsp_mult_27_w) when g_conjugate_b = false else TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_27_w);
+
+ u0 : ip_agi027_xxxx_complex_mult_27b
+ port map (
+ aclr => rst,
+ clock => clk,
+ dataa_imag => ai,
+ dataa_real => ar,
+ datab_imag => bi,
+ datab_real => br,
+ ena => clken,
+ result_imag => mult_im,
+ result_real => mult_re
+ );
+
+ -- Back to true input widths and then resize for output width
+ result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
+ result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
+ end generate;
+
-----------------------------------------------------------------------------
-- RTL variants that can infer multipliers for a technology, fits all widths
-----------------------------------------------------------------------------
@@ -328,7 +379,6 @@ begin
gen_ip_arria10_rtl_canonical : if g_variant = "RTL_C" and (g_technology = c_tech_arria10_proto or
g_technology = c_tech_arria10_e3sge3 or
g_technology = c_tech_arria10_e1sg or
-
g_technology = c_tech_arria10_e2sg) generate
-- support g_conjugate_b
bi <= in_bi when g_conjugate_b = false else TO_SVEC(-TO_SINT(in_bi), g_in_b_w);
@@ -356,4 +406,58 @@ begin
);
end generate;
+ -- RTL variant is for iwave
+ gen_ip_agi027_xxxx_rtl : if g_variant = "RTL" and (g_technology = c_tech_agi027_xxxx) generate
+ u0 : ip_agi027_xxxx_complex_mult_rtl
+ generic map (
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_out_p_w => g_out_p_w,
+ g_conjugate_b => g_conjugate_b,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_ar => in_ar,
+ in_ai => in_ai,
+ in_br => in_br,
+ in_bi => in_bi,
+ result_re => result_re,
+ result_im => result_im
+ );
+ end generate;
+
+ -- RTL variant is for iwave
+ gen_ip_agi027_xxxx_rtl_canonical : if g_variant = "RTL_C" and (g_technology = c_tech_agi027_xxxx) generate
+ -- support g_conjugate_b
+ bi <= in_bi when g_conjugate_b = false else TO_SVEC(-TO_SINT(in_bi), g_in_b_w);
+
+ u0 : ip_agi027_xxxx_complex_mult_rtl_canonical
+ generic map (
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_out_p_w => g_out_p_w,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_ar => in_ar,
+ in_ai => in_ai,
+ in_br => in_br,
+ in_bi => bi,
+ result_re => result_re,
+ result_im => result_im
+ );
+ end generate;
+
end str;
diff --git a/libraries/technology/mult/tech_mult.vhd b/libraries/technology/mult/tech_mult.vhd
index 02302d50192a9aa4cdf39b42eb9214238e82a9e8..340909990f2383f7021d32c1f645d8085ed290aa 100644
--- a/libraries/technology/mult/tech_mult.vhd
+++ b/libraries/technology/mult/tech_mult.vhd
@@ -1,23 +1,25 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2009
+-- Copyright 2009-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
library IEEE, common_lib, technology_lib;
use IEEE.std_logic_1164.all;
@@ -29,6 +31,7 @@ use work.tech_mult_component_pkg.all;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
library ip_stratixiv_mult_lib;
library ip_arria10_mult_lib;
+library ip_agi027_xxxx_mult_lib;
entity tech_mult is
generic (
@@ -146,6 +149,49 @@ begin
);
end generate;
+ gen_ip_agi027_xxxx_ip : if (g_technology = c_tech_agi027_xxxx and g_variant = "IP") generate
+ u0 : ip_agi027_xxxx_mult
+ generic map(
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_out_p_w => g_out_p_w,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_output => g_pipeline_output,
+ g_representation => g_representation
+ )
+ port map(
+ clk => clk,
+ clken => clken,
+ in_a => in_a,
+ in_b => in_b,
+ out_p => prod
+ );
+ end generate;
+
+ gen_ip_agi027_xxxx_rtl : if (g_technology = c_tech_agi027_xxxx and g_variant = "RTL") generate
+ u0 : ip_agi027_xxxx_mult_rtl
+ generic map(
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_out_p_w => g_out_p_w,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_output => g_pipeline_output,
+ g_representation => g_representation
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_a => in_a,
+ in_b => in_b,
+ out_p => prod
+ );
+ end generate;
+
gen_trunk : for I in 0 to g_nof_mult - 1 generate
-- Truncate MSbits, also for signed (common_pkg.vhd for explanation of RESIZE_SVEC)
out_p((I + 1) * g_out_p_w - 1 downto I * g_out_p_w) <= RESIZE_SVEC(prod((I + 1) * c_prod_w - 1 downto I * c_prod_w), g_out_p_w) when g_representation = "SIGNED" else
diff --git a/libraries/technology/mult/tech_mult_add2.vhd b/libraries/technology/mult/tech_mult_add2.vhd
index 59504b2139122a8bcd6ea3fc182460d1b59b3df7..caabbb03d31aa08a858c5e133167c390361dc632 100644
--- a/libraries/technology/mult/tech_mult_add2.vhd
+++ b/libraries/technology/mult/tech_mult_add2.vhd
@@ -1,23 +1,25 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2009
+-- Copyright 2009-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
library IEEE, common_lib, technology_lib;
use IEEE.std_logic_1164.all;
@@ -30,6 +32,7 @@ use work.tech_mult_component_pkg.all;
library ip_stratixiv_mult_lib;
library ip_arria10_e1sg_mult_add2_lib;
library ip_arria10_e2sg_mult_add2_lib;
+library ip_agi027_xxxx_mult_add2_lib;
entity tech_mult_add2 is
generic (
@@ -130,4 +133,28 @@ begin
);
end generate;
+ gen_ip_agi027_xxxx_rtl : if (g_technology = c_tech_agi027_xxxx and g_variant = "RTL") generate
+ u0 : ip_agi027_xxxx_mult_add2_rtl
+ generic map(
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_res_w => g_res_w,
+ g_force_dsp => g_force_dsp,
+ g_add_sub => g_add_sub,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_a => in_a,
+ in_b => in_b,
+ res => res
+ );
+ end generate;
+
end str;
diff --git a/libraries/technology/mult/tech_mult_add4.vhd b/libraries/technology/mult/tech_mult_add4.vhd
index bc2e5da25b59eb3e1acbb873bf9617eecea20c3b..effb07e3de72b451223763422c7ad12bd0b5b80f 100644
--- a/libraries/technology/mult/tech_mult_add4.vhd
+++ b/libraries/technology/mult/tech_mult_add4.vhd
@@ -1,23 +1,25 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2009
+-- Copyright 2009-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
library IEEE, common_lib, technology_lib;
use IEEE.std_logic_1164.all;
@@ -31,6 +33,7 @@ library ip_stratixiv_mult_lib;
library ip_arria10_e3sge3_mult_add4_lib;
library ip_arria10_e1sg_mult_add4_lib;
library ip_arria10_e2sg_mult_add4_lib;
+library ip_agi027_xxxx_mult_add4_lib;
entity tech_mult_add4 is
generic (
@@ -165,4 +168,30 @@ begin
);
end generate;
+ gen_ip_agi027_xxxx_rtl : if (g_technology = c_tech_agi027_xxxx and g_variant = "RTL") generate
+ u0 : ip_agi027_xxxx_mult_add4_rtl
+ generic map(
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_res_w => g_res_w,
+ g_force_dsp => g_force_dsp,
+ g_add_sub0 => g_add_sub0,
+ g_add_sub1 => g_add_sub1,
+ g_add_sub => g_add_sub,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_a => in_a,
+ in_b => in_b,
+ res => res
+ );
+ end generate;
+
end str;
diff --git a/libraries/technology/mult/tech_mult_component_pkg.vhd b/libraries/technology/mult/tech_mult_component_pkg.vhd
index 8d9668897ba9d69109eff6079f39ab095adb39d1..9e12d7f58eb29bfb3406e55a62b86c79bb440d7a 100644
--- a/libraries/technology/mult/tech_mult_component_pkg.vhd
+++ b/libraries/technology/mult/tech_mult_component_pkg.vhd
@@ -1,25 +1,27 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright 2014-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
-
--- Purpose: IP components declarations for various devices that get wrapped by the tech components
+-- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
+-- Purpose:
+-- IP components declarations for various devices that get wrapped by the tech components
library IEEE;
use IEEE.std_logic_1164.all;
@@ -296,6 +298,7 @@ package tech_mult_component_pkg is
-----------------------------------------------------------------------------
-- Arria 10 e1sg components
-----------------------------------------------------------------------------
+
component ip_arria10_e1sg_mult_add2_rtl is
generic (
g_in_a_w : positive;
@@ -371,9 +374,11 @@ package tech_mult_component_pkg is
result_imag : out std_logic_vector(53 downto 0) -- .result_imag
);
end component;
+
-----------------------------------------------------------------------------
-- Arria 10 e2sg components
-----------------------------------------------------------------------------
+
component ip_arria10_e2sg_mult_add2_rtl is
generic (
g_in_a_w : positive;
@@ -449,4 +454,175 @@ package tech_mult_component_pkg is
result_imag : out std_logic_vector(53 downto 0) -- .result_imag
);
end component;
+
+ -----------------------------------------------------------------------------
+ -- Agilex 7 (agi027) xxxx components
+ -----------------------------------------------------------------------------
+
+ component ip_agi027_xxxx_mult is
+ generic (
+ g_in_a_w : positive := 18; -- Width of the data A port
+ g_in_b_w : positive := 18; -- Width of the data B port
+ g_out_p_w : positive := 36; -- Width of the result port
+ g_nof_mult : positive := 1; -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 1; -- 0 or 1
+ g_pipeline_output : natural := 1; -- >= 0
+ g_representation : string := "SIGNED" -- or "UNSIGNED"
+ );
+ port (
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_a : in std_logic_vector(g_nof_mult * g_in_a_w - 1 downto 0);
+ in_b : in std_logic_vector(g_nof_mult * g_in_b_w - 1 downto 0);
+ out_p : out std_logic_vector(g_nof_mult * (g_in_a_w + g_in_b_w) - 1 downto 0)
+ );
+ end component;
+
+ component ip_agi027_xxxx_mult_rtl is
+ generic (
+ g_in_a_w : positive := 18;
+ g_in_b_w : positive := 18;
+ g_out_p_w : positive := 36; -- c_prod_w = g_in_a_w+g_in_b_w, use smaller g_out_p_w to truncate MSbits, or larger g_out_p_w to extend MSbits
+ g_nof_mult : positive := 1; -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 1; -- 0 or 1
+ g_pipeline_output : natural := 1; -- >= 0
+ g_representation : string := "SIGNED" -- or "UNSIGNED"
+ );
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_a : in std_logic_vector(g_nof_mult * g_in_a_w - 1 downto 0);
+ in_b : in std_logic_vector(g_nof_mult * g_in_b_w - 1 downto 0);
+ out_p : out std_logic_vector(g_nof_mult * (g_in_a_w + g_in_b_w) - 1 downto 0)
+ );
+ end component;
+
+ component ip_agi027_xxxx_mult_add2_rtl is
+ generic (
+ g_in_a_w : positive;
+ g_in_b_w : positive;
+ g_res_w : positive; -- g_in_a_w + g_in_b_w + log2(2)
+ g_force_dsp : boolean := true; -- when TRUE resize input width to >= 18
+ g_add_sub : string := "ADD"; -- or "SUB"
+ g_nof_mult : integer := 2; -- fixed
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 0; -- 0 or 1
+ g_pipeline_adder : natural := 1; -- 0 or 1
+ g_pipeline_output : natural := 1 -- >= 0
+ );
+ port (
+ rst : in std_logic := '0';
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_a : in std_logic_vector(g_nof_mult * g_in_a_w - 1 downto 0);
+ in_b : in std_logic_vector(g_nof_mult * g_in_b_w - 1 downto 0);
+ res : out std_logic_vector(g_res_w - 1 downto 0)
+ );
+ end component;
+
+ component ip_agi027_xxxx_mult_add4_rtl is
+ generic (
+ g_in_a_w : positive;
+ g_in_b_w : positive;
+ g_res_w : positive; -- g_in_a_w + g_in_b_w + log2(4)
+ g_force_dsp : boolean := true; -- when TRUE resize input width to >= 18
+ g_add_sub0 : string := "ADD"; -- or "SUB"
+ g_add_sub1 : string := "ADD"; -- or "SUB"
+ g_add_sub : string := "ADD"; -- or "SUB" only available with rtl architecture
+ g_nof_mult : integer := 4; -- fixed
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 0; -- 0 or 1
+ g_pipeline_adder : natural := 1; -- 0 or 1, first sum
+ g_pipeline_output : natural := 1 -- >= 0, second sum and optional rounding
+ );
+ port (
+ rst : in std_logic := '0';
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_a : in std_logic_vector(g_nof_mult * g_in_a_w - 1 downto 0);
+ in_b : in std_logic_vector(g_nof_mult * g_in_b_w - 1 downto 0);
+ res : out std_logic_vector(g_res_w - 1 downto 0)
+ );
+ end component;
+
+
+ component ip_agi027_xxxx_complex_mult_rtl is
+ generic (
+ g_in_a_w : positive := 18;
+ g_in_b_w : positive := 18;
+ g_out_p_w : positive := 36;
+ g_conjugate_b : boolean := false;
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 0; -- 0 or 1
+ g_pipeline_adder : natural := 1; -- 0 or 1
+ g_pipeline_output : natural := 1 -- >= 0
+ );
+ port (
+ rst : in std_logic := '0';
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_ar : in std_logic_vector(g_in_a_w - 1 downto 0);
+ in_ai : in std_logic_vector(g_in_a_w - 1 downto 0);
+ in_br : in std_logic_vector(g_in_b_w - 1 downto 0);
+ in_bi : in std_logic_vector(g_in_b_w - 1 downto 0);
+ result_re : out std_logic_vector(g_out_p_w - 1 downto 0);
+ result_im : out std_logic_vector(g_out_p_w - 1 downto 0)
+ );
+ end component;
+
+ component ip_agi027_xxxx_complex_mult_rtl_canonical is
+ generic (
+ g_in_a_w : positive;
+ g_in_b_w : positive;
+ g_out_p_w : positive; -- default use g_out_p_w = g_in_a_w+g_in_b_w = c_prod_w
+-- g_conjugate_b : BOOLEAN := FALSE;
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 0; -- 0 or 1
+ g_pipeline_adder : natural := 1; -- 0 or 1
+ g_pipeline_output : natural := 1 -- >= 0
+ );
+ port (
+ rst : in std_logic := '0';
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_ar : in std_logic_vector(g_in_a_w - 1 downto 0);
+ in_ai : in std_logic_vector(g_in_a_w - 1 downto 0);
+ in_br : in std_logic_vector(g_in_b_w - 1 downto 0);
+ in_bi : in std_logic_vector(g_in_b_w - 1 downto 0);
+ result_re : out std_logic_vector(g_out_p_w - 1 downto 0);
+ result_im : out std_logic_vector(g_out_p_w - 1 downto 0)
+ );
+ end component;
+
+ component ip_agi027_xxxx_complex_mult is
+ port (
+ dataa_real : in std_logic_vector(17 downto 0) := (others => '0'); -- complex_input.dataa_real
+ dataa_imag : in std_logic_vector(17 downto 0) := (others => '0'); -- .dataa_imag
+ datab_real : in std_logic_vector(17 downto 0) := (others => '0'); -- .datab_real
+ datab_imag : in std_logic_vector(17 downto 0) := (others => '0'); -- .datab_imag
+ clock : in std_logic := '0'; -- .clk
+ aclr : in std_logic := '0'; -- .aclr
+ ena : in std_logic := '0'; -- .ena
+ result_real : out std_logic_vector(35 downto 0); -- complex_output.result_real
+ result_imag : out std_logic_vector(35 downto 0) -- .result_imag
+ );
+ end component;
+
+ component ip_agi027_xxxx_complex_mult_27b is
+ port (
+ dataa_real : in std_logic_vector(26 downto 0) := (others => '0'); -- complex_input.dataa_real
+ dataa_imag : in std_logic_vector(26 downto 0) := (others => '0'); -- .dataa_imag
+ datab_real : in std_logic_vector(26 downto 0) := (others => '0'); -- .datab_real
+ datab_imag : in std_logic_vector(26 downto 0) := (others => '0'); -- .datab_imag
+ clock : in std_logic := '0'; -- .clk
+ aclr : in std_logic := '0'; -- .aclr
+ ena : in std_logic := '0'; -- .ena
+ result_real : out std_logic_vector(53 downto 0); -- complex_output.result_real
+ result_imag : out std_logic_vector(53 downto 0) -- .result_imag
+ );
+ end component;
+
end tech_mult_component_pkg;
diff --git a/libraries/technology/mult/tech_mult_pkg.vhd b/libraries/technology/mult/tech_mult_pkg.vhd
index 093a503af280e3ae167d8312b6ce3315a3cecc41..b86a07117932d2b59d163ee0bd28401711697f27 100644
--- a/libraries/technology/mult/tech_mult_pkg.vhd
+++ b/libraries/technology/mult/tech_mult_pkg.vhd
@@ -1,24 +1,25 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright 2014-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
library IEEE, technology_lib;
use IEEE.std_logic_1164.all;
@@ -36,5 +37,7 @@ package tech_mult_pkg is
constant c_tech_mult_stratixiv_ip : t_c_tech_mult_variant := (" IP", true);
constant c_tech_mult_arria10_rtl : t_c_tech_mult_variant := ("RTL", false);
constant c_tech_mult_arria10_ip : t_c_tech_mult_variant := (" IP", true);
+ constant c_tech_mult_agi027_xxxx_rtl : t_c_tech_mult_variant := ("RTL", false);
+ constant c_tech_mult_agi027_xxxx_ip : t_c_tech_mult_variant := (" IP", true);
end tech_mult_pkg;