From 214a7bd1e1a4f6a420c2e3bf8441266072a2fc94 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Thu, 17 Aug 2023 09:07:11 +0200
Subject: [PATCH] Add verify last re and im.
---
.../base/dp/tb/vhdl/dp_stream_verify.vhd | 19 +++++++++++++++----
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd b/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd
index 18f1cdcd87..cdc1fd67f9 100644
--- a/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd
@@ -52,7 +52,8 @@ entity dp_stream_verify is
generic (
g_instance_nr : natural := 0;
-- flow control
- g_random_w : natural := 14; -- use different random width for stimuli and for verify to have different random sequences
+ -- . use different random width for stimuli and for verify to have different random sequences
+ g_random_w : natural := 14;
g_pulse_active : natural := 1;
g_pulse_period : natural := 2;
g_flow_control : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
@@ -88,13 +89,19 @@ architecture tb of dp_stream_verify is
constant c_rl : natural := 1;
constant c_no_dut : boolean := true;
- signal random : std_logic_vector(g_random_w - 1 downto 0) := TO_UVEC(g_instance_nr, g_random_w); -- use different initialization to have different random sequences per stream
+ -- Use different initialization by g_instance_nr, to have different random sequences per stream
+ signal random : std_logic_vector(g_random_w - 1 downto 0) := TO_UVEC(g_instance_nr, g_random_w);
signal pulse : std_logic;
signal pulse_en : std_logic := '1';
signal i_snk_out : t_dp_siso := c_dp_siso_rdy;
signal prev_snk_out : t_dp_siso;
- signal hold_snk_in_data : std_logic_vector(c_dp_stream_data_w - 1 downto 0); -- used to hold valid data for verify at verify_expected_snk_in_evt
+
+ -- hold valid data for verify at verify_expected_snk_in_evt
+ signal hold_snk_in_data : std_logic_vector(c_dp_stream_data_w - 1 downto 0);
+ signal hold_snk_in_re : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0);
+ signal hold_snk_in_im : std_logic_vector(c_dp_stream_dsp_data_w - 1 downto 0);
+
signal snk_in_data : std_logic_vector(g_in_dat_w - 1 downto 0);
signal prev_snk_in : t_dp_sosi;
@@ -138,8 +145,10 @@ begin
proc_dp_verify_value("snk_in.eop", clk, verify_expected_snk_in_evt.eop, expected_snk_in.eop, detected_snk_in_ctrl.eop);
proc_dp_verify_value("snk_in.valid", clk, verify_expected_snk_in_evt.valid, expected_snk_in.valid, detected_snk_in_ctrl.valid);
- -- Verify that the last sosi data, bsn, channel and err fields are correct
+ -- Verify that the last sosi data, re, im, bsn, channel and err fields are correct
proc_dp_verify_value("snk_in.data", e_equal, clk, verify_expected_snk_in_evt.data, expected_snk_in.data, hold_snk_in_data);
+ proc_dp_verify_value("snk_in.re", e_equal, clk, verify_expected_snk_in_evt.re, expected_snk_in.re, hold_snk_in_re);
+ proc_dp_verify_value("snk_in.im", e_equal, clk, verify_expected_snk_in_evt.im, expected_snk_in.im, hold_snk_in_im);
proc_dp_verify_value("snk_in.bsn", e_equal, clk, verify_expected_snk_in_evt.bsn, expected_snk_in.bsn, snk_in.bsn);
proc_dp_verify_value("snk_in.channel", e_equal, clk, verify_expected_snk_in_evt.channel, expected_snk_in.channel, snk_in.channel);
proc_dp_verify_value("snk_in.err", e_equal, clk, verify_expected_snk_in_evt.err, expected_snk_in.err, snk_in.err);
@@ -196,5 +205,7 @@ begin
snk_in_data <= snk_in.data(g_in_dat_w - 1 downto 0);
hold_snk_in_data <= snk_in.data when snk_in.valid = '1';
+ hold_snk_in_re <= snk_in.re when snk_in.valid = '1';
+ hold_snk_in_im <= snk_in.im when snk_in.valid = '1';
end tb;
--
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