From 2109532a1015bdb2d0d5c19a119d80245a212737 Mon Sep 17 00:00:00 2001
From: Daniel van der Schuur <schuur@astron.nl>
Date: Mon, 17 Nov 2014 14:59:32 +0000
Subject: [PATCH] -Fixed syntax errors; -Compiles OK in modelsim.
---
applications/unb1_correlator/hdllib.cfg | 2 +-
.../src/vhdl/mmm_unb1_correlator.vhd | 440 ++++++++----------
.../src/vhdl/unb1_correlator.vhd | 9 +-
3 files changed, 207 insertions(+), 244 deletions(-)
diff --git a/applications/unb1_correlator/hdllib.cfg b/applications/unb1_correlator/hdllib.cfg
index 4726ed8a2c..d0ea2ac947 100644
--- a/applications/unb1_correlator/hdllib.cfg
+++ b/applications/unb1_correlator/hdllib.cfg
@@ -10,7 +10,7 @@ quartus_copy_files =
quartus/qsys_unb1_correlator.qsys .
synth_files =
- $HDL_BUILD_DIR/quartus/unb1_correlator/qsys_unb1_correlator.vhd
+ $HDL_BUILD_DIR/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.v
src/vhdl/mmm_unb1_correlator.vhd
src/vhdl/unb1_correlator.vhd
diff --git a/applications/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd b/applications/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
index 62d92a26c9..015531ea0e 100644
--- a/applications/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
+++ b/applications/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2013
+-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
@@ -19,7 +19,7 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, remu_lib, epcs_lib;
+LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
@@ -28,15 +28,12 @@ USE unb1_board_lib.unb1_board_pkg.ALL;
USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL;
-USE work.qsys_unb1_minimal_pkg.ALL;
-
-ENTITY mmm_unb1_minimal IS
+ENTITY mmm_unb1_correlator IS
GENERIC (
g_sim : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O
g_sim_unb_nr : NATURAL := 0;
- g_sim_node_nr : NATURAL := 0;
- g_use_qsys : BOOLEAN := FALSE
+ g_sim_node_nr : NATURAL := 0
);
PORT (
xo_clk : IN STD_LOGIC;
@@ -47,8 +44,6 @@ ENTITY mmm_unb1_minimal IS
mm_clk : OUT STD_LOGIC;
mm_locked : OUT STD_LOGIC;
- epcs_clk : OUT STD_LOGIC;
-
pout_wdi : OUT STD_LOGIC;
-- Manual WDI override
@@ -78,39 +73,18 @@ ENTITY mmm_unb1_minimal IS
eth1g_reg_miso : IN t_mem_miso;
eth1g_reg_interrupt : IN STD_LOGIC;
eth1g_ram_mosi : OUT t_mem_mosi;
- eth1g_ram_miso : IN t_mem_miso;
- -- EPCS read
- reg_dpmm_data_mosi : OUT t_mem_mosi;
- reg_dpmm_data_miso : IN t_mem_miso;
- reg_dpmm_ctrl_mosi : OUT t_mem_mosi;
- reg_dpmm_ctrl_miso : IN t_mem_miso;
-
- -- EPCS write
- reg_mmdp_data_mosi : OUT t_mem_mosi;
- reg_mmdp_data_miso : IN t_mem_miso;
- reg_mmdp_ctrl_mosi : OUT t_mem_mosi;
- reg_mmdp_ctrl_miso : IN t_mem_miso;
-
- -- EPCS status/control
- reg_epcs_mosi : OUT t_mem_mosi;
- reg_epcs_miso : IN t_mem_miso;
-
- -- Remote Update
- reg_remu_mosi : OUT t_mem_mosi;
- reg_remu_miso : IN t_mem_miso
+ eth1g_ram_miso : IN t_mem_miso
);
-END mmm_unb1_minimal;
+END mmm_unb1_correlator;
-ARCHITECTURE str OF mmm_unb1_minimal IS
+ARCHITECTURE str OF mmm_unb1_correlator IS
CONSTANT c_mm_clk_period : TIME := 8 ns; -- 125 MHz
- CONSTANT c_epcs_clk_period : TIME := 50 ns; -- 20 MHz
CONSTANT c_sim_node_type : STRING(1 TO 2):= sel_a_b(g_sim_node_nr<4, "FN", "BN");
CONSTANT c_sim_node_nr : NATURAL := sel_a_b(c_sim_node_type="BN", g_sim_node_nr-4, g_sim_node_nr);
SIGNAL i_mm_clk : STD_LOGIC := '1';
- SIGNAL i_epcs_clk : STD_LOGIC := '1';
----------------------------------------------------------------------------
-- mm_file component
@@ -130,10 +104,205 @@ ARCHITECTURE str OF mmm_unb1_minimal IS
);
END COMPONENT;
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
+ -----------------------------------------------------------------------------
+ COMPONENT qsys_unb1_test is
+ PORT (
+
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ mm_clk : out std_logic; -- clk
+ coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
+ coe_address_export_from_the_pio_pps : out std_logic;--_vector(0 downto 0); -- export
+ coe_waitrequest_export_to_the_reg_tr_10GbE : in std_logic := 'X'; -- export
+ coe_reset_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_write_export_from_the_reg_tr_xaui : out std_logic; -- export
+ coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_tr_xaui : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_ctrl : out std_logic;--_vector(0 downto 0); -- export
+ coe_clk_export_from_the_rom_system_info : out std_logic; -- export
+ coe_reset_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_tr_xaui : out std_logic_vector(10 downto 0); -- export
+ coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_read_export_from_the_reg_wdi : out std_logic; -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_waitrequest_export_to_the_reg_tr_xaui : in std_logic := 'X'; -- export
+ coe_clk_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_tr_10GbE : out std_logic; -- export
+ coe_reset_export_from_the_reg_tr_xaui : out std_logic; -- export
+ coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_data : out std_logic;--_vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_tr_10GbE : out std_logic_vector(14 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_address_export_from_the_reg_wdi : out std_logic;--_vector(0 downto 0); -- export
+ coe_write_export_from_the_pio_system_info : out std_logic; -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_pio_pps : out std_logic; -- export
+ coe_write_export_from_the_rom_system_info : out std_logic; -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ phasedone_from_the_altpll_0 : out std_logic; -- export
+ coe_read_export_from_the_rom_system_info : out std_logic; -- export
+ coe_reset_export_from_the_reg_epcs : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ clk_0 : in std_logic := 'X'; -- clk
+ coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_readdata_export_to_the_reg_tr_xaui : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
+ coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
+ coe_writedata_export_from_the_reg_tr_10GbE : out std_logic_vector(31 downto 0); -- export
+ tse_clk : out std_logic; -- clk
+ dp_clk : out std_logic; -- clk
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ epcs_clk : out std_logic; -- clk
+ coe_read_export_from_the_reg_tr_10GbE : out std_logic; -- export
+ coe_clk_export_from_the_reg_tr_10GbE : out std_logic; -- export
+ coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ out_port_from_the_pio_debug_wave : out std_logic_vector(31 downto 0); -- export
+ coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_tr_xaui : out std_logic; -- export
+ coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_pio_system_info : out std_logic; -- export
+ coe_read_export_from_the_pio_system_info : out std_logic; -- export
+ cal_reconf_clk : out std_logic; -- clk
+ coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_wdi : out std_logic; -- export
+ coe_clk_export_from_the_reg_epcs : out std_logic; -- export
+ coe_write_export_from_the_reg_remu : out std_logic; -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
+ out_port_from_the_pio_wdi : out std_logic; -- export
+ coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_address_export_from_the_reg_mmdp_ctrl : out std_logic;--_vector(0 downto 0); -- export
+ coe_write_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_wdi : out std_logic; -- export
+ coe_clk_export_from_the_reg_tr_xaui : out std_logic; -- export
+ coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_pio_pps : out std_logic; -- export
+ coe_clk_export_from_the_pio_system_info : out std_logic; -- export
+ coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
+ coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_reset_export_from_the_rom_system_info : out std_logic; -- export
+ coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_address_export_from_the_reg_mmdp_data : out std_logic;--_vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
+ coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
+ coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
+ areset_to_the_altpll_0 : in std_logic := 'X'; -- export
+ locked_from_the_altpll_0 : out std_logic; -- export
+ coe_readdata_export_to_the_reg_tr_10GbE : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_reset_export_from_the_reg_tr_10GbE : out std_logic; -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_remu : out std_logic; -- export
+ reg_bsn_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_read_export : out std_logic; -- export
+ reg_bsn_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_write_export : out std_logic; -- export
+ reg_bsn_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_bsn_monitor_clk_export : out std_logic; -- export
+ reg_bsn_monitor_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_tx_read_export : out std_logic; -- export
+ reg_dp_offload_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_write_export : out std_logic; -- export
+ reg_dp_offload_tx_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_offload_tx_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_tx_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_tx_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_tx_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_dp_offload_tx_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_hdr_dat_reset_export : out std_logic; -- export
+ reg_dp_offload_rx_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_rx_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_rx_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_rx_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_rx_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_dp_offload_rx_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_rx_hdr_dat_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_hdr_ovr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_tx_hdr_ovr_read_export : out std_logic; -- export
+ reg_dp_offload_tx_hdr_ovr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_hdr_ovr_write_export : out std_logic; -- export
+ reg_dp_offload_tx_hdr_ovr_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_dp_offload_tx_hdr_ovr_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_hdr_ovr_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_read_export : out std_logic; -- export
+ reg_diag_data_buffer_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_write_export : out std_logic; -- export
+ reg_diag_data_buffer_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_read_export : out std_logic; -- export
+ ram_diag_data_buffer_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_write_export : out std_logic; -- export
+ ram_diag_data_buffer_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buffer_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_reset_export : out std_logic; -- export
+ reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_read_export : out std_logic; -- export
+ reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_write_export : out std_logic; -- export
+ reg_diag_bg_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_clk_export : out std_logic; -- export
+ reg_diag_bg_reset_export : out std_logic; -- export
+ ram_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_read_export : out std_logic; -- export
+ ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_write_export : out std_logic; -- export
+ ram_diag_bg_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_diag_bg_clk_export : out std_logic; -- export
+ ram_diag_bg_reset_export : out std_logic -- export
+ );
+ end component qsys_unb1_test;
+
BEGIN
mm_clk <= i_mm_clk;
- epcs_clk <= i_epcs_clk;
----------------------------------------------------------------------------
@@ -143,7 +312,6 @@ BEGIN
i_mm_clk <= NOT i_mm_clk AFTER c_mm_clk_period/2;
mm_locked <= '0', '1' AFTER c_mm_clk_period*5;
- i_epcs_clk <= NOT i_epcs_clk AFTER c_epcs_clk_period/2;
u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
PORT MAP(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
@@ -175,156 +343,13 @@ BEGIN
----------------------------------------------------------------------------
-- SOPC or QSYS for synthesis
----------------------------------------------------------------------------
- gen_sopc : IF g_sim = FALSE AND g_use_qsys = FALSE GENERATE
- u_sopc : ENTITY work.sopc_unb1_minimal
- PORT MAP (
- clk_0 => xo_clk,
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk,
- tse_clk => eth1g_tse_clk,
- epcs_clk => i_epcs_clk,
-
- -- the_altpll_0
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
- areset_to_the_altpll_0 => xo_rst,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => OPEN,
-
- -- the_pio_pps
- coe_clk_export_from_the_pio_pps => OPEN,
- coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
- coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
- coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
- coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb1_board.
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_dpmm_data
- coe_clk_export_from_the_reg_dpmm_data => OPEN,
- coe_reset_export_from_the_reg_dpmm_data => OPEN,
- coe_address_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.address(0),
- coe_read_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.rd,
- coe_readdata_export_to_the_reg_dpmm_data => reg_dpmm_data_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wr,
- coe_writedata_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_dpmm_ctrl
- coe_clk_export_from_the_reg_dpmm_ctrl => OPEN,
- coe_reset_export_from_the_reg_dpmm_ctrl => OPEN,
- coe_address_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.address(0),
- coe_read_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.rd,
- coe_readdata_export_to_the_reg_dpmm_ctrl => reg_dpmm_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wr,
- coe_writedata_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_mmdp_data
- coe_clk_export_from_the_reg_mmdp_data => OPEN,
- coe_reset_export_from_the_reg_mmdp_data => OPEN,
- coe_address_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.address(0),
- coe_read_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.rd,
- coe_readdata_export_to_the_reg_mmdp_data => reg_mmdp_data_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wr,
- coe_writedata_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_mmdp_ctrl
- coe_clk_export_from_the_reg_mmdp_ctrl => OPEN,
- coe_reset_export_from_the_reg_mmdp_ctrl => OPEN,
- coe_address_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.address(0),
- coe_read_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.rd,
- coe_readdata_export_to_the_reg_mmdp_ctrl => reg_mmdp_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wr,
- coe_writedata_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_epcs
- coe_clk_export_from_the_reg_epcs => OPEN,
- coe_reset_export_from_the_reg_epcs => OPEN,
- coe_address_export_from_the_reg_epcs => reg_epcs_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
- coe_read_export_from_the_reg_epcs => reg_epcs_mosi.rd,
- coe_readdata_export_to_the_reg_epcs => reg_epcs_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_reg_epcs => reg_epcs_mosi.wr,
- coe_writedata_export_from_the_reg_epcs => reg_epcs_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_remu
- coe_clk_export_from_the_reg_remu => OPEN,
- coe_reset_export_from_the_reg_remu => OPEN,
- coe_address_export_from_the_reg_remu => reg_remu_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
- coe_read_export_from_the_reg_remu => reg_remu_mosi.rd,
- coe_readdata_export_to_the_reg_remu => reg_remu_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_reg_remu => reg_remu_mosi.wr,
- coe_writedata_export_from_the_reg_remu => reg_remu_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0)
- );
- END GENERATE;
-
- gen_qsys : IF g_sim = FALSE AND g_use_qsys = TRUE GENERATE
- u_qsys : qsys_unb1_minimal
+ gen_qsys_unb1_correlator : IF g_sim = FALSE GENERATE
+ u_qsys_unb1_correlator : ENTITY work.qsys_unb1_correlator
PORT MAP (
clk_0 => xo_clk,
reset_n => xo_rst_n,
mm_clk => i_mm_clk,
tse_clk => eth1g_tse_clk,
- epcs_clk => i_epcs_clk,
-- the_altpll_0
locked_from_the_altpll_0 => mm_locked,
@@ -394,61 +419,6 @@ BEGIN
-- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb1_board.
out_port_from_the_pio_wdi => pout_wdi,
- -- the_reg_dpmm_data
- coe_clk_export_from_the_reg_dpmm_data => OPEN,
- coe_reset_export_from_the_reg_dpmm_data => OPEN,
- coe_address_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.address(0),
- coe_read_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.rd,
- coe_readdata_export_to_the_reg_dpmm_data => reg_dpmm_data_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wr,
- coe_writedata_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_dpmm_ctrl
- coe_clk_export_from_the_reg_dpmm_ctrl => OPEN,
- coe_reset_export_from_the_reg_dpmm_ctrl => OPEN,
- coe_address_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.address(0),
- coe_read_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.rd,
- coe_readdata_export_to_the_reg_dpmm_ctrl => reg_dpmm_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wr,
- coe_writedata_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_mmdp_data
- coe_clk_export_from_the_reg_mmdp_data => OPEN,
- coe_reset_export_from_the_reg_mmdp_data => OPEN,
- coe_address_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.address(0),
- coe_read_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.rd,
- coe_readdata_export_to_the_reg_mmdp_data => reg_mmdp_data_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wr,
- coe_writedata_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_mmdp_ctrl
- coe_clk_export_from_the_reg_mmdp_ctrl => OPEN,
- coe_reset_export_from_the_reg_mmdp_ctrl => OPEN,
- coe_address_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.address(0),
- coe_read_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.rd,
- coe_readdata_export_to_the_reg_mmdp_ctrl => reg_mmdp_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wr,
- coe_writedata_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
-
- -- the_reg_epcs
- coe_clk_export_from_the_reg_epcs => OPEN,
- coe_reset_export_from_the_reg_epcs => OPEN,
- coe_address_export_from_the_reg_epcs => reg_epcs_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
- coe_read_export_from_the_reg_epcs => reg_epcs_mosi.rd,
- coe_readdata_export_to_the_reg_epcs => reg_epcs_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_reg_epcs => reg_epcs_mosi.wr,
- coe_writedata_export_from_the_reg_epcs => reg_epcs_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_remu
- coe_clk_export_from_the_reg_remu => OPEN,
- coe_reset_export_from_the_reg_remu => OPEN,
- coe_address_export_from_the_reg_remu => reg_remu_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
- coe_read_export_from_the_reg_remu => reg_remu_mosi.rd,
- coe_readdata_export_to_the_reg_remu => reg_remu_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_reg_remu => reg_remu_mosi.wr,
- coe_writedata_export_from_the_reg_remu => reg_remu_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
-- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
coe_clk_export_from_the_reg_wdi => OPEN,
coe_reset_export_from_the_reg_wdi => OPEN,
diff --git a/applications/unb1_correlator/src/vhdl/unb1_correlator.vhd b/applications/unb1_correlator/src/vhdl/unb1_correlator.vhd
index 07f050907f..52e50a741f 100644
--- a/applications/unb1_correlator/src/vhdl/unb1_correlator.vhd
+++ b/applications/unb1_correlator/src/vhdl/unb1_correlator.vhd
@@ -69,9 +69,6 @@ ARCHITECTURE str OF unb1_correlator IS
-- In simulation we don't need the 1GbE core for MM control, deselect it in c_use_phy based on g_sim
CONSTANT c_use_phy : t_c_unb1_board_use_phy := (sel_a_b(g_sim, 0, 1), 0, 0, 0, 0, 0, 0, 1);
- CONSTANT c_use_qsys : BOOLEAN := g_design_name="unb1_correlator_qsys";
- CONSTANT c_use_sopc : BOOLEAN := NOT c_use_qsys;
-
-- System
SIGNAL cs_sim : STD_LOGIC;
SIGNAL xo_clk : STD_LOGIC;
@@ -83,8 +80,6 @@ ARCHITECTURE str OF unb1_correlator IS
SIGNAL st_rst : STD_LOGIC;
SIGNAL st_clk : STD_LOGIC;
-
- SIGNAL epcs_clk : STD_LOGIC;
-- PIOs
SIGNAL pout_wdi : STD_LOGIC;
@@ -166,7 +161,7 @@ BEGIN
mm_locked => mm_locked,
mm_rst => mm_rst,
- epcs_clk => epcs_clk,
+ epcs_clk => '0',
dp_rst => st_rst,
dp_clk => st_clk,
@@ -249,8 +244,6 @@ BEGIN
mm_clk => mm_clk,
mm_locked => mm_locked,
- epcs_clk => epcs_clk,
-
-- PIOs
pout_wdi => pout_wdi,
--
GitLab