From 20f583e7dc0036c1af4bb9e0ded798fb23283b7f Mon Sep 17 00:00:00 2001
From: David Brouwer <dbrouwer@astron.nl>
Date: Mon, 18 Dec 2023 15:39:39 +0100
Subject: [PATCH] RTSD-209: tech_memory_ram_crwk_crw - For agilex 7
(agi027_xxxx) is also the ip_agi027_xxxx_ram_rw_rw added, but it is only
supporting clock_b and a ratio of 1 . Added library ip_agi027_xxxx_ram_lib.
So it can be used in the diag_databuffer.Fix 'can be created -> can be used'.
---
.../technology/memory/tech_memory_ram_crwk_crw.vhd | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
index 63e993d331..a58dde75ab 100644
--- a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
@@ -23,9 +23,12 @@
-- Remark:
-- The Agilex 7 (agi027_xxxx) doesn't support this IP as used for previous
-- FPGA technology identifiers (device types), and unfortunately, the rwk_rw
--- IP variant isn't supported either. Instead, the crk_cw IP can be created
+-- IP variant isn't supported either. Instead, the crk_cw IP can be used
-- when necessary. For more details please refer the README.txt in the
-- ip_agi027_xxxx/ram/ folder.
+-- . For Agilex 7 (agi027_xxxx) is also the ip_agi027_xxxx_ram_rw_rw added
+-- to this package, but it is only supporting clock_b and a ratio of 1.
+-- (So it can be used in the diag_databuffer).
library ieee, technology_lib;
use ieee.std_logic_1164.all;
@@ -39,6 +42,7 @@ library ip_arria10_ram_lib;
library ip_arria10_e3sge3_ram_lib;
library ip_arria10_e1sg_ram_lib;
library ip_arria10_e2sg_ram_lib;
+library ip_agi027_xxxx_ram_lib;
entity tech_memory_ram_crwk_crw is -- support different port data widths and corresponding address ranges
generic (
@@ -103,4 +107,10 @@ begin
port map (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
end generate;
+ gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
+ u0 : ip_agi027_xxxx_ram_rw_rw
+ generic map (false, g_adr_b_w, g_dat_b_w, g_nof_words_b, g_rd_latency, g_init_file)
+ port map (address_a, address_b, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
+ end generate;
+
end architecture;
--
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